1 /*-
2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: stable/9/sys/dev/ata/ata-lowlevel.c 258218 2013-11-16 10:47:58Z mav $");
29
30 #include "opt_ata.h"
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/endian.h>
35 #include <sys/ata.h>
36 #include <sys/conf.h>
37 #include <sys/ctype.h>
38 #include <sys/bus.h>
39 #include <sys/sema.h>
40 #include <sys/taskqueue.h>
41 #include <vm/uma.h>
42 #include <machine/bus.h>
43 #include <sys/rman.h>
44 #include <dev/ata/ata-all.h>
45 #include <dev/ata/ata-pci.h>
46 #include <ata_if.h>
47
48 /* prototypes */
49 static int ata_generic_status(device_t dev);
50 static int ata_wait(struct ata_channel *ch, int unit, u_int8_t);
51 static void ata_pio_read(struct ata_request *, int);
52 static void ata_pio_write(struct ata_request *, int);
53 static void ata_tf_read(struct ata_request *);
54 static void ata_tf_write(struct ata_request *);
55
56 /*
57 * low level ATA functions
58 */
59 void
ata_generic_hw(device_t dev)60 ata_generic_hw(device_t dev)
61 {
62 struct ata_channel *ch = device_get_softc(dev);
63
64 ch->hw.begin_transaction = ata_begin_transaction;
65 ch->hw.end_transaction = ata_end_transaction;
66 ch->hw.status = ata_generic_status;
67 ch->hw.softreset = NULL;
68 ch->hw.command = ata_generic_command;
69 ch->hw.tf_read = ata_tf_read;
70 ch->hw.tf_write = ata_tf_write;
71 ch->hw.pm_read = NULL;
72 ch->hw.pm_write = NULL;
73 }
74
75 /* must be called with ATA channel locked and state_mtx held */
76 int
ata_begin_transaction(struct ata_request * request)77 ata_begin_transaction(struct ata_request *request)
78 {
79 struct ata_channel *ch = device_get_softc(request->parent);
80 int dummy, error;
81
82 ATA_DEBUG_RQ(request, "begin transaction");
83
84 /* disable ATAPI DMA writes if HW doesn't support it */
85 if ((ch->flags & ATA_NO_ATAPI_DMA) &&
86 (request->flags & ATA_R_ATAPI) == ATA_R_ATAPI)
87 request->flags &= ~ATA_R_DMA;
88 if ((ch->flags & ATA_ATAPI_DMA_RO) &&
89 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) ==
90 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)))
91 request->flags &= ~ATA_R_DMA;
92
93 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) {
94
95 /* ATA PIO data transfer and control commands */
96 default:
97 {
98 /* record command direction here as our request might be gone later */
99 int write = (request->flags & ATA_R_WRITE);
100
101 /* issue command */
102 if (ch->hw.command(request)) {
103 device_printf(request->parent, "error issuing %s command\n",
104 ata_cmd2str(request));
105 request->result = EIO;
106 goto begin_finished;
107 }
108
109 /* device reset doesn't interrupt */
110 if (request->u.ata.command == ATA_DEVICE_RESET) {
111
112 int timeout = 1000000;
113 do {
114 DELAY(10);
115 request->status = ATA_IDX_INB(ch, ATA_STATUS);
116 } while (request->status & ATA_S_BUSY && timeout--);
117 if (request->status & ATA_S_ERROR)
118 request->error = ATA_IDX_INB(ch, ATA_ERROR);
119 ch->hw.tf_read(request);
120 goto begin_finished;
121 }
122
123 /* if write command output the data */
124 if (write) {
125 if (ata_wait(ch, request->unit, (ATA_S_READY | ATA_S_DRQ)) < 0) {
126 device_printf(request->parent,
127 "timeout waiting for write DRQ\n");
128 request->result = EIO;
129 goto begin_finished;
130 }
131 ata_pio_write(request, request->transfersize);
132 }
133 }
134 goto begin_continue;
135
136 /* ATA DMA data transfer commands */
137 case ATA_R_DMA:
138 /* check sanity, setup SG list and DMA engine */
139 if ((error = ch->dma.load(request, NULL, &dummy))) {
140 device_printf(request->parent, "setting up DMA failed\n");
141 request->result = error;
142 goto begin_finished;
143 }
144
145 /* start DMA engine if necessary */
146 if ((ch->flags & ATA_DMA_BEFORE_CMD) &&
147 ch->dma.start && ch->dma.start(request)) {
148 device_printf(request->parent, "error starting DMA\n");
149 request->result = EIO;
150 goto begin_finished;
151 }
152
153 /* issue command */
154 if (ch->hw.command(request)) {
155 device_printf(request->parent, "error issuing %s command\n",
156 ata_cmd2str(request));
157 request->result = EIO;
158 goto begin_finished;
159 }
160
161 /* start DMA engine */
162 if (!(ch->flags & ATA_DMA_BEFORE_CMD) &&
163 ch->dma.start && ch->dma.start(request)) {
164 device_printf(request->parent, "error starting DMA\n");
165 request->result = EIO;
166 goto begin_finished;
167 }
168 goto begin_continue;
169
170 /* ATAPI PIO commands */
171 case ATA_R_ATAPI:
172 /* is this just a POLL DSC command ? */
173 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
174 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit));
175 DELAY(10);
176 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC))
177 request->result = EBUSY;
178 goto begin_finished;
179 }
180
181 /* start ATAPI operation */
182 if (ch->hw.command(request)) {
183 device_printf(request->parent, "error issuing ATA PACKET command\n");
184 request->result = EIO;
185 goto begin_finished;
186 }
187 goto begin_continue;
188
189 /* ATAPI DMA commands */
190 case ATA_R_ATAPI|ATA_R_DMA:
191 /* is this just a POLL DSC command ? */
192 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
193 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit));
194 DELAY(10);
195 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC))
196 request->result = EBUSY;
197 goto begin_finished;
198 }
199
200 /* check sanity, setup SG list and DMA engine */
201 if ((error = ch->dma.load(request, NULL, &dummy))) {
202 device_printf(request->parent, "setting up DMA failed\n");
203 request->result = error;
204 goto begin_finished;
205 }
206
207 /* start ATAPI operation */
208 if (ch->hw.command(request)) {
209 device_printf(request->parent, "error issuing ATA PACKET command\n");
210 request->result = EIO;
211 goto begin_finished;
212 }
213
214 /* start DMA engine */
215 if (ch->dma.start && ch->dma.start(request)) {
216 request->result = EIO;
217 goto begin_finished;
218 }
219 goto begin_continue;
220 }
221 /* NOT REACHED */
222 printf("ata_begin_transaction OOPS!!!\n");
223
224 begin_finished:
225 if (ch->dma.unload) {
226 ch->dma.unload(request);
227 }
228 return ATA_OP_FINISHED;
229
230 begin_continue:
231 callout_reset(&request->callout, request->timeout * hz,
232 (timeout_t*)ata_timeout, request);
233 return ATA_OP_CONTINUES;
234 }
235
236 /* must be called with ATA channel locked and state_mtx held */
237 int
ata_end_transaction(struct ata_request * request)238 ata_end_transaction(struct ata_request *request)
239 {
240 struct ata_channel *ch = device_get_softc(request->parent);
241 int length;
242
243 ATA_DEBUG_RQ(request, "end transaction");
244
245 /* clear interrupt and get status */
246 request->status = ATA_IDX_INB(ch, ATA_STATUS);
247
248 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) {
249
250 /* ATA PIO data transfer and control commands */
251 default:
252
253 /* on timeouts we have no data or anything so just return */
254 if (request->flags & ATA_R_TIMEOUT)
255 goto end_finished;
256
257 /* Read back registers to the request struct. */
258 if ((request->status & ATA_S_ERROR) ||
259 (request->flags & (ATA_R_CONTROL | ATA_R_NEEDRESULT))) {
260 ch->hw.tf_read(request);
261 }
262
263 /* if we got an error we are done with the HW */
264 if (request->status & ATA_S_ERROR) {
265 request->error = ATA_IDX_INB(ch, ATA_ERROR);
266 goto end_finished;
267 }
268
269 /* are we moving data ? */
270 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
271
272 /* if read data get it */
273 if (request->flags & ATA_R_READ) {
274 int flags = ATA_S_DRQ;
275
276 if (request->u.ata.command != ATA_ATAPI_IDENTIFY)
277 flags |= ATA_S_READY;
278 if (ata_wait(ch, request->unit, flags) < 0) {
279 device_printf(request->parent,
280 "timeout waiting for read DRQ\n");
281 request->result = EIO;
282 goto end_finished;
283 }
284 ata_pio_read(request, request->transfersize);
285 }
286
287 /* update how far we've gotten */
288 request->donecount += request->transfersize;
289
290 /* do we need a scoop more ? */
291 if (request->bytecount > request->donecount) {
292
293 /* set this transfer size according to HW capabilities */
294 request->transfersize =
295 min((request->bytecount - request->donecount),
296 request->transfersize);
297
298 /* if data write command, output the data */
299 if (request->flags & ATA_R_WRITE) {
300
301 /* if we get an error here we are done with the HW */
302 if (ata_wait(ch, request->unit, (ATA_S_READY | ATA_S_DRQ)) < 0) {
303 device_printf(request->parent,
304 "timeout waiting for write DRQ\n");
305 request->status = ATA_IDX_INB(ch, ATA_STATUS);
306 goto end_finished;
307 }
308
309 /* output data and return waiting for new interrupt */
310 ata_pio_write(request, request->transfersize);
311 goto end_continue;
312 }
313
314 /* if data read command, return & wait for interrupt */
315 if (request->flags & ATA_R_READ)
316 goto end_continue;
317 }
318 }
319 /* done with HW */
320 goto end_finished;
321
322 /* ATA DMA data transfer commands */
323 case ATA_R_DMA:
324
325 /* stop DMA engine and get status */
326 if (ch->dma.stop)
327 request->dma->status = ch->dma.stop(request);
328
329 /* did we get error or data */
330 if (request->status & ATA_S_ERROR)
331 request->error = ATA_IDX_INB(ch, ATA_ERROR);
332 else if (request->dma->status & ATA_BMSTAT_ERROR)
333 request->status |= ATA_S_ERROR;
334 else if (!(request->flags & ATA_R_TIMEOUT))
335 request->donecount = request->bytecount;
336
337 /* Read back registers to the request struct. */
338 if ((request->status & ATA_S_ERROR) ||
339 (request->flags & (ATA_R_CONTROL | ATA_R_NEEDRESULT))) {
340 ch->hw.tf_read(request);
341 }
342
343 /* release SG list etc */
344 ch->dma.unload(request);
345
346 /* done with HW */
347 goto end_finished;
348
349 /* ATAPI PIO commands */
350 case ATA_R_ATAPI:
351 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8);
352
353 /* on timeouts we have no data or anything so just return */
354 if (request->flags & ATA_R_TIMEOUT)
355 goto end_finished;
356
357 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) |
358 (request->status & ATA_S_DRQ)) {
359
360 case ATAPI_P_CMDOUT:
361 /* this seems to be needed for some (slow) devices */
362 DELAY(10);
363
364 if (!(request->status & ATA_S_DRQ)) {
365 device_printf(request->parent, "command interrupt without DRQ\n");
366 request->status = ATA_S_ERROR;
367 goto end_finished;
368 }
369 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
370 (request->flags & ATA_R_ATAPI16) ? 8 : 6);
371 /* return wait for interrupt */
372 goto end_continue;
373
374 case ATAPI_P_WRITE:
375 if (request->flags & ATA_R_READ) {
376 request->status = ATA_S_ERROR;
377 device_printf(request->parent,
378 "%s trying to write on read buffer\n",
379 ata_cmd2str(request));
380 goto end_finished;
381 break;
382 }
383 ata_pio_write(request, length);
384 request->donecount += length;
385
386 /* set next transfer size according to HW capabilities */
387 request->transfersize = min((request->bytecount-request->donecount),
388 request->transfersize);
389 /* return wait for interrupt */
390 goto end_continue;
391
392 case ATAPI_P_READ:
393 if (request->flags & ATA_R_WRITE) {
394 request->status = ATA_S_ERROR;
395 device_printf(request->parent,
396 "%s trying to read on write buffer\n",
397 ata_cmd2str(request));
398 goto end_finished;
399 }
400 ata_pio_read(request, length);
401 request->donecount += length;
402
403 /* set next transfer size according to HW capabilities */
404 request->transfersize = min((request->bytecount-request->donecount),
405 request->transfersize);
406 /* return wait for interrupt */
407 goto end_continue;
408
409 case ATAPI_P_DONEDRQ:
410 device_printf(request->parent,
411 "WARNING - %s DONEDRQ non conformant device\n",
412 ata_cmd2str(request));
413 if (request->flags & ATA_R_READ) {
414 ata_pio_read(request, length);
415 request->donecount += length;
416 }
417 else if (request->flags & ATA_R_WRITE) {
418 ata_pio_write(request, length);
419 request->donecount += length;
420 }
421 else
422 request->status = ATA_S_ERROR;
423 /* FALLTHROUGH */
424
425 case ATAPI_P_ABORT:
426 case ATAPI_P_DONE:
427 if (request->status & (ATA_S_ERROR | ATA_S_DWF))
428 request->error = ATA_IDX_INB(ch, ATA_ERROR);
429 goto end_finished;
430
431 default:
432 device_printf(request->parent, "unknown transfer phase\n");
433 request->status = ATA_S_ERROR;
434 }
435
436 /* done with HW */
437 goto end_finished;
438
439 /* ATAPI DMA commands */
440 case ATA_R_ATAPI|ATA_R_DMA:
441
442 /* stop DMA engine and get status */
443 if (ch->dma.stop)
444 request->dma->status = ch->dma.stop(request);
445
446 /* did we get error or data */
447 if (request->status & (ATA_S_ERROR | ATA_S_DWF))
448 request->error = ATA_IDX_INB(ch, ATA_ERROR);
449 else if (request->dma->status & ATA_BMSTAT_ERROR)
450 request->status |= ATA_S_ERROR;
451 else if (!(request->flags & ATA_R_TIMEOUT))
452 request->donecount = request->bytecount;
453
454 /* release SG list etc */
455 ch->dma.unload(request);
456
457 /* done with HW */
458 goto end_finished;
459 }
460 /* NOT REACHED */
461 printf("ata_end_transaction OOPS!!\n");
462
463 end_finished:
464 callout_stop(&request->callout);
465 return ATA_OP_FINISHED;
466
467 end_continue:
468 return ATA_OP_CONTINUES;
469 }
470
471 /* must be called with ATA channel locked and state_mtx held */
472 void
ata_generic_reset(device_t dev)473 ata_generic_reset(device_t dev)
474 {
475 struct ata_channel *ch = device_get_softc(dev);
476
477 u_int8_t ostat0 = 0, stat0 = 0, ostat1 = 0, stat1 = 0;
478 u_int8_t err = 0, lsb = 0, msb = 0;
479 int mask = 0, timeout;
480
481 /* do we have any signs of ATA/ATAPI HW being present ? */
482 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER));
483 DELAY(10);
484 ostat0 = ATA_IDX_INB(ch, ATA_STATUS);
485 if (((ostat0 & 0xf8) != 0xf8 || (ch->flags & ATA_KNOWN_PRESENCE)) &&
486 ostat0 != 0xa5) {
487 stat0 = ATA_S_BUSY;
488 mask |= 0x01;
489 }
490
491 /* in some setups we dont want to test for a slave */
492 if (!(ch->flags & ATA_NO_SLAVE)) {
493 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_SLAVE));
494 DELAY(10);
495 ostat1 = ATA_IDX_INB(ch, ATA_STATUS);
496 if (((ostat1 & 0xf8) != 0xf8 || (ch->flags & ATA_KNOWN_PRESENCE)) &&
497 ostat1 != 0xa5) {
498 stat1 = ATA_S_BUSY;
499 mask |= 0x02;
500 }
501 }
502
503 if (bootverbose)
504 device_printf(dev, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n",
505 mask, ostat0, ostat1);
506
507 /* if nothing showed up there is no need to get any further */
508 /* XXX SOS is that too strong?, we just might lose devices here */
509 ch->devices = 0;
510 if (!mask)
511 return;
512
513 /* reset (both) devices on this channel */
514 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER));
515 DELAY(10);
516 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET);
517 ata_udelay(10000);
518 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS);
519 ata_udelay(100000);
520 ATA_IDX_INB(ch, ATA_ERROR);
521
522 /* wait for BUSY to go inactive */
523 for (timeout = 0; timeout < 310; timeout++) {
524 if ((mask & 0x01) && (stat0 & ATA_S_BUSY)) {
525 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_MASTER));
526 DELAY(10);
527 if (ch->flags & ATA_STATUS_IS_LONG)
528 stat0 = ATA_IDX_INL(ch, ATA_STATUS) & 0xff;
529 else
530 stat0 = ATA_IDX_INB(ch, ATA_STATUS);
531 err = ATA_IDX_INB(ch, ATA_ERROR);
532 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
533 msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
534 if (bootverbose)
535 device_printf(dev,
536 "stat0=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
537 stat0, err, lsb, msb);
538 if (stat0 == err && lsb == err && msb == err &&
539 timeout > (stat0 & ATA_S_BUSY ? 100 : 10))
540 mask &= ~0x01;
541 if (!(stat0 & ATA_S_BUSY)) {
542 if ((err & 0x7f) == ATA_E_ILI) {
543 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
544 ch->devices |= ATA_ATAPI_MASTER;
545 }
546 else if (lsb == 0 && msb == 0 && (stat0 & ATA_S_READY)) {
547 ch->devices |= ATA_ATA_MASTER;
548 }
549 }
550 else if ((stat0 & 0x0f) && err == lsb && err == msb) {
551 stat0 |= ATA_S_BUSY;
552 }
553 }
554 }
555
556 if ((mask & 0x02) && (stat1 & ATA_S_BUSY) &&
557 !((mask & 0x01) && (stat0 & ATA_S_BUSY))) {
558 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_SLAVE));
559 DELAY(10);
560 if (ch->flags & ATA_STATUS_IS_LONG)
561 stat1 = ATA_IDX_INL(ch, ATA_STATUS) & 0xff;
562 else
563 stat1 = ATA_IDX_INB(ch, ATA_STATUS);
564 err = ATA_IDX_INB(ch, ATA_ERROR);
565 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
566 msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
567 if (bootverbose)
568 device_printf(dev,
569 "stat1=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
570 stat1, err, lsb, msb);
571 if (stat1 == err && lsb == err && msb == err &&
572 timeout > (stat1 & ATA_S_BUSY ? 100 : 10))
573 mask &= ~0x02;
574 if (!(stat1 & ATA_S_BUSY)) {
575 if ((err & 0x7f) == ATA_E_ILI) {
576 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
577 ch->devices |= ATA_ATAPI_SLAVE;
578 }
579 else if (lsb == 0 && msb == 0 && (stat1 & ATA_S_READY)) {
580 ch->devices |= ATA_ATA_SLAVE;
581 }
582 }
583 else if ((stat1 & 0x0f) && err == lsb && err == msb) {
584 stat1 |= ATA_S_BUSY;
585 }
586 }
587 }
588
589 if ((ch->flags & ATA_KNOWN_PRESENCE) == 0 &&
590 timeout > ((mask == 0x03) ? 20 : 10)) {
591 if ((mask & 0x01) && stat0 == 0xff)
592 mask &= ~0x01;
593 if ((mask & 0x02) && stat1 == 0xff)
594 mask &= ~0x02;
595 }
596 if (((mask & 0x01) == 0 || !(stat0 & ATA_S_BUSY)) &&
597 ((mask & 0x02) == 0 || !(stat1 & ATA_S_BUSY)))
598 break;
599 ata_udelay(100000);
600 }
601
602 if (bootverbose)
603 device_printf(dev, "reset tp2 stat0=%02x stat1=%02x devices=0x%x\n",
604 stat0, stat1, ch->devices);
605 }
606
607 /* must be called with ATA channel locked and state_mtx held */
608 static int
ata_generic_status(device_t dev)609 ata_generic_status(device_t dev)
610 {
611 struct ata_channel *ch = device_get_softc(dev);
612
613 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
614 DELAY(100);
615 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY)
616 return 0;
617 }
618 return 1;
619 }
620
621 static int
ata_wait(struct ata_channel * ch,int unit,u_int8_t mask)622 ata_wait(struct ata_channel *ch, int unit, u_int8_t mask)
623 {
624 u_int8_t status;
625 int timeout = 0;
626
627 DELAY(1);
628
629 /* wait at max 1 second for device to get !BUSY */
630 while (timeout < 1000000) {
631 status = ATA_IDX_INB(ch, ATA_ALTSTAT);
632
633 /* if drive fails status, reselect the drive and try again */
634 if (status == 0xff) {
635 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(unit));
636 timeout += 1000;
637 DELAY(1000);
638 continue;
639 }
640
641 /* are we done ? */
642 if (!(status & ATA_S_BUSY))
643 break;
644
645 if (timeout > 1000) {
646 timeout += 1000;
647 DELAY(1000);
648 }
649 else {
650 timeout += 10;
651 DELAY(10);
652 }
653 }
654 if (timeout >= 1000000)
655 return -2;
656 if (!mask)
657 return (status & ATA_S_ERROR);
658
659 DELAY(1);
660
661 /* wait 50 msec for bits wanted */
662 timeout = 5000;
663 while (timeout--) {
664 status = ATA_IDX_INB(ch, ATA_ALTSTAT);
665 if ((status & mask) == mask)
666 return (status & ATA_S_ERROR);
667 DELAY(10);
668 }
669 return -3;
670 }
671
672 int
ata_generic_command(struct ata_request * request)673 ata_generic_command(struct ata_request *request)
674 {
675 struct ata_channel *ch = device_get_softc(request->parent);
676
677 /* select device */
678 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit));
679
680 /* ready to issue command ? */
681 if (ata_wait(ch, request->unit, 0) < 0) {
682 device_printf(request->parent, "timeout waiting to issue command\n");
683 request->flags |= ATA_R_TIMEOUT;
684 return (-1);
685 }
686
687 /* enable interrupt */
688 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
689
690 if (request->flags & ATA_R_ATAPI) {
691 int timeout = 5000;
692 int res;
693
694 /* issue packet command to controller */
695 if (request->flags & ATA_R_DMA) {
696 ATA_IDX_OUTB(ch, ATA_FEATURE, ATA_F_DMA);
697 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0);
698 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 0);
699 }
700 else {
701 ATA_IDX_OUTB(ch, ATA_FEATURE, 0);
702 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->transfersize);
703 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->transfersize >> 8);
704 }
705 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_PACKET_CMD);
706
707 /* command interrupt device ? just return and wait for interrupt */
708 if (request->flags & ATA_R_ATAPI_INTR)
709 return (0);
710
711 /* command processed ? */
712 res = ata_wait(ch, request->unit, 0);
713 if (res != 0) {
714 if (res < 0) {
715 device_printf(request->parent,
716 "timeout waiting for PACKET command\n");
717 request->flags |= ATA_R_TIMEOUT;
718 }
719 return (-1);
720 }
721 /* wait for ready to write ATAPI command block */
722 while (timeout--) {
723 int reason = ATA_IDX_INB(ch, ATA_IREASON);
724 int status = ATA_IDX_INB(ch, ATA_STATUS);
725
726 if (((reason & (ATA_I_CMD | ATA_I_IN)) |
727 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT)
728 break;
729 DELAY(20);
730 }
731 if (timeout <= 0) {
732 device_printf(request->parent,
733 "timeout waiting for ATAPI ready\n");
734 request->flags |= ATA_R_TIMEOUT;
735 return (-1);
736 }
737
738 /* this seems to be needed for some (slow) devices */
739 DELAY(10);
740
741 /* output command block */
742 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
743 (request->flags & ATA_R_ATAPI16) ? 8 : 6);
744 }
745 else {
746 ch->hw.tf_write(request);
747
748 /* issue command to controller */
749 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command);
750 }
751 return (0);
752 }
753
754 static void
ata_tf_read(struct ata_request * request)755 ata_tf_read(struct ata_request *request)
756 {
757 struct ata_channel *ch = device_get_softc(request->parent);
758
759 if (request->flags & ATA_R_48BIT) {
760 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT | ATA_A_HOB);
761 request->u.ata.count = (ATA_IDX_INB(ch, ATA_COUNT) << 8);
762 request->u.ata.lba =
763 ((u_int64_t)(ATA_IDX_INB(ch, ATA_SECTOR)) << 24) |
764 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_LSB)) << 32) |
765 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_MSB)) << 40);
766
767 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
768 request->u.ata.count |= ATA_IDX_INB(ch, ATA_COUNT);
769 request->u.ata.lba |=
770 (ATA_IDX_INB(ch, ATA_SECTOR) |
771 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
772 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16));
773 }
774 else {
775 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT);
776 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) |
777 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
778 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) |
779 ((ATA_IDX_INB(ch, ATA_DRIVE) & 0xf) << 24);
780 }
781 }
782
783 static void
ata_tf_write(struct ata_request * request)784 ata_tf_write(struct ata_request *request)
785 {
786 struct ata_channel *ch = device_get_softc(request->parent);
787 #ifndef ATA_CAM
788 struct ata_device *atadev = device_get_softc(request->dev);
789 #endif
790
791 if (request->flags & ATA_R_48BIT) {
792 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature >> 8);
793 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
794 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count >> 8);
795 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
796 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba >> 24);
797 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
798 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 32);
799 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
800 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 40);
801 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
802 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit));
803 }
804 else {
805 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
806 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
807 #ifndef ATA_CAM
808 if (atadev->flags & ATA_D_USE_CHS) {
809 int heads, sectors;
810
811 if (atadev->param.atavalid & ATA_FLAG_54_58) {
812 heads = atadev->param.current_heads;
813 sectors = atadev->param.current_sectors;
814 }
815 else {
816 heads = atadev->param.heads;
817 sectors = atadev->param.sectors;
818 }
819
820 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1);
821 ATA_IDX_OUTB(ch, ATA_CYL_LSB,
822 (request->u.ata.lba / (sectors * heads)));
823 ATA_IDX_OUTB(ch, ATA_CYL_MSB,
824 (request->u.ata.lba / (sectors * heads)) >> 8);
825 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit) |
826 (((request->u.ata.lba% (sectors * heads)) /
827 sectors) & 0xf));
828 }
829 else {
830 #endif
831 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
832 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
833 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
834 ATA_IDX_OUTB(ch, ATA_DRIVE,
835 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) |
836 ((request->u.ata.lba >> 24) & 0x0f));
837 #ifndef ATA_CAM
838 }
839 #endif
840 }
841 }
842
843 static void
ata_pio_read(struct ata_request * request,int length)844 ata_pio_read(struct ata_request *request, int length)
845 {
846 struct ata_channel *ch = device_get_softc(request->parent);
847 uint8_t *addr;
848 int size = min(request->transfersize, length);
849 int resid;
850 uint8_t buf[2] __aligned(sizeof(int16_t));
851 #ifndef __NO_STRICT_ALIGNMENT
852 int i;
853 #endif
854
855 addr = (uint8_t *)request->data + request->donecount;
856 if (__predict_false(ch->flags & ATA_USE_16BIT ||
857 (size % sizeof(int32_t)) || ((uintptr_t)addr % sizeof(int32_t)))) {
858 #ifndef __NO_STRICT_ALIGNMENT
859 if (__predict_false((uintptr_t)addr % sizeof(int16_t))) {
860 for (i = 0, resid = size & ~1; resid > 0; resid -=
861 sizeof(int16_t)) {
862 *(uint16_t *)&buf = ATA_IDX_INW_STRM(ch, ATA_DATA);
863 addr[i++] = buf[0];
864 addr[i++] = buf[1];
865 }
866 } else
867 #endif
868 ATA_IDX_INSW_STRM(ch, ATA_DATA, (void*)addr, size /
869 sizeof(int16_t));
870 if (size & 1) {
871 *(uint16_t *)&buf = ATA_IDX_INW_STRM(ch, ATA_DATA);
872 (addr + (size & ~1))[0] = buf[0];
873 }
874 } else
875 ATA_IDX_INSL_STRM(ch, ATA_DATA, (void*)addr, size / sizeof(int32_t));
876
877 if (request->transfersize < length) {
878 device_printf(request->parent, "WARNING - %s read data overrun %d>%d\n",
879 ata_cmd2str(request), length, request->transfersize);
880 for (resid = request->transfersize + (size & 1); resid < length;
881 resid += sizeof(int16_t))
882 ATA_IDX_INW(ch, ATA_DATA);
883 }
884 }
885
886 static void
ata_pio_write(struct ata_request * request,int length)887 ata_pio_write(struct ata_request *request, int length)
888 {
889 struct ata_channel *ch = device_get_softc(request->parent);
890 uint8_t *addr;
891 int size = min(request->transfersize, length);
892 int resid;
893 uint8_t buf[2] __aligned(sizeof(int16_t));
894 #ifndef __NO_STRICT_ALIGNMENT
895 int i;
896 #endif
897
898 size = min(request->transfersize, length);
899 addr = (uint8_t *)request->data + request->donecount;
900 if (__predict_false(ch->flags & ATA_USE_16BIT ||
901 (size % sizeof(int32_t)) || ((uintptr_t)addr % sizeof(int32_t)))) {
902 #ifndef __NO_STRICT_ALIGNMENT
903 if (__predict_false((uintptr_t)addr % sizeof(int16_t))) {
904 for (i = 0, resid = size & ~1; resid > 0; resid -=
905 sizeof(int16_t)) {
906 buf[0] = addr[i++];
907 buf[1] = addr[i++];
908 ATA_IDX_OUTW_STRM(ch, ATA_DATA, *(uint16_t *)&buf);
909 }
910 } else
911 #endif
912 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (void*)addr, size /
913 sizeof(int16_t));
914 if (size & 1) {
915 buf[0] = (addr + (size & ~1))[0];
916 ATA_IDX_OUTW_STRM(ch, ATA_DATA, *(uint16_t *)&buf);
917 }
918 } else
919 ATA_IDX_OUTSL_STRM(ch, ATA_DATA, (void*)addr, size / sizeof(int32_t));
920
921 if (request->transfersize < length) {
922 device_printf(request->parent, "WARNING - %s write data underrun %d>%d\n",
923 ata_cmd2str(request), length, request->transfersize);
924 for (resid = request->transfersize + (size & 1); resid < length;
925 resid += sizeof(int16_t))
926 ATA_IDX_OUTW(ch, ATA_DATA, 0);
927 }
928 }
929