1 /*- 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: stable/9/sys/dev/ed/if_edvar.h 264943 2014-04-25 21:32:38Z marius $ 28 */ 29 30 #ifndef SYS_DEV_ED_IF_EDVAR_H 31 #define SYS_DEV_ED_IF_EDVAR_H 32 33 #include <dev/mii/mii_bitbang.h> 34 35 /* 36 * ed_softc: per line info and status 37 */ 38 struct ed_softc { 39 struct ifnet *ifp; 40 struct ifmedia ifmedia; /* Media info */ 41 device_t dev; 42 struct mtx sc_mtx; 43 44 char *type_str; /* pointer to type string */ 45 u_char vendor; /* interface vendor */ 46 u_char type; /* interface type code */ 47 u_char chip_type; /* the type of chip (one of ED_CHIP_TYPE_*) */ 48 u_char isa16bit; /* width of access to card 0=8 or 1=16 */ 49 u_char mem_shared; /* NIC memory is shared with host */ 50 u_char xmit_busy; /* transmitter is busy */ 51 u_char enaddr[6]; 52 53 int port_used; /* nonzero if ports used */ 54 struct resource* port_res; /* resource for port range */ 55 struct resource* port_res2; /* resource for port range */ 56 bus_space_tag_t port_bst; 57 bus_space_handle_t port_bsh; 58 int mem_used; /* nonzero if memory used */ 59 struct resource* mem_res; /* resource for memory range */ 60 bus_space_tag_t mem_bst; 61 bus_space_handle_t mem_bsh; 62 struct resource* irq_res; /* resource for irq */ 63 void* irq_handle; /* handle for irq handler */ 64 int (*sc_media_ioctl)(struct ed_softc *sc, struct ifreq *ifr, 65 u_long command); 66 void (*sc_mediachg)(struct ed_softc *); 67 device_t miibus; /* MII bus for cards with MII. */ 68 mii_bitbang_ops_t mii_bitbang_ops; 69 struct callout tick_ch; 70 void (*sc_tick)(struct ed_softc *); 71 void (*readmem)(struct ed_softc *sc, bus_size_t src, uint8_t *dst, 72 uint16_t amount); 73 u_short (*sc_write_mbufs)(struct ed_softc *, struct mbuf *, bus_size_t); 74 75 int tx_timer; 76 int nic_offset; /* NIC (DS8390) I/O bus address offset */ 77 int asic_offset; /* ASIC I/O bus address offset */ 78 79 /* 80 * The following 'proto' variable is part of a work-around for 8013EBT asics 81 * being write-only. It's sort of a prototype/shadow of the real thing. 82 */ 83 u_char wd_laar_proto; 84 u_char cr_proto; 85 86 /* 87 * HP PC LAN PLUS card support. 88 */ 89 90 u_short hpp_options; /* flags controlling behaviour of the HP card */ 91 u_short hpp_id; /* software revision and other fields */ 92 caddr_t hpp_mem_start; /* Memory-mapped IO register address */ 93 94 bus_size_t mem_start; /* NIC memory start address */ 95 bus_size_t mem_end; /* NIC memory end address */ 96 uint32_t mem_size; /* total NIC memory size */ 97 bus_size_t mem_ring; /* start of RX ring-buffer (in NIC mem) */ 98 99 u_char txb_cnt; /* number of transmit buffers */ 100 u_char txb_inuse; /* number of TX buffers currently in-use */ 101 102 u_char txb_new; /* pointer to where new buffer will be added */ 103 u_char txb_next_tx; /* pointer to next buffer ready to xmit */ 104 u_short txb_len[8]; /* buffered xmit buffer lengths */ 105 u_char tx_page_start; /* first page of TX buffer area */ 106 u_char rec_page_start; /* first page of RX ring-buffer */ 107 u_char rec_page_stop; /* last page of RX ring-buffer */ 108 u_char next_packet; /* pointer to next unread RX packet */ 109 u_int tx_mem; /* Total amount of RAM for tx */ 110 u_int rx_mem; /* Total amount of RAM for rx */ 111 struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */ 112 }; 113 114 #define ed_nic_barrier(sc, port, length, flags) \ 115 bus_space_barrier(sc->port_bst, sc->port_bsh, \ 116 (sc)->nic_offset + (port), (length), (flags)) 117 118 #define ed_nic_inb(sc, port) \ 119 bus_space_read_1(sc->port_bst, sc->port_bsh, (sc)->nic_offset + (port)) 120 121 #define ed_nic_outb(sc, port, value) \ 122 bus_space_write_1(sc->port_bst, sc->port_bsh, \ 123 (sc)->nic_offset + (port), (value)) 124 125 #define ed_nic_inw(sc, port) \ 126 bus_space_read_2(sc->port_bst, sc->port_bsh, (sc)->nic_offset + (port)) 127 128 #define ed_nic_outw(sc, port, value) \ 129 bus_space_write_2(sc->port_bst, sc->port_bsh, \ 130 (sc)->nic_offset + (port), (value)) 131 132 #define ed_nic_insb(sc, port, addr, count) \ 133 bus_space_read_multi_1(sc->port_bst, sc->port_bsh, \ 134 (sc)->nic_offset + (port), (addr), (count)) 135 136 #define ed_nic_outsb(sc, port, addr, count) \ 137 bus_space_write_multi_1(sc->port_bst, sc->port_bsh, \ 138 (sc)->nic_offset + (port), (addr), (count)) 139 140 #define ed_nic_insw(sc, port, addr, count) \ 141 bus_space_read_multi_2(sc->port_bst, sc->port_bsh, \ 142 (sc)->nic_offset + (port), (uint16_t *)(addr), (count)) 143 144 #define ed_nic_outsw(sc, port, addr, count) \ 145 bus_space_write_multi_2(sc->port_bst, sc->port_bsh, \ 146 (sc)->nic_offset + (port), (uint16_t *)(addr), (count)) 147 148 #define ed_nic_insl(sc, port, addr, count) \ 149 bus_space_read_multi_4(sc->port_bst, sc->port_bsh, \ 150 (sc)->nic_offset + (port), (uint32_t *)(addr), (count)) 151 152 #define ed_nic_outsl(sc, port, addr, count) \ 153 bus_space_write_multi_4(sc->port_bst, sc->port_bsh, \ 154 (sc)->nic_offset + (port), (uint32_t *)(addr), (count)) 155 156 #define ed_asic_barrier(sc, port, length, flags) \ 157 bus_space_barrier(sc->port_bst, sc->port_bsh, \ 158 (sc)->asic_offset + (port), (length), (flags)) 159 160 #define ed_asic_inb(sc, port) \ 161 bus_space_read_1(sc->port_bst, sc->port_bsh, \ 162 (sc)->asic_offset + (port)) 163 164 #define ed_asic_outb(sc, port, value) \ 165 bus_space_write_1(sc->port_bst, sc->port_bsh, \ 166 (sc)->asic_offset + (port), (value)) 167 168 #define ed_asic_inw(sc, port) \ 169 bus_space_read_2(sc->port_bst, sc->port_bsh, \ 170 (sc)->asic_offset + (port)) 171 172 #define ed_asic_outw(sc, port, value) \ 173 bus_space_write_2(sc->port_bst, sc->port_bsh, \ 174 (sc)->asic_offset + (port), (value)) 175 176 #define ed_asic_insb(sc, port, addr, count) \ 177 bus_space_read_multi_1(sc->port_bst, sc->port_bsh, \ 178 (sc)->asic_offset + (port), (addr), (count)) 179 180 #define ed_asic_outsb(sc, port, addr, count) \ 181 bus_space_write_multi_1(sc->port_bst, sc->port_bsh, \ 182 (sc)->asic_offset + (port), (addr), (count)) 183 184 #define ed_asic_insw(sc, port, addr, count) \ 185 bus_space_read_multi_2(sc->port_bst, sc->port_bsh, \ 186 (sc)->asic_offset + (port), (uint16_t *)(addr), (count)) 187 188 #define ed_asic_outsw(sc, port, addr, count) \ 189 bus_space_write_multi_2(sc->port_bst, sc->port_bsh, \ 190 (sc)->asic_offset + (port), (uint16_t *)(addr), (count)) 191 192 #define ed_asic_insl(sc, port, addr, count) \ 193 bus_space_read_multi_4(sc->port_bst, sc->port_bsh, \ 194 (sc)->asic_offset + (port), (uint32_t *)(addr), (count)) 195 196 #define ed_asic_outsl(sc, port, addr, count) \ 197 bus_space_write_multi_4(sc->port_bst, sc->port_bsh, \ 198 (sc)->asic_offset + (port), (uint32_t *)(addr), (count)) 199 200 void ed_release_resources(device_t); 201 int ed_alloc_port(device_t, int, int); 202 int ed_alloc_memory(device_t, int, int); 203 int ed_alloc_irq(device_t, int, int); 204 205 int ed_probe_generic8390(struct ed_softc *); 206 int ed_probe_WD80x3(device_t, int, int); 207 int ed_probe_WD80x3_generic(device_t, int, uint16_t *[]); 208 int ed_probe_RTL80x9(device_t, int, int); 209 #ifdef ED_3C503 210 int ed_probe_3Com(device_t, int, int); 211 #endif 212 #ifdef ED_SIC 213 int ed_probe_SIC(device_t, int, int); 214 #endif 215 int ed_probe_Novell_generic(device_t, int); 216 int ed_probe_Novell(device_t, int, int); 217 void ed_Novell_read_mac(struct ed_softc *); 218 #ifdef ED_HPP 219 int ed_probe_HP_pclanp(device_t, int, int); 220 #endif 221 222 int ed_attach(device_t); 223 int ed_detach(device_t); 224 int ed_clear_memory(device_t); 225 int ed_isa_mem_ok(device_t, u_long, u_int); /* XXX isa specific */ 226 void ed_stop(struct ed_softc *); 227 void ed_shmem_readmem16(struct ed_softc *, bus_size_t, uint8_t *, uint16_t); 228 void ed_shmem_readmem8(struct ed_softc *, bus_size_t, uint8_t *, uint16_t); 229 u_short ed_shmem_write_mbufs(struct ed_softc *, struct mbuf *, bus_size_t); 230 void ed_pio_readmem(struct ed_softc *, bus_size_t, uint8_t *, uint16_t); 231 void ed_pio_writemem(struct ed_softc *, uint8_t *, uint16_t, uint16_t); 232 u_short ed_pio_write_mbufs(struct ed_softc *, struct mbuf *, bus_size_t); 233 234 void ed_disable_16bit_access(struct ed_softc *); 235 void ed_enable_16bit_access(struct ed_softc *); 236 237 void ed_gen_ifmedia_init(struct ed_softc *); 238 239 driver_intr_t edintr; 240 241 extern devclass_t ed_devclass; 242 243 244 /* 245 * Vendor types 246 */ 247 #define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */ 248 #define ED_VENDOR_3COM 0x01 /* 3Com */ 249 #define ED_VENDOR_NOVELL 0x02 /* Novell */ 250 #define ED_VENDOR_HP 0x03 /* Hewlett Packard */ 251 #define ED_VENDOR_SIC 0x04 /* Allied-Telesis SIC */ 252 253 /* 254 * Configure time flags 255 */ 256 /* 257 * this sets the default for enabling/disabling the transceiver 258 */ 259 #define ED_FLAGS_DISABLE_TRANCEIVER 0x0001 260 261 /* 262 * This forces the board to be used in 8/16bit mode even if it 263 * autoconfigs differently 264 */ 265 #define ED_FLAGS_FORCE_8BIT_MODE 0x0002 266 #define ED_FLAGS_FORCE_16BIT_MODE 0x0004 267 268 /* 269 * This disables the use of double transmit buffers. 270 */ 271 #define ED_FLAGS_NO_MULTI_BUFFERING 0x0008 272 273 /* 274 * This forces all operations with the NIC memory to use Programmed 275 * I/O (i.e. not via shared memory) 276 */ 277 #define ED_FLAGS_FORCE_PIO 0x0010 278 279 /* 280 * This forces a PC Card, and disables ISA memory range checks 281 */ 282 #define ED_FLAGS_PCCARD 0x0020 283 284 /* 285 * These are flags describing the chip type. 286 */ 287 #define ED_FLAGS_TOSH_ETHER 0x10000 288 #define ED_FLAGS_GWETHER 0x20000 289 290 #define ED_FLAGS_GETTYPE(flg) ((flg) & 0xff0000) 291 292 #define ED_MUTEX(_sc) (&(_sc)->sc_mtx) 293 #define ED_LOCK(_sc) mtx_lock(ED_MUTEX(_sc)) 294 #define ED_UNLOCK(_sc) mtx_unlock(ED_MUTEX(_sc)) 295 #define ED_LOCK_INIT(_sc) \ 296 mtx_init(ED_MUTEX(_sc), device_get_nameunit(_sc->dev), \ 297 MTX_NETWORK_LOCK, MTX_DEF) 298 #define ED_LOCK_DESTROY(_sc) mtx_destroy(ED_MUTEX(_sc)); 299 #define ED_ASSERT_LOCKED(_sc) mtx_assert(ED_MUTEX(_sc), MA_OWNED); 300 #define ED_ASSERT_UNLOCKED(_sc) mtx_assert(ED_MUTEX(_sc), MA_NOTOWNED); 301 302 #endif /* SYS_DEV_ED_IF_EDVAR_H */ 303