1 /*
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "opt_ah.h"
18
19 #include "ah.h"
20 #include "ah_desc.h"
21 #include "ah_internal.h"
22
23 #include "ar9300/ar9300desc.h"
24 #include "ar9300/ar9300.h"
25 #include "ar9300/ar9300reg.h"
26 #include "ar9300/ar9300phy.h"
27 #include "ah_devid.h"
28
29 #if AH_BYTE_ORDER == AH_BIG_ENDIAN
30 static void ar9300_swap_tx_desc(void *ds);
31 #endif
32
33 void
ar9300_tx_req_intr_desc(struct ath_hal * ah,void * ds)34 ar9300_tx_req_intr_desc(struct ath_hal *ah, void *ds)
35 {
36 HALDEBUG(ah, HAL_DEBUG_INTERRUPT,
37 "%s:Desc Interrupt not supported\n", __func__);
38 }
39
40 static inline u_int16_t
ar9300_calc_ptr_chk_sum(struct ar9300_txc * ads)41 ar9300_calc_ptr_chk_sum(struct ar9300_txc *ads)
42 {
43 u_int checksum;
44 u_int16_t ptrchecksum;
45
46 /* checksum = __bswap32(ads->ds_info) + ads->ds_link */
47 checksum = ads->ds_info + ads->ds_link
48 + ads->ds_data0 + ads->ds_ctl3
49 + ads->ds_data1 + ads->ds_ctl5
50 + ads->ds_data2 + ads->ds_ctl7
51 + ads->ds_data3 + ads->ds_ctl9;
52
53 ptrchecksum = ((checksum & 0xffff) + (checksum >> 16)) & AR_tx_ptr_chk_sum;
54 return ptrchecksum;
55 }
56
57 HAL_BOOL
ar9300_fill_tx_desc(struct ath_hal * ah,void * ds,HAL_DMA_ADDR * buf_addr,u_int32_t * seg_len,u_int desc_id,u_int qcu,HAL_KEY_TYPE key_type,HAL_BOOL first_seg,HAL_BOOL last_seg,const void * ds0)58 ar9300_fill_tx_desc(
59 struct ath_hal *ah,
60 void *ds,
61 HAL_DMA_ADDR *buf_addr,
62 u_int32_t *seg_len,
63 u_int desc_id,
64 u_int qcu,
65 HAL_KEY_TYPE key_type,
66 HAL_BOOL first_seg,
67 HAL_BOOL last_seg,
68 const void *ds0)
69 {
70 struct ar9300_txc *ads = AR9300TXC(ds);
71
72 /* Fill TXC info field */
73 ads->ds_info = TXC_INFO(qcu);
74
75 /* Set the buffer addresses */
76 ads->ds_data0 = buf_addr[0];
77 ads->ds_data1 = buf_addr[1];
78 ads->ds_data2 = buf_addr[2];
79 ads->ds_data3 = buf_addr[3];
80
81 /* Set the buffer lengths */
82 ads->ds_ctl3 = (seg_len[0] << AR_buf_len_S) & AR_buf_len;
83 ads->ds_ctl5 = (seg_len[1] << AR_buf_len_S) & AR_buf_len;
84 ads->ds_ctl7 = (seg_len[2] << AR_buf_len_S) & AR_buf_len;
85 ads->ds_ctl9 = (seg_len[3] << AR_buf_len_S) & AR_buf_len;
86
87 /* Fill in pointer checksum and descriptor id */
88 ads->ds_ctl10 = (desc_id << AR_tx_desc_id_S) | ar9300_calc_ptr_chk_sum(ads);
89
90 if (first_seg) {
91 /*
92 * First descriptor, don't clobber xmit control data
93 * setup by ar9300_set_11n_tx_desc.
94 *
95 * Note: AR_encr_type is already setup in the first descriptor by
96 * set_11n_tx_desc().
97 */
98 ads->ds_ctl12 |= (last_seg ? 0 : AR_tx_more);
99 } else if (last_seg) { /* !first_seg && last_seg */
100 /*
101 * Last descriptor in a multi-descriptor frame,
102 * copy the multi-rate transmit parameters from
103 * the first frame for processing on completion.
104 */
105 ads->ds_ctl11 = 0;
106 ads->ds_ctl12 = 0;
107 #ifdef AH_NEED_DESC_SWAP
108 ads->ds_ctl13 = __bswap32(AR9300TXC_CONST(ds0)->ds_ctl13);
109 ads->ds_ctl14 = __bswap32(AR9300TXC_CONST(ds0)->ds_ctl14);
110 ads->ds_ctl17 = __bswap32(SM(key_type, AR_encr_type));
111 #else
112 ads->ds_ctl13 = AR9300TXC_CONST(ds0)->ds_ctl13;
113 ads->ds_ctl14 = AR9300TXC_CONST(ds0)->ds_ctl14;
114 ads->ds_ctl17 = SM(key_type, AR_encr_type);
115 #endif
116 } else { /* !first_seg && !last_seg */
117 /*
118 * XXX Intermediate descriptor in a multi-descriptor frame.
119 */
120 ads->ds_ctl11 = 0;
121 ads->ds_ctl12 = AR_tx_more;
122 ads->ds_ctl13 = 0;
123 ads->ds_ctl14 = 0;
124 ads->ds_ctl17 = SM(key_type, AR_encr_type);
125 }
126
127 return AH_TRUE;
128 }
129
130 void
ar9300_set_desc_link(struct ath_hal * ah,void * ds,u_int32_t link)131 ar9300_set_desc_link(struct ath_hal *ah, void *ds, u_int32_t link)
132 {
133 struct ar9300_txc *ads = AR9300TXC(ds);
134
135 ads->ds_link = link;
136
137 /* TODO - checksum is calculated twice for subframes
138 * Once in filldesc and again when linked. Need to fix.
139 */
140 /* Fill in pointer checksum. Preserve descriptor id */
141 ads->ds_ctl10 &= ~AR_tx_ptr_chk_sum;
142 ads->ds_ctl10 |= ar9300_calc_ptr_chk_sum(ads);
143 }
144
145 void
ar9300_get_desc_link_ptr(struct ath_hal * ah,void * ds,u_int32_t ** link)146 ar9300_get_desc_link_ptr(struct ath_hal *ah, void *ds, u_int32_t **link)
147 {
148 struct ar9300_txc *ads = AR9300TXC(ds);
149
150 *link = &ads->ds_link;
151 }
152
153 void
ar9300_clear_tx_desc_status(struct ath_hal * ah,void * ds)154 ar9300_clear_tx_desc_status(struct ath_hal *ah, void *ds)
155 {
156 struct ar9300_txs *ads = AR9300TXS(ds);
157 ads->status1 = ads->status2 = 0;
158 ads->status3 = ads->status4 = 0;
159 ads->status5 = ads->status6 = 0;
160 ads->status7 = ads->status8 = 0;
161 }
162
163 #ifdef ATH_SWRETRY
164 void
ar9300_clear_dest_mask(struct ath_hal * ah,void * ds)165 ar9300_clear_dest_mask(struct ath_hal *ah, void *ds)
166 {
167 struct ar9300_txc *ads = AR9300TXC(ds);
168 ads->ds_ctl11 |= AR_clr_dest_mask;
169 }
170 #endif
171
172 #if AH_BYTE_ORDER == AH_BIG_ENDIAN
173 /* XXX what words need swapping */
174 /* Swap transmit descriptor */
175 static __inline void
ar9300_swap_tx_desc(void * dsp)176 ar9300_swap_tx_desc(void *dsp)
177 {
178 struct ar9300_txs *ds = (struct ar9300_txs *)dsp;
179
180 ds->ds_info = __bswap32(ds->ds_info);
181 ds->status1 = __bswap32(ds->status1);
182 ds->status2 = __bswap32(ds->status2);
183 ds->status3 = __bswap32(ds->status3);
184 ds->status4 = __bswap32(ds->status4);
185 ds->status5 = __bswap32(ds->status5);
186 ds->status6 = __bswap32(ds->status6);
187 ds->status7 = __bswap32(ds->status7);
188 ds->status8 = __bswap32(ds->status8);
189 }
190 #endif
191
192
193 /*
194 * Extract the transmit rate code.
195 */
196 void
ar9300_get_tx_rate_code(struct ath_hal * ah,void * ds,struct ath_tx_status * ts)197 ar9300_get_tx_rate_code(struct ath_hal *ah, void *ds, struct ath_tx_status *ts)
198 {
199 struct ar9300_txc *ads = AR9300TXC(ds);
200
201 switch (ts->ts_finaltsi) {
202 case 0:
203 ts->ts_rate = MS(ads->ds_ctl14, AR_xmit_rate0);
204 break;
205 case 1:
206 ts->ts_rate = MS(ads->ds_ctl14, AR_xmit_rate1);
207 break;
208 case 2:
209 ts->ts_rate = MS(ads->ds_ctl14, AR_xmit_rate2);
210 break;
211 case 3:
212 ts->ts_rate = MS(ads->ds_ctl14, AR_xmit_rate3);
213 break;
214 }
215
216 ar9300_set_selfgenrate_limit(ah, ts->ts_rate);
217 }
218
219 /*
220 * Get TX Status descriptor contents.
221 */
222 void
ar9300_get_raw_tx_desc(struct ath_hal * ah,u_int32_t * txstatus)223 ar9300_get_raw_tx_desc(struct ath_hal *ah, u_int32_t *txstatus)
224 {
225 struct ath_hal_9300 *ahp = AH9300(ah);
226 struct ar9300_txs *ads;
227
228 ads = &ahp->ts_ring[ahp->ts_tail];
229
230 OS_MEMCPY(txstatus, ads, sizeof(struct ar9300_txs));
231 }
232
233 /*
234 * Processing of HW TX descriptor.
235 */
236 HAL_STATUS
ar9300_proc_tx_desc(struct ath_hal * ah,void * txstatus)237 ar9300_proc_tx_desc(struct ath_hal *ah, void *txstatus)
238 {
239 struct ath_hal_9300 *ahp = AH9300(ah);
240 struct ar9300_txs *ads;
241 struct ath_tx_status *ts = (struct ath_tx_status *)txstatus;
242 u_int32_t dsinfo;
243
244 ads = &ahp->ts_ring[ahp->ts_tail];
245
246 if ((ads->status8 & AR_tx_done) == 0) {
247 return HAL_EINPROGRESS;
248 }
249
250 /*
251 * Sanity check
252 */
253
254 #if 0
255 ath_hal_printf(ah,
256 "CHH: tail=%d\n", ahp->ts_tail);
257 ath_hal_printf(ah,
258 "CHH: ds_info 0x%x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
259 ads->ds_info,
260 ads->status1,
261 ads->status2,
262 ads->status3,
263 ads->status4,
264 ads->status5,
265 ads->status6,
266 ads->status7,
267 ads->status8);
268 #endif
269
270
271 /* Increment the tail to point to the next status element. */
272 ahp->ts_tail = (ahp->ts_tail + 1) & (ahp->ts_size-1);
273
274 /*
275 ** For big endian systems, ds_info is not swapped as the other
276 ** registers are. Ensure we use the bswap32 version (which is
277 ** defined to "nothing" in little endian systems
278 */
279
280 dsinfo = ads->ds_info;
281
282 if ((MS(dsinfo, AR_desc_id) != ATHEROS_VENDOR_ID) ||
283 (MS(dsinfo, AR_tx_rx_desc) != 1))
284 {
285 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "%s: Tx Descriptor error %x\n",
286 __func__, dsinfo);
287 HALASSERT(0);
288 /* Zero out the status for reuse */
289 OS_MEMZERO(ads, sizeof(struct ar9300_txs));
290 return HAL_EIO;
291 }
292
293 /* Update software copies of the HW status */
294 ts->ts_queue_id = MS(dsinfo, AR_tx_qcu_num);
295 ts->ts_desc_id = MS(ads->status1, AR_tx_desc_id);
296 ts->ts_seqnum = MS(ads->status8, AR_seq_num);
297 ts->ts_tstamp = ads->status4;
298 ts->ts_status = 0;
299 ts->ts_flags = 0;
300
301 if (ads->status3 & AR_excessive_retries) {
302 ts->ts_status |= HAL_TXERR_XRETRY;
303 }
304 if (ads->status3 & AR_filtered) {
305 ts->ts_status |= HAL_TXERR_FILT;
306 }
307 if (ads->status3 & AR_fifounderrun) {
308 ts->ts_status |= HAL_TXERR_FIFO;
309 ar9300_update_tx_trig_level(ah, AH_TRUE);
310 }
311 if (ads->status8 & AR_tx_op_exceeded) {
312 ts->ts_status |= HAL_TXERR_XTXOP;
313 }
314 if (ads->status3 & AR_tx_timer_expired) {
315 ts->ts_status |= HAL_TXERR_TIMER_EXPIRED;
316 }
317 if (ads->status3 & AR_desc_cfg_err) {
318 ts->ts_flags |= HAL_TX_DESC_CFG_ERR;
319 }
320 if (ads->status3 & AR_tx_data_underrun) {
321 ts->ts_flags |= HAL_TX_DATA_UNDERRUN;
322 ar9300_update_tx_trig_level(ah, AH_TRUE);
323 }
324 if (ads->status3 & AR_tx_delim_underrun) {
325 ts->ts_flags |= HAL_TX_DELIM_UNDERRUN;
326 ar9300_update_tx_trig_level(ah, AH_TRUE);
327 }
328 if (ads->status2 & AR_tx_ba_status) {
329 ts->ts_flags |= HAL_TX_BA;
330 ts->ts_ba_low = ads->status5;
331 ts->ts_ba_high = ads->status6;
332 }
333
334 /*
335 * Extract the transmit rate.
336 */
337 ts->ts_finaltsi = MS(ads->status8, AR_final_tx_idx);
338
339 ts->ts_rssi = MS(ads->status7, AR_tx_rssi_combined);
340 ts->ts_rssi_ctl[0] = MS(ads->status2, AR_tx_rssi_ant00);
341 ts->ts_rssi_ctl[1] = MS(ads->status2, AR_tx_rssi_ant01);
342 ts->ts_rssi_ctl[2] = MS(ads->status2, AR_tx_rssi_ant02);
343 ts->ts_rssi_ext[0] = MS(ads->status7, AR_tx_rssi_ant10);
344 ts->ts_rssi_ext[1] = MS(ads->status7, AR_tx_rssi_ant11);
345 ts->ts_rssi_ext[2] = MS(ads->status7, AR_tx_rssi_ant12);
346 ts->ts_shortretry = MS(ads->status3, AR_rts_fail_cnt);
347 ts->ts_longretry = MS(ads->status3, AR_data_fail_cnt);
348 ts->ts_virtcol = MS(ads->status3, AR_virt_retry_cnt);
349 ts->ts_antenna = 0;
350
351 /* extract TID from block ack */
352 ts->ts_tid = MS(ads->status8, AR_tx_tid);
353
354 /* Zero out the status for reuse */
355 OS_MEMZERO(ads, sizeof(struct ar9300_txs));
356
357 return HAL_OK;
358 }
359
360 /*
361 * Calculate air time of a transmit packet
362 * if comp_wastedt is 1, calculate air time only for failed subframes
363 * this is required for VOW_DCS ( dynamic channel selection )
364 */
365 u_int32_t
ar9300_calc_tx_airtime(struct ath_hal * ah,void * ds,struct ath_tx_status * ts,HAL_BOOL comp_wastedt,u_int8_t nbad,u_int8_t nframes)366 ar9300_calc_tx_airtime(struct ath_hal *ah, void *ds, struct ath_tx_status *ts,
367 HAL_BOOL comp_wastedt, u_int8_t nbad, u_int8_t nframes )
368 {
369 struct ar9300_txc *ads = AR9300TXC(ds);
370 int finalindex_tries;
371 u_int32_t airtime, lastrate_dur;
372
373
374 /*
375 * Number of attempts made on the final index
376 * Note: If no BA was recv, then the data_fail_cnt is the number of tries
377 * made on the final index. If BA was recv, then add 1 to account for the
378 * successful attempt.
379 */
380 if ( !comp_wastedt ){
381 finalindex_tries = ts->ts_longretry + (ts->ts_flags & HAL_TX_BA)? 1 : 0;
382 } else {
383 finalindex_tries = ts->ts_longretry ;
384 }
385
386 /*
387 * Calculate time of transmit on air for packet including retries
388 * at different rates.
389 */
390 switch (ts->ts_finaltsi) {
391 case 0:
392 lastrate_dur = MS(ads->ds_ctl15, AR_packet_dur0);
393 airtime = (lastrate_dur * finalindex_tries);
394 break;
395 case 1:
396 lastrate_dur = MS(ads->ds_ctl15, AR_packet_dur1);
397 airtime = (lastrate_dur * finalindex_tries) +
398 (MS(ads->ds_ctl13, AR_xmit_data_tries0) *
399 MS(ads->ds_ctl15, AR_packet_dur0));
400 break;
401 case 2:
402 lastrate_dur = MS(ads->ds_ctl16, AR_packet_dur2);
403 airtime = (lastrate_dur * finalindex_tries) +
404 (MS(ads->ds_ctl13, AR_xmit_data_tries1) *
405 MS(ads->ds_ctl15, AR_packet_dur1)) +
406 (MS(ads->ds_ctl13, AR_xmit_data_tries0) *
407 MS(ads->ds_ctl15, AR_packet_dur0));
408 break;
409 case 3:
410 lastrate_dur = MS(ads->ds_ctl16, AR_packet_dur3);
411 airtime = (lastrate_dur * finalindex_tries) +
412 (MS(ads->ds_ctl13, AR_xmit_data_tries2) *
413 MS(ads->ds_ctl16, AR_packet_dur2)) +
414 (MS(ads->ds_ctl13, AR_xmit_data_tries1) *
415 MS(ads->ds_ctl15, AR_packet_dur1)) +
416 (MS(ads->ds_ctl13, AR_xmit_data_tries0) *
417 MS(ads->ds_ctl15, AR_packet_dur0));
418 break;
419 default:
420 HALASSERT(0);
421 return 0;
422 }
423
424 if ( comp_wastedt && (ts->ts_flags & HAL_TX_BA)){
425 airtime += nbad?((lastrate_dur*nbad) / nframes):0;
426 }
427 return airtime;
428
429 }
430
431 #ifdef AH_PRIVATE_DIAG
432 void
ar9300__cont_tx_mode(struct ath_hal * ah,void * ds,int mode)433 ar9300__cont_tx_mode(struct ath_hal *ah, void *ds, int mode)
434 {
435 #if 0
436 static int qnum = 0;
437 int i;
438 unsigned int qbits, val, val1, val2;
439 int prefetch;
440 struct ar9300_txs *ads = AR9300TXS(ds);
441
442 if (mode == 10) {
443 return;
444 }
445
446 if (mode == 7) { /* print status from the cont tx desc */
447 if (ads) {
448 val1 = ads->ds_txstatus1;
449 val2 = ads->ds_txstatus2;
450 HALDEBUG(ah, HAL_DEBUG_TXDESC, "s0(%x) s1(%x)\n",
451 (unsigned)val1, (unsigned)val2);
452 }
453 HALDEBUG(ah, HAL_DEBUG_TXDESC, "txe(%x) txd(%x)\n",
454 OS_REG_READ(ah, AR_Q_TXE),
455 OS_REG_READ(ah, AR_Q_TXD)
456 );
457 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
458 val = OS_REG_READ(ah, AR_QTXDP(i));
459 val2 = OS_REG_READ(ah, AR_QSTS(i)) & AR_Q_STS_PEND_FR_CNT;
460 HALDEBUG(ah, HAL_DEBUG_TXDESC, "[%d] %x %d\n", i, val, val2);
461 }
462 return;
463 }
464 if (mode == 8) { /* set TXE for qnum */
465 OS_REG_WRITE(ah, AR_Q_TXE, 1 << qnum);
466 return;
467 }
468 if (mode == 9) {
469 prefetch = (int)ds;
470 return;
471 }
472
473 if (mode >= 1) { /* initiate cont tx operation */
474 /* Disable AGC to A2 */
475 qnum = (int) ds;
476
477 OS_REG_WRITE(ah, AR_PHY_TEST,
478 (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR) );
479
480 OS_REG_WRITE(ah, 0x9864, OS_REG_READ(ah, 0x9864) | 0x7f000);
481 OS_REG_WRITE(ah, 0x9924, OS_REG_READ(ah, 0x9924) | 0x7f00fe);
482 OS_REG_WRITE(ah, AR_DIAG_SW,
483 (OS_REG_READ(ah, AR_DIAG_SW) |
484 (AR_DIAG_FORCE_RX_CLEAR + AR_DIAG_IGNORE_VIRT_CS)) );
485
486
487 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* set receive disable */
488
489 if (mode == 3 || mode == 4) {
490 int txcfg;
491
492 if (mode == 3) {
493 OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
494 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
495 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 100);
496 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 100);
497 OS_REG_WRITE(ah, AR_TIME_OUT, 2);
498 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, 100);
499 }
500
501 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
502 /* enable prefetch on qnum */
503 OS_REG_WRITE(ah, AR_D_FPCTL, 0x10 | qnum);
504 txcfg = 5 | (6 << AR_FTRIG_S);
505 OS_REG_WRITE(ah, AR_TXCFG, txcfg);
506
507 OS_REG_WRITE(ah, AR_QMISC(qnum), /* set QCU modes */
508 AR_Q_MISC_DCU_EARLY_TERM_REQ
509 + AR_Q_MISC_FSP_ASAP
510 + AR_Q_MISC_CBR_INCR_DIS1
511 + AR_Q_MISC_CBR_INCR_DIS0
512 );
513
514 /* stop tx dma all all except qnum */
515 qbits = 0x3ff;
516 qbits &= ~(1 << qnum);
517 for (i = 0; i < 10; i++) {
518 if (i == qnum) {
519 continue;
520 }
521 OS_REG_WRITE(ah, AR_Q_TXD, 1 << i);
522 }
523
524 OS_REG_WRITE(ah, AR_Q_TXD, qbits);
525
526 /* clear and freeze MIB counters */
527 OS_REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC);
528 OS_REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
529
530 OS_REG_WRITE(ah, AR_DMISC(qnum),
531 (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
532 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
533 + (AR_D_MISC_ARB_LOCKOUT_IGNORE)
534 + (AR_D_MISC_POST_FR_BKOFF_DIS)
535 + (AR_D_MISC_VIR_COL_HANDLING_IGNORE <<
536 AR_D_MISC_VIR_COL_HANDLING_S));
537
538 for (i = 0; i < HAL_NUM_TX_QUEUES + 2; i++) { /* disconnect QCUs */
539 if (i == qnum) {
540 continue;
541 }
542 OS_REG_WRITE(ah, AR_DQCUMASK(i), 0);
543 }
544 }
545 }
546 if (mode == 0) {
547 OS_REG_WRITE(ah, AR_PHY_TEST,
548 (OS_REG_READ(ah, AR_PHY_TEST) & ~PHY_AGC_CLR));
549 OS_REG_WRITE(ah, AR_DIAG_SW,
550 (OS_REG_READ(ah, AR_DIAG_SW) &
551 ~(AR_DIAG_FORCE_RX_CLEAR + AR_DIAG_IGNORE_VIRT_CS)));
552 }
553 #endif
554 }
555 #endif
556
557 void
ar9300_set_paprd_tx_desc(struct ath_hal * ah,void * ds,int chain_num)558 ar9300_set_paprd_tx_desc(struct ath_hal *ah, void *ds, int chain_num)
559 {
560 struct ar9300_txc *ads = AR9300TXC(ds);
561
562 ads->ds_ctl12 |= SM((1 << chain_num), AR_paprd_chain_mask);
563 }
564 HAL_STATUS
ar9300_is_tx_done(struct ath_hal * ah)565 ar9300_is_tx_done(struct ath_hal *ah)
566 {
567 struct ath_hal_9300 *ahp = AH9300(ah);
568 struct ar9300_txs *ads;
569
570 ads = &ahp->ts_ring[ahp->ts_tail];
571
572 if (ads->status8 & AR_tx_done) {
573 return HAL_OK;
574 }
575 return HAL_EINPROGRESS;
576 }
577
578 void
ar9300_set_11n_tx_desc(struct ath_hal * ah,void * ds,u_int pkt_len,HAL_PKT_TYPE type,u_int tx_power,u_int key_ix,HAL_KEY_TYPE key_type,u_int flags)579 ar9300_set_11n_tx_desc(
580 struct ath_hal *ah,
581 void *ds,
582 u_int pkt_len,
583 HAL_PKT_TYPE type,
584 u_int tx_power,
585 u_int key_ix,
586 HAL_KEY_TYPE key_type,
587 u_int flags)
588 {
589 struct ar9300_txc *ads = AR9300TXC(ds);
590 struct ath_hal_9300 *ahp = AH9300(ah);
591
592 HALASSERT(is_valid_pkt_type(type));
593 HALASSERT(is_valid_key_type(key_type));
594
595 tx_power += ahp->ah_tx_power_index_offset;
596 if (tx_power > 63) {
597 tx_power = 63;
598 }
599 ads->ds_ctl11 =
600 (pkt_len & AR_frame_len)
601 | (flags & HAL_TXDESC_VMF ? AR_virt_more_frag : 0)
602 | SM(tx_power, AR_xmit_power0)
603 | (flags & HAL_TXDESC_VEOL ? AR_veol : 0)
604 | (flags & HAL_TXDESC_CLRDMASK ? AR_clr_dest_mask : 0)
605 | (key_ix != HAL_TXKEYIX_INVALID ? AR_dest_idx_valid : 0)
606 | (flags & HAL_TXDESC_LOWRXCHAIN ? AR_low_rx_chain : 0);
607
608 ads->ds_ctl12 =
609 (key_ix != HAL_TXKEYIX_INVALID ? SM(key_ix, AR_dest_idx) : 0)
610 | SM(type, AR_frame_type)
611 | (flags & HAL_TXDESC_NOACK ? AR_no_ack : 0)
612 | (flags & HAL_TXDESC_EXT_ONLY ? AR_ext_only : 0)
613 | (flags & HAL_TXDESC_EXT_AND_CTL ? AR_ext_and_ctl : 0);
614
615 ads->ds_ctl17 =
616 SM(key_type, AR_encr_type) | (flags & HAL_TXDESC_LDPC ? AR_ldpc : 0);
617
618 ads->ds_ctl18 = 0;
619 ads->ds_ctl19 = AR_not_sounding; /* set not sounding for normal frame */
620
621
622 /*
623 * Clear Ness1/2/3 (Number of Extension Spatial Streams) fields.
624 * Ness0 is cleared in ctl19. See EV66059 (BB panic).
625 */
626 ads->ds_ctl20 = 0;
627 ads->ds_ctl21 = 0;
628 ads->ds_ctl22 = 0;
629 }
630
ar9300_set_rx_chainmask(struct ath_hal * ah,int rxchainmask)631 void ar9300_set_rx_chainmask(struct ath_hal *ah, int rxchainmask)
632 {
633 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rxchainmask);
634 }
635
ar9300_update_loc_ctl_reg(struct ath_hal * ah,int pos_bit)636 void ar9300_update_loc_ctl_reg(struct ath_hal *ah, int pos_bit)
637 {
638 u_int32_t reg_val;
639 reg_val = OS_REG_READ(ah, AR_LOC_CTL_REG);
640 if (pos_bit) {
641 if (!(reg_val & AR_LOC_CTL_REG_FS)) {
642 /* set fast timestamp bit in the regiter */
643 OS_REG_WRITE(ah, AR_LOC_CTL_REG, (reg_val | AR_LOC_CTL_REG_FS));
644 OS_REG_WRITE(ah, AR_LOC_TIMER_REG, 0);
645 }
646 }
647 else {
648 OS_REG_WRITE(ah, AR_LOC_CTL_REG, (reg_val & ~AR_LOC_CTL_REG_FS));
649 }
650 }
651
652 #if 0
653 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
654 static const u_int8_t ba_duration_delta[] = {
655 24, /* 0: BPSK */
656 12, /* 1: QPSK 1/2 */
657 12, /* 2: QPSK 3/4 */
658 4, /* 3: 16-QAM 1/2 */
659 4, /* 4: 16-QAM 3/4 */
660 4, /* 5: 64-QAM 2/3 */
661 4, /* 6: 64-QAM 3/4 */
662 4, /* 7: 64-QAM 5/6 */
663 24, /* 8: BPSK */
664 12, /* 9: QPSK 1/2 */
665 12, /* 10: QPSK 3/4 */
666 4, /* 11: 16-QAM 1/2 */
667 4, /* 12: 16-QAM 3/4 */
668 4, /* 13: 64-QAM 2/3 */
669 4, /* 14: 64-QAM 3/4 */
670 4, /* 15: 64-QAM 5/6 */
671 };
672 #endif
673
674
675 static u_int8_t
ar9300_get_tx_mode(u_int rate_flags)676 ar9300_get_tx_mode(u_int rate_flags)
677 {
678
679 /* Check whether STBC is enabled if TxBF is not enabled */
680 if (rate_flags & HAL_RATESERIES_STBC){
681 return AR9300_STBC_MODE;
682 }
683 return AR9300_DEF_MODE;
684 }
685 void
ar9300_set_11n_rate_scenario(struct ath_hal * ah,void * ds,void * lastds,u_int dur_update_en,u_int rts_cts_rate,u_int rts_cts_duration,HAL_11N_RATE_SERIES series[],u_int nseries,u_int flags,u_int32_t smart_antenna)686 ar9300_set_11n_rate_scenario(
687 struct ath_hal *ah,
688 void *ds,
689 void *lastds,
690 u_int dur_update_en,
691 u_int rts_cts_rate,
692 u_int rts_cts_duration,
693 HAL_11N_RATE_SERIES series[],
694 u_int nseries,
695 u_int flags,
696 u_int32_t smart_antenna)
697 {
698 struct ath_hal_private *ap = AH_PRIVATE(ah);
699 struct ar9300_txc *ads = AR9300TXC(ds);
700 struct ar9300_txc *last_ads = AR9300TXC(lastds);
701 u_int32_t ds_ctl11;
702 u_int8_t ant, cal_pkt = 0;
703 u_int mode, tx_mode = AR9300_DEF_MODE;
704
705 HALASSERT(nseries == 4);
706 (void)nseries;
707 (void)rts_cts_duration; /* use H/W to calculate RTSCTSDuration */
708
709 ds_ctl11 = ads->ds_ctl11;
710 /*
711 * Rate control settings override
712 */
713 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
714 if (flags & HAL_TXDESC_RTSENA) {
715 ds_ctl11 &= ~AR_cts_enable;
716 ds_ctl11 |= AR_rts_enable;
717 } else {
718 ds_ctl11 &= ~AR_rts_enable;
719 ds_ctl11 |= AR_cts_enable;
720 }
721 } else {
722 ds_ctl11 = (ds_ctl11 & ~(AR_rts_enable | AR_cts_enable));
723 }
724
725 mode = ath_hal_get_curmode(ah, ap->ah_curchan);
726 cal_pkt = (ads->ds_ctl12 & AR_paprd_chain_mask)?1:0;
727
728 if (ah->ah_config.ath_hal_desc_tpc) {
729 int16_t txpower;
730
731 if (!cal_pkt) {
732 /* Series 0 TxPower */
733 tx_mode = ar9300_get_tx_mode(series[0].RateFlags);
734 txpower = ar9300_get_rate_txpower(ah, mode, series[0].RateIndex,
735 series[0].ChSel, tx_mode);
736 } else {
737 txpower = AH9300(ah)->paprd_training_power;
738 }
739 ds_ctl11 &= ~AR_xmit_power0;
740 ds_ctl11 |=
741 set_11n_tx_power(0, AH_MIN(txpower, series[0].tx_power_cap));
742 }
743
744 ads->ds_ctl11 = ds_ctl11;
745
746
747 ads->ds_ctl13 = set_11n_tries(series, 0)
748 | set_11n_tries(series, 1)
749 | set_11n_tries(series, 2)
750 | set_11n_tries(series, 3)
751 | (dur_update_en ? AR_dur_update_ena : 0)
752 | SM(0, AR_burst_dur);
753
754 ads->ds_ctl14 = set_11n_rate(series, 0)
755 | set_11n_rate(series, 1)
756 | set_11n_rate(series, 2)
757 | set_11n_rate(series, 3);
758
759 ads->ds_ctl15 = set_11n_pkt_dur_rts_cts(series, 0)
760 | set_11n_pkt_dur_rts_cts(series, 1);
761
762 ads->ds_ctl16 = set_11n_pkt_dur_rts_cts(series, 2)
763 | set_11n_pkt_dur_rts_cts(series, 3);
764
765 ads->ds_ctl18 = set_11n_rate_flags(series, 0)
766 | set_11n_rate_flags(series, 1)
767 | set_11n_rate_flags(series, 2)
768 | set_11n_rate_flags(series, 3)
769 | SM(rts_cts_rate, AR_rts_cts_rate);
770 /* set not sounding for normal frame */
771 ads->ds_ctl19 = AR_not_sounding;
772
773 if (ah->ah_config.ath_hal_desc_tpc) {
774 int16_t txpower;
775
776 if (!cal_pkt) {
777 /* Series 1 TxPower */
778 tx_mode = ar9300_get_tx_mode(series[1].RateFlags);
779 txpower = ar9300_get_rate_txpower(
780 ah, mode, series[1].RateIndex, series[1].ChSel, tx_mode);
781 } else {
782 txpower = AH9300(ah)->paprd_training_power;
783 }
784 ads->ds_ctl20 |=
785 set_11n_tx_power(1, AH_MIN(txpower, series[1].tx_power_cap));
786
787
788 /* Series 2 TxPower */
789 if (!cal_pkt) {
790 tx_mode = ar9300_get_tx_mode(series[2].RateFlags);
791 txpower = ar9300_get_rate_txpower(
792 ah, mode, series[2].RateIndex, series[2].ChSel, tx_mode);
793 } else {
794 txpower = AH9300(ah)->paprd_training_power;
795 }
796 ads->ds_ctl21 |=
797 set_11n_tx_power(2, AH_MIN(txpower, series[2].tx_power_cap));
798
799 /* Series 3 TxPower */
800 if (!cal_pkt) {
801 tx_mode = ar9300_get_tx_mode(series[3].RateFlags);
802 txpower = ar9300_get_rate_txpower(
803 ah, mode, series[3].RateIndex, series[3].ChSel, tx_mode);
804 } else {
805 txpower = AH9300(ah)->paprd_training_power;
806 }
807 ads->ds_ctl22 |=
808 set_11n_tx_power(3, AH_MIN(txpower, series[3].tx_power_cap));
809 }
810
811 if (smart_antenna != 0xffffffff)
812 {
813 /* TX DESC dword 19 to 23 are used for smart antenna configuaration
814 * ctl19 for rate series 0 ... ctrl22 for series 3
815 * bits[2:0] used to configure smart anntenna
816 */
817 ant = (smart_antenna&0x000000ff);
818 ads->ds_ctl19 |= ant; /* rateseries 0 */
819
820 ant = (smart_antenna&0x0000ff00) >> 8;
821 ads->ds_ctl20 |= ant; /* rateseries 1 */
822
823 ant = (smart_antenna&0x00ff0000) >> 16;
824 ads->ds_ctl21 |= ant; /* rateseries 2 */
825
826 ant = (smart_antenna&0xff000000) >> 24;
827 ads->ds_ctl22 |= ant; /* rateseries 3 */
828 }
829
830 #ifdef AH_NEED_DESC_SWAP
831 last_ads->ds_ctl13 = __bswap32(ads->ds_ctl13);
832 last_ads->ds_ctl14 = __bswap32(ads->ds_ctl14);
833 #else
834 last_ads->ds_ctl13 = ads->ds_ctl13;
835 last_ads->ds_ctl14 = ads->ds_ctl14;
836 #endif
837 }
838
839 void
ar9300_set_11n_aggr_first(struct ath_hal * ah,struct ath_desc * ds,u_int aggr_len,u_int num_delims)840 ar9300_set_11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
841 u_int aggr_len, u_int num_delims)
842 {
843 struct ar9300_txc *ads = AR9300TXC(ds);
844
845 ads->ds_ctl12 |= (AR_is_aggr | AR_more_aggr);
846
847 ads->ds_ctl17 &= ~AR_aggr_len;
848 ads->ds_ctl17 &= ~AR_pad_delim;
849 /* XXX should use a stack variable! */
850 ads->ds_ctl17 |= SM(aggr_len, AR_aggr_len);
851 ads->ds_ctl17 |= SM(num_delims, AR_pad_delim);
852 }
853
854 void
ar9300_set_11n_aggr_middle(struct ath_hal * ah,struct ath_desc * ds,u_int num_delims)855 ar9300_set_11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
856 u_int num_delims)
857 {
858 struct ar9300_txc *ads = AR9300TXC(ds);
859 unsigned int ctl17;
860
861 ads->ds_ctl12 |= (AR_is_aggr | AR_more_aggr);
862
863 /*
864 * We use a stack variable to manipulate ctl6 to reduce uncached
865 * read modify, modfiy, write.
866 */
867 ctl17 = ads->ds_ctl17;
868 ctl17 &= ~AR_pad_delim;
869 ctl17 |= SM(num_delims, AR_pad_delim);
870 ads->ds_ctl17 = ctl17;
871 }
872
873 void
ar9300_set_11n_aggr_last(struct ath_hal * ah,struct ath_desc * ds)874 ar9300_set_11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds)
875 {
876 struct ar9300_txc *ads = AR9300TXC(ds);
877
878 ads->ds_ctl12 |= AR_is_aggr;
879 ads->ds_ctl12 &= ~AR_more_aggr;
880 ads->ds_ctl17 &= ~AR_pad_delim;
881 }
882
883 void
ar9300_clr_11n_aggr(struct ath_hal * ah,struct ath_desc * ds)884 ar9300_clr_11n_aggr(struct ath_hal *ah, struct ath_desc *ds)
885 {
886 struct ar9300_txc *ads = AR9300TXC(ds);
887
888 ads->ds_ctl12 &= (~AR_is_aggr & ~AR_more_aggr);
889 }
890
891 void
ar9300_set_11n_burst_duration(struct ath_hal * ah,struct ath_desc * ds,u_int burst_duration)892 ar9300_set_11n_burst_duration(struct ath_hal *ah, struct ath_desc *ds,
893 u_int burst_duration)
894 {
895 struct ar9300_txc *ads = AR9300TXC(ds);
896
897 ads->ds_ctl13 &= ~AR_burst_dur;
898 ads->ds_ctl13 |= SM(burst_duration, AR_burst_dur);
899 }
900
901 void
ar9300_set_11n_rifs_burst_middle(struct ath_hal * ah,void * ds)902 ar9300_set_11n_rifs_burst_middle(struct ath_hal *ah, void *ds)
903 {
904 struct ar9300_txc *ads = AR9300TXC(ds);
905
906 ads->ds_ctl12 |= AR_more_rifs | AR_no_ack;
907 }
908
909 void
ar9300_set_11n_rifs_burst_last(struct ath_hal * ah,void * ds)910 ar9300_set_11n_rifs_burst_last(struct ath_hal *ah, void *ds)
911 {
912 struct ar9300_txc *ads = AR9300TXC(ds);
913
914 ads->ds_ctl12 &= (~AR_more_aggr & ~AR_more_rifs);
915 }
916
917 void
ar9300_clr_11n_rifs_burst(struct ath_hal * ah,void * ds)918 ar9300_clr_11n_rifs_burst(struct ath_hal *ah, void *ds)
919 {
920 struct ar9300_txc *ads = AR9300TXC(ds);
921
922 ads->ds_ctl12 &= (~AR_more_rifs & ~AR_no_ack);
923 }
924
925 void
ar9300_set_11n_aggr_rifs_burst(struct ath_hal * ah,void * ds)926 ar9300_set_11n_aggr_rifs_burst(struct ath_hal *ah, void *ds)
927 {
928 struct ar9300_txc *ads = AR9300TXC(ds);
929
930 ads->ds_ctl12 |= AR_no_ack;
931 ads->ds_ctl12 &= ~AR_more_rifs;
932 }
933
934 void
ar9300_set_11n_virtual_more_frag(struct ath_hal * ah,struct ath_desc * ds,u_int vmf)935 ar9300_set_11n_virtual_more_frag(struct ath_hal *ah, struct ath_desc *ds,
936 u_int vmf)
937 {
938 struct ar9300_txc *ads = AR9300TXC(ds);
939
940 if (vmf) {
941 ads->ds_ctl11 |= AR_virt_more_frag;
942 } else {
943 ads->ds_ctl11 &= ~AR_virt_more_frag;
944 }
945 }
946
947 void
ar9300_get_desc_info(struct ath_hal * ah,HAL_DESC_INFO * desc_info)948 ar9300_get_desc_info(struct ath_hal *ah, HAL_DESC_INFO *desc_info)
949 {
950 desc_info->txctl_numwords = TXCTL_NUMWORDS(ah);
951 desc_info->txctl_offset = TXCTL_OFFSET(ah);
952 desc_info->txstatus_numwords = TXSTATUS_NUMWORDS(ah);
953 desc_info->txstatus_offset = TXSTATUS_OFFSET(ah);
954
955 desc_info->rxctl_numwords = RXCTL_NUMWORDS(ah);
956 desc_info->rxctl_offset = RXCTL_OFFSET(ah);
957 desc_info->rxstatus_numwords = RXSTATUS_NUMWORDS(ah);
958 desc_info->rxstatus_offset = RXSTATUS_OFFSET(ah);
959 }
960