1 /*
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD: stable/9/sys/dev/ath/ath_hal/ar5416/ar5416_recv.c 224512 2011-07-30 13:25:11Z adrian $
18 */
19 #include "opt_ah.h"
20
21 #include "ah.h"
22 #include "ah_desc.h"
23 #include "ah_internal.h"
24
25 #include "ar5416/ar5416.h"
26 #include "ar5416/ar5416reg.h"
27 #include "ar5416/ar5416desc.h"
28
29 /*
30 * Get the receive filter.
31 */
32 uint32_t
ar5416GetRxFilter(struct ath_hal * ah)33 ar5416GetRxFilter(struct ath_hal *ah)
34 {
35 uint32_t bits = OS_REG_READ(ah, AR_RX_FILTER);
36 uint32_t phybits = OS_REG_READ(ah, AR_PHY_ERR);
37
38 if (phybits & AR_PHY_ERR_RADAR)
39 bits |= HAL_RX_FILTER_PHYRADAR;
40 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
41 bits |= HAL_RX_FILTER_PHYERR;
42 return bits;
43 }
44
45 /*
46 * Set the receive filter.
47 */
48 void
ar5416SetRxFilter(struct ath_hal * ah,u_int32_t bits)49 ar5416SetRxFilter(struct ath_hal *ah, u_int32_t bits)
50 {
51 uint32_t phybits;
52
53 OS_REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff));
54 phybits = 0;
55 if (bits & HAL_RX_FILTER_PHYRADAR)
56 phybits |= AR_PHY_ERR_RADAR;
57 if (bits & HAL_RX_FILTER_PHYERR)
58 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
59 OS_REG_WRITE(ah, AR_PHY_ERR, phybits);
60 if (phybits) {
61 OS_REG_WRITE(ah, AR_RXCFG,
62 OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
63 } else {
64 OS_REG_WRITE(ah, AR_RXCFG,
65 OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);
66 }
67 }
68
69 /*
70 * Start receive at the PCU engine
71 */
72 void
ar5416StartPcuReceive(struct ath_hal * ah)73 ar5416StartPcuReceive(struct ath_hal *ah)
74 {
75 struct ath_hal_private *ahp = AH_PRIVATE(ah);
76
77 HALDEBUG(ah, HAL_DEBUG_RX, "%s: Start PCU Receive \n", __func__);
78 ar5212EnableMibCounters(ah);
79 /* NB: restore current settings */
80 ar5416AniReset(ah, ahp->ah_curchan, ahp->ah_opmode, AH_TRUE);
81 /*
82 * NB: must do after enabling phy errors to avoid rx
83 * frames w/ corrupted descriptor status.
84 */
85 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
86 }
87
88 /*
89 * Stop receive at the PCU engine
90 * and abort current frame in PCU
91 */
92 void
ar5416StopPcuReceive(struct ath_hal * ah)93 ar5416StopPcuReceive(struct ath_hal *ah)
94 {
95 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
96
97 HALDEBUG(ah, HAL_DEBUG_RX, "%s: Stop PCU Receive \n", __func__);
98 ar5212DisableMibCounters(ah);
99 }
100
101 /*
102 * Initialize RX descriptor, by clearing the status and setting
103 * the size (and any other flags).
104 */
105 HAL_BOOL
ar5416SetupRxDesc(struct ath_hal * ah,struct ath_desc * ds,uint32_t size,u_int flags)106 ar5416SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds,
107 uint32_t size, u_int flags)
108 {
109 struct ar5416_desc *ads = AR5416DESC(ds);
110 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
111
112 HALASSERT((size &~ AR_BufLen) == 0);
113
114 ads->ds_ctl1 = size & AR_BufLen;
115 if (flags & HAL_RXDESC_INTREQ)
116 ads->ds_ctl1 |= AR_RxIntrReq;
117
118 /* this should be enough */
119 ads->ds_rxstatus8 &= ~AR_RxDone;
120
121 /* clear the rest of the status fields */
122 if (! pCap->halAutoSleepSupport)
123 OS_MEMZERO(&(ads->u), sizeof(ads->u));
124
125 return AH_TRUE;
126 }
127
128 /*
129 * Process an RX descriptor, and return the status to the caller.
130 * Copy some hardware specific items into the software portion
131 * of the descriptor.
132 *
133 * NB: the caller is responsible for validating the memory contents
134 * of the descriptor (e.g. flushing any cached copy).
135 */
136 HAL_STATUS
ar5416ProcRxDesc(struct ath_hal * ah,struct ath_desc * ds,uint32_t pa,struct ath_desc * nds,uint64_t tsf,struct ath_rx_status * rs)137 ar5416ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds,
138 uint32_t pa, struct ath_desc *nds, uint64_t tsf,
139 struct ath_rx_status *rs)
140 {
141 struct ar5416_desc *ads = AR5416DESC(ds);
142
143 if ((ads->ds_rxstatus8 & AR_RxDone) == 0)
144 return HAL_EINPROGRESS;
145
146 rs->rs_status = 0;
147 rs->rs_flags = 0;
148
149 rs->rs_datalen = ads->ds_rxstatus1 & AR_DataLen;
150 rs->rs_tstamp = ads->AR_RcvTimestamp;
151
152 /* XXX what about KeyCacheMiss? */
153
154 rs->rs_rssi = MS(ads->ds_rxstatus4, AR_RxRSSICombined);
155 rs->rs_rssi_ctl[0] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt00);
156 rs->rs_rssi_ctl[1] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt01);
157 rs->rs_rssi_ctl[2] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt02);
158 rs->rs_rssi_ext[0] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt10);
159 rs->rs_rssi_ext[1] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt11);
160 rs->rs_rssi_ext[2] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt12);
161
162 if (ads->ds_rxstatus8 & AR_RxKeyIdxValid)
163 rs->rs_keyix = MS(ads->ds_rxstatus8, AR_KeyIdx);
164 else
165 rs->rs_keyix = HAL_RXKEYIX_INVALID;
166
167 /* NB: caller expected to do rate table mapping */
168 rs->rs_rate = RXSTATUS_RATE(ah, ads);
169 rs->rs_more = (ads->ds_rxstatus1 & AR_RxMore) ? 1 : 0;
170
171 rs->rs_isaggr = (ads->ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
172 rs->rs_moreaggr = (ads->ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
173 rs->rs_antenna = MS(ads->ds_rxstatus3, AR_RxAntenna);
174
175 if (ads->ds_rxstatus3 & AR_GI)
176 rs->rs_flags |= HAL_RX_GI;
177 if (ads->ds_rxstatus3 & AR_2040)
178 rs->rs_flags |= HAL_RX_2040;
179
180 if (ads->ds_rxstatus8 & AR_PreDelimCRCErr)
181 rs->rs_flags |= HAL_RX_DELIM_CRC_PRE;
182 if (ads->ds_rxstatus8 & AR_PostDelimCRCErr)
183 rs->rs_flags |= HAL_RX_DELIM_CRC_POST;
184 if (ads->ds_rxstatus8 & AR_DecryptBusyErr)
185 rs->rs_flags |= HAL_RX_DECRYPT_BUSY;
186 if (ads->ds_rxstatus8 & AR_HiRxChain)
187 rs->rs_flags |= HAL_RX_HI_RX_CHAIN;
188
189 if ((ads->ds_rxstatus8 & AR_RxFrameOK) == 0) {
190 /*
191 * These four bits should not be set together. The
192 * 5416 spec states a Michael error can only occur if
193 * DecryptCRCErr not set (and TKIP is used). Experience
194 * indicates however that you can also get Michael errors
195 * when a CRC error is detected, but these are specious.
196 * Consequently we filter them out here so we don't
197 * confuse and/or complicate drivers.
198 */
199 if (ads->ds_rxstatus8 & AR_CRCErr)
200 rs->rs_status |= HAL_RXERR_CRC;
201 else if (ads->ds_rxstatus8 & AR_PHYErr) {
202 u_int phyerr;
203
204 rs->rs_status |= HAL_RXERR_PHY;
205 phyerr = MS(ads->ds_rxstatus8, AR_PHYErrCode);
206 rs->rs_phyerr = phyerr;
207 } else if (ads->ds_rxstatus8 & AR_DecryptCRCErr)
208 rs->rs_status |= HAL_RXERR_DECRYPT;
209 else if (ads->ds_rxstatus8 & AR_MichaelErr)
210 rs->rs_status |= HAL_RXERR_MIC;
211 }
212
213 return HAL_OK;
214 }
215