1 /*
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD: stable/9/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c 225444 2011-09-08 01:23:05Z adrian $
18 */
19 #include "opt_ah.h"
20
21 #include "ah.h"
22 #include "ah_internal.h"
23 #include "ah_devid.h"
24
25 #include "ah_eeprom_v14.h"
26
27 #include "ar5416/ar5416.h"
28 #include "ar5416/ar5416reg.h"
29 #include "ar5416/ar5416phy.h"
30
31 #include "ar5416/ar5416.ini"
32
33 static void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore);
34 static void ar5416WriteIni(struct ath_hal *ah,
35 const struct ieee80211_channel *chan);
36 static void ar5416SpurMitigate(struct ath_hal *ah,
37 const struct ieee80211_channel *chan);
38
39 static void
ar5416AniSetup(struct ath_hal * ah)40 ar5416AniSetup(struct ath_hal *ah)
41 {
42 static const struct ar5212AniParams aniparams = {
43 .maxNoiseImmunityLevel = 4, /* levels 0..4 */
44 .totalSizeDesired = { -55, -55, -55, -55, -62 },
45 .coarseHigh = { -14, -14, -14, -14, -12 },
46 .coarseLow = { -64, -64, -64, -64, -70 },
47 .firpwr = { -78, -78, -78, -78, -80 },
48 .maxSpurImmunityLevel = 2,
49 .cycPwrThr1 = { 2, 4, 6 },
50 .maxFirstepLevel = 2, /* levels 0..2 */
51 .firstep = { 0, 4, 8 },
52 .ofdmTrigHigh = 500,
53 .ofdmTrigLow = 200,
54 .cckTrigHigh = 200,
55 .cckTrigLow = 100,
56 .rssiThrHigh = 40,
57 .rssiThrLow = 7,
58 .period = 100,
59 };
60 /* NB: disable ANI noise immmunity for reliable RIFS rx */
61 AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL);
62 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
63 }
64
65 /*
66 * AR5416 doesn't do OLC or temperature compensation.
67 */
68 static void
ar5416olcInit(struct ath_hal * ah)69 ar5416olcInit(struct ath_hal *ah)
70 {
71 }
72
73 static void
ar5416olcTempCompensation(struct ath_hal * ah)74 ar5416olcTempCompensation(struct ath_hal *ah)
75 {
76 }
77
78 /*
79 * Attach for an AR5416 part.
80 */
81 void
ar5416InitState(struct ath_hal_5416 * ahp5416,uint16_t devid,HAL_SOFTC sc,HAL_BUS_TAG st,HAL_BUS_HANDLE sh,HAL_STATUS * status)82 ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc,
83 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
84 {
85 struct ath_hal_5212 *ahp;
86 struct ath_hal *ah;
87
88 ahp = &ahp5416->ah_5212;
89 ar5212InitState(ahp, devid, sc, st, sh, status);
90 ah = &ahp->ah_priv.h;
91
92 /* override 5212 methods for our needs */
93 ah->ah_magic = AR5416_MAGIC;
94 ah->ah_getRateTable = ar5416GetRateTable;
95 ah->ah_detach = ar5416Detach;
96
97 /* Reset functions */
98 ah->ah_reset = ar5416Reset;
99 ah->ah_phyDisable = ar5416PhyDisable;
100 ah->ah_disable = ar5416Disable;
101 ah->ah_configPCIE = ar5416ConfigPCIE;
102 ah->ah_perCalibration = ar5416PerCalibration;
103 ah->ah_perCalibrationN = ar5416PerCalibrationN,
104 ah->ah_resetCalValid = ar5416ResetCalValid,
105 ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit;
106 ah->ah_setTxPower = ar5416SetTransmitPower;
107 ah->ah_setBoardValues = ar5416SetBoardValues;
108
109 /* Transmit functions */
110 ah->ah_stopTxDma = ar5416StopTxDma;
111 ah->ah_setupTxDesc = ar5416SetupTxDesc;
112 ah->ah_setupXTxDesc = ar5416SetupXTxDesc;
113 ah->ah_fillTxDesc = ar5416FillTxDesc;
114 ah->ah_procTxDesc = ar5416ProcTxDesc;
115 ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates;
116 ah->ah_setupTxQueue = ar5416SetupTxQueue;
117 ah->ah_resetTxQueue = ar5416ResetTxQueue;
118
119 /* Receive Functions */
120 ah->ah_getRxFilter = ar5416GetRxFilter;
121 ah->ah_setRxFilter = ar5416SetRxFilter;
122 ah->ah_startPcuReceive = ar5416StartPcuReceive;
123 ah->ah_stopPcuReceive = ar5416StopPcuReceive;
124 ah->ah_setupRxDesc = ar5416SetupRxDesc;
125 ah->ah_procRxDesc = ar5416ProcRxDesc;
126 ah->ah_rxMonitor = ar5416RxMonitor;
127 ah->ah_aniPoll = ar5416AniPoll;
128 ah->ah_procMibEvent = ar5416ProcessMibIntr;
129
130 /* Misc Functions */
131 ah->ah_getCapability = ar5416GetCapability;
132 ah->ah_getDiagState = ar5416GetDiagState;
133 ah->ah_setLedState = ar5416SetLedState;
134 ah->ah_gpioCfgOutput = ar5416GpioCfgOutput;
135 ah->ah_gpioCfgInput = ar5416GpioCfgInput;
136 ah->ah_gpioGet = ar5416GpioGet;
137 ah->ah_gpioSet = ar5416GpioSet;
138 ah->ah_gpioSetIntr = ar5416GpioSetIntr;
139 ah->ah_getTsf64 = ar5416GetTsf64;
140 ah->ah_resetTsf = ar5416ResetTsf;
141 ah->ah_getRfGain = ar5416GetRfgain;
142 ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch;
143 ah->ah_setDecompMask = ar5416SetDecompMask;
144 ah->ah_setCoverageClass = ar5416SetCoverageClass;
145 ah->ah_setQuiet = ar5416SetQuiet;
146
147 ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry;
148 ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry;
149
150 /* DFS Functions */
151 ah->ah_enableDfs = ar5416EnableDfs;
152 ah->ah_getDfsThresh = ar5416GetDfsThresh;
153 ah->ah_procRadarEvent = ar5416ProcessRadarEvent;
154 ah->ah_isFastClockEnabled = ar5416IsFastClockEnabled;
155
156 /* Power Management Functions */
157 ah->ah_setPowerMode = ar5416SetPowerMode;
158
159 /* Beacon Management Functions */
160 ah->ah_setBeaconTimers = ar5416SetBeaconTimers;
161 ah->ah_beaconInit = ar5416BeaconInit;
162 ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers;
163 ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers;
164 ah->ah_getNextTBTT = ar5416GetNextTBTT;
165
166 /* 802.11n Functions */
167 ah->ah_chainTxDesc = ar5416ChainTxDesc;
168 ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc;
169 ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc;
170 ah->ah_set11nRateScenario = ar5416Set11nRateScenario;
171 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle;
172 ah->ah_clr11nAggr = ar5416Clr11nAggr;
173 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration;
174 ah->ah_get11nExtBusy = ar5416Get11nExtBusy;
175 ah->ah_set11nMac2040 = ar5416Set11nMac2040;
176 ah->ah_get11nRxClear = ar5416Get11nRxClear;
177 ah->ah_set11nRxClear = ar5416Set11nRxClear;
178
179 /* Interrupt functions */
180 ah->ah_isInterruptPending = ar5416IsInterruptPending;
181 ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts;
182 ah->ah_setInterrupts = ar5416SetInterrupts;
183
184 ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes;
185 ahp->ah_priv.ah_eepromRead = ar5416EepromRead;
186 #ifdef AH_SUPPORT_WRITE_EEPROM
187 ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite;
188 #endif
189 ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits;
190
191 /* Internal ops */
192 AH5416(ah)->ah_writeIni = ar5416WriteIni;
193 AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate;
194
195 /* Internal baseband ops */
196 AH5416(ah)->ah_initPLL = ar5416InitPLL;
197
198 /* Internal calibration ops */
199 AH5416(ah)->ah_cal_initcal = ar5416InitCalHardware;
200
201 /* Internal TX power control related operations */
202 AH5416(ah)->ah_olcInit = ar5416olcInit;
203 AH5416(ah)->ah_olcTempCompensation = ar5416olcTempCompensation;
204 AH5416(ah)->ah_setPowerCalTable = ar5416SetPowerCalTable;
205
206 /*
207 * Start by setting all Owl devices to 2x2
208 */
209 AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK;
210 AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK;
211
212 /* Enable all ANI functions to begin with */
213 AH5416(ah)->ah_ani_function = 0xffffffff;
214
215 /* Set overridable ANI methods */
216 AH5212(ah)->ah_aniControl = ar5416AniControl;
217 }
218
219 uint32_t
ar5416GetRadioRev(struct ath_hal * ah)220 ar5416GetRadioRev(struct ath_hal *ah)
221 {
222 uint32_t val;
223 int i;
224
225 /* Read Radio Chip Rev Extract */
226 OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
227 for (i = 0; i < 8; i++)
228 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
229 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
230 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
231 return ath_hal_reverseBits(val, 8);
232 }
233
234 /*
235 * Attach for an AR5416 part.
236 */
237 static struct ath_hal *
ar5416Attach(uint16_t devid,HAL_SOFTC sc,HAL_BUS_TAG st,HAL_BUS_HANDLE sh,uint16_t * eepromdata,HAL_STATUS * status)238 ar5416Attach(uint16_t devid, HAL_SOFTC sc,
239 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
240 HAL_STATUS *status)
241 {
242 struct ath_hal_5416 *ahp5416;
243 struct ath_hal_5212 *ahp;
244 struct ath_hal *ah;
245 uint32_t val;
246 HAL_STATUS ecode;
247 HAL_BOOL rfStatus;
248
249 HALDEBUG_G(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
250 __func__, sc, (void*) st, (void*) sh);
251
252 /* NB: memory is returned zero'd */
253 ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) +
254 /* extra space for Owl 2.1/2.2 WAR */
255 sizeof(ar5416Addac)
256 );
257 if (ahp5416 == AH_NULL) {
258 HALDEBUG_G(AH_NULL, HAL_DEBUG_ANY,
259 "%s: cannot allocate memory for state block\n", __func__);
260 *status = HAL_ENOMEM;
261 return AH_NULL;
262 }
263 ar5416InitState(ahp5416, devid, sc, st, sh, status);
264 ahp = &ahp5416->ah_5212;
265 ah = &ahp->ah_priv.h;
266
267 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
268 /* reset chip */
269 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__);
270 ecode = HAL_EIO;
271 goto bad;
272 }
273
274 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
275 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__);
276 ecode = HAL_EIO;
277 goto bad;
278 }
279 /* Read Revisions from Chips before taking out of reset */
280 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;
281 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S;
282 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION;
283 AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE);
284
285 /* setup common ini data; rf backends handle remainder */
286 HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6);
287 HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2);
288
289 HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3);
290 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2);
291 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2);
292 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2);
293 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3);
294 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3);
295 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2);
296 HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2);
297
298 if (! IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */
299 ath_hal_printf(ah, "[ath] Enabling CLKDRV workaround for AR5416 < v2.2\n");
300 struct ini {
301 uint32_t *data; /* NB: !const */
302 int rows, cols;
303 };
304 /* override CLKDRV value */
305 OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac));
306 AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1];
307 HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0;
308 }
309
310 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2);
311 ar5416AttachPCIE(ah);
312
313 ecode = ath_hal_v14EepromAttach(ah);
314 if (ecode != HAL_OK)
315 goto bad;
316
317 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
318 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
319 __func__);
320 ecode = HAL_EIO;
321 goto bad;
322 }
323
324 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
325
326 if (!ar5212ChipTest(ah)) {
327 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
328 __func__);
329 ecode = HAL_ESELFTEST;
330 goto bad;
331 }
332
333 /*
334 * Set correct Baseband to analog shift
335 * setting to access analog chips.
336 */
337 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
338
339 /* Read Radio Chip Rev Extract */
340 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah);
341 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
342 case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */
343 case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */
344 case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */
345 case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */
346 break;
347 default:
348 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
349 /*
350 * When RF_Silen is used the analog chip is reset.
351 * So when the system boots with radio switch off
352 * the RF chip rev reads back as zero and we need
353 * to use the mac+phy revs to set the radio rev.
354 */
355 AH_PRIVATE(ah)->ah_analog5GhzRev =
356 AR_RAD5133_SREV_MAJOR;
357 break;
358 }
359 /* NB: silently accept anything in release code per Atheros */
360 #ifdef AH_DEBUG
361 HALDEBUG(ah, HAL_DEBUG_ANY,
362 "%s: 5G Radio Chip Rev 0x%02X is not supported by "
363 "this driver\n", __func__,
364 AH_PRIVATE(ah)->ah_analog5GhzRev);
365 ecode = HAL_ENOTSUPP;
366 goto bad;
367 #endif
368 }
369
370 /*
371 * Got everything we need now to setup the capabilities.
372 */
373 if (!ar5416FillCapabilityInfo(ah)) {
374 ecode = HAL_EEREAD;
375 goto bad;
376 }
377
378 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
379 if (ecode != HAL_OK) {
380 HALDEBUG(ah, HAL_DEBUG_ANY,
381 "%s: error getting mac address from EEPROM\n", __func__);
382 goto bad;
383 }
384 /* XXX How about the serial number ? */
385 /* Read Reg Domain */
386 AH_PRIVATE(ah)->ah_currentRD =
387 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
388 AH_PRIVATE(ah)->ah_currentRDext =
389 ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL);
390
391 /*
392 * ah_miscMode is populated by ar5416FillCapabilityInfo()
393 * starting from griffin. Set here to make sure that
394 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
395 * placed into hardware.
396 */
397 if (ahp->ah_miscMode != 0)
398 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
399
400 rfStatus = ar2133RfAttach(ah, &ecode);
401 if (!rfStatus) {
402 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
403 __func__, ecode);
404 goto bad;
405 }
406
407 ar5416AniSetup(ah); /* Anti Noise Immunity */
408
409 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ;
410 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ;
411 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ;
412 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ;
413 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ;
414 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
415
416 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
417
418 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
419
420 return ah;
421 bad:
422 if (ahp)
423 ar5416Detach((struct ath_hal *) ahp);
424 if (status)
425 *status = ecode;
426 return AH_NULL;
427 }
428
429 void
ar5416Detach(struct ath_hal * ah)430 ar5416Detach(struct ath_hal *ah)
431 {
432 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__);
433
434 HALASSERT(ah != AH_NULL);
435 HALASSERT(ah->ah_magic == AR5416_MAGIC);
436
437 /* Make sure that chip is awake before writing to it */
438 if (! ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
439 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
440 "%s: failed to wake up chip\n",
441 __func__);
442
443 ar5416AniDetach(ah);
444 ar5212RfDetach(ah);
445 ah->ah_disable(ah);
446 ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
447 ath_hal_eepromDetach(ah);
448 ath_hal_free(ah);
449 }
450
451 void
ar5416AttachPCIE(struct ath_hal * ah)452 ar5416AttachPCIE(struct ath_hal *ah)
453 {
454 if (AH_PRIVATE(ah)->ah_ispcie)
455 ath_hal_configPCIE(ah, AH_FALSE);
456 else
457 ath_hal_disablePCIE(ah);
458 }
459
460 static void
ar5416ConfigPCIE(struct ath_hal * ah,HAL_BOOL restore)461 ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
462 {
463 if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
464 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
465 OS_DELAY(1000);
466 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
467 OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
468 }
469 }
470
471 static void
ar5416WriteIni(struct ath_hal * ah,const struct ieee80211_channel * chan)472 ar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
473 {
474 u_int modesIndex, freqIndex;
475 int regWrites = 0;
476
477 /* Setup the indices for the next set of register array writes */
478 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
479 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
480 freqIndex = 2;
481 if (IEEE80211_IS_CHAN_HT40(chan))
482 modesIndex = 3;
483 else if (IEEE80211_IS_CHAN_108G(chan))
484 modesIndex = 5;
485 else
486 modesIndex = 4;
487 } else {
488 freqIndex = 1;
489 if (IEEE80211_IS_CHAN_HT40(chan) ||
490 IEEE80211_IS_CHAN_TURBO(chan))
491 modesIndex = 2;
492 else
493 modesIndex = 1;
494 }
495
496 /* Set correct Baseband to analog shift setting to access analog chips. */
497 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
498
499 /*
500 * Write addac shifts
501 */
502 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
503
504 /* NB: only required for Sowl */
505 if (AR_SREV_SOWL(ah))
506 ar5416EepromSetAddac(ah, chan);
507
508 regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1,
509 regWrites);
510 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
511
512 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
513 modesIndex, regWrites);
514 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
515 1, regWrites);
516
517 /* XXX updated regWrites? */
518 AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites);
519 }
520
521 /*
522 * Convert to baseband spur frequency given input channel frequency
523 * and compute register settings below.
524 */
525
526 static void
ar5416SpurMitigate(struct ath_hal * ah,const struct ieee80211_channel * chan)527 ar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan)
528 {
529 uint16_t freq = ath_hal_gethwchannel(ah, chan);
530 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
531 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 };
532 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
533 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 };
534 static const int inc[4] = { 0, 100, 0, 0 };
535
536 int bb_spur = AR_NO_SPUR;
537 int bin, cur_bin;
538 int spur_freq_sd;
539 int spur_delta_phase;
540 int denominator;
541 int upper, lower, cur_vit_mask;
542 int tmp, new;
543 int i;
544
545 int8_t mask_m[123];
546 int8_t mask_p[123];
547 int8_t mask_amt;
548 int tmp_mask;
549 int cur_bb_spur;
550 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan);
551
552 OS_MEMZERO(mask_m, sizeof(mask_m));
553 OS_MEMZERO(mask_p, sizeof(mask_p));
554
555 /*
556 * Need to verify range +/- 9.5 for static ht20, otherwise spur
557 * is out-of-band and can be ignored.
558 */
559 /* XXX ath9k changes */
560 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
561 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz);
562 if (AR_NO_SPUR == cur_bb_spur)
563 break;
564 cur_bb_spur = cur_bb_spur - (freq * 10);
565 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
566 bb_spur = cur_bb_spur;
567 break;
568 }
569 }
570 if (AR_NO_SPUR == bb_spur)
571 return;
572
573 bin = bb_spur * 32;
574
575 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0));
576 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
577 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
578 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
579 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
580
581 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new);
582
583 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
584 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
585 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
586 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
587 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
588 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new);
589 /*
590 * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz
591 * config, no offset for HT20.
592 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20,
593 * /80 for dyn2040.
594 */
595 spur_delta_phase = ((bb_spur * 524288) / 100) &
596 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
597 /*
598 * in 11A mode the denominator of spur_freq_sd should be 40 and
599 * it should be 44 in 11G
600 */
601 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400;
602 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
603
604 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
605 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
606 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
607 OS_REG_WRITE(ah, AR_PHY_TIMING11, new);
608
609
610 /*
611 * ============================================
612 * pilot mask 1 [31:0] = +6..-26, no 0 bin
613 * pilot mask 2 [19:0] = +26..+7
614 *
615 * channel mask 1 [31:0] = +6..-26, no 0 bin
616 * channel mask 2 [19:0] = +26..+7
617 */
618 //cur_bin = -26;
619 cur_bin = -6000;
620 upper = bin + 100;
621 lower = bin - 100;
622
623 for (i = 0; i < 4; i++) {
624 int pilot_mask = 0;
625 int chan_mask = 0;
626 int bp = 0;
627 for (bp = 0; bp < 30; bp++) {
628 if ((cur_bin > lower) && (cur_bin < upper)) {
629 pilot_mask = pilot_mask | 0x1 << bp;
630 chan_mask = chan_mask | 0x1 << bp;
631 }
632 cur_bin += 100;
633 }
634 cur_bin += inc[i];
635 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
636 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask);
637 }
638
639 /* =================================================
640 * viterbi mask 1 based on channel magnitude
641 * four levels 0-3
642 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c)
643 * [1 2 2 1] for -9.6 or [1 2 1] for +16
644 * - enable_mask_ppm, all bins move with freq
645 *
646 * - mask_select, 8 bits for rates (reg 67,0x990c)
647 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c)
648 * choose which mask to use mask or mask2
649 */
650
651 /*
652 * viterbi mask 2 2nd set for per data rate puncturing
653 * four levels 0-3
654 * - mask_select, 8 bits for rates (reg 67)
655 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994)
656 * [1 2 2 1] for -9.6 or [1 2 1] for +16
657 */
658 cur_vit_mask = 6100;
659 upper = bin + 120;
660 lower = bin - 120;
661
662 for (i = 0; i < 123; i++) {
663 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
664 if ((abs(cur_vit_mask - bin)) < 75) {
665 mask_amt = 1;
666 } else {
667 mask_amt = 0;
668 }
669 if (cur_vit_mask < 0) {
670 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
671 } else {
672 mask_p[cur_vit_mask / 100] = mask_amt;
673 }
674 }
675 cur_vit_mask -= 100;
676 }
677
678 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
679 | (mask_m[48] << 26) | (mask_m[49] << 24)
680 | (mask_m[50] << 22) | (mask_m[51] << 20)
681 | (mask_m[52] << 18) | (mask_m[53] << 16)
682 | (mask_m[54] << 14) | (mask_m[55] << 12)
683 | (mask_m[56] << 10) | (mask_m[57] << 8)
684 | (mask_m[58] << 6) | (mask_m[59] << 4)
685 | (mask_m[60] << 2) | (mask_m[61] << 0);
686 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
687 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
688
689 tmp_mask = (mask_m[31] << 28)
690 | (mask_m[32] << 26) | (mask_m[33] << 24)
691 | (mask_m[34] << 22) | (mask_m[35] << 20)
692 | (mask_m[36] << 18) | (mask_m[37] << 16)
693 | (mask_m[48] << 14) | (mask_m[39] << 12)
694 | (mask_m[40] << 10) | (mask_m[41] << 8)
695 | (mask_m[42] << 6) | (mask_m[43] << 4)
696 | (mask_m[44] << 2) | (mask_m[45] << 0);
697 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
698 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
699
700 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
701 | (mask_m[18] << 26) | (mask_m[18] << 24)
702 | (mask_m[20] << 22) | (mask_m[20] << 20)
703 | (mask_m[22] << 18) | (mask_m[22] << 16)
704 | (mask_m[24] << 14) | (mask_m[24] << 12)
705 | (mask_m[25] << 10) | (mask_m[26] << 8)
706 | (mask_m[27] << 6) | (mask_m[28] << 4)
707 | (mask_m[29] << 2) | (mask_m[30] << 0);
708 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
709 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
710
711 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28)
712 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24)
713 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20)
714 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16)
715 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12)
716 | (mask_m[10] << 10) | (mask_m[11] << 8)
717 | (mask_m[12] << 6) | (mask_m[13] << 4)
718 | (mask_m[14] << 2) | (mask_m[15] << 0);
719 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
720 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
721
722 tmp_mask = (mask_p[15] << 28)
723 | (mask_p[14] << 26) | (mask_p[13] << 24)
724 | (mask_p[12] << 22) | (mask_p[11] << 20)
725 | (mask_p[10] << 18) | (mask_p[ 9] << 16)
726 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12)
727 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8)
728 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4)
729 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0);
730 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
731 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
732
733 tmp_mask = (mask_p[30] << 28)
734 | (mask_p[29] << 26) | (mask_p[28] << 24)
735 | (mask_p[27] << 22) | (mask_p[26] << 20)
736 | (mask_p[25] << 18) | (mask_p[24] << 16)
737 | (mask_p[23] << 14) | (mask_p[22] << 12)
738 | (mask_p[21] << 10) | (mask_p[20] << 8)
739 | (mask_p[19] << 6) | (mask_p[18] << 4)
740 | (mask_p[17] << 2) | (mask_p[16] << 0);
741 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
742 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
743
744 tmp_mask = (mask_p[45] << 28)
745 | (mask_p[44] << 26) | (mask_p[43] << 24)
746 | (mask_p[42] << 22) | (mask_p[41] << 20)
747 | (mask_p[40] << 18) | (mask_p[39] << 16)
748 | (mask_p[38] << 14) | (mask_p[37] << 12)
749 | (mask_p[36] << 10) | (mask_p[35] << 8)
750 | (mask_p[34] << 6) | (mask_p[33] << 4)
751 | (mask_p[32] << 2) | (mask_p[31] << 0);
752 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
753 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
754
755 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
756 | (mask_p[59] << 26) | (mask_p[58] << 24)
757 | (mask_p[57] << 22) | (mask_p[56] << 20)
758 | (mask_p[55] << 18) | (mask_p[54] << 16)
759 | (mask_p[53] << 14) | (mask_p[52] << 12)
760 | (mask_p[51] << 10) | (mask_p[50] << 8)
761 | (mask_p[49] << 6) | (mask_p[48] << 4)
762 | (mask_p[47] << 2) | (mask_p[46] << 0);
763 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
764 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
765 }
766
767 /*
768 * Fill all software cached or static hardware state information.
769 * Return failure if capabilities are to come from EEPROM and
770 * cannot be read.
771 */
772 HAL_BOOL
ar5416FillCapabilityInfo(struct ath_hal * ah)773 ar5416FillCapabilityInfo(struct ath_hal *ah)
774 {
775 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
776 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps;
777 uint16_t val;
778
779 /* Construct wireless mode from EEPROM */
780 pCap->halWirelessModes = 0;
781 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
782 pCap->halWirelessModes |= HAL_MODE_11A
783 | HAL_MODE_11NA_HT20
784 | HAL_MODE_11NA_HT40PLUS
785 | HAL_MODE_11NA_HT40MINUS
786 ;
787 }
788 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) {
789 pCap->halWirelessModes |= HAL_MODE_11G
790 | HAL_MODE_11NG_HT20
791 | HAL_MODE_11NG_HT40PLUS
792 | HAL_MODE_11NG_HT40MINUS
793 ;
794 pCap->halWirelessModes |= HAL_MODE_11A
795 | HAL_MODE_11NA_HT20
796 | HAL_MODE_11NA_HT40PLUS
797 | HAL_MODE_11NA_HT40MINUS
798 ;
799 }
800
801 pCap->halLow2GhzChan = 2312;
802 pCap->halHigh2GhzChan = 2732;
803
804 pCap->halLow5GhzChan = 4915;
805 pCap->halHigh5GhzChan = 6100;
806
807 pCap->halCipherCkipSupport = AH_FALSE;
808 pCap->halCipherTkipSupport = AH_TRUE;
809 pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES);
810
811 pCap->halMicCkipSupport = AH_FALSE;
812 pCap->halMicTkipSupport = AH_TRUE;
813 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES);
814 /*
815 * Starting with Griffin TX+RX mic keys can be combined
816 * in one key cache slot.
817 */
818 pCap->halTkipMicTxRxKeySupport = AH_TRUE;
819 pCap->halChanSpreadSupport = AH_TRUE;
820 pCap->halSleepAfterBeaconBroken = AH_TRUE;
821
822 pCap->halCompressSupport = AH_FALSE;
823 pCap->halBurstSupport = AH_TRUE;
824 pCap->halFastFramesSupport = AH_FALSE; /* XXX? */
825 pCap->halChapTuningSupport = AH_TRUE;
826 pCap->halTurboPrimeSupport = AH_TRUE;
827
828 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G;
829
830 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */
831 pCap->halVEOLSupport = AH_TRUE;
832 pCap->halBssIdMaskSupport = AH_TRUE;
833 pCap->halMcastKeySrchSupport = AH_TRUE; /* Works on AR5416 and later */
834 pCap->halTsfAddSupport = AH_TRUE;
835 pCap->hal4AddrAggrSupport = AH_FALSE; /* Broken in Owl */
836
837 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK)
838 pCap->halTotalQueues = val;
839 else
840 pCap->halTotalQueues = HAL_NUM_TX_QUEUES;
841
842 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK)
843 pCap->halKeyCacheSize = val;
844 else
845 pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE;
846
847 /* XXX not needed */
848 pCap->halChanHalfRate = AH_FALSE; /* XXX ? */
849 pCap->halChanQuarterRate = AH_FALSE; /* XXX ? */
850
851 pCap->halTstampPrecision = 32;
852 pCap->halHwPhyCounterSupport = AH_TRUE;
853 pCap->halIntrMask = HAL_INT_COMMON
854 | HAL_INT_RX
855 | HAL_INT_TX
856 | HAL_INT_FATAL
857 | HAL_INT_BNR
858 | HAL_INT_BMISC
859 | HAL_INT_DTIMSYNC
860 | HAL_INT_TSFOOR
861 | HAL_INT_CST
862 | HAL_INT_GTT
863 ;
864
865 pCap->halFastCCSupport = AH_TRUE;
866 pCap->halNumGpioPins = 6;
867 pCap->halWowSupport = AH_FALSE;
868 pCap->halWowMatchPatternExact = AH_FALSE;
869 pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */
870 pCap->halAutoSleepSupport = AH_FALSE;
871 pCap->hal4kbSplitTransSupport = AH_TRUE;
872 /* Disable this so Block-ACK works correctly */
873 pCap->halHasRxSelfLinkedTail = AH_FALSE;
874 #if 0 /* XXX not yet */
875 pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ);
876 pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ);
877 #endif
878 pCap->halHTSupport = AH_TRUE;
879 pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL);
880 /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */
881 pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL);
882 /* AR5416 may have 3 antennas but is a 2x2 stream device */
883 pCap->halTxStreams = 2;
884 pCap->halRxStreams = 2;
885 pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */
886 pCap->halMbssidAggrSupport = AH_FALSE; /* Broken on Owl */
887 pCap->halForcePpmSupport = AH_TRUE;
888 pCap->halEnhancedPmSupport = AH_TRUE;
889 pCap->halBssidMatchSupport = AH_TRUE;
890 pCap->halGTTSupport = AH_TRUE;
891 pCap->halCSTSupport = AH_TRUE;
892 pCap->halEnhancedDfsSupport = AH_FALSE;
893 /* Hardware supports 32 bit TSF values in the RX descriptor */
894 pCap->halHasLongRxDescTsf = AH_TRUE;
895
896 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&
897 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {
898 /* NB: enabled by default */
899 ahpriv->ah_rfkillEnabled = AH_TRUE;
900 pCap->halRfSilentSupport = AH_TRUE;
901 }
902
903 ahpriv->ah_rxornIsFatal = AH_FALSE;
904
905 return AH_TRUE;
906 }
907
908 static const char*
ar5416Probe(uint16_t vendorid,uint16_t devid)909 ar5416Probe(uint16_t vendorid, uint16_t devid)
910 {
911 if (vendorid == ATHEROS_VENDOR_ID &&
912 (devid == AR5416_DEVID_PCI || devid == AR5416_DEVID_PCIE))
913 return "Atheros 5416";
914 return AH_NULL;
915 }
916 AH_CHIP(AR5416, ar5416Probe, ar5416Attach);
917