1 /*
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD: stable/9/sys/dev/ath/ath_hal/ar5212/ar5212_recv.c 220423 2011-04-07 13:14:51Z adrian $
18 */
19 #include "opt_ah.h"
20
21 #include "ah.h"
22 #include "ah_internal.h"
23
24 #include "ar5212/ar5212.h"
25 #include "ar5212/ar5212reg.h"
26 #include "ar5212/ar5212desc.h"
27
28 /*
29 * Get the RXDP.
30 */
31 uint32_t
ar5212GetRxDP(struct ath_hal * ath)32 ar5212GetRxDP(struct ath_hal *ath)
33 {
34 return OS_REG_READ(ath, AR_RXDP);
35 }
36
37 /*
38 * Set the RxDP.
39 */
40 void
ar5212SetRxDP(struct ath_hal * ah,uint32_t rxdp)41 ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp)
42 {
43 OS_REG_WRITE(ah, AR_RXDP, rxdp);
44 HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
45 }
46
47 /*
48 * Set Receive Enable bits.
49 */
50 void
ar5212EnableReceive(struct ath_hal * ah)51 ar5212EnableReceive(struct ath_hal *ah)
52 {
53 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
54 }
55
56 /*
57 * Stop Receive at the DMA engine
58 */
59 HAL_BOOL
ar5212StopDmaReceive(struct ath_hal * ah)60 ar5212StopDmaReceive(struct ath_hal *ah)
61 {
62 OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP);
63 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
64 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
65 OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP_ERR);
66 #ifdef AH_DEBUG
67 ath_hal_printf(ah, "%s: dma failed to stop in 10ms\n"
68 "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
69 __func__,
70 OS_REG_READ(ah, AR_CR),
71 OS_REG_READ(ah, AR_DIAG_SW));
72 #endif
73 return AH_FALSE;
74 } else {
75 return AH_TRUE;
76 }
77 }
78
79 /*
80 * Start Transmit at the PCU engine (unpause receive)
81 */
82 void
ar5212StartPcuReceive(struct ath_hal * ah)83 ar5212StartPcuReceive(struct ath_hal *ah)
84 {
85 struct ath_hal_private *ahp = AH_PRIVATE(ah);
86
87 OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_PCU_START);
88 OS_REG_WRITE(ah, AR_DIAG_SW,
89 OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS);
90 ar5212EnableMibCounters(ah);
91 /* NB: restore current settings */
92 ar5212AniReset(ah, ahp->ah_curchan, ahp->ah_opmode, AH_TRUE);
93 }
94
95 /*
96 * Stop Transmit at the PCU engine (pause receive)
97 */
98 void
ar5212StopPcuReceive(struct ath_hal * ah)99 ar5212StopPcuReceive(struct ath_hal *ah)
100 {
101 OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_PCU_STOP);
102 OS_REG_WRITE(ah, AR_DIAG_SW,
103 OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_RX_DIS);
104 ar5212DisableMibCounters(ah);
105 }
106
107 /*
108 * Set multicast filter 0 (lower 32-bits)
109 * filter 1 (upper 32-bits)
110 */
111 void
ar5212SetMulticastFilter(struct ath_hal * ah,uint32_t filter0,uint32_t filter1)112 ar5212SetMulticastFilter(struct ath_hal *ah, uint32_t filter0, uint32_t filter1)
113 {
114 OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);
115 OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);
116 }
117
118 /*
119 * Clear multicast filter by index
120 */
121 HAL_BOOL
ar5212ClrMulticastFilterIndex(struct ath_hal * ah,uint32_t ix)122 ar5212ClrMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
123 {
124 uint32_t val;
125
126 if (ix >= 64)
127 return AH_FALSE;
128 if (ix >= 32) {
129 val = OS_REG_READ(ah, AR_MCAST_FIL1);
130 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));
131 } else {
132 val = OS_REG_READ(ah, AR_MCAST_FIL0);
133 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));
134 }
135 return AH_TRUE;
136 }
137
138 /*
139 * Set multicast filter by index
140 */
141 HAL_BOOL
ar5212SetMulticastFilterIndex(struct ath_hal * ah,uint32_t ix)142 ar5212SetMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
143 {
144 uint32_t val;
145
146 if (ix >= 64)
147 return AH_FALSE;
148 if (ix >= 32) {
149 val = OS_REG_READ(ah, AR_MCAST_FIL1);
150 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))));
151 } else {
152 val = OS_REG_READ(ah, AR_MCAST_FIL0);
153 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix)));
154 }
155 return AH_TRUE;
156 }
157
158 /*
159 * Get the receive filter.
160 */
161 uint32_t
ar5212GetRxFilter(struct ath_hal * ah)162 ar5212GetRxFilter(struct ath_hal *ah)
163 {
164 uint32_t bits = OS_REG_READ(ah, AR_RX_FILTER);
165 uint32_t phybits = OS_REG_READ(ah, AR_PHY_ERR);
166 if (phybits & AR_PHY_ERR_RADAR)
167 bits |= HAL_RX_FILTER_PHYRADAR;
168 if (phybits & (AR_PHY_ERR_OFDM_TIMING|AR_PHY_ERR_CCK_TIMING))
169 bits |= HAL_RX_FILTER_PHYERR;
170 if (AH_PRIVATE(ah)->ah_caps.halBssidMatchSupport &&
171 (AH5212(ah)->ah_miscMode & AR_MISC_MODE_BSSID_MATCH_FORCE))
172 bits |= HAL_RX_FILTER_BSSID;
173 return bits;
174 }
175
176 /*
177 * Set the receive filter.
178 */
179 void
ar5212SetRxFilter(struct ath_hal * ah,uint32_t bits)180 ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits)
181 {
182 struct ath_hal_5212 *ahp = AH5212(ah);
183 uint32_t phybits;
184
185 OS_REG_WRITE(ah, AR_RX_FILTER,
186 bits &~ (HAL_RX_FILTER_PHYRADAR|HAL_RX_FILTER_PHYERR|
187 HAL_RX_FILTER_BSSID));
188 phybits = 0;
189 if (bits & HAL_RX_FILTER_PHYRADAR)
190 phybits |= AR_PHY_ERR_RADAR;
191 if (bits & HAL_RX_FILTER_PHYERR)
192 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
193 OS_REG_WRITE(ah, AR_PHY_ERR, phybits);
194 if (phybits) {
195 OS_REG_WRITE(ah, AR_RXCFG,
196 OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
197 } else {
198 OS_REG_WRITE(ah, AR_RXCFG,
199 OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);
200 }
201 if (AH_PRIVATE(ah)->ah_caps.halBssidMatchSupport) {
202 if (bits & HAL_RX_FILTER_BSSID)
203 ahp->ah_miscMode |= AR_MISC_MODE_BSSID_MATCH_FORCE;
204 else
205 ahp->ah_miscMode &= ~AR_MISC_MODE_BSSID_MATCH_FORCE;
206 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
207 }
208 }
209
210 /*
211 * Initialize RX descriptor, by clearing the status and setting
212 * the size (and any other flags).
213 */
214 HAL_BOOL
ar5212SetupRxDesc(struct ath_hal * ah,struct ath_desc * ds,uint32_t size,u_int flags)215 ar5212SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds,
216 uint32_t size, u_int flags)
217 {
218 struct ar5212_desc *ads = AR5212DESC(ds);
219
220 HALASSERT((size &~ AR_BufLen) == 0);
221
222 ads->ds_ctl0 = 0;
223 ads->ds_ctl1 = size & AR_BufLen;
224
225 if (flags & HAL_RXDESC_INTREQ)
226 ads->ds_ctl1 |= AR_RxInterReq;
227 ads->ds_rxstatus0 = ads->ds_rxstatus1 = 0;
228
229 return AH_TRUE;
230 }
231
232 /*
233 * Process an RX descriptor, and return the status to the caller.
234 * Copy some hardware specific items into the software portion
235 * of the descriptor.
236 *
237 * NB: the caller is responsible for validating the memory contents
238 * of the descriptor (e.g. flushing any cached copy).
239 */
240 HAL_STATUS
ar5212ProcRxDesc(struct ath_hal * ah,struct ath_desc * ds,uint32_t pa,struct ath_desc * nds,uint64_t tsf,struct ath_rx_status * rs)241 ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds,
242 uint32_t pa, struct ath_desc *nds, uint64_t tsf,
243 struct ath_rx_status *rs)
244 {
245 struct ar5212_desc *ads = AR5212DESC(ds);
246 struct ar5212_desc *ands = AR5212DESC(nds);
247
248 if ((ads->ds_rxstatus1 & AR_Done) == 0)
249 return HAL_EINPROGRESS;
250 /*
251 * Given the use of a self-linked tail be very sure that the hw is
252 * done with this descriptor; the hw may have done this descriptor
253 * once and picked it up again...make sure the hw has moved on.
254 */
255 if ((ands->ds_rxstatus1&AR_Done) == 0 && OS_REG_READ(ah, AR_RXDP) == pa)
256 return HAL_EINPROGRESS;
257
258 rs->rs_datalen = ads->ds_rxstatus0 & AR_DataLen;
259 rs->rs_tstamp = MS(ads->ds_rxstatus1, AR_RcvTimestamp);
260 rs->rs_status = 0;
261 /* XXX what about KeyCacheMiss? */
262 rs->rs_rssi = MS(ads->ds_rxstatus0, AR_RcvSigStrength);
263 /* discard invalid h/w rssi data */
264 if (rs->rs_rssi == -128)
265 rs->rs_rssi = 0;
266 if (ads->ds_rxstatus1 & AR_KeyIdxValid)
267 rs->rs_keyix = MS(ads->ds_rxstatus1, AR_KeyIdx);
268 else
269 rs->rs_keyix = HAL_RXKEYIX_INVALID;
270 /* NB: caller expected to do rate table mapping */
271 rs->rs_rate = MS(ads->ds_rxstatus0, AR_RcvRate);
272 rs->rs_antenna = MS(ads->ds_rxstatus0, AR_RcvAntenna);
273 rs->rs_more = (ads->ds_rxstatus0 & AR_More) ? 1 : 0;
274
275 if ((ads->ds_rxstatus1 & AR_FrmRcvOK) == 0) {
276 /*
277 * These four bits should not be set together. The
278 * 5212 spec states a Michael error can only occur if
279 * DecryptCRCErr not set (and TKIP is used). Experience
280 * indicates however that you can also get Michael errors
281 * when a CRC error is detected, but these are specious.
282 * Consequently we filter them out here so we don't
283 * confuse and/or complicate drivers.
284 */
285 if (ads->ds_rxstatus1 & AR_CRCErr)
286 rs->rs_status |= HAL_RXERR_CRC;
287 else if (ads->ds_rxstatus1 & AR_PHYErr) {
288 u_int phyerr;
289
290 rs->rs_status |= HAL_RXERR_PHY;
291 phyerr = MS(ads->ds_rxstatus1, AR_PHYErrCode);
292 rs->rs_phyerr = phyerr;
293 if (!AH5212(ah)->ah_hasHwPhyCounters &&
294 phyerr != HAL_PHYERR_RADAR)
295 ar5212AniPhyErrReport(ah, rs);
296 } else if (ads->ds_rxstatus1 & AR_DecryptCRCErr)
297 rs->rs_status |= HAL_RXERR_DECRYPT;
298 else if (ads->ds_rxstatus1 & AR_MichaelErr)
299 rs->rs_status |= HAL_RXERR_MIC;
300 }
301 return HAL_OK;
302 }
303