1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __AMDGPU_OBJECT_H__
29 #define __AMDGPU_OBJECT_H__
30
31 #include <drm/amdgpu_drm.h>
32 #include "amdgpu.h"
33 #include "amdgpu_res_cursor.h"
34
35 #ifdef CONFIG_MMU_NOTIFIER
36 #include <linux/mmu_notifier.h>
37 #endif
38
39 #define AMDGPU_BO_INVALID_OFFSET LONG_MAX
40 #define AMDGPU_BO_MAX_PLACEMENTS 3
41
42 /* BO flag to indicate a KFD userptr BO */
43 #define AMDGPU_AMDKFD_CREATE_USERPTR_BO (1ULL << 63)
44
45 #define to_amdgpu_bo_user(abo) container_of((abo), struct amdgpu_bo_user, bo)
46 #define to_amdgpu_bo_vm(abo) container_of((abo), struct amdgpu_bo_vm, bo)
47
48 struct amdgpu_bo_param {
49 unsigned long size;
50 int byte_align;
51 u32 bo_ptr_size;
52 u32 domain;
53 u32 preferred_domain;
54 u64 flags;
55 enum ttm_bo_type type;
56 bool no_wait_gpu;
57 struct dma_resv *resv;
58 void (*destroy)(struct ttm_buffer_object *bo);
59 /* xcp partition number plus 1, 0 means any partition */
60 int8_t xcp_id_plus1;
61 };
62
63 /* bo virtual addresses in a vm */
64 struct amdgpu_bo_va_mapping {
65 struct amdgpu_bo_va *bo_va;
66 struct list_head list;
67 struct rb_node rb;
68 uint64_t start;
69 uint64_t last;
70 uint64_t __subtree_last;
71 uint64_t offset;
72 uint64_t flags;
73 };
74
75 /* User space allocated BO in a VM */
76 struct amdgpu_bo_va {
77 struct amdgpu_vm_bo_base base;
78
79 /* protected by bo being reserved */
80 unsigned ref_count;
81
82 /* all other members protected by the VM PD being reserved */
83 struct dma_fence *last_pt_update;
84
85 /* mappings for this bo_va */
86 struct list_head invalids;
87 struct list_head valids;
88
89 /* If the mappings are cleared or filled */
90 bool cleared;
91
92 bool is_xgmi;
93
94 /*
95 * protected by vm reservation lock
96 * if non-zero, cannot unmap from GPU because user queues may still access it
97 */
98 unsigned int queue_refcount;
99 };
100
101 struct amdgpu_bo {
102 /* Protected by tbo.reserved */
103 u32 preferred_domains;
104 u32 allowed_domains;
105 struct ttm_place placements[AMDGPU_BO_MAX_PLACEMENTS];
106 struct ttm_placement placement;
107 struct ttm_buffer_object tbo;
108 struct ttm_bo_kmap_obj kmap;
109 u64 flags;
110 /* per VM structure for page tables and with virtual addresses */
111 struct amdgpu_vm_bo_base *vm_bo;
112 /* Constant after initialization */
113 struct amdgpu_device *adev;
114 struct amdgpu_bo *parent;
115
116 #ifdef CONFIG_MMU_NOTIFIER
117 struct mmu_interval_notifier notifier;
118 #endif
119 struct kgd_mem *kfd_bo;
120
121 /*
122 * For GPUs with spatial partitioning, xcp partition number, -1 means
123 * any partition. For other ASICs without spatial partition, always 0
124 * for memory accounting.
125 */
126 int8_t xcp_id;
127 };
128
129 struct amdgpu_bo_user {
130 struct amdgpu_bo bo;
131 u64 tiling_flags;
132 u64 metadata_flags;
133 void *metadata;
134 u32 metadata_size;
135
136 };
137
138 struct amdgpu_bo_vm {
139 struct amdgpu_bo bo;
140 struct amdgpu_vm_bo_base entries[];
141 };
142
143 struct amdgpu_mem_stats {
144 /* current VRAM usage, includes visible VRAM */
145 uint64_t vram;
146 /* current shared VRAM usage, includes visible VRAM */
147 uint64_t vram_shared;
148 /* current visible VRAM usage */
149 uint64_t visible_vram;
150 /* current GTT usage */
151 uint64_t gtt;
152 /* current shared GTT usage */
153 uint64_t gtt_shared;
154 /* current system memory usage */
155 uint64_t cpu;
156 /* current shared system memory usage */
157 uint64_t cpu_shared;
158 /* sum of evicted buffers, includes visible VRAM */
159 uint64_t evicted_vram;
160 /* sum of evicted buffers due to CPU access */
161 uint64_t evicted_visible_vram;
162 /* how much userspace asked for, includes vis.VRAM */
163 uint64_t requested_vram;
164 /* how much userspace asked for */
165 uint64_t requested_visible_vram;
166 /* how much userspace asked for */
167 uint64_t requested_gtt;
168 };
169
ttm_to_amdgpu_bo(struct ttm_buffer_object * tbo)170 static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object *tbo)
171 {
172 return container_of(tbo, struct amdgpu_bo, tbo);
173 }
174
175 /**
176 * amdgpu_mem_type_to_domain - return domain corresponding to mem_type
177 * @mem_type: ttm memory type
178 *
179 * Returns corresponding domain of the ttm mem_type
180 */
amdgpu_mem_type_to_domain(u32 mem_type)181 static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type)
182 {
183 switch (mem_type) {
184 case TTM_PL_VRAM:
185 return AMDGPU_GEM_DOMAIN_VRAM;
186 case TTM_PL_TT:
187 return AMDGPU_GEM_DOMAIN_GTT;
188 case TTM_PL_SYSTEM:
189 return AMDGPU_GEM_DOMAIN_CPU;
190 case AMDGPU_PL_GDS:
191 return AMDGPU_GEM_DOMAIN_GDS;
192 case AMDGPU_PL_GWS:
193 return AMDGPU_GEM_DOMAIN_GWS;
194 case AMDGPU_PL_OA:
195 return AMDGPU_GEM_DOMAIN_OA;
196 case AMDGPU_PL_DOORBELL:
197 return AMDGPU_GEM_DOMAIN_DOORBELL;
198 default:
199 break;
200 }
201 return 0;
202 }
203
204 /**
205 * amdgpu_bo_reserve - reserve bo
206 * @bo: bo structure
207 * @no_intr: don't return -ERESTARTSYS on pending signal
208 *
209 * Returns:
210 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
211 * a signal. Release all buffer reservations and return to user-space.
212 */
amdgpu_bo_reserve(struct amdgpu_bo * bo,bool no_intr)213 static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr)
214 {
215 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
216 int r;
217
218 r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL);
219 if (unlikely(r != 0)) {
220 if (r != -ERESTARTSYS)
221 dev_err(adev->dev, "%p reserve failed\n", bo);
222 return r;
223 }
224 return 0;
225 }
226
amdgpu_bo_unreserve(struct amdgpu_bo * bo)227 static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo)
228 {
229 ttm_bo_unreserve(&bo->tbo);
230 }
231
amdgpu_bo_size(struct amdgpu_bo * bo)232 static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo)
233 {
234 return bo->tbo.base.size;
235 }
236
amdgpu_bo_ngpu_pages(struct amdgpu_bo * bo)237 static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo)
238 {
239 return bo->tbo.base.size / AMDGPU_GPU_PAGE_SIZE;
240 }
241
amdgpu_bo_gpu_page_alignment(struct amdgpu_bo * bo)242 static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo)
243 {
244 return (bo->tbo.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
245 }
246
247 /**
248 * amdgpu_bo_mmap_offset - return mmap offset of bo
249 * @bo: amdgpu object for which we query the offset
250 *
251 * Returns mmap offset of the object.
252 */
amdgpu_bo_mmap_offset(struct amdgpu_bo * bo)253 static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)
254 {
255 return drm_vma_node_offset_addr(&bo->tbo.base.vma_node);
256 }
257
258 /**
259 * amdgpu_bo_explicit_sync - return whether the bo is explicitly synced
260 */
amdgpu_bo_explicit_sync(struct amdgpu_bo * bo)261 static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)
262 {
263 return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
264 }
265
266 /**
267 * amdgpu_bo_encrypted - test if the BO is encrypted
268 * @bo: pointer to a buffer object
269 *
270 * Return true if the buffer object is encrypted, false otherwise.
271 */
amdgpu_bo_encrypted(struct amdgpu_bo * bo)272 static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo)
273 {
274 return bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED;
275 }
276
277 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
278 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
279
280 int amdgpu_bo_create(struct amdgpu_device *adev,
281 struct amdgpu_bo_param *bp,
282 struct amdgpu_bo **bo_ptr);
283 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
284 unsigned long size, int align,
285 u32 domain, struct amdgpu_bo **bo_ptr,
286 u64 *gpu_addr, void **cpu_addr);
287 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
288 unsigned long size, int align,
289 u32 domain, struct amdgpu_bo **bo_ptr,
290 u64 *gpu_addr, void **cpu_addr);
291 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
292 uint64_t offset, uint64_t size,
293 struct amdgpu_bo **bo_ptr, void **cpu_addr);
294 int amdgpu_bo_create_user(struct amdgpu_device *adev,
295 struct amdgpu_bo_param *bp,
296 struct amdgpu_bo_user **ubo_ptr);
297 int amdgpu_bo_create_vm(struct amdgpu_device *adev,
298 struct amdgpu_bo_param *bp,
299 struct amdgpu_bo_vm **ubo_ptr);
300 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
301 void **cpu_addr);
302 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
303 void *amdgpu_bo_kptr(struct amdgpu_bo *bo);
304 void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
305 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo);
306 void amdgpu_bo_unref(struct amdgpu_bo **bo);
307 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain);
308 void amdgpu_bo_unpin(struct amdgpu_bo *bo);
309 int amdgpu_bo_init(struct amdgpu_device *adev);
310 void amdgpu_bo_fini(struct amdgpu_device *adev);
311 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
312 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
313 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
314 uint32_t metadata_size, uint64_t flags);
315 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
316 size_t buffer_size, uint32_t *metadata_size,
317 uint64_t *flags);
318 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
319 bool evict,
320 struct ttm_resource *new_mem);
321 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo);
322 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
323 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
324 bool shared);
325 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv,
326 enum amdgpu_sync_mode sync_mode, void *owner,
327 bool intr);
328 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr);
329 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);
330 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo);
331 void amdgpu_bo_get_memory(struct amdgpu_bo *bo,
332 struct amdgpu_mem_stats *stats);
333 uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev,
334 uint32_t domain);
335
336 /*
337 * sub allocation
338 */
339 static inline struct amdgpu_sa_manager *
to_amdgpu_sa_manager(struct drm_suballoc_manager * manager)340 to_amdgpu_sa_manager(struct drm_suballoc_manager *manager)
341 {
342 return container_of(manager, struct amdgpu_sa_manager, base);
343 }
344
amdgpu_sa_bo_gpu_addr(struct drm_suballoc * sa_bo)345 static inline uint64_t amdgpu_sa_bo_gpu_addr(struct drm_suballoc *sa_bo)
346 {
347 return to_amdgpu_sa_manager(sa_bo->manager)->gpu_addr +
348 drm_suballoc_soffset(sa_bo);
349 }
350
amdgpu_sa_bo_cpu_addr(struct drm_suballoc * sa_bo)351 static inline void *amdgpu_sa_bo_cpu_addr(struct drm_suballoc *sa_bo)
352 {
353 return to_amdgpu_sa_manager(sa_bo->manager)->cpu_ptr +
354 drm_suballoc_soffset(sa_bo);
355 }
356
357 int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
358 struct amdgpu_sa_manager *sa_manager,
359 unsigned size, u32 align, u32 domain);
360 void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
361 struct amdgpu_sa_manager *sa_manager);
362 int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
363 struct amdgpu_sa_manager *sa_manager);
364 int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
365 struct drm_suballoc **sa_bo,
366 unsigned int size);
367 void amdgpu_sa_bo_free(struct amdgpu_device *adev,
368 struct drm_suballoc **sa_bo,
369 struct dma_fence *fence);
370 #if defined(CONFIG_DEBUG_FS)
371 void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
372 struct seq_file *m);
373 u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m);
374 #endif
375 void amdgpu_debugfs_sa_init(struct amdgpu_device *adev);
376
377 bool amdgpu_bo_support_uswc(u64 bo_flags);
378
379
380 #endif
381