1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 * Christian König
28 */
29 #include <linux/seq_file.h>
30 #include <linux/slab.h>
31 #include <linux/debugfs.h>
32 #include <drm/drmP.h>
33 #include <drm/amdgpu_drm.h>
34 #include "amdgpu.h"
35 #include "atom.h"
36
37 /*
38 * Rings
39 * Most engines on the GPU are fed via ring buffers. Ring
40 * buffers are areas of GPU accessible memory that the host
41 * writes commands into and the GPU reads commands out of.
42 * There is a rptr (read pointer) that determines where the
43 * GPU is currently reading, and a wptr (write pointer)
44 * which determines where the host has written. When the
45 * pointers are equal, the ring is idle. When the host
46 * writes commands to the ring buffer, it increments the
47 * wptr. The GPU then starts fetching commands and executes
48 * them until the pointers are equal again.
49 */
50 static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
51 struct amdgpu_ring *ring);
52 static void amdgpu_debugfs_ring_fini(struct amdgpu_ring *ring);
53
54 /**
55 * amdgpu_ring_alloc - allocate space on the ring buffer
56 *
57 * @adev: amdgpu_device pointer
58 * @ring: amdgpu_ring structure holding ring information
59 * @ndw: number of dwords to allocate in the ring buffer
60 *
61 * Allocate @ndw dwords in the ring buffer (all asics).
62 * Returns 0 on success, error on failure.
63 */
amdgpu_ring_alloc(struct amdgpu_ring * ring,unsigned ndw)64 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw)
65 {
66 /* Align requested size with padding so unlock_commit can
67 * pad safely */
68 ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask;
69
70 /* Make sure we aren't trying to allocate more space
71 * than the maximum for one submission
72 */
73 if (WARN_ON_ONCE(ndw > ring->max_dw))
74 return -ENOMEM;
75
76 ring->count_dw = ndw;
77 ring->wptr_old = ring->wptr;
78
79 if (ring->funcs->begin_use)
80 ring->funcs->begin_use(ring);
81
82 return 0;
83 }
84
85 /** amdgpu_ring_insert_nop - insert NOP packets
86 *
87 * @ring: amdgpu_ring structure holding ring information
88 * @count: the number of NOP packets to insert
89 *
90 * This is the generic insert_nop function for rings except SDMA
91 */
amdgpu_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)92 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
93 {
94 int i;
95
96 for (i = 0; i < count; i++)
97 amdgpu_ring_write(ring, ring->funcs->nop);
98 }
99
100 /** amdgpu_ring_generic_pad_ib - pad IB with NOP packets
101 *
102 * @ring: amdgpu_ring structure holding ring information
103 * @ib: IB to add NOP packets to
104 *
105 * This is the generic pad_ib function for rings except SDMA
106 */
amdgpu_ring_generic_pad_ib(struct amdgpu_ring * ring,struct amdgpu_ib * ib)107 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
108 {
109 while (ib->length_dw & ring->funcs->align_mask)
110 ib->ptr[ib->length_dw++] = ring->funcs->nop;
111 }
112
113 /**
114 * amdgpu_ring_commit - tell the GPU to execute the new
115 * commands on the ring buffer
116 *
117 * @adev: amdgpu_device pointer
118 * @ring: amdgpu_ring structure holding ring information
119 *
120 * Update the wptr (write pointer) to tell the GPU to
121 * execute new commands on the ring buffer (all asics).
122 */
amdgpu_ring_commit(struct amdgpu_ring * ring)123 void amdgpu_ring_commit(struct amdgpu_ring *ring)
124 {
125 uint32_t count;
126
127 /* We pad to match fetch size */
128 count = ring->funcs->align_mask + 1 -
129 (ring->wptr & ring->funcs->align_mask);
130 count %= ring->funcs->align_mask + 1;
131 ring->funcs->insert_nop(ring, count);
132
133 mb();
134 amdgpu_ring_set_wptr(ring);
135
136 if (ring->funcs->end_use)
137 ring->funcs->end_use(ring);
138
139 if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ)
140 amdgpu_ring_lru_touch(ring->adev, ring);
141 }
142
143 /**
144 * amdgpu_ring_undo - reset the wptr
145 *
146 * @ring: amdgpu_ring structure holding ring information
147 *
148 * Reset the driver's copy of the wptr (all asics).
149 */
amdgpu_ring_undo(struct amdgpu_ring * ring)150 void amdgpu_ring_undo(struct amdgpu_ring *ring)
151 {
152 ring->wptr = ring->wptr_old;
153
154 if (ring->funcs->end_use)
155 ring->funcs->end_use(ring);
156 }
157
158 /**
159 * amdgpu_ring_priority_put - restore a ring's priority
160 *
161 * @ring: amdgpu_ring structure holding the information
162 * @priority: target priority
163 *
164 * Release a request for executing at @priority
165 */
amdgpu_ring_priority_put(struct amdgpu_ring * ring,enum drm_sched_priority priority)166 void amdgpu_ring_priority_put(struct amdgpu_ring *ring,
167 enum drm_sched_priority priority)
168 {
169 int i;
170
171 if (!ring->funcs->set_priority)
172 return;
173
174 if (atomic_dec_return(&ring->num_jobs[priority]) > 0)
175 return;
176
177 /* no need to restore if the job is already at the lowest priority */
178 if (priority == DRM_SCHED_PRIORITY_NORMAL)
179 return;
180
181 mutex_lock(&ring->priority_mutex);
182 /* something higher prio is executing, no need to decay */
183 if (ring->priority > priority)
184 goto out_unlock;
185
186 /* decay priority to the next level with a job available */
187 for (i = priority; i >= DRM_SCHED_PRIORITY_MIN; i--) {
188 if (i == DRM_SCHED_PRIORITY_NORMAL
189 || atomic_read(&ring->num_jobs[i])) {
190 ring->priority = i;
191 ring->funcs->set_priority(ring, i);
192 break;
193 }
194 }
195
196 out_unlock:
197 mutex_unlock(&ring->priority_mutex);
198 }
199
200 /**
201 * amdgpu_ring_priority_get - change the ring's priority
202 *
203 * @ring: amdgpu_ring structure holding the information
204 * @priority: target priority
205 *
206 * Request a ring's priority to be raised to @priority (refcounted).
207 */
amdgpu_ring_priority_get(struct amdgpu_ring * ring,enum drm_sched_priority priority)208 void amdgpu_ring_priority_get(struct amdgpu_ring *ring,
209 enum drm_sched_priority priority)
210 {
211 if (!ring->funcs->set_priority)
212 return;
213
214 if (atomic_inc_return(&ring->num_jobs[priority]) <= 0)
215 return;
216
217 mutex_lock(&ring->priority_mutex);
218 if (priority <= ring->priority)
219 goto out_unlock;
220
221 ring->priority = priority;
222 ring->funcs->set_priority(ring, priority);
223
224 out_unlock:
225 mutex_unlock(&ring->priority_mutex);
226 }
227
228 /**
229 * amdgpu_ring_init - init driver ring struct.
230 *
231 * @adev: amdgpu_device pointer
232 * @ring: amdgpu_ring structure holding ring information
233 * @max_ndw: maximum number of dw for ring alloc
234 * @nop: nop packet for this ring
235 *
236 * Initialize the driver information for the selected ring (all asics).
237 * Returns 0 on success, error on failure.
238 */
amdgpu_ring_init(struct amdgpu_device * adev,struct amdgpu_ring * ring,unsigned max_dw,struct amdgpu_irq_src * irq_src,unsigned irq_type)239 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
240 unsigned max_dw, struct amdgpu_irq_src *irq_src,
241 unsigned irq_type)
242 {
243 int r, i;
244 int sched_hw_submission = amdgpu_sched_hw_submission;
245
246 /* Set the hw submission limit higher for KIQ because
247 * it's used for a number of gfx/compute tasks by both
248 * KFD and KGD which may have outstanding fences and
249 * it doesn't really use the gpu scheduler anyway;
250 * KIQ tasks get submitted directly to the ring.
251 */
252 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
253 sched_hw_submission = max(sched_hw_submission, 256);
254
255 if (ring->adev == NULL) {
256 if (adev->num_rings >= AMDGPU_MAX_RINGS)
257 return -EINVAL;
258
259 ring->adev = adev;
260 ring->idx = adev->num_rings++;
261 adev->rings[ring->idx] = ring;
262 r = amdgpu_fence_driver_init_ring(ring, sched_hw_submission);
263 if (r)
264 return r;
265 }
266
267 r = amdgpu_device_wb_get(adev, &ring->rptr_offs);
268 if (r) {
269 dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
270 return r;
271 }
272
273 r = amdgpu_device_wb_get(adev, &ring->wptr_offs);
274 if (r) {
275 dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
276 return r;
277 }
278
279 r = amdgpu_device_wb_get(adev, &ring->fence_offs);
280 if (r) {
281 dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r);
282 return r;
283 }
284
285 r = amdgpu_device_wb_get(adev, &ring->cond_exe_offs);
286 if (r) {
287 dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r);
288 return r;
289 }
290 ring->cond_exe_gpu_addr = adev->wb.gpu_addr + (ring->cond_exe_offs * 4);
291 ring->cond_exe_cpu_addr = &adev->wb.wb[ring->cond_exe_offs];
292 /* always set cond_exec_polling to CONTINUE */
293 *ring->cond_exe_cpu_addr = 1;
294
295 r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type);
296 if (r) {
297 dev_err(adev->dev, "failed initializing fences (%d).\n", r);
298 return r;
299 }
300
301 ring->ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission);
302
303 ring->buf_mask = (ring->ring_size / 4) - 1;
304 ring->ptr_mask = ring->funcs->support_64bit_ptrs ?
305 0xffffffffffffffff : ring->buf_mask;
306 /* Allocate ring buffer */
307 if (ring->ring_obj == NULL) {
308 r = amdgpu_bo_create_kernel(adev, ring->ring_size + ring->funcs->extra_dw, PAGE_SIZE,
309 AMDGPU_GEM_DOMAIN_GTT,
310 &ring->ring_obj,
311 (u64 *)&ring->gpu_addr,
312 (void **)&ring->ring);
313 if (r) {
314 dev_err(adev->dev, "(%d) ring create failed\n", r);
315 return r;
316 }
317 amdgpu_ring_clear_ring(ring);
318 }
319
320 ring->max_dw = max_dw;
321 ring->priority = DRM_SCHED_PRIORITY_NORMAL;
322 lockinit(&ring->priority_mutex, "agrpm", 0, LK_CANRECURSE);
323 INIT_LIST_HEAD(&ring->lru_list);
324 amdgpu_ring_lru_touch(adev, ring);
325
326 for (i = 0; i < DRM_SCHED_PRIORITY_MAX; ++i)
327 atomic_set(&ring->num_jobs[i], 0);
328
329 if (amdgpu_debugfs_ring_init(adev, ring)) {
330 DRM_ERROR("Failed to register debugfs file for rings !\n");
331 }
332
333 return 0;
334 }
335
336 /**
337 * amdgpu_ring_fini - tear down the driver ring struct.
338 *
339 * @adev: amdgpu_device pointer
340 * @ring: amdgpu_ring structure holding ring information
341 *
342 * Tear down the driver information for the selected ring (all asics).
343 */
amdgpu_ring_fini(struct amdgpu_ring * ring)344 void amdgpu_ring_fini(struct amdgpu_ring *ring)
345 {
346 ring->ready = false;
347
348 /* Not to finish a ring which is not initialized */
349 if (!(ring->adev) || !(ring->adev->rings[ring->idx]))
350 return;
351
352 amdgpu_device_wb_free(ring->adev, ring->rptr_offs);
353 amdgpu_device_wb_free(ring->adev, ring->wptr_offs);
354
355 amdgpu_device_wb_free(ring->adev, ring->cond_exe_offs);
356 amdgpu_device_wb_free(ring->adev, ring->fence_offs);
357
358 amdgpu_bo_free_kernel(&ring->ring_obj,
359 (u64 *)&ring->gpu_addr,
360 (void **)&ring->ring);
361
362 amdgpu_debugfs_ring_fini(ring);
363
364 dma_fence_put(ring->vmid_wait);
365 ring->vmid_wait = NULL;
366 ring->me = 0;
367
368 ring->adev->rings[ring->idx] = NULL;
369 }
370
amdgpu_ring_lru_touch_locked(struct amdgpu_device * adev,struct amdgpu_ring * ring)371 static void amdgpu_ring_lru_touch_locked(struct amdgpu_device *adev,
372 struct amdgpu_ring *ring)
373 {
374 /* list_move_tail handles the case where ring isn't part of the list */
375 list_move_tail(&ring->lru_list, &adev->ring_lru_list);
376 }
377
amdgpu_ring_is_blacklisted(struct amdgpu_ring * ring,int * blacklist,int num_blacklist)378 static bool amdgpu_ring_is_blacklisted(struct amdgpu_ring *ring,
379 int *blacklist, int num_blacklist)
380 {
381 int i;
382
383 for (i = 0; i < num_blacklist; i++) {
384 if (ring->idx == blacklist[i])
385 return true;
386 }
387
388 return false;
389 }
390
391 /**
392 * amdgpu_ring_lru_get - get the least recently used ring for a HW IP block
393 *
394 * @adev: amdgpu_device pointer
395 * @type: amdgpu_ring_type enum
396 * @blacklist: blacklisted ring ids array
397 * @num_blacklist: number of entries in @blacklist
398 * @lru_pipe_order: find a ring from the least recently used pipe
399 * @ring: output ring
400 *
401 * Retrieve the amdgpu_ring structure for the least recently used ring of
402 * a specific IP block (all asics).
403 * Returns 0 on success, error on failure.
404 */
amdgpu_ring_lru_get(struct amdgpu_device * adev,int type,int * blacklist,int num_blacklist,bool lru_pipe_order,struct amdgpu_ring ** ring)405 int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type,
406 int *blacklist, int num_blacklist,
407 bool lru_pipe_order, struct amdgpu_ring **ring)
408 {
409 struct amdgpu_ring *entry;
410
411 /* List is sorted in LRU order, find first entry corresponding
412 * to the desired HW IP */
413 *ring = NULL;
414 spin_lock(&adev->ring_lru_list_lock);
415 list_for_each_entry(entry, &adev->ring_lru_list, lru_list) {
416 if (entry->funcs->type != type)
417 continue;
418
419 if (amdgpu_ring_is_blacklisted(entry, blacklist, num_blacklist))
420 continue;
421
422 if (!*ring) {
423 *ring = entry;
424
425 /* We are done for ring LRU */
426 if (!lru_pipe_order)
427 break;
428 }
429
430 /* Move all rings on the same pipe to the end of the list */
431 if (entry->pipe == (*ring)->pipe)
432 amdgpu_ring_lru_touch_locked(adev, entry);
433 }
434
435 /* Move the ring we found to the end of the list */
436 if (*ring)
437 amdgpu_ring_lru_touch_locked(adev, *ring);
438
439 spin_unlock(&adev->ring_lru_list_lock);
440
441 if (!*ring) {
442 DRM_ERROR("Ring LRU contains no entries for ring type:%d\n", type);
443 return -EINVAL;
444 }
445
446 return 0;
447 }
448
449 /**
450 * amdgpu_ring_lru_touch - mark a ring as recently being used
451 *
452 * @adev: amdgpu_device pointer
453 * @ring: ring to touch
454 *
455 * Move @ring to the tail of the lru list
456 */
amdgpu_ring_lru_touch(struct amdgpu_device * adev,struct amdgpu_ring * ring)457 void amdgpu_ring_lru_touch(struct amdgpu_device *adev, struct amdgpu_ring *ring)
458 {
459 spin_lock(&adev->ring_lru_list_lock);
460 amdgpu_ring_lru_touch_locked(adev, ring);
461 spin_unlock(&adev->ring_lru_list_lock);
462 }
463
464 /**
465 * amdgpu_ring_emit_reg_write_reg_wait_helper - ring helper
466 *
467 * @adev: amdgpu_device pointer
468 * @reg0: register to write
469 * @reg1: register to wait on
470 * @ref: reference value to write/wait on
471 * @mask: mask to wait on
472 *
473 * Helper for rings that don't support write and wait in a
474 * single oneshot packet.
475 */
amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring * ring,uint32_t reg0,uint32_t reg1,uint32_t ref,uint32_t mask)476 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
477 uint32_t reg0, uint32_t reg1,
478 uint32_t ref, uint32_t mask)
479 {
480 amdgpu_ring_emit_wreg(ring, reg0, ref);
481 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
482 }
483
484 /*
485 * Debugfs info
486 */
487 #if defined(CONFIG_DEBUG_FS)
488
489 /* Layout of file is 12 bytes consisting of
490 * - rptr
491 * - wptr
492 * - driver's copy of wptr
493 *
494 * followed by n-words of ring data
495 */
amdgpu_debugfs_ring_read(struct file * f,char __user * buf,size_t size,loff_t * pos)496 static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,
497 size_t size, loff_t *pos)
498 {
499 struct amdgpu_ring *ring = file_inode(f)->i_private;
500 int r, i;
501 uint32_t value, result, early[3];
502
503 if (*pos & 3 || size & 3)
504 return -EINVAL;
505
506 result = 0;
507
508 if (*pos < 12) {
509 early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask;
510 early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask;
511 early[2] = ring->wptr & ring->buf_mask;
512 for (i = *pos / 4; i < 3 && size; i++) {
513 r = put_user(early[i], (uint32_t *)buf);
514 if (r)
515 return r;
516 buf += 4;
517 result += 4;
518 size -= 4;
519 *pos += 4;
520 }
521 }
522
523 while (size) {
524 if (*pos >= (ring->ring_size + 12))
525 return result;
526
527 value = ring->ring[(*pos - 12)/4];
528 r = put_user(value, (uint32_t*)buf);
529 if (r)
530 return r;
531 buf += 4;
532 result += 4;
533 size -= 4;
534 *pos += 4;
535 }
536
537 return result;
538 }
539
540 static const struct file_operations amdgpu_debugfs_ring_fops = {
541 .owner = THIS_MODULE,
542 .read = amdgpu_debugfs_ring_read,
543 .llseek = default_llseek
544 };
545
546 #endif
547
amdgpu_debugfs_ring_init(struct amdgpu_device * adev,struct amdgpu_ring * ring)548 static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
549 struct amdgpu_ring *ring)
550 {
551 #if defined(CONFIG_DEBUG_FS)
552 struct drm_minor *minor = adev->ddev->primary;
553 struct dentry *ent, *root = minor->debugfs_root;
554 char name[32];
555
556 sprintf(name, "amdgpu_ring_%s", ring->name);
557
558 ent = debugfs_create_file(name,
559 S_IFREG | S_IRUGO, root,
560 ring, &amdgpu_debugfs_ring_fops);
561 if (!ent)
562 return -ENOMEM;
563
564 i_size_write(ent->d_inode, ring->ring_size + 12);
565 ring->ent = ent;
566 #endif
567 return 0;
568 }
569
amdgpu_debugfs_ring_fini(struct amdgpu_ring * ring)570 static void amdgpu_debugfs_ring_fini(struct amdgpu_ring *ring)
571 {
572 #if defined(CONFIG_DEBUG_FS)
573 debugfs_remove(ring->ent);
574 #endif
575 }
576