1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29 /**
30 * DOC: Interrupt Handling
31 *
32 * Interrupts generated within GPU hardware raise interrupt requests that are
33 * passed to amdgpu IRQ handler which is responsible for detecting source and
34 * type of the interrupt and dispatching matching handlers. If handling an
35 * interrupt requires calling kernel functions that may sleep processing is
36 * dispatched to work handlers.
37 *
38 * If MSI functionality is not disabled by module parameter then MSI
39 * support will be enabled.
40 *
41 * For GPU interrupt sources that may be driven by another driver, IRQ domain
42 * support is used (with mapping between virtual and hardware IRQs).
43 */
44
45 #include <linux/irq.h>
46 #include <linux/pci.h>
47
48 #include <drm/drm_vblank.h>
49 #include <drm/amdgpu_drm.h>
50 #include <drm/drm_drv.h>
51 #include "amdgpu.h"
52 #include "amdgpu_ih.h"
53 #include "atom.h"
54 #include "amdgpu_connectors.h"
55 #include "amdgpu_trace.h"
56 #include "amdgpu_amdkfd.h"
57 #include "amdgpu_ras.h"
58
59 #include <linux/pm_runtime.h>
60
61 #ifdef CONFIG_DRM_AMD_DC
62 #include "amdgpu_dm_irq.h"
63 #endif
64
65 #define AMDGPU_WAIT_IDLE_TIMEOUT 200
66
67 const char *soc15_ih_clientid_name[] = {
68 "IH",
69 "SDMA2 or ACP",
70 "ATHUB",
71 "BIF",
72 "SDMA3 or DCE",
73 "SDMA4 or ISP",
74 "VMC1 or PCIE0",
75 "RLC",
76 "SDMA0",
77 "SDMA1",
78 "SE0SH",
79 "SE1SH",
80 "SE2SH",
81 "SE3SH",
82 "VCN1 or UVD1",
83 "THM",
84 "VCN or UVD",
85 "SDMA5 or VCE0",
86 "VMC",
87 "SDMA6 or XDMA",
88 "GRBM_CP",
89 "ATS",
90 "ROM_SMUIO",
91 "DF",
92 "SDMA7 or VCE1",
93 "PWR",
94 "reserved",
95 "UTCL2",
96 "EA",
97 "UTCL2LOG",
98 "MP0",
99 "MP1"
100 };
101
102 const int node_id_to_phys_map[NODEID_MAX] = {
103 [AID0_NODEID] = 0,
104 [XCD0_NODEID] = 0,
105 [XCD1_NODEID] = 1,
106 [AID1_NODEID] = 1,
107 [XCD2_NODEID] = 2,
108 [XCD3_NODEID] = 3,
109 [AID2_NODEID] = 2,
110 [XCD4_NODEID] = 4,
111 [XCD5_NODEID] = 5,
112 [AID3_NODEID] = 3,
113 [XCD6_NODEID] = 6,
114 [XCD7_NODEID] = 7,
115 };
116
117 /**
118 * amdgpu_irq_disable_all - disable *all* interrupts
119 *
120 * @adev: amdgpu device pointer
121 *
122 * Disable all types of interrupts from all sources.
123 */
amdgpu_irq_disable_all(struct amdgpu_device * adev)124 void amdgpu_irq_disable_all(struct amdgpu_device *adev)
125 {
126 unsigned long irqflags;
127 unsigned int i, j, k;
128 int r;
129
130 spin_lock_irqsave(&adev->irq.lock, irqflags);
131 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
132 if (!adev->irq.client[i].sources)
133 continue;
134
135 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
136 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
137
138 if (!src || !src->funcs->set || !src->num_types)
139 continue;
140
141 for (k = 0; k < src->num_types; ++k) {
142 r = src->funcs->set(adev, src, k,
143 AMDGPU_IRQ_STATE_DISABLE);
144 if (r)
145 DRM_ERROR("error disabling interrupt (%d)\n",
146 r);
147 }
148 }
149 }
150 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
151 }
152
153 /**
154 * amdgpu_irq_handler - IRQ handler
155 *
156 * @irq: IRQ number (unused)
157 * @arg: pointer to DRM device
158 *
159 * IRQ handler for amdgpu driver (all ASICs).
160 *
161 * Returns:
162 * result of handling the IRQ, as defined by &irqreturn_t
163 */
amdgpu_irq_handler(void * arg)164 irqreturn_t amdgpu_irq_handler(void *arg)
165 {
166 struct drm_device *dev = (struct drm_device *) arg;
167 struct amdgpu_device *adev = drm_to_adev(dev);
168 irqreturn_t ret;
169
170 if (!adev->irq.installed)
171 return 0;
172
173 ret = amdgpu_ih_process(adev, &adev->irq.ih);
174 if (ret == IRQ_HANDLED)
175 pm_runtime_mark_last_busy(dev->dev);
176
177 amdgpu_ras_interrupt_fatal_error_handler(adev);
178
179 return ret;
180 }
181
182 /**
183 * amdgpu_irq_handle_ih1 - kick of processing for IH1
184 *
185 * @work: work structure in struct amdgpu_irq
186 *
187 * Kick of processing IH ring 1.
188 */
amdgpu_irq_handle_ih1(struct work_struct * work)189 static void amdgpu_irq_handle_ih1(struct work_struct *work)
190 {
191 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
192 irq.ih1_work);
193
194 amdgpu_ih_process(adev, &adev->irq.ih1);
195 }
196
197 /**
198 * amdgpu_irq_handle_ih2 - kick of processing for IH2
199 *
200 * @work: work structure in struct amdgpu_irq
201 *
202 * Kick of processing IH ring 2.
203 */
amdgpu_irq_handle_ih2(struct work_struct * work)204 static void amdgpu_irq_handle_ih2(struct work_struct *work)
205 {
206 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
207 irq.ih2_work);
208
209 amdgpu_ih_process(adev, &adev->irq.ih2);
210 }
211
212 /**
213 * amdgpu_irq_handle_ih_soft - kick of processing for ih_soft
214 *
215 * @work: work structure in struct amdgpu_irq
216 *
217 * Kick of processing IH soft ring.
218 */
amdgpu_irq_handle_ih_soft(struct work_struct * work)219 static void amdgpu_irq_handle_ih_soft(struct work_struct *work)
220 {
221 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
222 irq.ih_soft_work);
223
224 amdgpu_ih_process(adev, &adev->irq.ih_soft);
225 }
226
227 /**
228 * amdgpu_msi_ok - check whether MSI functionality is enabled
229 *
230 * @adev: amdgpu device pointer (unused)
231 *
232 * Checks whether MSI functionality has been disabled via module parameter
233 * (all ASICs).
234 *
235 * Returns:
236 * *true* if MSIs are allowed to be enabled or *false* otherwise
237 */
amdgpu_msi_ok(struct amdgpu_device * adev)238 bool amdgpu_msi_ok(struct amdgpu_device *adev)
239 {
240 if (amdgpu_msi == 1)
241 return true;
242 else if (amdgpu_msi == 0)
243 return false;
244
245 return true;
246 }
247
amdgpu_restore_msix(struct amdgpu_device * adev)248 static void amdgpu_restore_msix(struct amdgpu_device *adev)
249 {
250 STUB();
251 #ifdef notyet
252 u16 ctrl;
253
254 pci_read_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
255 if (!(ctrl & PCI_MSIX_FLAGS_ENABLE))
256 return;
257
258 /* VF FLR */
259 ctrl &= ~PCI_MSIX_FLAGS_ENABLE;
260 pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl);
261 ctrl |= PCI_MSIX_FLAGS_ENABLE;
262 pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl);
263 #endif
264 }
265
266 /**
267 * amdgpu_irq_init - initialize interrupt handling
268 *
269 * @adev: amdgpu device pointer
270 *
271 * Sets up work functions for hotplug and reset interrupts, enables MSI
272 * functionality, initializes vblank, hotplug and reset interrupt handling.
273 *
274 * Returns:
275 * 0 on success or error code on failure
276 */
amdgpu_irq_init(struct amdgpu_device * adev)277 int amdgpu_irq_init(struct amdgpu_device *adev)
278 {
279 unsigned int irq, flags;
280 int r;
281
282 mtx_init(&adev->irq.lock, IPL_TTY);
283
284 #ifdef notyet
285 /* Enable MSI if not disabled by module parameter */
286 adev->irq.msi_enabled = false;
287
288 if (!amdgpu_msi_ok(adev))
289 flags = PCI_IRQ_INTX;
290 else
291 flags = PCI_IRQ_ALL_TYPES;
292
293 /* we only need one vector */
294 r = pci_alloc_irq_vectors(adev->pdev, 1, 1, flags);
295 if (r < 0) {
296 dev_err(adev->dev, "Failed to alloc msi vectors\n");
297 return r;
298 }
299
300 if (amdgpu_msi_ok(adev)) {
301 adev->irq.msi_enabled = true;
302 dev_dbg(adev->dev, "using MSI/MSI-X.\n");
303 }
304 #endif
305
306 INIT_WORK(&adev->irq.ih1_work, amdgpu_irq_handle_ih1);
307 INIT_WORK(&adev->irq.ih2_work, amdgpu_irq_handle_ih2);
308 INIT_WORK(&adev->irq.ih_soft_work, amdgpu_irq_handle_ih_soft);
309
310 /* Use vector 0 for MSI-X. */
311 r = pci_irq_vector(adev->pdev, 0);
312 if (r < 0)
313 goto free_vectors;
314 irq = r;
315
316 /* PCI devices require shared interrupts. */
317 r = request_irq(irq, amdgpu_irq_handler, IRQF_SHARED, adev_to_drm(adev)->driver->name,
318 adev_to_drm(adev));
319 if (r)
320 goto free_vectors;
321
322 adev->irq.installed = true;
323 adev->irq.irq = irq;
324 adev_to_drm(adev)->max_vblank_count = 0x00ffffff;
325
326 DRM_DEBUG("amdgpu: irq initialized.\n");
327 return 0;
328
329 free_vectors:
330 if (adev->irq.msi_enabled)
331 pci_free_irq_vectors(adev->pdev);
332
333 adev->irq.msi_enabled = false;
334 return r;
335 }
336
amdgpu_irq_fini_hw(struct amdgpu_device * adev)337 void amdgpu_irq_fini_hw(struct amdgpu_device *adev)
338 {
339 if (adev->irq.installed) {
340 free_irq(adev->irq.irq, adev_to_drm(adev));
341 adev->irq.installed = false;
342 if (adev->irq.msi_enabled)
343 pci_free_irq_vectors(adev->pdev);
344 }
345
346 amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft);
347 amdgpu_ih_ring_fini(adev, &adev->irq.ih);
348 amdgpu_ih_ring_fini(adev, &adev->irq.ih1);
349 amdgpu_ih_ring_fini(adev, &adev->irq.ih2);
350 }
351
352 /**
353 * amdgpu_irq_fini_sw - shut down interrupt handling
354 *
355 * @adev: amdgpu device pointer
356 *
357 * Tears down work functions for hotplug and reset interrupts, disables MSI
358 * functionality, shuts down vblank, hotplug and reset interrupt handling,
359 * turns off interrupts from all sources (all ASICs).
360 */
amdgpu_irq_fini_sw(struct amdgpu_device * adev)361 void amdgpu_irq_fini_sw(struct amdgpu_device *adev)
362 {
363 unsigned int i, j;
364
365 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
366 if (!adev->irq.client[i].sources)
367 continue;
368
369 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
370 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
371
372 if (!src)
373 continue;
374
375 kfree(src->enabled_types);
376 src->enabled_types = NULL;
377 }
378 kfree(adev->irq.client[i].sources);
379 adev->irq.client[i].sources = NULL;
380 }
381 }
382
383 /**
384 * amdgpu_irq_add_id - register IRQ source
385 *
386 * @adev: amdgpu device pointer
387 * @client_id: client id
388 * @src_id: source id
389 * @source: IRQ source pointer
390 *
391 * Registers IRQ source on a client.
392 *
393 * Returns:
394 * 0 on success or error code otherwise
395 */
amdgpu_irq_add_id(struct amdgpu_device * adev,unsigned int client_id,unsigned int src_id,struct amdgpu_irq_src * source)396 int amdgpu_irq_add_id(struct amdgpu_device *adev,
397 unsigned int client_id, unsigned int src_id,
398 struct amdgpu_irq_src *source)
399 {
400 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX)
401 return -EINVAL;
402
403 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
404 return -EINVAL;
405
406 if (!source->funcs)
407 return -EINVAL;
408
409 if (!adev->irq.client[client_id].sources) {
410 adev->irq.client[client_id].sources =
411 kcalloc(AMDGPU_MAX_IRQ_SRC_ID,
412 sizeof(struct amdgpu_irq_src *),
413 GFP_KERNEL);
414 if (!adev->irq.client[client_id].sources)
415 return -ENOMEM;
416 }
417
418 if (adev->irq.client[client_id].sources[src_id] != NULL)
419 return -EINVAL;
420
421 if (source->num_types && !source->enabled_types) {
422 atomic_t *types;
423
424 types = kcalloc(source->num_types, sizeof(atomic_t),
425 GFP_KERNEL);
426 if (!types)
427 return -ENOMEM;
428
429 source->enabled_types = types;
430 }
431
432 adev->irq.client[client_id].sources[src_id] = source;
433 return 0;
434 }
435
436 /**
437 * amdgpu_irq_dispatch - dispatch IRQ to IP blocks
438 *
439 * @adev: amdgpu device pointer
440 * @ih: interrupt ring instance
441 *
442 * Dispatches IRQ to IP blocks.
443 */
amdgpu_irq_dispatch(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)444 void amdgpu_irq_dispatch(struct amdgpu_device *adev,
445 struct amdgpu_ih_ring *ih)
446 {
447 u32 ring_index = ih->rptr >> 2;
448 struct amdgpu_iv_entry entry;
449 unsigned int client_id, src_id;
450 struct amdgpu_irq_src *src;
451 bool handled = false;
452 int r;
453
454 entry.ih = ih;
455 entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
456
457 /*
458 * timestamp is not supported on some legacy SOCs (cik, cz, iceland,
459 * si and tonga), so initialize timestamp and timestamp_src to 0
460 */
461 entry.timestamp = 0;
462 entry.timestamp_src = 0;
463
464 amdgpu_ih_decode_iv(adev, &entry);
465
466 trace_amdgpu_iv(ih - &adev->irq.ih, &entry);
467
468 client_id = entry.client_id;
469 src_id = entry.src_id;
470
471 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) {
472 DRM_DEBUG("Invalid client_id in IV: %d\n", client_id);
473
474 } else if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {
475 DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);
476
477 } else if (((client_id == AMDGPU_IRQ_CLIENTID_LEGACY) ||
478 (client_id == SOC15_IH_CLIENTID_ISP)) &&
479 adev->irq.virq[src_id]) {
480 STUB();
481 #ifdef notyet
482 generic_handle_domain_irq(adev->irq.domain, src_id);
483 #endif
484
485 } else if (!adev->irq.client[client_id].sources) {
486 DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n",
487 client_id, src_id);
488
489 } else if ((src = adev->irq.client[client_id].sources[src_id])) {
490 r = src->funcs->process(adev, src, &entry);
491 if (r < 0)
492 DRM_ERROR("error processing interrupt (%d)\n", r);
493 else if (r)
494 handled = true;
495
496 } else {
497 DRM_DEBUG("Unregistered interrupt src_id: %d of client_id:%d\n",
498 src_id, client_id);
499 }
500
501 /* Send it to amdkfd as well if it isn't already handled */
502 if (!handled)
503 amdgpu_amdkfd_interrupt(adev, entry.iv_entry);
504
505 if (amdgpu_ih_ts_after(ih->processed_timestamp, entry.timestamp))
506 ih->processed_timestamp = entry.timestamp;
507 }
508
509 /**
510 * amdgpu_irq_delegate - delegate IV to soft IH ring
511 *
512 * @adev: amdgpu device pointer
513 * @entry: IV entry
514 * @num_dw: size of IV
515 *
516 * Delegate the IV to the soft IH ring and schedule processing of it. Used
517 * if the hardware delegation to IH1 or IH2 doesn't work for some reason.
518 */
amdgpu_irq_delegate(struct amdgpu_device * adev,struct amdgpu_iv_entry * entry,unsigned int num_dw)519 void amdgpu_irq_delegate(struct amdgpu_device *adev,
520 struct amdgpu_iv_entry *entry,
521 unsigned int num_dw)
522 {
523 amdgpu_ih_ring_write(adev, &adev->irq.ih_soft, entry->iv_entry, num_dw);
524 schedule_work(&adev->irq.ih_soft_work);
525 }
526
527 /**
528 * amdgpu_irq_update - update hardware interrupt state
529 *
530 * @adev: amdgpu device pointer
531 * @src: interrupt source pointer
532 * @type: type of interrupt
533 *
534 * Updates interrupt state for the specific source (all ASICs).
535 */
amdgpu_irq_update(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type)536 int amdgpu_irq_update(struct amdgpu_device *adev,
537 struct amdgpu_irq_src *src, unsigned int type)
538 {
539 unsigned long irqflags;
540 enum amdgpu_interrupt_state state;
541 int r;
542
543 spin_lock_irqsave(&adev->irq.lock, irqflags);
544
545 /* We need to determine after taking the lock, otherwise
546 * we might disable just enabled interrupts again
547 */
548 if (amdgpu_irq_enabled(adev, src, type))
549 state = AMDGPU_IRQ_STATE_ENABLE;
550 else
551 state = AMDGPU_IRQ_STATE_DISABLE;
552
553 r = src->funcs->set(adev, src, type, state);
554 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
555 return r;
556 }
557
558 /**
559 * amdgpu_irq_gpu_reset_resume_helper - update interrupt states on all sources
560 *
561 * @adev: amdgpu device pointer
562 *
563 * Updates state of all types of interrupts on all sources on resume after
564 * reset.
565 */
amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device * adev)566 void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
567 {
568 int i, j, k;
569
570 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
571 amdgpu_restore_msix(adev);
572
573 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
574 if (!adev->irq.client[i].sources)
575 continue;
576
577 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
578 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
579
580 if (!src || !src->funcs || !src->funcs->set)
581 continue;
582 for (k = 0; k < src->num_types; k++)
583 amdgpu_irq_update(adev, src, k);
584 }
585 }
586 }
587
588 /**
589 * amdgpu_irq_get - enable interrupt
590 *
591 * @adev: amdgpu device pointer
592 * @src: interrupt source pointer
593 * @type: type of interrupt
594 *
595 * Enables specified type of interrupt on the specified source (all ASICs).
596 *
597 * Returns:
598 * 0 on success or error code otherwise
599 */
amdgpu_irq_get(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type)600 int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
601 unsigned int type)
602 {
603 if (!adev->irq.installed)
604 return -ENOENT;
605
606 if (type >= src->num_types)
607 return -EINVAL;
608
609 if (!src->enabled_types || !src->funcs->set)
610 return -EINVAL;
611
612 if (atomic_inc_return(&src->enabled_types[type]) == 1)
613 return amdgpu_irq_update(adev, src, type);
614
615 return 0;
616 }
617
618 /**
619 * amdgpu_irq_put - disable interrupt
620 *
621 * @adev: amdgpu device pointer
622 * @src: interrupt source pointer
623 * @type: type of interrupt
624 *
625 * Enables specified type of interrupt on the specified source (all ASICs).
626 *
627 * Returns:
628 * 0 on success or error code otherwise
629 */
amdgpu_irq_put(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type)630 int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
631 unsigned int type)
632 {
633 if (!adev->irq.installed)
634 return -ENOENT;
635
636 if (type >= src->num_types)
637 return -EINVAL;
638
639 if (!src->enabled_types || !src->funcs->set)
640 return -EINVAL;
641
642 if (WARN_ON(!amdgpu_irq_enabled(adev, src, type)))
643 return -EINVAL;
644
645 if (atomic_dec_and_test(&src->enabled_types[type]))
646 return amdgpu_irq_update(adev, src, type);
647
648 return 0;
649 }
650
651 /**
652 * amdgpu_irq_enabled - check whether interrupt is enabled or not
653 *
654 * @adev: amdgpu device pointer
655 * @src: interrupt source pointer
656 * @type: type of interrupt
657 *
658 * Checks whether the given type of interrupt is enabled on the given source.
659 *
660 * Returns:
661 * *true* if interrupt is enabled, *false* if interrupt is disabled or on
662 * invalid parameters
663 */
amdgpu_irq_enabled(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type)664 bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
665 unsigned int type)
666 {
667 if (!adev->irq.installed)
668 return false;
669
670 if (type >= src->num_types)
671 return false;
672
673 if (!src->enabled_types || !src->funcs->set)
674 return false;
675
676 return !!atomic_read(&src->enabled_types[type]);
677 }
678
679 #ifdef __linux__
680 /* XXX: Generic IRQ handling */
amdgpu_irq_mask(struct irq_data * irqd)681 static void amdgpu_irq_mask(struct irq_data *irqd)
682 {
683 /* XXX */
684 }
685
amdgpu_irq_unmask(struct irq_data * irqd)686 static void amdgpu_irq_unmask(struct irq_data *irqd)
687 {
688 /* XXX */
689 }
690
691 /* amdgpu hardware interrupt chip descriptor */
692 static struct irq_chip amdgpu_irq_chip = {
693 .name = "amdgpu-ih",
694 .irq_mask = amdgpu_irq_mask,
695 .irq_unmask = amdgpu_irq_unmask,
696 };
697 #endif
698
699 #ifdef __linux__
700 /**
701 * amdgpu_irqdomain_map - create mapping between virtual and hardware IRQ numbers
702 *
703 * @d: amdgpu IRQ domain pointer (unused)
704 * @irq: virtual IRQ number
705 * @hwirq: hardware irq number
706 *
707 * Current implementation assigns simple interrupt handler to the given virtual
708 * IRQ.
709 *
710 * Returns:
711 * 0 on success or error code otherwise
712 */
amdgpu_irqdomain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)713 static int amdgpu_irqdomain_map(struct irq_domain *d,
714 unsigned int irq, irq_hw_number_t hwirq)
715 {
716 if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID)
717 return -EPERM;
718
719 irq_set_chip_and_handler(irq,
720 &amdgpu_irq_chip, handle_simple_irq);
721 return 0;
722 }
723
724 /* Implementation of methods for amdgpu IRQ domain */
725 static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
726 .map = amdgpu_irqdomain_map,
727 };
728 #endif
729
730 /**
731 * amdgpu_irq_add_domain - create a linear IRQ domain
732 *
733 * @adev: amdgpu device pointer
734 *
735 * Creates an IRQ domain for GPU interrupt sources
736 * that may be driven by another driver (e.g., ACP).
737 *
738 * Returns:
739 * 0 on success or error code otherwise
740 */
amdgpu_irq_add_domain(struct amdgpu_device * adev)741 int amdgpu_irq_add_domain(struct amdgpu_device *adev)
742 {
743 #ifdef __linux__
744 adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID,
745 &amdgpu_hw_irqdomain_ops, adev);
746 if (!adev->irq.domain) {
747 DRM_ERROR("GPU irq add domain failed\n");
748 return -ENODEV;
749 }
750 #endif
751
752 return 0;
753 }
754
755 /**
756 * amdgpu_irq_remove_domain - remove the IRQ domain
757 *
758 * @adev: amdgpu device pointer
759 *
760 * Removes the IRQ domain for GPU interrupt sources
761 * that may be driven by another driver (e.g., ACP).
762 */
amdgpu_irq_remove_domain(struct amdgpu_device * adev)763 void amdgpu_irq_remove_domain(struct amdgpu_device *adev)
764 {
765 STUB();
766 #if 0
767 if (adev->irq.domain) {
768 irq_domain_remove(adev->irq.domain);
769 adev->irq.domain = NULL;
770 }
771 #endif
772 }
773
774 /**
775 * amdgpu_irq_create_mapping - create mapping between domain Linux IRQs
776 *
777 * @adev: amdgpu device pointer
778 * @src_id: IH source id
779 *
780 * Creates mapping between a domain IRQ (GPU IH src id) and a Linux IRQ
781 * Use this for components that generate a GPU interrupt, but are driven
782 * by a different driver (e.g., ACP).
783 *
784 * Returns:
785 * Linux IRQ
786 */
amdgpu_irq_create_mapping(struct amdgpu_device * adev,unsigned int src_id)787 unsigned int amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned int src_id)
788 {
789 STUB();
790 return 0;
791 #if 0
792 adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id);
793
794 return adev->irq.virq[src_id];
795 #endif
796 }
797