1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27 #include <linux/export.h>
28 #include <linux/pci.h>
29
30 #include <drm/drm_edid.h>
31 #include <drm/amdgpu_drm.h>
32 #include "amdgpu.h"
33 #include "amdgpu_i2c.h"
34 #include "amdgpu_atombios.h"
35 #include "atom.h"
36 #include "atombios_dp.h"
37 #include "atombios_i2c.h"
38
39 #include <dev/i2c/i2cvar.h>
40 #include <dev/i2c/i2c_bitbang.h>
41
42 /* bit banging i2c */
amdgpu_i2c_pre_xfer(struct i2c_adapter * i2c_adap)43 static int amdgpu_i2c_pre_xfer(struct i2c_adapter *i2c_adap)
44 {
45 struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
46 struct amdgpu_device *adev = drm_to_adev(i2c->dev);
47 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
48 uint32_t temp;
49
50 mutex_lock(&i2c->mutex);
51
52 /* switch the pads to ddc mode */
53 if (rec->hw_capable) {
54 temp = RREG32(rec->mask_clk_reg);
55 temp &= ~(1 << 16);
56 WREG32(rec->mask_clk_reg, temp);
57 }
58
59 /* clear the output pin values */
60 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
61 WREG32(rec->a_clk_reg, temp);
62
63 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
64 WREG32(rec->a_data_reg, temp);
65
66 /* set the pins to input */
67 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
68 WREG32(rec->en_clk_reg, temp);
69
70 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
71 WREG32(rec->en_data_reg, temp);
72
73 /* mask the gpio pins for software use */
74 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
75 WREG32(rec->mask_clk_reg, temp);
76 temp = RREG32(rec->mask_clk_reg);
77
78 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
79 WREG32(rec->mask_data_reg, temp);
80 temp = RREG32(rec->mask_data_reg);
81
82 return 0;
83 }
84
amdgpu_i2c_post_xfer(struct i2c_adapter * i2c_adap)85 static void amdgpu_i2c_post_xfer(struct i2c_adapter *i2c_adap)
86 {
87 struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
88 struct amdgpu_device *adev = drm_to_adev(i2c->dev);
89 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
90 uint32_t temp;
91
92 /* unmask the gpio pins for software use */
93 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;
94 WREG32(rec->mask_clk_reg, temp);
95 temp = RREG32(rec->mask_clk_reg);
96
97 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;
98 WREG32(rec->mask_data_reg, temp);
99 temp = RREG32(rec->mask_data_reg);
100
101 mutex_unlock(&i2c->mutex);
102 }
103
amdgpu_i2c_get_clock(void * i2c_priv)104 static int amdgpu_i2c_get_clock(void *i2c_priv)
105 {
106 struct amdgpu_i2c_chan *i2c = i2c_priv;
107 struct amdgpu_device *adev = drm_to_adev(i2c->dev);
108 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
109 uint32_t val;
110
111 /* read the value off the pin */
112 val = RREG32(rec->y_clk_reg);
113 val &= rec->y_clk_mask;
114
115 return (val != 0);
116 }
117
118
amdgpu_i2c_get_data(void * i2c_priv)119 static int amdgpu_i2c_get_data(void *i2c_priv)
120 {
121 struct amdgpu_i2c_chan *i2c = i2c_priv;
122 struct amdgpu_device *adev = drm_to_adev(i2c->dev);
123 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
124 uint32_t val;
125
126 /* read the value off the pin */
127 val = RREG32(rec->y_data_reg);
128 val &= rec->y_data_mask;
129
130 return (val != 0);
131 }
132
amdgpu_i2c_set_clock(void * i2c_priv,int clock)133 static void amdgpu_i2c_set_clock(void *i2c_priv, int clock)
134 {
135 struct amdgpu_i2c_chan *i2c = i2c_priv;
136 struct amdgpu_device *adev = drm_to_adev(i2c->dev);
137 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
138 uint32_t val;
139
140 /* set pin direction */
141 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
142 val |= clock ? 0 : rec->en_clk_mask;
143 WREG32(rec->en_clk_reg, val);
144 }
145
amdgpu_i2c_set_data(void * i2c_priv,int data)146 static void amdgpu_i2c_set_data(void *i2c_priv, int data)
147 {
148 struct amdgpu_i2c_chan *i2c = i2c_priv;
149 struct amdgpu_device *adev = drm_to_adev(i2c->dev);
150 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
151 uint32_t val;
152
153 /* set pin direction */
154 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
155 val |= data ? 0 : rec->en_data_mask;
156 WREG32(rec->en_data_reg, val);
157 }
158
159 void amdgpu_bb_set_bits(void *, uint32_t);
160 void amdgpu_bb_set_dir(void *, uint32_t);
161 uint32_t amdgpu_bb_read_bits(void *);
162
163 int amdgpu_acquire_bus(void *, int);
164 void amdgpu_release_bus(void *, int);
165 int amdgpu_send_start(void *, int);
166 int amdgpu_send_stop(void *, int);
167 int amdgpu_initiate_xfer(void *, i2c_addr_t, int);
168 int amdgpu_read_byte(void *, u_int8_t *, int);
169 int amdgpu_write_byte(void *, u_int8_t, int);
170
171 #define AMDGPU_BB_SDA (1 << I2C_BIT_SDA)
172 #define AMDGPU_BB_SCL (1 << I2C_BIT_SCL)
173
174 struct i2c_bitbang_ops amdgpu_bbops = {
175 amdgpu_bb_set_bits,
176 amdgpu_bb_set_dir,
177 amdgpu_bb_read_bits,
178 { AMDGPU_BB_SDA, AMDGPU_BB_SCL, 0, 0 }
179 };
180
181 void
amdgpu_bb_set_bits(void * cookie,uint32_t bits)182 amdgpu_bb_set_bits(void *cookie, uint32_t bits)
183 {
184 amdgpu_i2c_set_clock(cookie, bits & AMDGPU_BB_SCL);
185 amdgpu_i2c_set_data(cookie, bits & AMDGPU_BB_SDA);
186 }
187
188 void
amdgpu_bb_set_dir(void * cookie,uint32_t bits)189 amdgpu_bb_set_dir(void *cookie, uint32_t bits)
190 {
191 }
192
193 uint32_t
amdgpu_bb_read_bits(void * cookie)194 amdgpu_bb_read_bits(void *cookie)
195 {
196 uint32_t bits = 0;
197
198 if (amdgpu_i2c_get_clock(cookie))
199 bits |= AMDGPU_BB_SCL;
200 if (amdgpu_i2c_get_data(cookie))
201 bits |= AMDGPU_BB_SDA;
202
203 return bits;
204 }
205
206 int
amdgpu_acquire_bus(void * cookie,int flags)207 amdgpu_acquire_bus(void *cookie, int flags)
208 {
209 struct amdgpu_i2c_chan *i2c = cookie;
210 amdgpu_i2c_pre_xfer(&i2c->adapter);
211 return (0);
212 }
213
214 void
amdgpu_release_bus(void * cookie,int flags)215 amdgpu_release_bus(void *cookie, int flags)
216 {
217 struct amdgpu_i2c_chan *i2c = cookie;
218 amdgpu_i2c_post_xfer(&i2c->adapter);
219 }
220
221 int
amdgpu_send_start(void * cookie,int flags)222 amdgpu_send_start(void *cookie, int flags)
223 {
224 return (i2c_bitbang_send_start(cookie, flags, &amdgpu_bbops));
225 }
226
227 int
amdgpu_send_stop(void * cookie,int flags)228 amdgpu_send_stop(void *cookie, int flags)
229 {
230 return (i2c_bitbang_send_stop(cookie, flags, &amdgpu_bbops));
231 }
232
233 int
amdgpu_initiate_xfer(void * cookie,i2c_addr_t addr,int flags)234 amdgpu_initiate_xfer(void *cookie, i2c_addr_t addr, int flags)
235 {
236 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, &amdgpu_bbops));
237 }
238
239 int
amdgpu_read_byte(void * cookie,u_int8_t * bytep,int flags)240 amdgpu_read_byte(void *cookie, u_int8_t *bytep, int flags)
241 {
242 return (i2c_bitbang_read_byte(cookie, bytep, flags, &amdgpu_bbops));
243 }
244
245 int
amdgpu_write_byte(void * cookie,u_int8_t byte,int flags)246 amdgpu_write_byte(void *cookie, u_int8_t byte, int flags)
247 {
248 return (i2c_bitbang_write_byte(cookie, byte, flags, &amdgpu_bbops));
249 }
250
251 static const struct i2c_algorithm amdgpu_atombios_i2c_algo = {
252 .master_xfer = amdgpu_atombios_i2c_xfer,
253 .functionality = amdgpu_atombios_i2c_func,
254 };
255
amdgpu_i2c_create(struct drm_device * dev,const struct amdgpu_i2c_bus_rec * rec,const char * name)256 struct amdgpu_i2c_chan *amdgpu_i2c_create(struct drm_device *dev,
257 const struct amdgpu_i2c_bus_rec *rec,
258 const char *name)
259 {
260 struct amdgpu_i2c_chan *i2c;
261 int ret;
262
263 /* don't add the mm_i2c bus unless hw_i2c is enabled */
264 if (rec->mm_i2c && (amdgpu_hw_i2c == 0))
265 return NULL;
266
267 i2c = kzalloc(sizeof(struct amdgpu_i2c_chan), GFP_KERNEL);
268 if (i2c == NULL)
269 return NULL;
270
271 i2c->rec = *rec;
272 #ifdef __linux__
273 i2c->adapter.owner = THIS_MODULE;
274 i2c->adapter.dev.parent = dev->dev;
275 #endif
276 i2c->dev = dev;
277 i2c_set_adapdata(&i2c->adapter, i2c);
278 rw_init(&i2c->mutex, "agiic");
279 if (rec->hw_capable &&
280 amdgpu_hw_i2c) {
281 /* hw i2c using atom */
282 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
283 "AMDGPU i2c hw bus %s", name);
284 i2c->adapter.algo = &amdgpu_atombios_i2c_algo;
285 ret = i2c_add_adapter(&i2c->adapter);
286 if (ret)
287 goto out_free;
288 } else {
289 /* set the amdgpu bit adapter */
290 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
291 "AMDGPU i2c bit bus %s", name);
292 i2c->adapter.algo_data = &i2c->bit;
293 #ifdef notyet
294 i2c->bit.pre_xfer = amdgpu_i2c_pre_xfer;
295 i2c->bit.post_xfer = amdgpu_i2c_post_xfer;
296 i2c->bit.setsda = amdgpu_i2c_set_data;
297 i2c->bit.setscl = amdgpu_i2c_set_clock;
298 i2c->bit.getsda = amdgpu_i2c_get_data;
299 i2c->bit.getscl = amdgpu_i2c_get_clock;
300 i2c->bit.udelay = 10;
301 i2c->bit.timeout = usecs_to_jiffies(2200); /* from VESA */
302 i2c->bit.data = i2c;
303 #else
304 i2c->bit.ic.ic_cookie = i2c;
305 i2c->bit.ic.ic_acquire_bus = amdgpu_acquire_bus;
306 i2c->bit.ic.ic_release_bus = amdgpu_release_bus;
307 i2c->bit.ic.ic_send_start = amdgpu_send_start;
308 i2c->bit.ic.ic_send_stop = amdgpu_send_stop;
309 i2c->bit.ic.ic_initiate_xfer = amdgpu_initiate_xfer;
310 i2c->bit.ic.ic_read_byte = amdgpu_read_byte;
311 i2c->bit.ic.ic_write_byte = amdgpu_write_byte;
312 #endif
313 ret = i2c_bit_add_bus(&i2c->adapter);
314 if (ret) {
315 DRM_ERROR("Failed to register bit i2c %s\n", name);
316 goto out_free;
317 }
318 }
319
320 return i2c;
321 out_free:
322 kfree(i2c);
323 return NULL;
324
325 }
326
amdgpu_i2c_destroy(struct amdgpu_i2c_chan * i2c)327 void amdgpu_i2c_destroy(struct amdgpu_i2c_chan *i2c)
328 {
329 if (!i2c)
330 return;
331 WARN_ON(i2c->has_aux);
332 i2c_del_adapter(&i2c->adapter);
333 kfree(i2c);
334 }
335
336 /* Add the default buses */
amdgpu_i2c_init(struct amdgpu_device * adev)337 void amdgpu_i2c_init(struct amdgpu_device *adev)
338 {
339 if (amdgpu_hw_i2c)
340 DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n");
341
342 amdgpu_atombios_i2c_init(adev);
343 }
344
345 /* remove all the buses */
amdgpu_i2c_fini(struct amdgpu_device * adev)346 void amdgpu_i2c_fini(struct amdgpu_device *adev)
347 {
348 int i;
349
350 for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) {
351 if (adev->i2c_bus[i]) {
352 amdgpu_i2c_destroy(adev->i2c_bus[i]);
353 adev->i2c_bus[i] = NULL;
354 }
355 }
356 }
357
358 /* Add additional buses */
amdgpu_i2c_add(struct amdgpu_device * adev,const struct amdgpu_i2c_bus_rec * rec,const char * name)359 void amdgpu_i2c_add(struct amdgpu_device *adev,
360 const struct amdgpu_i2c_bus_rec *rec,
361 const char *name)
362 {
363 struct drm_device *dev = adev_to_drm(adev);
364 int i;
365
366 for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) {
367 if (!adev->i2c_bus[i]) {
368 adev->i2c_bus[i] = amdgpu_i2c_create(dev, rec, name);
369 return;
370 }
371 }
372 }
373
374 /* looks up bus based on id */
375 struct amdgpu_i2c_chan *
amdgpu_i2c_lookup(struct amdgpu_device * adev,const struct amdgpu_i2c_bus_rec * i2c_bus)376 amdgpu_i2c_lookup(struct amdgpu_device *adev,
377 const struct amdgpu_i2c_bus_rec *i2c_bus)
378 {
379 int i;
380
381 for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) {
382 if (adev->i2c_bus[i] &&
383 (adev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) {
384 return adev->i2c_bus[i];
385 }
386 }
387 return NULL;
388 }
389
amdgpu_i2c_get_byte(struct amdgpu_i2c_chan * i2c_bus,u8 slave_addr,u8 addr,u8 * val)390 static int amdgpu_i2c_get_byte(struct amdgpu_i2c_chan *i2c_bus,
391 u8 slave_addr,
392 u8 addr,
393 u8 *val)
394 {
395 u8 out_buf[2];
396 u8 in_buf[2];
397 struct i2c_msg msgs[] = {
398 {
399 .addr = slave_addr,
400 .flags = 0,
401 .len = 1,
402 .buf = out_buf,
403 },
404 {
405 .addr = slave_addr,
406 .flags = I2C_M_RD,
407 .len = 1,
408 .buf = in_buf,
409 }
410 };
411
412 out_buf[0] = addr;
413 out_buf[1] = 0;
414
415 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) != 2) {
416 DRM_DEBUG("i2c 0x%02x read failed\n", addr);
417 return -EIO;
418 }
419
420 *val = in_buf[0];
421 DRM_DEBUG("val = 0x%02x\n", *val);
422
423 return 0;
424 }
425
amdgpu_i2c_put_byte(struct amdgpu_i2c_chan * i2c_bus,u8 slave_addr,u8 addr,u8 val)426 static int amdgpu_i2c_put_byte(struct amdgpu_i2c_chan *i2c_bus,
427 u8 slave_addr,
428 u8 addr,
429 u8 val)
430 {
431 uint8_t out_buf[2];
432 struct i2c_msg msg = {
433 .addr = slave_addr,
434 .flags = 0,
435 .len = 2,
436 .buf = out_buf,
437 };
438
439 out_buf[0] = addr;
440 out_buf[1] = val;
441
442 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1) {
443 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n", addr, val);
444 return -EIO;
445 }
446
447 return 0;
448 }
449
450 /* ddc router switching */
451 void
amdgpu_i2c_router_select_ddc_port(const struct amdgpu_connector * amdgpu_connector)452 amdgpu_i2c_router_select_ddc_port(const struct amdgpu_connector *amdgpu_connector)
453 {
454 u8 val = 0;
455
456 if (!amdgpu_connector->router.ddc_valid)
457 return;
458
459 if (!amdgpu_connector->router_bus)
460 return;
461
462 if (amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
463 amdgpu_connector->router.i2c_addr,
464 0x3, &val))
465 return;
466 val &= ~amdgpu_connector->router.ddc_mux_control_pin;
467 amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
468 amdgpu_connector->router.i2c_addr,
469 0x3, val);
470 if (amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
471 amdgpu_connector->router.i2c_addr,
472 0x1, &val))
473 return;
474 val &= ~amdgpu_connector->router.ddc_mux_control_pin;
475 val |= amdgpu_connector->router.ddc_mux_state;
476 amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
477 amdgpu_connector->router.i2c_addr,
478 0x1, val);
479 }
480
481 /* clock/data router switching */
482 void
amdgpu_i2c_router_select_cd_port(const struct amdgpu_connector * amdgpu_connector)483 amdgpu_i2c_router_select_cd_port(const struct amdgpu_connector *amdgpu_connector)
484 {
485 u8 val;
486
487 if (!amdgpu_connector->router.cd_valid)
488 return;
489
490 if (!amdgpu_connector->router_bus)
491 return;
492
493 if (amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
494 amdgpu_connector->router.i2c_addr,
495 0x3, &val))
496 return;
497 val &= ~amdgpu_connector->router.cd_mux_control_pin;
498 amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
499 amdgpu_connector->router.i2c_addr,
500 0x3, val);
501 if (amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
502 amdgpu_connector->router.i2c_addr,
503 0x1, &val))
504 return;
505 val &= ~amdgpu_connector->router.cd_mux_control_pin;
506 val |= amdgpu_connector->router.cd_mux_state;
507 amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
508 amdgpu_connector->router.i2c_addr,
509 0x1, val);
510 }
511