1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __AMDGPU_H__
29 #define __AMDGPU_H__
30
31 #ifdef pr_fmt
32 #undef pr_fmt
33 #endif
34
35 #define pr_fmt(fmt) "amdgpu: " fmt
36
37 #ifdef dev_fmt
38 #undef dev_fmt
39 #endif
40
41 #define dev_fmt(fmt) "amdgpu: " fmt
42
43 #include "amdgpu_ctx.h"
44
45 #include <linux/atomic.h>
46 #include <linux/wait.h>
47 #include <linux/list.h>
48 #include <linux/kref.h>
49 #include <linux/rbtree.h>
50 #include <linux/hashtable.h>
51 #include <linux/dma-fence.h>
52 #include <linux/pci.h>
53
54 #include <drm/ttm/ttm_bo.h>
55 #include <drm/ttm/ttm_placement.h>
56
57 #include <drm/amdgpu_drm.h>
58 #include <drm/drm_gem.h>
59 #include <drm/drm_ioctl.h>
60
61 #include <dev/wscons/wsconsio.h>
62 #include <dev/wscons/wsdisplayvar.h>
63 #include <dev/rasops/rasops.h>
64
65 #include <kgd_kfd_interface.h>
66 #include "dm_pp_interface.h"
67 #include "kgd_pp_interface.h"
68
69 #include "amd_shared.h"
70 #include "amdgpu_mode.h"
71 #include "amdgpu_ih.h"
72 #include "amdgpu_irq.h"
73 #include "amdgpu_ucode.h"
74 #include "amdgpu_ttm.h"
75 #include "amdgpu_psp.h"
76 #include "amdgpu_gds.h"
77 #include "amdgpu_sync.h"
78 #include "amdgpu_ring.h"
79 #include "amdgpu_vm.h"
80 #include "amdgpu_dpm.h"
81 #include "amdgpu_acp.h"
82 #include "amdgpu_uvd.h"
83 #include "amdgpu_vce.h"
84 #include "amdgpu_vcn.h"
85 #include "amdgpu_jpeg.h"
86 #include "amdgpu_vpe.h"
87 #include "amdgpu_umsch_mm.h"
88 #include "amdgpu_gmc.h"
89 #include "amdgpu_gfx.h"
90 #include "amdgpu_sdma.h"
91 #include "amdgpu_lsdma.h"
92 #include "amdgpu_nbio.h"
93 #include "amdgpu_hdp.h"
94 #include "amdgpu_dm.h"
95 #include "amdgpu_virt.h"
96 #include "amdgpu_csa.h"
97 #include "amdgpu_mes_ctx.h"
98 #include "amdgpu_gart.h"
99 #include "amdgpu_debugfs.h"
100 #include "amdgpu_job.h"
101 #include "amdgpu_bo_list.h"
102 #include "amdgpu_gem.h"
103 #include "amdgpu_doorbell.h"
104 #include "amdgpu_amdkfd.h"
105 #include "amdgpu_discovery.h"
106 #include "amdgpu_mes.h"
107 #include "amdgpu_umc.h"
108 #include "amdgpu_mmhub.h"
109 #include "amdgpu_gfxhub.h"
110 #include "amdgpu_df.h"
111 #include "amdgpu_smuio.h"
112 #include "amdgpu_fdinfo.h"
113 #include "amdgpu_mca.h"
114 #include "amdgpu_aca.h"
115 #include "amdgpu_ras.h"
116 #include "amdgpu_xcp.h"
117 #include "amdgpu_seq64.h"
118 #include "amdgpu_reg_state.h"
119 #if defined(CONFIG_DRM_AMD_ISP)
120 #include "amdgpu_isp.h"
121 #endif
122
123 #define MAX_GPU_INSTANCE 64
124
125 #define GFX_SLICE_PERIOD msecs_to_jiffies(250)
126
127 struct amdgpu_gpu_instance {
128 struct amdgpu_device *adev;
129 int mgpu_fan_enabled;
130 };
131
132 struct amdgpu_mgpu_info {
133 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
134 struct rwlock mutex;
135 uint32_t num_gpu;
136 uint32_t num_dgpu;
137 uint32_t num_apu;
138
139 /* delayed reset_func for XGMI configuration if necessary */
140 struct delayed_work delayed_reset_work;
141 bool pending_reset;
142 };
143
144 enum amdgpu_ss {
145 AMDGPU_SS_DRV_LOAD,
146 AMDGPU_SS_DEV_D0,
147 AMDGPU_SS_DEV_D3,
148 AMDGPU_SS_DRV_UNLOAD
149 };
150
151 struct amdgpu_hwip_reg_entry {
152 u32 hwip;
153 u32 inst;
154 u32 seg;
155 u32 reg_offset;
156 const char *reg_name;
157 };
158
159 struct amdgpu_watchdog_timer {
160 bool timeout_fatal_disable;
161 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */
162 };
163
164 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
165
166 /*
167 * Modules parameters.
168 */
169 extern int amdgpu_modeset;
170 extern unsigned int amdgpu_vram_limit;
171 extern int amdgpu_vis_vram_limit;
172 extern int amdgpu_gart_size;
173 extern int amdgpu_gtt_size;
174 extern int amdgpu_moverate;
175 extern int amdgpu_audio;
176 extern int amdgpu_disp_priority;
177 extern int amdgpu_hw_i2c;
178 extern int amdgpu_pcie_gen2;
179 extern int amdgpu_msi;
180 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
181 extern int amdgpu_dpm;
182 extern int amdgpu_fw_load_type;
183 extern int amdgpu_aspm;
184 extern int amdgpu_runtime_pm;
185 extern uint amdgpu_ip_block_mask;
186 extern int amdgpu_bapm;
187 extern int amdgpu_deep_color;
188 extern int amdgpu_vm_size;
189 extern int amdgpu_vm_block_size;
190 extern int amdgpu_vm_fragment_size;
191 extern int amdgpu_vm_fault_stop;
192 extern int amdgpu_vm_debug;
193 extern int amdgpu_vm_update_mode;
194 extern int amdgpu_exp_hw_support;
195 extern int amdgpu_dc;
196 extern int amdgpu_sched_jobs;
197 extern int amdgpu_sched_hw_submission;
198 extern uint amdgpu_pcie_gen_cap;
199 extern uint amdgpu_pcie_lane_cap;
200 extern u64 amdgpu_cg_mask;
201 extern uint amdgpu_pg_mask;
202 extern uint amdgpu_sdma_phase_quantum;
203 extern char *amdgpu_disable_cu;
204 extern char *amdgpu_virtual_display;
205 extern uint amdgpu_pp_feature_mask;
206 extern uint amdgpu_force_long_training;
207 extern int amdgpu_lbpw;
208 extern int amdgpu_compute_multipipe;
209 extern int amdgpu_gpu_recovery;
210 extern int amdgpu_emu_mode;
211 extern uint amdgpu_smu_memory_pool_size;
212 extern int amdgpu_smu_pptable_id;
213 extern uint amdgpu_dc_feature_mask;
214 extern uint amdgpu_freesync_vid_mode;
215 extern uint amdgpu_dc_debug_mask;
216 extern uint amdgpu_dc_visual_confirm;
217 extern int amdgpu_dm_abm_level;
218 extern int amdgpu_backlight;
219 extern int amdgpu_damage_clips;
220 extern struct amdgpu_mgpu_info mgpu_info;
221 extern int amdgpu_ras_enable;
222 extern uint amdgpu_ras_mask;
223 extern int amdgpu_bad_page_threshold;
224 extern bool amdgpu_ignore_bad_page_threshold;
225 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer;
226 extern int amdgpu_async_gfx_ring;
227 extern int amdgpu_mcbp;
228 extern int amdgpu_discovery;
229 extern int amdgpu_mes;
230 extern int amdgpu_mes_log_enable;
231 extern int amdgpu_mes_kiq;
232 extern int amdgpu_uni_mes;
233 extern int amdgpu_noretry;
234 extern int amdgpu_force_asic_type;
235 extern int amdgpu_smartshift_bias;
236 extern int amdgpu_use_xgmi_p2p;
237 extern int amdgpu_mtype_local;
238 extern bool enforce_isolation;
239 #ifdef CONFIG_HSA_AMD
240 extern int sched_policy;
241 extern bool debug_evictions;
242 extern bool no_system_mem_limit;
243 extern int halt_if_hws_hang;
244 extern uint amdgpu_svm_default_granularity;
245 #else
246 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;
247 static const bool __maybe_unused debug_evictions; /* = false */
248 static const bool __maybe_unused no_system_mem_limit;
249 static const int __maybe_unused halt_if_hws_hang;
250 #endif
251 #ifdef CONFIG_HSA_AMD_P2P
252 extern bool pcie_p2p;
253 #endif
254
255 extern int amdgpu_tmz;
256 extern int amdgpu_reset_method;
257
258 #ifdef CONFIG_DRM_AMDGPU_SI
259 extern int amdgpu_si_support;
260 #endif
261 #ifdef CONFIG_DRM_AMDGPU_CIK
262 extern int amdgpu_cik_support;
263 #endif
264 extern int amdgpu_num_kcq;
265
266 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)
267 #define AMDGPU_UMSCHFW_LOG_SIZE (32 * 1024)
268 extern int amdgpu_vcnfw_log;
269 extern int amdgpu_sg_display;
270 extern int amdgpu_umsch_mm;
271 extern int amdgpu_seamless;
272 extern int amdgpu_umsch_mm_fwlog;
273
274 extern int amdgpu_user_partt_mode;
275 extern int amdgpu_agp;
276
277 extern int amdgpu_wbrf;
278
279 #define AMDGPU_VM_MAX_NUM_CTX 4096
280 #define AMDGPU_SG_THRESHOLD (256*1024*1024)
281 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
282 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
283 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
284 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
285 #define AMDGPUFB_CONN_LIMIT 4
286 #define AMDGPU_BIOS_NUM_SCRATCH 16
287
288 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */
289
290 /* hard reset data */
291 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
292
293 /* reset flags */
294 #define AMDGPU_RESET_GFX (1 << 0)
295 #define AMDGPU_RESET_COMPUTE (1 << 1)
296 #define AMDGPU_RESET_DMA (1 << 2)
297 #define AMDGPU_RESET_CP (1 << 3)
298 #define AMDGPU_RESET_GRBM (1 << 4)
299 #define AMDGPU_RESET_DMA1 (1 << 5)
300 #define AMDGPU_RESET_RLC (1 << 6)
301 #define AMDGPU_RESET_SEM (1 << 7)
302 #define AMDGPU_RESET_IH (1 << 8)
303 #define AMDGPU_RESET_VMC (1 << 9)
304 #define AMDGPU_RESET_MC (1 << 10)
305 #define AMDGPU_RESET_DISPLAY (1 << 11)
306 #define AMDGPU_RESET_UVD (1 << 12)
307 #define AMDGPU_RESET_VCE (1 << 13)
308 #define AMDGPU_RESET_VCE1 (1 << 14)
309
310 /* max cursor sizes (in pixels) */
311 #define CIK_CURSOR_WIDTH 128
312 #define CIK_CURSOR_HEIGHT 128
313
314 /* smart shift bias level limits */
315 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
316 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
317
318 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */
319 #define AMDGPU_SWCTF_EXTRA_DELAY 50
320
321 struct amdgpu_xcp_mgr;
322 struct amdgpu_device;
323 struct amdgpu_irq_src;
324 struct amdgpu_fpriv;
325 struct amdgpu_bo_va_mapping;
326 struct kfd_vm_fault_info;
327 struct amdgpu_hive_info;
328 struct amdgpu_reset_context;
329 struct amdgpu_reset_control;
330
331 enum amdgpu_cp_irq {
332 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
333 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
334 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
335 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
336 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
337 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
338 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
339 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
340 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
341 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
342
343 AMDGPU_CP_IRQ_LAST
344 };
345
346 enum amdgpu_thermal_irq {
347 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
348 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
349
350 AMDGPU_THERMAL_IRQ_LAST
351 };
352
353 enum amdgpu_kiq_irq {
354 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
355 AMDGPU_CP_KIQ_IRQ_LAST
356 };
357 #define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */
358 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
359 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
360 #define MAX_KIQ_REG_TRY 1000
361
362 int amdgpu_device_ip_set_clockgating_state(void *dev,
363 enum amd_ip_block_type block_type,
364 enum amd_clockgating_state state);
365 int amdgpu_device_ip_set_powergating_state(void *dev,
366 enum amd_ip_block_type block_type,
367 enum amd_powergating_state state);
368 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
369 u64 *flags);
370 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
371 enum amd_ip_block_type block_type);
372 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
373 enum amd_ip_block_type block_type);
374
375 #define AMDGPU_MAX_IP_NUM 16
376
377 struct amdgpu_ip_block_status {
378 bool valid;
379 bool sw;
380 bool hw;
381 bool late_initialized;
382 bool hang;
383 };
384
385 struct amdgpu_ip_block_version {
386 const enum amd_ip_block_type type;
387 const u32 major;
388 const u32 minor;
389 const u32 rev;
390 const struct amd_ip_funcs *funcs;
391 };
392
393 struct amdgpu_ip_block {
394 struct amdgpu_ip_block_status status;
395 const struct amdgpu_ip_block_version *version;
396 };
397
398 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
399 enum amd_ip_block_type type,
400 u32 major, u32 minor);
401
402 struct amdgpu_ip_block *
403 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
404 enum amd_ip_block_type type);
405
406 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
407 const struct amdgpu_ip_block_version *ip_block_version);
408
409 /*
410 * BIOS.
411 */
412 bool amdgpu_get_bios(struct amdgpu_device *adev);
413 bool amdgpu_read_bios(struct amdgpu_device *adev);
414 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,
415 u8 *bios, u32 length_bytes);
416 /*
417 * Clocks
418 */
419
420 #define AMDGPU_MAX_PPLL 3
421
422 struct amdgpu_clock {
423 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
424 struct amdgpu_pll spll;
425 struct amdgpu_pll mpll;
426 /* 10 Khz units */
427 uint32_t default_mclk;
428 uint32_t default_sclk;
429 uint32_t default_dispclk;
430 uint32_t current_dispclk;
431 uint32_t dp_extclk;
432 uint32_t max_pixel_clock;
433 };
434
435 /* sub-allocation manager, it has to be protected by another lock.
436 * By conception this is an helper for other part of the driver
437 * like the indirect buffer or semaphore, which both have their
438 * locking.
439 *
440 * Principe is simple, we keep a list of sub allocation in offset
441 * order (first entry has offset == 0, last entry has the highest
442 * offset).
443 *
444 * When allocating new object we first check if there is room at
445 * the end total_size - (last_object_offset + last_object_size) >=
446 * alloc_size. If so we allocate new object there.
447 *
448 * When there is not enough room at the end, we start waiting for
449 * each sub object until we reach object_offset+object_size >=
450 * alloc_size, this object then become the sub object we return.
451 *
452 * Alignment can't be bigger than page size.
453 *
454 * Hole are not considered for allocation to keep things simple.
455 * Assumption is that there won't be hole (all object on same
456 * alignment).
457 */
458
459 struct amdgpu_sa_manager {
460 struct drm_suballoc_manager base;
461 struct amdgpu_bo *bo;
462 uint64_t gpu_addr;
463 void *cpu_ptr;
464 };
465
466 int amdgpu_fence_slab_init(void);
467 void amdgpu_fence_slab_fini(void);
468
469 /*
470 * IRQS.
471 */
472
473 struct amdgpu_flip_work {
474 struct delayed_work flip_work;
475 struct work_struct unpin_work;
476 struct amdgpu_device *adev;
477 int crtc_id;
478 u32 target_vblank;
479 uint64_t base;
480 struct drm_pending_vblank_event *event;
481 struct amdgpu_bo *old_abo;
482 unsigned shared_count;
483 struct dma_fence **shared;
484 struct dma_fence_cb cb;
485 bool async;
486 };
487
488
489 /*
490 * file private structure
491 */
492
493 struct amdgpu_fpriv {
494 struct amdgpu_vm vm;
495 struct amdgpu_bo_va *prt_va;
496 struct amdgpu_bo_va *csa_va;
497 struct amdgpu_bo_va *seq64_va;
498 struct rwlock bo_list_lock;
499 struct idr bo_list_handles;
500 struct amdgpu_ctx_mgr ctx_mgr;
501 /** GPU partition selection */
502 uint32_t xcp_id;
503 };
504
505 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
506
507 /*
508 * Writeback
509 */
510 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
511
512 struct amdgpu_wb {
513 struct amdgpu_bo *wb_obj;
514 volatile uint32_t *wb;
515 uint64_t gpu_addr;
516 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
517 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
518 spinlock_t lock;
519 };
520
521 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
522 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
523
524 /*
525 * Benchmarking
526 */
527 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
528
529 /*
530 * ASIC specific register table accessible by UMD
531 */
532 struct amdgpu_allowed_register_entry {
533 uint32_t reg_offset;
534 bool grbm_indexed;
535 };
536
537 /**
538 * enum amd_reset_method - Methods for resetting AMD GPU devices
539 *
540 * @AMD_RESET_METHOD_NONE: The device will not be reset.
541 * @AMD_RESET_LEGACY: Method reserved for SI, CIK and VI ASICs.
542 * @AMD_RESET_MODE0: Reset the entire ASIC. Not currently available for the
543 * any device.
544 * @AMD_RESET_MODE1: Resets all IP blocks on the ASIC (SDMA, GFX, VCN, etc.)
545 * individually. Suitable only for some discrete GPU, not
546 * available for all ASICs.
547 * @AMD_RESET_MODE2: Resets a lesser level of IPs compared to MODE1. Which IPs
548 * are reset depends on the ASIC. Notably doesn't reset IPs
549 * shared with the CPU on APUs or the memory controllers (so
550 * VRAM is not lost). Not available on all ASICs.
551 * @AMD_RESET_BACO: BACO (Bus Alive, Chip Off) method powers off and on the card
552 * but without powering off the PCI bus. Suitable only for
553 * discrete GPUs.
554 * @AMD_RESET_PCI: Does a full bus reset using core Linux subsystem PCI reset
555 * and does a secondary bus reset or FLR, depending on what the
556 * underlying hardware supports.
557 *
558 * Methods available for AMD GPU driver for resetting the device. Not all
559 * methods are suitable for every device. User can override the method using
560 * module parameter `reset_method`.
561 */
562 enum amd_reset_method {
563 AMD_RESET_METHOD_NONE = -1,
564 AMD_RESET_METHOD_LEGACY = 0,
565 AMD_RESET_METHOD_MODE0,
566 AMD_RESET_METHOD_MODE1,
567 AMD_RESET_METHOD_MODE2,
568 AMD_RESET_METHOD_BACO,
569 AMD_RESET_METHOD_PCI,
570 };
571
572 struct amdgpu_video_codec_info {
573 u32 codec_type;
574 u32 max_width;
575 u32 max_height;
576 u32 max_pixels_per_frame;
577 u32 max_level;
578 };
579
580 #define codec_info_build(type, width, height, level) \
581 .codec_type = type,\
582 .max_width = width,\
583 .max_height = height,\
584 .max_pixels_per_frame = height * width,\
585 .max_level = level,
586
587 struct amdgpu_video_codecs {
588 const u32 codec_count;
589 const struct amdgpu_video_codec_info *codec_array;
590 };
591
592 /*
593 * ASIC specific functions.
594 */
595 struct amdgpu_asic_funcs {
596 bool (*read_disabled_bios)(struct amdgpu_device *adev);
597 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
598 u8 *bios, u32 length_bytes);
599 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
600 u32 sh_num, u32 reg_offset, u32 *value);
601 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
602 int (*reset)(struct amdgpu_device *adev);
603 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
604 /* get the reference clock */
605 u32 (*get_xclk)(struct amdgpu_device *adev);
606 /* MM block clocks */
607 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
608 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
609 /* static power management */
610 int (*get_pcie_lanes)(struct amdgpu_device *adev);
611 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
612 /* get config memsize register */
613 u32 (*get_config_memsize)(struct amdgpu_device *adev);
614 /* flush hdp write queue */
615 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
616 /* invalidate hdp read cache */
617 void (*invalidate_hdp)(struct amdgpu_device *adev,
618 struct amdgpu_ring *ring);
619 /* check if the asic needs a full reset of if soft reset will work */
620 bool (*need_full_reset)(struct amdgpu_device *adev);
621 /* initialize doorbell layout for specific asic*/
622 void (*init_doorbell_index)(struct amdgpu_device *adev);
623 /* PCIe bandwidth usage */
624 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
625 uint64_t *count1);
626 /* do we need to reset the asic at init time (e.g., kexec) */
627 bool (*need_reset_on_init)(struct amdgpu_device *adev);
628 /* PCIe replay counter */
629 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
630 /* device supports BACO */
631 int (*supports_baco)(struct amdgpu_device *adev);
632 /* pre asic_init quirks */
633 void (*pre_asic_init)(struct amdgpu_device *adev);
634 /* enter/exit umd stable pstate */
635 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
636 /* query video codecs */
637 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode,
638 const struct amdgpu_video_codecs **codecs);
639 /* encode "> 32bits" smn addressing */
640 u64 (*encode_ext_smn_addressing)(int ext_id);
641
642 ssize_t (*get_reg_state)(struct amdgpu_device *adev,
643 enum amdgpu_reg_state reg_state, void *buf,
644 size_t max_size);
645 };
646
647 /*
648 * IOCTL.
649 */
650 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
651 struct drm_file *filp);
652
653 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
654 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
655 struct drm_file *filp);
656 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
657 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
658 struct drm_file *filp);
659
660 /* VRAM scratch page for HDP bug, default vram page */
661 struct amdgpu_mem_scratch {
662 struct amdgpu_bo *robj;
663 volatile uint32_t *ptr;
664 u64 gpu_addr;
665 };
666
667 /*
668 * CGS
669 */
670 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
671 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
672
673 /*
674 * Core structure, functions and helpers.
675 */
676 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
677 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
678
679 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t);
680 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t);
681
682 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
683 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
684
685 typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device*, uint64_t);
686 typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device*, uint64_t, uint64_t);
687
688 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
689 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
690
691 struct amdgpu_mmio_remap {
692 u32 reg_offset;
693 resource_size_t bus_addr;
694 };
695
696 /* Define the HW IP blocks will be used in driver , add more if necessary */
697 enum amd_hw_ip_block_type {
698 GC_HWIP = 1,
699 HDP_HWIP,
700 SDMA0_HWIP,
701 SDMA1_HWIP,
702 SDMA2_HWIP,
703 SDMA3_HWIP,
704 SDMA4_HWIP,
705 SDMA5_HWIP,
706 SDMA6_HWIP,
707 SDMA7_HWIP,
708 LSDMA_HWIP,
709 MMHUB_HWIP,
710 ATHUB_HWIP,
711 NBIO_HWIP,
712 MP0_HWIP,
713 MP1_HWIP,
714 UVD_HWIP,
715 VCN_HWIP = UVD_HWIP,
716 JPEG_HWIP = VCN_HWIP,
717 VCN1_HWIP,
718 VCE_HWIP,
719 VPE_HWIP,
720 DF_HWIP,
721 DCE_HWIP,
722 OSSSYS_HWIP,
723 SMUIO_HWIP,
724 PWR_HWIP,
725 NBIF_HWIP,
726 THM_HWIP,
727 CLK_HWIP,
728 UMC_HWIP,
729 RSMU_HWIP,
730 XGMI_HWIP,
731 DCI_HWIP,
732 PCIE_HWIP,
733 ISP_HWIP,
734 MAX_HWIP
735 };
736
737 #define HWIP_MAX_INSTANCE 44
738
739 #define HW_ID_MAX 300
740 #define IP_VERSION_FULL(mj, mn, rv, var, srev) \
741 (((mj) << 24) | ((mn) << 16) | ((rv) << 8) | ((var) << 4) | (srev))
742 #define IP_VERSION(mj, mn, rv) IP_VERSION_FULL(mj, mn, rv, 0, 0)
743 #define IP_VERSION_MAJ(ver) ((ver) >> 24)
744 #define IP_VERSION_MIN(ver) (((ver) >> 16) & 0xFF)
745 #define IP_VERSION_REV(ver) (((ver) >> 8) & 0xFF)
746 #define IP_VERSION_VARIANT(ver) (((ver) >> 4) & 0xF)
747 #define IP_VERSION_SUBREV(ver) ((ver) & 0xF)
748 #define IP_VERSION_MAJ_MIN_REV(ver) ((ver) >> 8)
749
750 struct amdgpu_ip_map_info {
751 /* Map of logical to actual dev instances/mask */
752 uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE];
753 int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev,
754 enum amd_hw_ip_block_type block,
755 int8_t inst);
756 uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev,
757 enum amd_hw_ip_block_type block,
758 uint32_t mask);
759 };
760
761 struct amd_powerplay {
762 void *pp_handle;
763 const struct amd_pm_funcs *pp_funcs;
764 };
765
766 struct ip_discovery_top;
767
768 /* polaris10 kickers */
769 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \
770 ((rid == 0xE3) || \
771 (rid == 0xE4) || \
772 (rid == 0xE5) || \
773 (rid == 0xE7) || \
774 (rid == 0xEF))) || \
775 ((did == 0x6FDF) && \
776 ((rid == 0xE7) || \
777 (rid == 0xEF) || \
778 (rid == 0xFF))))
779
780 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \
781 ((rid == 0xE1) || \
782 (rid == 0xF7)))
783
784 /* polaris11 kickers */
785 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \
786 ((rid == 0xE0) || \
787 (rid == 0xE5))) || \
788 ((did == 0x67FF) && \
789 ((rid == 0xCF) || \
790 (rid == 0xEF) || \
791 (rid == 0xFF))))
792
793 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \
794 ((rid == 0xE2)))
795
796 /* polaris12 kickers */
797 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \
798 ((rid == 0xC0) || \
799 (rid == 0xC1) || \
800 (rid == 0xC3) || \
801 (rid == 0xC7))) || \
802 ((did == 0x6981) && \
803 ((rid == 0x00) || \
804 (rid == 0x01) || \
805 (rid == 0x10))))
806
807 struct amdgpu_mqd_prop {
808 uint64_t mqd_gpu_addr;
809 uint64_t hqd_base_gpu_addr;
810 uint64_t rptr_gpu_addr;
811 uint64_t wptr_gpu_addr;
812 uint32_t queue_size;
813 bool use_doorbell;
814 uint32_t doorbell_index;
815 uint64_t eop_gpu_addr;
816 uint32_t hqd_pipe_priority;
817 uint32_t hqd_queue_priority;
818 bool allow_tunneling;
819 bool hqd_active;
820 };
821
822 struct amdgpu_mqd {
823 unsigned mqd_size;
824 int (*init_mqd)(struct amdgpu_device *adev, void *mqd,
825 struct amdgpu_mqd_prop *p);
826 };
827
828 #define AMDGPU_RESET_MAGIC_NUM 64
829 #define AMDGPU_MAX_DF_PERFMONS 4
830 struct amdgpu_reset_domain;
831 struct amdgpu_fru_info;
832
833 /*
834 * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise.
835 */
836 #define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size)
837
838 struct amdgpu_device {
839 struct device self;
840 struct device *dev;
841 struct pci_dev *pdev;
842 struct drm_device ddev;
843
844 pci_chipset_tag_t pc;
845 pcitag_t pa_tag;
846 pci_intr_handle_t intrh;
847 bus_space_tag_t iot;
848 bus_space_tag_t memt;
849 bus_dma_tag_t dmat;
850 void *irqh;
851
852 void (*switchcb)(void *, int, int);
853 void *switchcbarg;
854 void *switchcookie;
855 struct task switchtask;
856 struct rasops_info ro;
857 int console;
858 int primary;
859
860 struct task burner_task;
861 int burner_fblank;
862
863 unsigned long fb_aper_offset;
864 unsigned long fb_aper_size;
865
866 #ifdef CONFIG_DRM_AMD_ACP
867 struct amdgpu_acp acp;
868 #endif
869 struct amdgpu_hive_info *hive;
870 struct amdgpu_xcp_mgr *xcp_mgr;
871 /* ASIC */
872 enum amd_asic_type asic_type;
873 uint32_t family;
874 uint32_t rev_id;
875 uint32_t external_rev_id;
876 unsigned long flags;
877 unsigned long apu_flags;
878 int usec_timeout;
879 const struct amdgpu_asic_funcs *asic_funcs;
880 bool shutdown;
881 bool need_swiotlb;
882 bool accel_working;
883 struct notifier_block acpi_nb;
884 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
885 #ifdef notyet
886 struct debugfs_blob_wrapper debugfs_vbios_blob;
887 struct debugfs_blob_wrapper debugfs_discovery_blob;
888 #endif
889 struct rwlock srbm_mutex;
890 /* GRBM index mutex. Protects concurrent access to GRBM index */
891 struct rwlock grbm_idx_mutex;
892 struct dev_pm_domain vga_pm_domain;
893 bool have_disp_power_ref;
894 bool have_atomics_support;
895
896 /* BIOS */
897 bool is_atom_fw;
898 uint8_t *bios;
899 uint32_t bios_size;
900 uint32_t bios_scratch_reg_offset;
901 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
902
903 /* Register/doorbell mmio */
904 resource_size_t rmmio_base;
905 resource_size_t rmmio_size;
906 void __iomem *rmmio;
907 bus_space_tag_t rmmio_bst;
908 bus_space_handle_t rmmio_bsh;
909 /* protects concurrent MM_INDEX/DATA based register access */
910 spinlock_t mmio_idx_lock;
911 struct amdgpu_mmio_remap rmmio_remap;
912 /* protects concurrent SMC based register access */
913 spinlock_t smc_idx_lock;
914 amdgpu_rreg_t smc_rreg;
915 amdgpu_wreg_t smc_wreg;
916 /* protects concurrent PCIE register access */
917 spinlock_t pcie_idx_lock;
918 amdgpu_rreg_t pcie_rreg;
919 amdgpu_wreg_t pcie_wreg;
920 amdgpu_rreg_t pciep_rreg;
921 amdgpu_wreg_t pciep_wreg;
922 amdgpu_rreg_ext_t pcie_rreg_ext;
923 amdgpu_wreg_ext_t pcie_wreg_ext;
924 amdgpu_rreg64_t pcie_rreg64;
925 amdgpu_wreg64_t pcie_wreg64;
926 amdgpu_rreg64_ext_t pcie_rreg64_ext;
927 amdgpu_wreg64_ext_t pcie_wreg64_ext;
928 /* protects concurrent UVD register access */
929 spinlock_t uvd_ctx_idx_lock;
930 amdgpu_rreg_t uvd_ctx_rreg;
931 amdgpu_wreg_t uvd_ctx_wreg;
932 /* protects concurrent DIDT register access */
933 spinlock_t didt_idx_lock;
934 amdgpu_rreg_t didt_rreg;
935 amdgpu_wreg_t didt_wreg;
936 /* protects concurrent gc_cac register access */
937 spinlock_t gc_cac_idx_lock;
938 amdgpu_rreg_t gc_cac_rreg;
939 amdgpu_wreg_t gc_cac_wreg;
940 /* protects concurrent se_cac register access */
941 spinlock_t se_cac_idx_lock;
942 amdgpu_rreg_t se_cac_rreg;
943 amdgpu_wreg_t se_cac_wreg;
944 /* protects concurrent ENDPOINT (audio) register access */
945 spinlock_t audio_endpt_idx_lock;
946 amdgpu_block_rreg_t audio_endpt_rreg;
947 amdgpu_block_wreg_t audio_endpt_wreg;
948 struct amdgpu_doorbell doorbell;
949
950 /* clock/pll info */
951 struct amdgpu_clock clock;
952
953 /* MC */
954 struct amdgpu_gmc gmc;
955 struct amdgpu_gart gart;
956 dma_addr_t dummy_page_addr;
957 struct amdgpu_vm_manager vm_manager;
958 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
959 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS);
960
961 /* memory management */
962 struct amdgpu_mman mman;
963 struct amdgpu_mem_scratch mem_scratch;
964 struct amdgpu_wb wb;
965 atomic64_t num_bytes_moved;
966 atomic64_t num_evictions;
967 atomic64_t num_vram_cpu_page_faults;
968 atomic_t gpu_reset_counter;
969 atomic_t vram_lost_counter;
970
971 /* data for buffer migration throttling */
972 struct {
973 spinlock_t lock;
974 s64 last_update_us;
975 s64 accum_us; /* accumulated microseconds */
976 s64 accum_us_vis; /* for visible VRAM */
977 u32 log2_max_MBps;
978 } mm_stats;
979
980 /* display */
981 bool enable_virtual_display;
982 struct amdgpu_vkms_output *amdgpu_vkms_output;
983 struct amdgpu_mode_info mode_info;
984 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
985 struct delayed_work hotplug_work;
986 struct amdgpu_irq_src crtc_irq;
987 struct amdgpu_irq_src vline0_irq;
988 struct amdgpu_irq_src vupdate_irq;
989 struct amdgpu_irq_src pageflip_irq;
990 struct amdgpu_irq_src hpd_irq;
991 struct amdgpu_irq_src dmub_trace_irq;
992 struct amdgpu_irq_src dmub_outbox_irq;
993
994 /* rings */
995 u64 fence_context;
996 unsigned num_rings;
997 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
998 struct dma_fence __rcu *gang_submit;
999 bool ib_pool_ready;
1000 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX];
1001 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
1002
1003 /* interrupts */
1004 struct amdgpu_irq irq;
1005
1006 /* powerplay */
1007 struct amd_powerplay powerplay;
1008 struct amdgpu_pm pm;
1009 u64 cg_flags;
1010 u32 pg_flags;
1011
1012 /* nbio */
1013 struct amdgpu_nbio nbio;
1014
1015 /* hdp */
1016 struct amdgpu_hdp hdp;
1017
1018 /* smuio */
1019 struct amdgpu_smuio smuio;
1020
1021 /* mmhub */
1022 struct amdgpu_mmhub mmhub;
1023
1024 /* gfxhub */
1025 struct amdgpu_gfxhub gfxhub;
1026
1027 /* gfx */
1028 struct amdgpu_gfx gfx;
1029
1030 /* sdma */
1031 struct amdgpu_sdma sdma;
1032
1033 /* lsdma */
1034 struct amdgpu_lsdma lsdma;
1035
1036 /* uvd */
1037 struct amdgpu_uvd uvd;
1038
1039 /* vce */
1040 struct amdgpu_vce vce;
1041
1042 /* vcn */
1043 struct amdgpu_vcn vcn;
1044
1045 /* jpeg */
1046 struct amdgpu_jpeg jpeg;
1047
1048 /* vpe */
1049 struct amdgpu_vpe vpe;
1050
1051 /* umsch */
1052 struct amdgpu_umsch_mm umsch_mm;
1053 bool enable_umsch_mm;
1054
1055 /* firmwares */
1056 struct amdgpu_firmware firmware;
1057
1058 /* PSP */
1059 struct psp_context psp;
1060
1061 /* GDS */
1062 struct amdgpu_gds gds;
1063
1064 /* for userq and VM fences */
1065 struct amdgpu_seq64 seq64;
1066
1067 /* KFD */
1068 struct amdgpu_kfd_dev kfd;
1069
1070 /* UMC */
1071 struct amdgpu_umc umc;
1072
1073 /* display related functionality */
1074 struct amdgpu_display_manager dm;
1075
1076 #if defined(CONFIG_DRM_AMD_ISP)
1077 /* isp */
1078 struct amdgpu_isp isp;
1079 #endif
1080
1081 /* mes */
1082 bool enable_mes;
1083 bool enable_mes_kiq;
1084 bool enable_uni_mes;
1085 struct amdgpu_mes mes;
1086 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM];
1087
1088 /* df */
1089 struct amdgpu_df df;
1090
1091 /* MCA */
1092 struct amdgpu_mca mca;
1093
1094 /* ACA */
1095 struct amdgpu_aca aca;
1096
1097 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
1098 uint32_t harvest_ip_mask;
1099 int num_ip_blocks;
1100 struct rwlock mn_lock;
1101 DECLARE_HASHTABLE(mn_hash, 7);
1102
1103 /* tracking pinned memory */
1104 atomic64_t vram_pin_size;
1105 atomic64_t visible_pin_size;
1106 atomic64_t gart_pin_size;
1107
1108 /* soc15 register offset based on ip, instance and segment */
1109 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
1110 struct amdgpu_ip_map_info ip_map;
1111
1112 /* delayed work_func for deferring clockgating during resume */
1113 struct delayed_work delayed_init_work;
1114
1115 struct amdgpu_virt virt;
1116
1117 /* record hw reset is performed */
1118 bool has_hw_reset;
1119 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
1120
1121 /* s3/s4 mask */
1122 bool in_suspend;
1123 bool in_s3;
1124 bool in_s4;
1125 bool in_s0ix;
1126 /* indicate amdgpu suspension status */
1127 bool suspend_complete;
1128
1129 enum pp_mp1_state mp1_state;
1130 struct amdgpu_doorbell_index doorbell_index;
1131
1132 struct rwlock notifier_lock;
1133
1134 int asic_reset_res;
1135 struct work_struct xgmi_reset_work;
1136 struct list_head reset_list;
1137
1138 long gfx_timeout;
1139 long sdma_timeout;
1140 long video_timeout;
1141 long compute_timeout;
1142 long psp_timeout;
1143
1144 uint64_t unique_id;
1145 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
1146
1147 /* enable runtime pm on the device */
1148 bool in_runpm;
1149 bool has_pr3;
1150
1151 bool ucode_sysfs_en;
1152
1153 struct amdgpu_fru_info *fru_info;
1154 atomic_t throttling_logging_enabled;
1155 struct ratelimit_state throttling_logging_rs;
1156 uint32_t ras_hw_enabled;
1157 uint32_t ras_enabled;
1158
1159 bool no_hw_access;
1160 struct pci_saved_state *pci_state;
1161 pci_channel_state_t pci_channel_state;
1162
1163 /* Track auto wait count on s_barrier settings */
1164 bool barrier_has_auto_waitcnt;
1165
1166 struct amdgpu_reset_control *reset_cntl;
1167 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE];
1168
1169 bool ram_is_direct_mapped;
1170
1171 struct list_head ras_list;
1172
1173 struct ip_discovery_top *ip_top;
1174
1175 struct amdgpu_reset_domain *reset_domain;
1176
1177 struct rwlock benchmark_mutex;
1178
1179 bool scpm_enabled;
1180 uint32_t scpm_status;
1181
1182 struct work_struct reset_work;
1183
1184 bool job_hang;
1185 bool dc_enabled;
1186 /* Mask of active clusters */
1187 uint32_t aid_mask;
1188
1189 /* Debug */
1190 bool debug_vm;
1191 bool debug_largebar;
1192 bool debug_disable_soft_recovery;
1193 bool debug_use_vram_fw_buf;
1194 bool debug_enable_ras_aca;
1195 bool debug_exp_resets;
1196
1197 bool enforce_isolation[MAX_XCP];
1198 /* Added this mutex for cleaner shader isolation between GFX and compute processes */
1199 struct rwlock enforce_isolation_mutex;
1200 };
1201
amdgpu_ip_version(const struct amdgpu_device * adev,uint8_t ip,uint8_t inst)1202 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev,
1203 uint8_t ip, uint8_t inst)
1204 {
1205 /* This considers only major/minor/rev and ignores
1206 * subrevision/variant fields.
1207 */
1208 return adev->ip_versions[ip][inst] & ~0xFFU;
1209 }
1210
amdgpu_ip_version_full(const struct amdgpu_device * adev,uint8_t ip,uint8_t inst)1211 static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev,
1212 uint8_t ip, uint8_t inst)
1213 {
1214 /* This returns full version - major/minor/rev/variant/subrevision */
1215 return adev->ip_versions[ip][inst];
1216 }
1217
drm_to_adev(struct drm_device * ddev)1218 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
1219 {
1220 return container_of(ddev, struct amdgpu_device, ddev);
1221 }
1222
adev_to_drm(struct amdgpu_device * adev)1223 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev)
1224 {
1225 return &adev->ddev;
1226 }
1227
amdgpu_ttm_adev(struct ttm_device * bdev)1228 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev)
1229 {
1230 return container_of(bdev, struct amdgpu_device, mman.bdev);
1231 }
1232
1233 int amdgpu_device_init(struct amdgpu_device *adev,
1234 uint32_t flags);
1235 void amdgpu_device_fini_hw(struct amdgpu_device *adev);
1236 void amdgpu_device_fini_sw(struct amdgpu_device *adev);
1237
1238 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1239
1240 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
1241 void *buf, size_t size, bool write);
1242 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
1243 void *buf, size_t size, bool write);
1244
1245 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1246 void *buf, size_t size, bool write);
1247 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev,
1248 uint32_t inst, uint32_t reg_addr, char reg_name[],
1249 uint32_t expected_value, uint32_t mask);
1250 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
1251 uint32_t reg, uint32_t acc_flags);
1252 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev,
1253 u64 reg_addr);
1254 uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev,
1255 uint32_t reg, uint32_t acc_flags,
1256 uint32_t xcc_id);
1257 void amdgpu_device_wreg(struct amdgpu_device *adev,
1258 uint32_t reg, uint32_t v,
1259 uint32_t acc_flags);
1260 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev,
1261 u64 reg_addr, u32 reg_data);
1262 void amdgpu_device_xcc_wreg(struct amdgpu_device *adev,
1263 uint32_t reg, uint32_t v,
1264 uint32_t acc_flags,
1265 uint32_t xcc_id);
1266 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
1267 uint32_t reg, uint32_t v, uint32_t xcc_id);
1268 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1269 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1270
1271 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
1272 u32 reg_addr);
1273 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
1274 u32 reg_addr);
1275 u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev,
1276 u64 reg_addr);
1277 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
1278 u32 reg_addr, u32 reg_data);
1279 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
1280 u32 reg_addr, u64 reg_data);
1281 void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev,
1282 u64 reg_addr, u64 reg_data);
1283 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev);
1284 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1285 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1286
1287 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev);
1288
1289 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
1290 struct amdgpu_reset_context *reset_context);
1291
1292 int amdgpu_do_asic_reset(struct list_head *device_list_handle,
1293 struct amdgpu_reset_context *reset_context);
1294
1295 int emu_soc_asic_init(struct amdgpu_device *adev);
1296
1297 /*
1298 * Registers read & write functions.
1299 */
1300 #define AMDGPU_REGS_NO_KIQ (1<<1)
1301 #define AMDGPU_REGS_RLC (1<<2)
1302
1303 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1304 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1305
1306 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0)
1307 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0)
1308
1309 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1310 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1311
1312 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1313 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1314 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1315 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1316 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1317 #define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst)
1318 #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst)
1319 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1320 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1321 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1322 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1323 #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg))
1324 #define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v))
1325 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1326 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1327 #define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg))
1328 #define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v))
1329 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1330 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1331 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1332 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1333 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1334 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1335 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1336 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1337 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1338 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1339 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1340 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1341 #define WREG32_P(reg, val, mask) \
1342 do { \
1343 uint32_t tmp_ = RREG32(reg); \
1344 tmp_ &= (mask); \
1345 tmp_ |= ((val) & ~(mask)); \
1346 WREG32(reg, tmp_); \
1347 } while (0)
1348 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1349 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1350 #define WREG32_PLL_P(reg, val, mask) \
1351 do { \
1352 uint32_t tmp_ = RREG32_PLL(reg); \
1353 tmp_ &= (mask); \
1354 tmp_ |= ((val) & ~(mask)); \
1355 WREG32_PLL(reg, tmp_); \
1356 } while (0)
1357
1358 #define WREG32_SMC_P(_Reg, _Val, _Mask) \
1359 do { \
1360 u32 tmp = RREG32_SMC(_Reg); \
1361 tmp &= (_Mask); \
1362 tmp |= ((_Val) & ~(_Mask)); \
1363 WREG32_SMC(_Reg, tmp); \
1364 } while (0)
1365
1366 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1367
1368 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1369 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1370
1371 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
1372 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1373 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1374
1375 #define REG_GET_FIELD(value, reg, field) \
1376 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1377
1378 #define WREG32_FIELD(reg, field, val) \
1379 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1380
1381 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1382 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1383
1384 #define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l))
1385 /*
1386 * BIOS helpers.
1387 */
1388 #define RBIOS8(i) (adev->bios[i])
1389 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1390 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1391
1392 /*
1393 * ASICs macro.
1394 */
1395 #define amdgpu_asic_set_vga_state(adev, state) \
1396 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0)
1397 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1398 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1399 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1400 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1401 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1402 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1403 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1404 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1405 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1406 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1407 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1408 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1409 #define amdgpu_asic_flush_hdp(adev, r) \
1410 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r)))
1411 #define amdgpu_asic_invalidate_hdp(adev, r) \
1412 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \
1413 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0))
1414 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1415 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1416 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1417 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1418 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1419 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1420 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
1421 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
1422 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
1423 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c))
1424
1425 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter))
1426
1427 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i))
1428 #define for_each_inst(i, inst_mask) \
1429 for (i = ffs(inst_mask); i-- != 0; \
1430 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1)))
1431
1432 /* Common functions */
1433 bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
1434 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1435 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1436 struct amdgpu_job *job,
1437 struct amdgpu_reset_context *reset_context);
1438 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1439 int amdgpu_device_pci_reset(struct amdgpu_device *adev);
1440 bool amdgpu_device_need_post(struct amdgpu_device *adev);
1441 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev);
1442 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
1443
1444 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1445 u64 num_vis_bytes);
1446 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1447 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1448 const u32 *registers,
1449 const u32 array_size);
1450
1451 int amdgpu_device_mode1_reset(struct amdgpu_device *adev);
1452 bool amdgpu_device_supports_atpx(struct drm_device *dev);
1453 bool amdgpu_device_supports_px(struct drm_device *dev);
1454 bool amdgpu_device_supports_boco(struct drm_device *dev);
1455 bool amdgpu_device_supports_smart_shift(struct drm_device *dev);
1456 int amdgpu_device_supports_baco(struct drm_device *dev);
1457 void amdgpu_device_detect_runtime_pm_mode(struct amdgpu_device *adev);
1458 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1459 struct amdgpu_device *peer_adev);
1460 int amdgpu_device_baco_enter(struct drm_device *dev);
1461 int amdgpu_device_baco_exit(struct drm_device *dev);
1462
1463 void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
1464 struct amdgpu_ring *ring);
1465 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
1466 struct amdgpu_ring *ring);
1467
1468 void amdgpu_device_halt(struct amdgpu_device *adev);
1469 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
1470 u32 reg);
1471 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
1472 u32 reg, u32 v);
1473 struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev);
1474 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
1475 struct dma_fence *gang);
1476 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev);
1477
1478 /* atpx handler */
1479 #if defined(CONFIG_VGA_SWITCHEROO)
1480 void amdgpu_register_atpx_handler(void);
1481 void amdgpu_unregister_atpx_handler(void);
1482 bool amdgpu_has_atpx_dgpu_power_cntl(void);
1483 bool amdgpu_is_atpx_hybrid(void);
1484 bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1485 bool amdgpu_has_atpx(void);
1486 #else
amdgpu_register_atpx_handler(void)1487 static inline void amdgpu_register_atpx_handler(void) {}
amdgpu_unregister_atpx_handler(void)1488 static inline void amdgpu_unregister_atpx_handler(void) {}
amdgpu_has_atpx_dgpu_power_cntl(void)1489 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
amdgpu_is_atpx_hybrid(void)1490 static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
amdgpu_atpx_dgpu_req_power_for_displays(void)1491 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
amdgpu_has_atpx(void)1492 static inline bool amdgpu_has_atpx(void) { return false; }
1493 #endif
1494
1495 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1496 void *amdgpu_atpx_get_dhandle(void);
1497 #else
amdgpu_atpx_get_dhandle(void)1498 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1499 #endif
1500
1501 /*
1502 * KMS
1503 */
1504 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1505 extern const int amdgpu_max_kms_ioctl;
1506
1507 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
1508 void amdgpu_driver_unload_kms(struct drm_device *dev);
1509 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1510 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1511 struct drm_file *file_priv);
1512 void amdgpu_driver_release_kms(struct drm_device *dev);
1513
1514 int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1515 int amdgpu_device_prepare(struct drm_device *dev);
1516 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1517 int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1518 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
1519 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
1520 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
1521 int amdgpu_info_ioctl(struct drm_device *dev, void *data,
1522 struct drm_file *filp);
1523
1524 /*
1525 * functions used by amdgpu_encoder.c
1526 */
1527 struct amdgpu_afmt_acr {
1528 u32 clock;
1529
1530 int n_32khz;
1531 int cts_32khz;
1532
1533 int n_44_1khz;
1534 int cts_44_1khz;
1535
1536 int n_48khz;
1537 int cts_48khz;
1538
1539 };
1540
1541 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1542
1543 /* amdgpu_acpi.c */
1544
1545 struct amdgpu_numa_info {
1546 uint64_t size;
1547 int pxm;
1548 int nid;
1549 };
1550
1551 /* ATCS Device/Driver State */
1552 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0
1553 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3
1554 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0
1555 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1
1556
1557 #if defined(CONFIG_ACPI)
1558 int amdgpu_acpi_init(struct amdgpu_device *adev);
1559 void amdgpu_acpi_fini(struct amdgpu_device *adev);
1560 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1561 bool amdgpu_acpi_is_power_shift_control_supported(void);
1562 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1563 u8 perf_req, bool advertise);
1564 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1565 u8 dev_state, bool drv_state);
1566 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state);
1567 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1568 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset,
1569 u64 *tmr_size);
1570 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id,
1571 struct amdgpu_numa_info *numa_info);
1572
1573 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
1574 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev);
1575 void amdgpu_acpi_detect(void);
1576 void amdgpu_acpi_release(void);
1577 #else
amdgpu_acpi_init(struct amdgpu_device * adev)1578 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
amdgpu_acpi_get_tmr_info(struct amdgpu_device * adev,u64 * tmr_offset,u64 * tmr_size)1579 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev,
1580 u64 *tmr_offset, u64 *tmr_size)
1581 {
1582 return -EINVAL;
1583 }
amdgpu_acpi_get_mem_info(struct amdgpu_device * adev,int xcc_id,struct amdgpu_numa_info * numa_info)1584 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev,
1585 int xcc_id,
1586 struct amdgpu_numa_info *numa_info)
1587 {
1588 return -EINVAL;
1589 }
amdgpu_acpi_fini(struct amdgpu_device * adev)1590 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
amdgpu_acpi_should_gpu_reset(struct amdgpu_device * adev)1591 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; }
amdgpu_acpi_detect(void)1592 static inline void amdgpu_acpi_detect(void) { }
amdgpu_acpi_release(void)1593 static inline void amdgpu_acpi_release(void) { }
amdgpu_acpi_is_power_shift_control_supported(void)1594 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
amdgpu_acpi_power_shift_control(struct amdgpu_device * adev,u8 dev_state,bool drv_state)1595 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1596 u8 dev_state, bool drv_state) { return 0; }
amdgpu_acpi_smart_shift_update(struct drm_device * dev,enum amdgpu_ss ss_state)1597 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev,
1598 enum amdgpu_ss ss_state) { return 0; }
amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps * caps)1599 static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps) { }
1600 #endif
1601
1602 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)
1603 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
1604 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
1605 void amdgpu_choose_low_power_state(struct amdgpu_device *adev);
1606 #else
amdgpu_acpi_is_s0ix_active(struct amdgpu_device * adev)1607 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
amdgpu_acpi_is_s3_active(struct amdgpu_device * adev)1608 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }
amdgpu_choose_low_power_state(struct amdgpu_device * adev)1609 static inline void amdgpu_choose_low_power_state(struct amdgpu_device *adev) { }
1610 #endif
1611
1612 void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1613 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1614
1615 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev,
1616 pci_channel_state_t state);
1617 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev);
1618 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
1619 void amdgpu_pci_resume(struct pci_dev *pdev);
1620
1621 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
1622 bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
1623
1624 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev);
1625
1626 int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1627 enum amd_clockgating_state state);
1628 int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
1629 enum amd_powergating_state state);
1630
amdgpu_device_has_timeouts_enabled(struct amdgpu_device * adev)1631 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev)
1632 {
1633 return amdgpu_gpu_recovery != 0 &&
1634 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT &&
1635 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT &&
1636 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT &&
1637 adev->video_timeout != MAX_SCHEDULE_TIMEOUT;
1638 }
1639
1640 #include "amdgpu_object.h"
1641
amdgpu_is_tmz(struct amdgpu_device * adev)1642 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1643 {
1644 return adev->gmc.tmz_enabled;
1645 }
1646
1647 int amdgpu_in_reset(struct amdgpu_device *adev);
1648
1649 extern const struct attribute_group amdgpu_vram_mgr_attr_group;
1650 extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
1651 extern const struct attribute_group amdgpu_flash_attr_group;
1652
1653 #endif
1654