1 /*-
2 * Copyright (c) 2011 Chelsio Communications, Inc.
3 * All rights reserved.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: stable/9/sys/dev/cxgbe/adapter.h 269358 2014-07-31 23:14:59Z np $
28 *
29 */
30
31 #ifndef __T4_ADAPTER_H__
32 #define __T4_ADAPTER_H__
33
34 #include <sys/kernel.h>
35 #include <sys/bus.h>
36 #include <sys/rman.h>
37 #include <sys/types.h>
38 #include <sys/malloc.h>
39 #include <dev/pci/pcivar.h>
40 #include <dev/pci/pcireg.h>
41 #include <machine/bus.h>
42 #include <sys/socket.h>
43 #include <sys/sysctl.h>
44 #include <net/ethernet.h>
45 #include <net/if.h>
46 #include <net/if_media.h>
47 #include <netinet/in.h>
48 #include <netinet/tcp_lro.h>
49
50 #include "offload.h"
51 #include "firmware/t4fw_interface.h"
52
53 MALLOC_DECLARE(M_CXGBE);
54 #define CXGBE_UNIMPLEMENTED(s) \
55 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
56
57 #if defined(__i386__) || defined(__amd64__)
58 static __inline void
prefetch(void * x)59 prefetch(void *x)
60 {
61 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
62 }
63 #else
64 #define prefetch(x)
65 #endif
66
67 #ifndef SYSCTL_ADD_UQUAD
68 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
69 #define sysctl_handle_64 sysctl_handle_quad
70 #define CTLTYPE_U64 CTLTYPE_QUAD
71 #endif
72
73 #if (__FreeBSD_version >= 900030) || \
74 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000))
75 #define SBUF_DRAIN 1
76 #endif
77
78 #ifdef __amd64__
79 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */
80 static __inline uint64_t
t4_bus_space_read_8(bus_space_tag_t tag,bus_space_handle_t handle,bus_size_t offset)81 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
82 bus_size_t offset)
83 {
84 KASSERT(tag == X86_BUS_SPACE_MEM,
85 ("%s: can only handle mem space", __func__));
86
87 return (*(volatile uint64_t *)(handle + offset));
88 }
89
90 static __inline void
t4_bus_space_write_8(bus_space_tag_t tag,bus_space_handle_t bsh,bus_size_t offset,uint64_t value)91 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
92 bus_size_t offset, uint64_t value)
93 {
94 KASSERT(tag == X86_BUS_SPACE_MEM,
95 ("%s: can only handle mem space", __func__));
96
97 *(volatile uint64_t *)(bsh + offset) = value;
98 }
99 #else
100 static __inline uint64_t
t4_bus_space_read_8(bus_space_tag_t tag,bus_space_handle_t handle,bus_size_t offset)101 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
102 bus_size_t offset)
103 {
104 return (uint64_t)bus_space_read_4(tag, handle, offset) +
105 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32);
106 }
107
108 static __inline void
t4_bus_space_write_8(bus_space_tag_t tag,bus_space_handle_t bsh,bus_size_t offset,uint64_t value)109 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
110 bus_size_t offset, uint64_t value)
111 {
112 bus_space_write_4(tag, bsh, offset, value);
113 bus_space_write_4(tag, bsh, offset + 4, value >> 32);
114 }
115 #endif
116
117 struct adapter;
118 typedef struct adapter adapter_t;
119
120 enum {
121 FW_IQ_QSIZE = 256,
122 FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */
123
124 RX_IQ_QSIZE = 1024,
125 RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */
126
127 EQ_ESIZE = 64, /* All egress queues use this entry size */
128
129 RX_FL_ESIZE = EQ_ESIZE, /* 8 64bit addresses */
130 #if MJUMPAGESIZE != MCLBYTES
131 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */
132 #else
133 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */
134 #endif
135 CL_METADATA_SIZE = CACHE_LINE_SIZE,
136
137 CTRL_EQ_QSIZE = 128,
138
139 TX_EQ_QSIZE = 1024,
140 TX_SGL_SEGS = 36,
141 TX_WR_FLITS = SGE_MAX_WR_LEN / 8
142 };
143
144 enum {
145 /* adapter intr_type */
146 INTR_INTX = (1 << 0),
147 INTR_MSI = (1 << 1),
148 INTR_MSIX = (1 << 2)
149 };
150
151 enum {
152 /* flags understood by begin_synchronized_op */
153 HOLD_LOCK = (1 << 0),
154 SLEEP_OK = (1 << 1),
155 INTR_OK = (1 << 2),
156
157 /* flags understood by end_synchronized_op */
158 LOCK_HELD = HOLD_LOCK,
159 };
160
161 enum {
162 /* adapter flags */
163 FULL_INIT_DONE = (1 << 0),
164 FW_OK = (1 << 1),
165 INTR_DIRECT = (1 << 2), /* direct interrupts for everything */
166 MASTER_PF = (1 << 3),
167 ADAP_SYSCTL_CTX = (1 << 4),
168 TOM_INIT_DONE = (1 << 5),
169 BUF_PACKING_OK = (1 << 6),
170
171 CXGBE_BUSY = (1 << 9),
172
173 /* port flags */
174 DOOMED = (1 << 0),
175 PORT_INIT_DONE = (1 << 1),
176 PORT_SYSCTL_CTX = (1 << 2),
177 };
178
179 #define IS_DOOMED(pi) ((pi)->flags & DOOMED)
180 #define SET_DOOMED(pi) do {(pi)->flags |= DOOMED;} while (0)
181 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY)
182 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0)
183 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
184
185 struct port_info {
186 device_t dev;
187 struct adapter *adapter;
188
189 struct ifnet *ifp;
190 struct ifmedia media;
191
192 struct mtx pi_lock;
193 char lockname[16];
194 unsigned long flags;
195 int if_flags;
196
197 uint16_t *rss;
198 uint16_t viid;
199 int16_t xact_addr_filt;/* index of exact MAC address filter */
200 uint16_t rss_size; /* size of VI's RSS table slice */
201 uint8_t lport; /* associated offload logical port */
202 int8_t mdio_addr;
203 uint8_t port_type;
204 uint8_t mod_type;
205 uint8_t port_id;
206 uint8_t tx_chan;
207 uint8_t rx_chan_map; /* rx MPS channel bitmap */
208
209 /* These need to be int as they are used in sysctl */
210 int ntxq; /* # of tx queues */
211 int first_txq; /* index of first tx queue */
212 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */
213 int nrxq; /* # of rx queues */
214 int first_rxq; /* index of first rx queue */
215 #ifdef TCP_OFFLOAD
216 int nofldtxq; /* # of offload tx queues */
217 int first_ofld_txq; /* index of first offload tx queue */
218 int nofldrxq; /* # of offload rx queues */
219 int first_ofld_rxq; /* index of first offload rx queue */
220 #endif
221 int tmr_idx;
222 int pktc_idx;
223 int qsize_rxq;
224 int qsize_txq;
225
226 int linkdnrc;
227 struct link_config link_cfg;
228 struct port_stats stats;
229
230 eventhandler_tag vlan_c;
231
232 struct callout tick;
233 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */
234
235 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
236 };
237
238 /* Where the cluster came from, how it has been carved up. */
239 struct cluster_layout {
240 int8_t zidx;
241 int8_t hwidx;
242 uint16_t region1; /* mbufs laid out within this region */
243 /* region2 is the DMA region */
244 uint16_t region3; /* cluster_metadata within this region */
245 };
246
247 struct cluster_metadata {
248 u_int refcount;
249 #ifdef INVARIANTS
250 struct fl_sdesc *sd; /* For debug only. Could easily be stale */
251 #endif
252 };
253
254 struct fl_sdesc {
255 caddr_t cl;
256 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */
257 struct cluster_layout cll;
258 };
259
260 struct tx_desc {
261 __be64 flit[8];
262 };
263
264 struct tx_map {
265 struct mbuf *m;
266 bus_dmamap_t map;
267 };
268
269 /* DMA maps used for tx */
270 struct tx_maps {
271 struct tx_map *maps;
272 uint32_t map_total; /* # of DMA maps */
273 uint32_t map_pidx; /* next map to be used */
274 uint32_t map_cidx; /* reclaimed up to this index */
275 uint32_t map_avail; /* # of available maps */
276 };
277
278 struct tx_sdesc {
279 uint8_t desc_used; /* # of hardware descriptors used by the WR */
280 uint8_t credits; /* NIC txq: # of frames sent out in the WR */
281 };
282
283 enum {
284 /* iq flags */
285 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */
286 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */
287 IQ_INTR = (1 << 2), /* iq takes direct interrupt */
288 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */
289
290 /* iq state */
291 IQS_DISABLED = 0,
292 IQS_BUSY = 1,
293 IQS_IDLE = 2,
294 };
295
296 /*
297 * Ingress Queue: T4 is producer, driver is consumer.
298 */
299 struct sge_iq {
300 bus_dma_tag_t desc_tag;
301 bus_dmamap_t desc_map;
302 bus_addr_t ba; /* bus address of descriptor ring */
303 uint32_t flags;
304 uint16_t abs_id; /* absolute SGE id for the iq */
305 int8_t intr_pktc_idx; /* packet count threshold index */
306 int8_t pad0;
307 __be64 *desc; /* KVA of descriptor ring */
308
309 volatile int state;
310 struct adapter *adapter;
311 const __be64 *cdesc; /* current descriptor */
312 uint8_t gen; /* generation bit */
313 uint8_t intr_params; /* interrupt holdoff parameters */
314 uint8_t intr_next; /* XXX: holdoff for next interrupt */
315 uint8_t esize; /* size (bytes) of each entry in the queue */
316 uint16_t qsize; /* size (# of entries) of the queue */
317 uint16_t cidx; /* consumer index */
318 uint16_t cntxt_id; /* SGE context id for the iq */
319
320 STAILQ_ENTRY(sge_iq) link;
321 };
322
323 enum {
324 EQ_CTRL = 1,
325 EQ_ETH = 2,
326 #ifdef TCP_OFFLOAD
327 EQ_OFLD = 3,
328 #endif
329
330 /* eq flags */
331 EQ_TYPEMASK = 7, /* 3 lsbits hold the type */
332 EQ_ALLOCATED = (1 << 3), /* firmware resources allocated */
333 EQ_DOOMED = (1 << 4), /* about to be destroyed */
334 EQ_CRFLUSHED = (1 << 5), /* expecting an update from SGE */
335 EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */
336 };
337
338 /* Listed in order of preference. Update t4_sysctls too if you change these */
339 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB};
340
341 /*
342 * Egress Queue: driver is producer, T4 is consumer.
343 *
344 * Note: A free list is an egress queue (driver produces the buffers and T4
345 * consumes them) but it's special enough to have its own struct (see sge_fl).
346 */
347 struct sge_eq {
348 unsigned int flags; /* MUST be first */
349 unsigned int cntxt_id; /* SGE context id for the eq */
350 bus_dma_tag_t desc_tag;
351 bus_dmamap_t desc_map;
352 char lockname[16];
353 struct mtx eq_lock;
354
355 struct tx_desc *desc; /* KVA of descriptor ring */
356 bus_addr_t ba; /* bus address of descriptor ring */
357 struct sge_qstat *spg; /* status page, for convenience */
358 int doorbells;
359 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */
360 u_int udb_qid; /* relative qid within the doorbell page */
361 uint16_t cap; /* max # of desc, for convenience */
362 uint16_t avail; /* available descriptors, for convenience */
363 uint16_t qsize; /* size (# of entries) of the queue */
364 uint16_t cidx; /* consumer idx (desc idx) */
365 uint16_t pidx; /* producer idx (desc idx) */
366 uint16_t pending; /* # of descriptors used since last doorbell */
367 uint16_t iqid; /* iq that gets egr_update for the eq */
368 uint8_t tx_chan; /* tx channel used by the eq */
369 struct task tx_task;
370 struct callout tx_callout;
371
372 /* stats */
373
374 uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for eq */
375 uint32_t unstalled; /* recovered from stall */
376 };
377
378 struct sw_zone_info {
379 uma_zone_t zone; /* zone that this cluster comes from */
380 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */
381 int type; /* EXT_xxx type of the cluster */
382 int8_t head_hwidx;
383 int8_t tail_hwidx;
384 };
385
386 struct hw_buf_info {
387 int8_t zidx; /* backpointer to zone; -ve means unused */
388 int8_t next; /* next hwidx for this zone; -1 means no more */
389 int size;
390 };
391
392 enum {
393 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */
394 FL_DOOMED = (1 << 1), /* about to be destroyed */
395 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */
396 };
397
398 #define FL_RUNNING_LOW(fl) (fl->cap - fl->needed <= fl->lowat)
399 #define FL_NOT_RUNNING_LOW(fl) (fl->cap - fl->needed >= 2 * fl->lowat)
400
401 struct sge_fl {
402 bus_dma_tag_t desc_tag;
403 bus_dmamap_t desc_map;
404 struct cluster_layout cll_def; /* default refill zone, layout */
405 struct cluster_layout cll_alt; /* alternate refill zone, layout */
406 struct mtx fl_lock;
407 char lockname[16];
408 int flags;
409
410 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
411 bus_addr_t ba; /* bus address of descriptor ring */
412 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
413 uint32_t cap; /* max # of buffers, for convenience */
414 uint16_t qsize; /* size (# of entries) of the queue */
415 uint16_t cntxt_id; /* SGE context id for the freelist */
416 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */
417 uint32_t rx_offset; /* offset in fl buf (when buffer packing) */
418 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */
419 uint32_t needed; /* # of buffers needed to fill up fl. */
420 uint32_t lowat; /* # of buffers <= this means fl needs help */
421 uint32_t pending; /* # of bufs allocated since last doorbell */
422 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
423
424 struct mbuf *m0;
425 struct mbuf **pnext;
426 u_int remaining;
427
428 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */
429 uint64_t mbuf_inlined; /* # of mbuf created within clusters */
430 uint64_t cl_allocated; /* # of clusters allocated */
431 uint64_t cl_recycled; /* # of clusters recycled */
432 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */
433 };
434
435 /* txq: SGE egress queue + what's needed for Ethernet NIC */
436 struct sge_txq {
437 struct sge_eq eq; /* MUST be first */
438
439 struct ifnet *ifp; /* the interface this txq belongs to */
440 bus_dma_tag_t tx_tag; /* tag for transmit buffers */
441 struct buf_ring *br; /* tx buffer ring */
442 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
443 struct mbuf *m; /* held up due to temporary resource shortage */
444
445 struct tx_maps txmaps;
446
447 /* stats for common events first */
448
449 uint64_t txcsum; /* # of times hardware assisted with checksum */
450 uint64_t tso_wrs; /* # of TSO work requests */
451 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
452 uint64_t imm_wrs; /* # of work requests with immediate data */
453 uint64_t sgl_wrs; /* # of work requests with direct SGL */
454 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
455 uint64_t txpkts_wrs; /* # of coalesced tx work requests */
456 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */
457
458 /* stats for not-that-common events */
459
460 uint32_t no_dmamap; /* no DMA map to load the mbuf */
461 uint32_t no_desc; /* out of hardware descriptors */
462 } __aligned(CACHE_LINE_SIZE);
463
464 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
465 struct sge_rxq {
466 struct sge_iq iq; /* MUST be first */
467 struct sge_fl fl; /* MUST follow iq */
468
469 struct ifnet *ifp; /* the interface this rxq belongs to */
470 #if defined(INET) || defined(INET6)
471 struct lro_ctrl lro; /* LRO state */
472 #endif
473
474 /* stats for common events first */
475
476 uint64_t rxcsum; /* # of times hardware assisted with checksum */
477 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
478
479 /* stats for not-that-common events */
480
481 } __aligned(CACHE_LINE_SIZE);
482
483 static inline struct sge_rxq *
iq_to_rxq(struct sge_iq * iq)484 iq_to_rxq(struct sge_iq *iq)
485 {
486
487 return (__containerof(iq, struct sge_rxq, iq));
488 }
489
490
491 #ifdef TCP_OFFLOAD
492 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
493 struct sge_ofld_rxq {
494 struct sge_iq iq; /* MUST be first */
495 struct sge_fl fl; /* MUST follow iq */
496 } __aligned(CACHE_LINE_SIZE);
497
498 static inline struct sge_ofld_rxq *
iq_to_ofld_rxq(struct sge_iq * iq)499 iq_to_ofld_rxq(struct sge_iq *iq)
500 {
501
502 return (__containerof(iq, struct sge_ofld_rxq, iq));
503 }
504 #endif
505
506 struct wrqe {
507 STAILQ_ENTRY(wrqe) link;
508 struct sge_wrq *wrq;
509 int wr_len;
510 uint64_t wr[] __aligned(16);
511 };
512
513 /*
514 * wrq: SGE egress queue that is given prebuilt work requests. Both the control
515 * and offload tx queues are of this type.
516 */
517 struct sge_wrq {
518 struct sge_eq eq; /* MUST be first */
519
520 struct adapter *adapter;
521
522 /* List of WRs held up due to lack of tx descriptors */
523 STAILQ_HEAD(, wrqe) wr_list;
524
525 /* stats for common events first */
526
527 uint64_t tx_wrs; /* # of tx work requests */
528
529 /* stats for not-that-common events */
530
531 uint32_t no_desc; /* out of hardware descriptors */
532 } __aligned(CACHE_LINE_SIZE);
533
534 struct sge {
535 int timer_val[SGE_NTIMERS];
536 int counter_val[SGE_NCOUNTERS];
537 int fl_starve_threshold;
538 int fl_starve_threshold2;
539 int eq_s_qpp;
540 int iq_s_qpp;
541
542 int nrxq; /* total # of Ethernet rx queues */
543 int ntxq; /* total # of Ethernet tx tx queues */
544 #ifdef TCP_OFFLOAD
545 int nofldrxq; /* total # of TOE rx queues */
546 int nofldtxq; /* total # of TOE tx queues */
547 #endif
548 int niq; /* total # of ingress queues */
549 int neq; /* total # of egress queues */
550
551 struct sge_iq fwq; /* Firmware event queue */
552 struct sge_wrq mgmtq; /* Management queue (control queue) */
553 struct sge_wrq *ctrlq; /* Control queues */
554 struct sge_txq *txq; /* NIC tx queues */
555 struct sge_rxq *rxq; /* NIC rx queues */
556 #ifdef TCP_OFFLOAD
557 struct sge_wrq *ofld_txq; /* TOE tx queues */
558 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
559 #endif
560
561 uint16_t iq_start;
562 int eq_start;
563 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
564 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
565
566 int pack_boundary;
567 int8_t safe_hwidx1; /* may not have room for metadata */
568 int8_t safe_hwidx2; /* with room for metadata and maybe more */
569 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES];
570 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES];
571 };
572
573 struct rss_header;
574 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
575 struct mbuf *);
576 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *);
577 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
578
579 struct adapter {
580 SLIST_ENTRY(adapter) link;
581 device_t dev;
582 struct cdev *cdev;
583
584 /* PCIe register resources */
585 int regs_rid;
586 struct resource *regs_res;
587 int msix_rid;
588 struct resource *msix_res;
589 bus_space_handle_t bh;
590 bus_space_tag_t bt;
591 bus_size_t mmio_len;
592 int udbs_rid;
593 struct resource *udbs_res;
594 volatile uint8_t *udbs_base;
595
596 unsigned int pf;
597 unsigned int mbox;
598
599 /* Interrupt information */
600 int intr_type;
601 int intr_count;
602 struct irq {
603 struct resource *res;
604 int rid;
605 void *tag;
606 } *irq;
607
608 bus_dma_tag_t dmat; /* Parent DMA tag */
609
610 struct sge sge;
611
612 struct taskqueue *tq[NCHAN]; /* taskqueues that flush data out */
613 struct port_info *port[MAX_NPORTS];
614 uint8_t chan_map[NCHAN];
615
616 #ifdef TCP_OFFLOAD
617 void *tom_softc; /* (struct tom_data *) */
618 struct tom_tunables tt;
619 #endif
620 struct l2t_data *l2t; /* L2 table */
621 struct tid_info tids;
622
623 int doorbells;
624 int open_device_map;
625 #ifdef TCP_OFFLOAD
626 int offload_map;
627 #endif
628 int flags;
629
630 char fw_version[32];
631 char cfg_file[32];
632 u_int cfcsum;
633 struct adapter_params params;
634 struct t4_virt_res vres;
635
636 uint16_t linkcaps;
637 uint16_t niccaps;
638 uint16_t toecaps;
639 uint16_t rdmacaps;
640 uint16_t iscsicaps;
641 uint16_t fcoecaps;
642
643 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */
644
645 struct mtx sc_lock;
646 char lockname[16];
647
648 /* Starving free lists */
649 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */
650 TAILQ_HEAD(, sge_fl) sfl;
651 struct callout sfl_callout;
652
653 an_handler_t an_handler __aligned(CACHE_LINE_SIZE);
654 fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */
655 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */
656
657 #ifdef INVARIANTS
658 const char *last_op;
659 const void *last_op_thr;
660 #endif
661
662 int sc_do_rxcopy;
663 };
664
665 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock)
666 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock)
667 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED)
668 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
669
670 /* XXX: not bulletproof, but much better than nothing */
671 #define ASSERT_SYNCHRONIZED_OP(sc) \
672 KASSERT(IS_BUSY(sc) && \
673 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \
674 ("%s: operation not synchronized.", __func__))
675
676 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock)
677 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock)
678 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED)
679 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
680
681 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock)
682 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock)
683 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock)
684 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED)
685 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
686
687 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
688 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
689 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
690 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
691
692 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock)
693 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock)
694 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock)
695 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED)
696 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
697
698 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
699 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq)
700 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
701 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
702 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
703
704 #define for_each_txq(pi, iter, q) \
705 for (q = &pi->adapter->sge.txq[pi->first_txq], iter = 0; \
706 iter < pi->ntxq; ++iter, ++q)
707 #define for_each_rxq(pi, iter, q) \
708 for (q = &pi->adapter->sge.rxq[pi->first_rxq], iter = 0; \
709 iter < pi->nrxq; ++iter, ++q)
710 #define for_each_ofld_txq(pi, iter, q) \
711 for (q = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq], iter = 0; \
712 iter < pi->nofldtxq; ++iter, ++q)
713 #define for_each_ofld_rxq(pi, iter, q) \
714 for (q = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq], iter = 0; \
715 iter < pi->nofldrxq; ++iter, ++q)
716
717 /* One for errors, one for firmware events */
718 #define T4_EXTRA_INTR 2
719
720 static inline uint32_t
t4_read_reg(struct adapter * sc,uint32_t reg)721 t4_read_reg(struct adapter *sc, uint32_t reg)
722 {
723
724 return bus_space_read_4(sc->bt, sc->bh, reg);
725 }
726
727 static inline void
t4_write_reg(struct adapter * sc,uint32_t reg,uint32_t val)728 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
729 {
730
731 bus_space_write_4(sc->bt, sc->bh, reg, val);
732 }
733
734 static inline uint64_t
t4_read_reg64(struct adapter * sc,uint32_t reg)735 t4_read_reg64(struct adapter *sc, uint32_t reg)
736 {
737
738 return t4_bus_space_read_8(sc->bt, sc->bh, reg);
739 }
740
741 static inline void
t4_write_reg64(struct adapter * sc,uint32_t reg,uint64_t val)742 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
743 {
744
745 t4_bus_space_write_8(sc->bt, sc->bh, reg, val);
746 }
747
748 static inline void
t4_os_pci_read_cfg1(struct adapter * sc,int reg,uint8_t * val)749 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
750 {
751
752 *val = pci_read_config(sc->dev, reg, 1);
753 }
754
755 static inline void
t4_os_pci_write_cfg1(struct adapter * sc,int reg,uint8_t val)756 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
757 {
758
759 pci_write_config(sc->dev, reg, val, 1);
760 }
761
762 static inline void
t4_os_pci_read_cfg2(struct adapter * sc,int reg,uint16_t * val)763 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
764 {
765
766 *val = pci_read_config(sc->dev, reg, 2);
767 }
768
769 static inline void
t4_os_pci_write_cfg2(struct adapter * sc,int reg,uint16_t val)770 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
771 {
772
773 pci_write_config(sc->dev, reg, val, 2);
774 }
775
776 static inline void
t4_os_pci_read_cfg4(struct adapter * sc,int reg,uint32_t * val)777 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
778 {
779
780 *val = pci_read_config(sc->dev, reg, 4);
781 }
782
783 static inline void
t4_os_pci_write_cfg4(struct adapter * sc,int reg,uint32_t val)784 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
785 {
786
787 pci_write_config(sc->dev, reg, val, 4);
788 }
789
790 static inline struct port_info *
adap2pinfo(struct adapter * sc,int idx)791 adap2pinfo(struct adapter *sc, int idx)
792 {
793
794 return (sc->port[idx]);
795 }
796
797 static inline void
t4_os_set_hw_addr(struct adapter * sc,int idx,uint8_t hw_addr[])798 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[])
799 {
800
801 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN);
802 }
803
804 static inline bool
is_10G_port(const struct port_info * pi)805 is_10G_port(const struct port_info *pi)
806 {
807
808 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0);
809 }
810
811 static inline bool
is_40G_port(const struct port_info * pi)812 is_40G_port(const struct port_info *pi)
813 {
814
815 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0);
816 }
817
818 static inline int
tx_resume_threshold(struct sge_eq * eq)819 tx_resume_threshold(struct sge_eq *eq)
820 {
821
822 return (eq->qsize / 4);
823 }
824
825 /* t4_main.c */
826 void t4_tx_task(void *, int);
827 void t4_tx_callout(void *);
828 int t4_os_find_pci_capability(struct adapter *, int);
829 int t4_os_pci_save_state(struct adapter *);
830 int t4_os_pci_restore_state(struct adapter *);
831 void t4_os_portmod_changed(const struct adapter *, int);
832 void t4_os_link_changed(struct adapter *, int, int, int);
833 void t4_iterate(void (*)(struct adapter *, void *), void *);
834 int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t);
835 int t4_register_an_handler(struct adapter *, an_handler_t);
836 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t);
837 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
838 int begin_synchronized_op(struct adapter *, struct port_info *, int, char *);
839 void end_synchronized_op(struct adapter *, int);
840
841 /* t4_sge.c */
842 void t4_sge_modload(void);
843 void t4_init_sge_cpl_handlers(struct adapter *);
844 void t4_tweak_chip_settings(struct adapter *);
845 int t4_read_chip_settings(struct adapter *);
846 int t4_create_dma_tag(struct adapter *);
847 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *,
848 struct sysctl_oid_list *);
849 int t4_destroy_dma_tag(struct adapter *);
850 int t4_setup_adapter_queues(struct adapter *);
851 int t4_teardown_adapter_queues(struct adapter *);
852 int t4_setup_port_queues(struct port_info *);
853 int t4_teardown_port_queues(struct port_info *);
854 int t4_alloc_tx_maps(struct tx_maps *, bus_dma_tag_t, int, int);
855 void t4_free_tx_maps(struct tx_maps *, bus_dma_tag_t);
856 void t4_intr_all(void *);
857 void t4_intr(void *);
858 void t4_intr_err(void *);
859 void t4_intr_evt(void *);
860 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *);
861 int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *);
862 void t4_update_fl_bufsize(struct ifnet *);
863 int can_resume_tx(struct sge_eq *);
864
865 static inline struct wrqe *
alloc_wrqe(int wr_len,struct sge_wrq * wrq)866 alloc_wrqe(int wr_len, struct sge_wrq *wrq)
867 {
868 int len = offsetof(struct wrqe, wr) + wr_len;
869 struct wrqe *wr;
870
871 wr = malloc(len, M_CXGBE, M_NOWAIT);
872 if (__predict_false(wr == NULL))
873 return (NULL);
874 wr->wr_len = wr_len;
875 wr->wrq = wrq;
876 return (wr);
877 }
878
879 static inline void *
wrtod(struct wrqe * wr)880 wrtod(struct wrqe *wr)
881 {
882 return (&wr->wr[0]);
883 }
884
885 static inline void
free_wrqe(struct wrqe * wr)886 free_wrqe(struct wrqe *wr)
887 {
888 free(wr, M_CXGBE);
889 }
890
891 static inline void
t4_wrq_tx(struct adapter * sc,struct wrqe * wr)892 t4_wrq_tx(struct adapter *sc, struct wrqe *wr)
893 {
894 struct sge_wrq *wrq = wr->wrq;
895
896 TXQ_LOCK(wrq);
897 t4_wrq_tx_locked(sc, wrq, wr);
898 TXQ_UNLOCK(wrq);
899 }
900
901 #endif
902