1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 1996, by Steve Passe
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. The name of the developer may NOT be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 #include "opt_acpi.h"
30 #include "opt_apic.h"
31 #include "opt_cpu.h"
32 #include "opt_kstack_pages.h"
33 #include "opt_pmap.h"
34 #include "opt_sched.h"
35 #include "opt_smp.h"
36
37 #if !defined(lint)
38 #if !defined(SMP)
39 #error How did you get here?
40 #endif
41
42 #ifndef DEV_APIC
43 #error The apic device is required for SMP, add "device apic" to your config file.
44 #endif
45 #endif /* not lint */
46
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/bus.h>
50 #include <sys/cons.h> /* cngetc() */
51 #include <sys/cpuset.h>
52 #ifdef GPROF
53 #include <sys/gmon.h>
54 #endif
55 #include <sys/kdb.h>
56 #include <sys/kernel.h>
57 #include <sys/ktr.h>
58 #include <sys/lock.h>
59 #include <sys/malloc.h>
60 #include <sys/memrange.h>
61 #include <sys/mutex.h>
62 #include <sys/pcpu.h>
63 #include <sys/proc.h>
64 #include <sys/sched.h>
65 #include <sys/smp.h>
66 #include <sys/sysctl.h>
67
68 #include <vm/vm.h>
69 #include <vm/vm_param.h>
70 #include <vm/pmap.h>
71 #include <vm/vm_kern.h>
72 #include <vm/vm_extern.h>
73
74 #include <x86/apicreg.h>
75 #include <machine/clock.h>
76 #include <machine/cpu.h>
77 #include <machine/cputypes.h>
78 #include <x86/mca.h>
79 #include <machine/md_var.h>
80 #include <machine/pcb.h>
81 #include <machine/psl.h>
82 #include <machine/smp.h>
83 #include <machine/specialreg.h>
84 #include <x86/ucode.h>
85
86 #ifdef DEV_ACPI
87 #include <contrib/dev/acpica/include/acpi.h>
88 #include <dev/acpica/acpivar.h>
89 #endif
90
91 #define WARMBOOT_TARGET 0
92 #define WARMBOOT_OFF (PMAP_MAP_LOW + 0x0467)
93 #define WARMBOOT_SEG (PMAP_MAP_LOW + 0x0469)
94
95 #define CMOS_REG (0x70)
96 #define CMOS_DATA (0x71)
97 #define BIOS_RESET (0x0f)
98 #define BIOS_WARM (0x0a)
99
100 /*
101 * this code MUST be enabled here and in mpboot.s.
102 * it follows the very early stages of AP boot by placing values in CMOS ram.
103 * it NORMALLY will never be needed and thus the primitive method for enabling.
104 *
105 #define CHECK_POINTS
106 */
107
108 #if defined(CHECK_POINTS)
109 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
110 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
111
112 #define CHECK_INIT(D); \
113 CHECK_WRITE(0x34, (D)); \
114 CHECK_WRITE(0x35, (D)); \
115 CHECK_WRITE(0x36, (D)); \
116 CHECK_WRITE(0x37, (D)); \
117 CHECK_WRITE(0x38, (D)); \
118 CHECK_WRITE(0x39, (D));
119
120 #define CHECK_PRINT(S); \
121 printf("%s: %d, %d, %d, %d, %d, %d\n", \
122 (S), \
123 CHECK_READ(0x34), \
124 CHECK_READ(0x35), \
125 CHECK_READ(0x36), \
126 CHECK_READ(0x37), \
127 CHECK_READ(0x38), \
128 CHECK_READ(0x39));
129
130 #else /* CHECK_POINTS */
131
132 #define CHECK_INIT(D)
133 #define CHECK_PRINT(S)
134 #define CHECK_WRITE(A, D)
135
136 #endif /* CHECK_POINTS */
137
138 /*
139 * Local data and functions.
140 */
141
142 static void install_ap_tramp(void);
143 static int start_all_aps(void);
144 static int start_ap(int apic_id);
145
146 static char *ap_copyout_buf;
147 static char *ap_tramp_stack_base;
148
149 unsigned int boot_address;
150
151 #define MiB(v) (v ## ULL << 20)
152
153 /* Allocate memory for the AP trampoline. */
154 void
alloc_ap_trampoline(vm_paddr_t * physmap,unsigned int * physmap_idx)155 alloc_ap_trampoline(vm_paddr_t *physmap, unsigned int *physmap_idx)
156 {
157 unsigned int i;
158 bool allocated;
159
160 allocated = false;
161 for (i = *physmap_idx; i <= *physmap_idx; i -= 2) {
162 /*
163 * Find a memory region big enough and below the 1MB boundary
164 * for the trampoline code.
165 * NB: needs to be page aligned.
166 */
167 if (physmap[i] >= MiB(1) ||
168 (trunc_page(physmap[i + 1]) - round_page(physmap[i])) <
169 round_page(bootMP_size))
170 continue;
171
172 allocated = true;
173 /*
174 * Try to steal from the end of the region to mimic previous
175 * behaviour, else fallback to steal from the start.
176 */
177 if (physmap[i + 1] < MiB(1)) {
178 boot_address = trunc_page(physmap[i + 1]);
179 if ((physmap[i + 1] - boot_address) < bootMP_size)
180 boot_address -= round_page(bootMP_size);
181 physmap[i + 1] = boot_address;
182 } else {
183 boot_address = round_page(physmap[i]);
184 physmap[i] = boot_address + round_page(bootMP_size);
185 }
186 if (physmap[i] == physmap[i + 1] && *physmap_idx != 0) {
187 memmove(&physmap[i], &physmap[i + 2],
188 sizeof(*physmap) * (*physmap_idx - i + 2));
189 *physmap_idx -= 2;
190 }
191 break;
192 }
193
194 if (!allocated) {
195 boot_address = basemem * 1024 - bootMP_size;
196 if (bootverbose)
197 printf(
198 "Cannot find enough space for the boot trampoline, placing it at %#x",
199 boot_address);
200 }
201 }
202
203 /*
204 * Initialize the IPI handlers and start up the AP's.
205 */
206 void
cpu_mp_start(void)207 cpu_mp_start(void)
208 {
209 int i;
210
211 /* Initialize the logical ID to APIC ID table. */
212 for (i = 0; i < MAXCPU; i++) {
213 cpu_apic_ids[i] = -1;
214 }
215
216 /* Install an inter-CPU IPI for TLB invalidation */
217 setidt(IPI_INVLTLB, IDTVEC(invltlb),
218 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
219 setidt(IPI_INVLPG, IDTVEC(invlpg),
220 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
221 setidt(IPI_INVLRNG, IDTVEC(invlrng),
222 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
223
224 /* Install an inter-CPU IPI for cache invalidation. */
225 setidt(IPI_INVLCACHE, IDTVEC(invlcache),
226 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
227
228 /* Install an inter-CPU IPI for all-CPU rendezvous */
229 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous),
230 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
231
232 /* Install generic inter-CPU IPI handler */
233 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler),
234 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
235
236 /* Install an inter-CPU IPI for CPU stop/restart */
237 setidt(IPI_STOP, IDTVEC(cpustop),
238 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
239
240 /* Install an inter-CPU IPI for CPU suspend/resume */
241 setidt(IPI_SUSPEND, IDTVEC(cpususpend),
242 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
243
244 /* Install an IPI for calling delayed SWI */
245 setidt(IPI_SWI, IDTVEC(ipi_swi),
246 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
247
248 /* Set boot_cpu_id if needed. */
249 if (boot_cpu_id == -1) {
250 boot_cpu_id = PCPU_GET(apic_id);
251 cpu_info[boot_cpu_id].cpu_bsp = 1;
252 } else
253 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
254 ("BSP's APIC ID doesn't match boot_cpu_id"));
255
256 /* Probe logical/physical core configuration. */
257 topo_probe();
258
259 assign_cpu_ids();
260
261 /* Start each Application Processor */
262 start_all_aps();
263
264 set_interrupt_apic_ids();
265
266 #if defined(DEV_ACPI) && MAXMEMDOM > 1
267 acpi_pxm_set_cpu_locality();
268 #endif
269 }
270
271 /*
272 * AP CPU's call this to initialize themselves.
273 */
274 void
init_secondary(void)275 init_secondary(void)
276 {
277 struct pcpu *pc;
278 struct i386tss *common_tssp;
279 struct region_descriptor r_gdt, r_idt;
280 int gsel_tss, myid, x;
281 u_int cr0;
282
283 /* bootAP is set in start_ap() to our ID. */
284 myid = bootAP;
285
286 /* Update microcode before doing anything else. */
287 ucode_load_ap(myid);
288
289 /* Get per-cpu data */
290 pc = &__pcpu[myid];
291
292 /* prime data page for it to use */
293 pcpu_init(pc, myid, sizeof(struct pcpu));
294 dpcpu_init(dpcpu, myid);
295 pc->pc_apic_id = cpu_apic_ids[myid];
296 pc->pc_prvspace = pc;
297 pc->pc_curthread = 0;
298 pc->pc_common_tssp = common_tssp = &(__pcpu[0].pc_common_tssp)[myid];
299
300 fix_cpuid();
301
302 gdt_segs[GPRIV_SEL].ssd_base = (int)pc;
303 gdt_segs[GPROC0_SEL].ssd_base = (int)common_tssp;
304 gdt_segs[GLDT_SEL].ssd_base = (int)ldt;
305
306 for (x = 0; x < NGDT; x++) {
307 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
308 }
309
310 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
311 r_gdt.rd_base = (int) &gdt[myid * NGDT];
312 lgdt(&r_gdt); /* does magic intra-segment return */
313
314 r_idt.rd_limit = sizeof(struct gate_descriptor) * NIDT - 1;
315 r_idt.rd_base = (int)idt;
316 lidt(&r_idt);
317
318 lldt(_default_ldt);
319 PCPU_SET(currentldt, _default_ldt);
320
321 PCPU_SET(trampstk, (uintptr_t)ap_tramp_stack_base + TRAMP_STACK_SZ -
322 VM86_STACK_SPACE);
323
324 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
325 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
326 common_tssp->tss_esp0 = PCPU_GET(trampstk);
327 common_tssp->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
328 common_tssp->tss_ioopt = sizeof(struct i386tss) << 16;
329 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd);
330 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt));
331 ltr(gsel_tss);
332
333 PCPU_SET(fsgs_gdt, &gdt[myid * NGDT + GUFS_SEL].sd);
334 PCPU_SET(copyout_buf, ap_copyout_buf);
335
336 /*
337 * Set to a known state:
338 * Set by mpboot.s: CR0_PG, CR0_PE
339 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
340 */
341 cr0 = rcr0();
342 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
343 load_cr0(cr0);
344 CHECK_WRITE(0x38, 5);
345
346 /* signal our startup to the BSP. */
347 mp_naps++;
348 CHECK_WRITE(0x39, 6);
349
350 /* Spin until the BSP releases the AP's. */
351 while (atomic_load_acq_int(&aps_ready) == 0)
352 ia32_pause();
353
354 /* BSP may have changed PTD while we were waiting */
355 invltlb();
356
357 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
358 lidt(&r_idt);
359 #endif
360
361 init_secondary_tail();
362 }
363
364 /*
365 * start each AP in our list
366 */
367 #define TMPMAP_START 1
368 static int
start_all_aps(void)369 start_all_aps(void)
370 {
371 u_char mpbiosreason;
372 u_int32_t mpbioswarmvec;
373 int apic_id, cpu;
374
375 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
376
377 pmap_remap_lower(true);
378
379 /* install the AP 1st level boot code */
380 install_ap_tramp();
381
382 /* save the current value of the warm-start vector */
383 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
384 outb(CMOS_REG, BIOS_RESET);
385 mpbiosreason = inb(CMOS_DATA);
386
387 /* take advantage of the P==V mapping for PTD[0] for AP boot */
388
389 /* start each AP */
390 for (cpu = 1; cpu < mp_ncpus; cpu++) {
391 apic_id = cpu_apic_ids[cpu];
392
393 /* allocate and set up a boot stack data page */
394 bootstacks[cpu] = (char *)kmem_malloc(kstack_pages * PAGE_SIZE,
395 M_WAITOK | M_ZERO);
396 dpcpu = (void *)kmem_malloc(DPCPU_SIZE, M_WAITOK | M_ZERO);
397 /* setup a vector to our boot code */
398 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
399 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
400 outb(CMOS_REG, BIOS_RESET);
401 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
402
403 bootSTK = (char *)bootstacks[cpu] + kstack_pages *
404 PAGE_SIZE - 4;
405 bootAP = cpu;
406
407 ap_tramp_stack_base = pmap_trm_alloc(TRAMP_STACK_SZ, M_NOWAIT);
408 ap_copyout_buf = pmap_trm_alloc(TRAMP_COPYOUT_SZ, M_NOWAIT);
409
410 /* attempt to start the Application Processor */
411 CHECK_INIT(99); /* setup checkpoints */
412 if (!start_ap(apic_id)) {
413 printf("AP #%d (PHY# %d) failed!\n", cpu, apic_id);
414 CHECK_PRINT("trace"); /* show checkpoints */
415 /* better panic as the AP may be running loose */
416 printf("panic y/n? [y] ");
417 if (cngetc() != 'n')
418 panic("bye-bye");
419 }
420 CHECK_PRINT("trace"); /* show checkpoints */
421
422 CPU_SET(cpu, &all_cpus); /* record AP in CPU map */
423 }
424
425 pmap_remap_lower(false);
426
427 /* restore the warmstart vector */
428 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
429
430 outb(CMOS_REG, BIOS_RESET);
431 outb(CMOS_DATA, mpbiosreason);
432
433 /* number of APs actually started */
434 return mp_naps;
435 }
436
437 /*
438 * load the 1st level AP boot code into base memory.
439 */
440
441 /* targets for relocation */
442 extern void bigJump(void);
443 extern void bootCodeSeg(void);
444 extern void bootDataSeg(void);
445 extern void MPentry(void);
446 extern u_int MP_GDT;
447 extern u_int mp_gdtbase;
448
449 static void
install_ap_tramp(void)450 install_ap_tramp(void)
451 {
452 int x;
453 int size = *(int *) ((u_long) & bootMP_size);
454 vm_offset_t va = boot_address;
455 u_char *src = (u_char *) ((u_long) bootMP);
456 u_char *dst = (u_char *) va;
457 u_int boot_base = (u_int) bootMP;
458 u_int8_t *dst8;
459 u_int16_t *dst16;
460 u_int32_t *dst32;
461
462 KASSERT (size <= PAGE_SIZE,
463 ("'size' do not fit into PAGE_SIZE, as expected."));
464 pmap_kenter(va, boot_address);
465 pmap_invalidate_page (kernel_pmap, va);
466 for (x = 0; x < size; ++x)
467 *dst++ = *src++;
468
469 /*
470 * modify addresses in code we just moved to basemem. unfortunately we
471 * need fairly detailed info about mpboot.s for this to work. changes
472 * to mpboot.s might require changes here.
473 */
474
475 /* boot code is located in KERNEL space */
476 dst = (u_char *) va;
477
478 /* modify the lgdt arg */
479 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
480 *dst32 = boot_address + ((u_int) & MP_GDT - boot_base);
481
482 /* modify the ljmp target for MPentry() */
483 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
484 *dst32 = (u_int)MPentry;
485
486 /* modify the target for boot code segment */
487 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
488 dst8 = (u_int8_t *) (dst16 + 1);
489 *dst16 = (u_int) boot_address & 0xffff;
490 *dst8 = ((u_int) boot_address >> 16) & 0xff;
491
492 /* modify the target for boot data segment */
493 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
494 dst8 = (u_int8_t *) (dst16 + 1);
495 *dst16 = (u_int) boot_address & 0xffff;
496 *dst8 = ((u_int) boot_address >> 16) & 0xff;
497 }
498
499 /*
500 * This function starts the AP (application processor) identified
501 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
502 * to accomplish this. This is necessary because of the nuances
503 * of the different hardware we might encounter. It isn't pretty,
504 * but it seems to work.
505 */
506 static int
start_ap(int apic_id)507 start_ap(int apic_id)
508 {
509 int vector, ms;
510 int cpus;
511
512 /* calculate the vector */
513 vector = (boot_address >> 12) & 0xff;
514
515 /* used as a watchpoint to signal AP startup */
516 cpus = mp_naps;
517
518 ipi_startup(apic_id, vector);
519
520 /* Wait up to 5 seconds for it to start. */
521 for (ms = 0; ms < 5000; ms++) {
522 if (mp_naps > cpus)
523 return 1; /* return SUCCESS */
524 DELAY(1000);
525 }
526 return 0; /* return FAILURE */
527 }
528
529 /*
530 * Flush the TLB on other CPU's
531 */
532
533 /* Variables needed for SMP tlb shootdown. */
534 vm_offset_t smp_tlb_addr1, smp_tlb_addr2;
535 pmap_t smp_tlb_pmap;
536 volatile uint32_t smp_tlb_generation;
537
538 /*
539 * Used by pmap to request cache or TLB invalidation on local and
540 * remote processors. Mask provides the set of remote CPUs which are
541 * to be signalled with the invalidation IPI. Vector specifies which
542 * invalidation IPI is used. As an optimization, the curcpu_cb
543 * callback is invoked on the calling CPU while waiting for remote
544 * CPUs to complete the operation.
545 *
546 * The callback function is called unconditionally on the caller's
547 * underlying processor, even when this processor is not set in the
548 * mask. So, the callback function must be prepared to handle such
549 * spurious invocations.
550 */
551 static void
smp_targeted_tlb_shootdown(cpuset_t mask,u_int vector,pmap_t pmap,vm_offset_t addr1,vm_offset_t addr2,smp_invl_cb_t curcpu_cb)552 smp_targeted_tlb_shootdown(cpuset_t mask, u_int vector, pmap_t pmap,
553 vm_offset_t addr1, vm_offset_t addr2, smp_invl_cb_t curcpu_cb)
554 {
555 cpuset_t other_cpus;
556 volatile uint32_t *p_cpudone;
557 uint32_t generation;
558 int cpu;
559
560 /*
561 * It is not necessary to signal other CPUs while booting or
562 * when in the debugger.
563 */
564 if (kdb_active || KERNEL_PANICKED() || !smp_started) {
565 curcpu_cb(pmap, addr1, addr2);
566 return;
567 }
568
569 sched_pin();
570
571 /*
572 * Check for other cpus. Return if none.
573 */
574 if (CPU_ISFULLSET(&mask)) {
575 if (mp_ncpus <= 1)
576 goto nospinexit;
577 } else {
578 CPU_CLR(PCPU_GET(cpuid), &mask);
579 if (CPU_EMPTY(&mask))
580 goto nospinexit;
581 }
582
583 KASSERT((read_eflags() & PSL_I) != 0,
584 ("smp_targeted_tlb_shootdown: interrupts disabled"));
585 mtx_lock_spin(&smp_ipi_mtx);
586 smp_tlb_addr1 = addr1;
587 smp_tlb_addr2 = addr2;
588 smp_tlb_pmap = pmap;
589 generation = ++smp_tlb_generation;
590 if (CPU_ISFULLSET(&mask)) {
591 ipi_all_but_self(vector);
592 other_cpus = all_cpus;
593 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
594 } else {
595 other_cpus = mask;
596 ipi_selected(mask, vector);
597 }
598 curcpu_cb(pmap, addr1, addr2);
599 CPU_FOREACH_ISSET(cpu, &other_cpus) {
600 p_cpudone = &cpuid_to_pcpu[cpu]->pc_smp_tlb_done;
601 while (*p_cpudone != generation)
602 ia32_pause();
603 }
604 mtx_unlock_spin(&smp_ipi_mtx);
605 sched_unpin();
606 return;
607
608 nospinexit:
609 curcpu_cb(pmap, addr1, addr2);
610 sched_unpin();
611 }
612
613 void
smp_masked_invltlb(cpuset_t mask,pmap_t pmap,smp_invl_cb_t curcpu_cb)614 smp_masked_invltlb(cpuset_t mask, pmap_t pmap, smp_invl_cb_t curcpu_cb)
615 {
616 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, pmap, 0, 0, curcpu_cb);
617 #ifdef COUNT_XINVLTLB_HITS
618 ipi_global++;
619 #endif
620 }
621
622 void
smp_masked_invlpg(cpuset_t mask,vm_offset_t addr,pmap_t pmap,smp_invl_cb_t curcpu_cb)623 smp_masked_invlpg(cpuset_t mask, vm_offset_t addr, pmap_t pmap,
624 smp_invl_cb_t curcpu_cb)
625 {
626 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, pmap, addr, 0, curcpu_cb);
627 #ifdef COUNT_XINVLTLB_HITS
628 ipi_page++;
629 #endif
630 }
631
632 void
smp_masked_invlpg_range(cpuset_t mask,vm_offset_t addr1,vm_offset_t addr2,pmap_t pmap,smp_invl_cb_t curcpu_cb)633 smp_masked_invlpg_range(cpuset_t mask, vm_offset_t addr1, vm_offset_t addr2,
634 pmap_t pmap, smp_invl_cb_t curcpu_cb)
635 {
636 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, pmap, addr1, addr2,
637 curcpu_cb);
638 #ifdef COUNT_XINVLTLB_HITS
639 ipi_range++;
640 ipi_range_size += (addr2 - addr1) / PAGE_SIZE;
641 #endif
642 }
643
644 void
smp_cache_flush(smp_invl_cb_t curcpu_cb)645 smp_cache_flush(smp_invl_cb_t curcpu_cb)
646 {
647 smp_targeted_tlb_shootdown(all_cpus, IPI_INVLCACHE, NULL, 0, 0,
648 curcpu_cb);
649 }
650
651 /*
652 * Handlers for TLB related IPIs
653 */
654 void
invltlb_handler(void)655 invltlb_handler(void)
656 {
657 uint32_t generation;
658
659 trap_check_kstack();
660 #ifdef COUNT_XINVLTLB_HITS
661 xhits_gbl[PCPU_GET(cpuid)]++;
662 #endif /* COUNT_XINVLTLB_HITS */
663 #ifdef COUNT_IPIS
664 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
665 #endif /* COUNT_IPIS */
666
667 /*
668 * Reading the generation here allows greater parallelism
669 * since invalidating the TLB is a serializing operation.
670 */
671 generation = smp_tlb_generation;
672 if (smp_tlb_pmap == kernel_pmap)
673 invltlb_glob();
674 PCPU_SET(smp_tlb_done, generation);
675 }
676
677 void
invlpg_handler(void)678 invlpg_handler(void)
679 {
680 uint32_t generation;
681
682 trap_check_kstack();
683 #ifdef COUNT_XINVLTLB_HITS
684 xhits_pg[PCPU_GET(cpuid)]++;
685 #endif /* COUNT_XINVLTLB_HITS */
686 #ifdef COUNT_IPIS
687 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
688 #endif /* COUNT_IPIS */
689
690 generation = smp_tlb_generation; /* Overlap with serialization */
691 if (smp_tlb_pmap == kernel_pmap)
692 invlpg(smp_tlb_addr1);
693 PCPU_SET(smp_tlb_done, generation);
694 }
695
696 void
invlrng_handler(void)697 invlrng_handler(void)
698 {
699 vm_offset_t addr, addr2;
700 uint32_t generation;
701
702 trap_check_kstack();
703 #ifdef COUNT_XINVLTLB_HITS
704 xhits_rng[PCPU_GET(cpuid)]++;
705 #endif /* COUNT_XINVLTLB_HITS */
706 #ifdef COUNT_IPIS
707 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++;
708 #endif /* COUNT_IPIS */
709
710 addr = smp_tlb_addr1;
711 addr2 = smp_tlb_addr2;
712 generation = smp_tlb_generation; /* Overlap with serialization */
713 if (smp_tlb_pmap == kernel_pmap) {
714 do {
715 invlpg(addr);
716 addr += PAGE_SIZE;
717 } while (addr < addr2);
718 }
719
720 PCPU_SET(smp_tlb_done, generation);
721 }
722
723 void
invlcache_handler(void)724 invlcache_handler(void)
725 {
726 uint32_t generation;
727
728 trap_check_kstack();
729 #ifdef COUNT_IPIS
730 (*ipi_invlcache_counts[PCPU_GET(cpuid)])++;
731 #endif /* COUNT_IPIS */
732
733 /*
734 * Reading the generation here allows greater parallelism
735 * since wbinvd is a serializing instruction. Without the
736 * temporary, we'd wait for wbinvd to complete, then the read
737 * would execute, then the dependent write, which must then
738 * complete before return from interrupt.
739 */
740 generation = smp_tlb_generation;
741 wbinvd();
742 PCPU_SET(smp_tlb_done, generation);
743 }
744