1 /*-
2 * Product specific probe and attach routines for:
3 * 3940, 2940, aic7895, aic7890, aic7880,
4 * aic7870, aic7860 and aic7850 SCSI controllers
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 *
8 * Copyright (c) 1994-2001 Justin T. Gibbs.
9 * Copyright (c) 2000-2001 Adaptec Inc.
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions, and the following disclaimer,
17 * without modification.
18 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
19 * substantially similar to the "NO WARRANTY" disclaimer below
20 * ("Disclaimer") and any redistribution must be conditioned upon
21 * including a substantially similar Disclaimer requirement for further
22 * binary redistribution.
23 * 3. Neither the names of the above-listed copyright holders nor the names
24 * of any contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * Alternatively, this software may be distributed under the terms of the
28 * GNU General Public License ("GPL") version 2 as published by the Free
29 * Software Foundation.
30 *
31 * NO WARRANTY
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
35 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
36 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
40 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
41 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
42 * POSSIBILITY OF SUCH DAMAGES.
43 *
44 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#78 $
45 */
46
47 #ifdef __linux__
48 #include "aic7xxx_osm.h"
49 #include "aic7xxx_inline.h"
50 #include "aic7xxx_93cx6.h"
51 #else
52 #include <sys/cdefs.h>
53 #include <dev/aic7xxx/aic7xxx_osm.h>
54 #include <dev/aic7xxx/aic7xxx_inline.h>
55 #include <dev/aic7xxx/aic7xxx_93cx6.h>
56 #endif
57
58 static __inline uint64_t
ahc_compose_id(u_int device,u_int vendor,u_int subdevice,u_int subvendor)59 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
60 {
61 uint64_t id;
62
63 id = subvendor
64 | (subdevice << 16)
65 | ((uint64_t)vendor << 32)
66 | ((uint64_t)device << 48);
67
68 return (id);
69 }
70
71 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
72 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
73 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull
74 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull
75 #define ID_9005_SISL_ID 0x0005900500000000ull
76 #define ID_AIC7850 0x5078900400000000ull
77 #define ID_AHA_2902_04_10_15_20C_30C 0x5078900478509004ull
78 #define ID_AIC7855 0x5578900400000000ull
79 #define ID_AIC7859 0x3860900400000000ull
80 #define ID_AHA_2930CU 0x3860900438699004ull
81 #define ID_AIC7860 0x6078900400000000ull
82 #define ID_AIC7860C 0x6078900478609004ull
83 #define ID_AHA_1480A 0x6075900400000000ull
84 #define ID_AHA_2940AU_0 0x6178900400000000ull
85 #define ID_AHA_2940AU_1 0x6178900478619004ull
86 #define ID_AHA_2940AU_CN 0x2178900478219004ull
87 #define ID_AHA_2930C_VAR 0x6038900438689004ull
88
89 #define ID_AIC7870 0x7078900400000000ull
90 #define ID_AHA_2940 0x7178900400000000ull
91 #define ID_AHA_3940 0x7278900400000000ull
92 #define ID_AHA_398X 0x7378900400000000ull
93 #define ID_AHA_2944 0x7478900400000000ull
94 #define ID_AHA_3944 0x7578900400000000ull
95 #define ID_AHA_4944 0x7678900400000000ull
96
97 #define ID_AIC7880 0x8078900400000000ull
98 #define ID_AIC7880_B 0x8078900478809004ull
99 #define ID_AHA_2940U 0x8178900400000000ull
100 #define ID_AHA_3940U 0x8278900400000000ull
101 #define ID_AHA_2944U 0x8478900400000000ull
102 #define ID_AHA_3944U 0x8578900400000000ull
103 #define ID_AHA_398XU 0x8378900400000000ull
104 #define ID_AHA_4944U 0x8678900400000000ull
105 #define ID_AHA_2940UB 0x8178900478819004ull
106 #define ID_AHA_2930U 0x8878900478889004ull
107 #define ID_AHA_2940U_PRO 0x8778900478879004ull
108 #define ID_AHA_2940U_CN 0x0078900478009004ull
109
110 #define ID_AIC7895 0x7895900478959004ull
111 #define ID_AIC7895_ARO 0x7890900478939004ull
112 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull
113 #define ID_AHA_2940U_DUAL 0x7895900478919004ull
114 #define ID_AHA_3940AU 0x7895900478929004ull
115 #define ID_AHA_3944AU 0x7895900478949004ull
116
117 #define ID_AIC7890 0x001F9005000F9005ull
118 #define ID_AIC7890_ARO 0x00139005000F9005ull
119 #define ID_AAA_131U2 0x0013900500039005ull
120 #define ID_AHA_2930U2 0x0011900501819005ull
121 #define ID_AHA_2940U2B 0x00109005A1009005ull
122 #define ID_AHA_2940U2_OEM 0x0010900521809005ull
123 #define ID_AHA_2940U2 0x00109005A1809005ull
124 #define ID_AHA_2950U2B 0x00109005E1009005ull
125
126 #define ID_AIC7892 0x008F9005FFFF9005ull
127 #define ID_AIC7892_ARO 0x00839005FFFF9005ull
128 #define ID_AHA_29160 0x00809005E2A09005ull
129 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull
130 #define ID_AHA_29160N 0x0080900562A09005ull
131 #define ID_AHA_29160C 0x0080900562209005ull
132 #define ID_AHA_29160B 0x00809005E2209005ull
133 #define ID_AHA_19160B 0x0081900562A19005ull
134 #define ID_AHA_2915_30LP 0x0082900502109005ull
135
136 #define ID_AIC7896 0x005F9005FFFF9005ull
137 #define ID_AIC7896_ARO 0x00539005FFFF9005ull
138 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull
139 #define ID_AHA_3950U2B_1 0x00509005F5009005ull
140 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull
141 #define ID_AHA_3950U2D_1 0x00519005B5009005ull
142
143 #define ID_AIC7899 0x00CF9005FFFF9005ull
144 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull
145 #define ID_AHA_3960D 0x00C09005F6209005ull
146 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull
147
148 #define ID_AIC7810 0x1078900400000000ull
149 #define ID_AIC7815 0x7815900400000000ull
150
151 #define DEVID_9005_TYPE(id) ((id) & 0xF)
152 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
153 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */
154 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */
155 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
156
157 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
158 #define DEVID_9005_MAXRATE_U160 0x0
159 #define DEVID_9005_MAXRATE_ULTRA2 0x1
160 #define DEVID_9005_MAXRATE_ULTRA 0x2
161 #define DEVID_9005_MAXRATE_FAST 0x3
162
163 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6)
164
165 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8)
166 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */
167
168 #define SUBID_9005_TYPE(id) ((id) & 0xF)
169 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */
170 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */
171 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */
172 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */
173
174 #define SUBID_9005_TYPE_KNOWN(id) \
175 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \
176 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \
177 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \
178 || (((id) & 0xF) == SUBID_9005_TYPE_RAID))
179
180 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
181 #define SUBID_9005_MAXRATE_ULTRA2 0x0
182 #define SUBID_9005_MAXRATE_ULTRA 0x1
183 #define SUBID_9005_MAXRATE_U160 0x2
184 #define SUBID_9005_MAXRATE_RESERVED 0x3
185
186 #define SUBID_9005_SEEPTYPE(id) \
187 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
188 ? ((id) & 0xC0) >> 6 \
189 : ((id) & 0x300) >> 8)
190 #define SUBID_9005_SEEPTYPE_NONE 0x0
191 #define SUBID_9005_SEEPTYPE_1K 0x1
192 #define SUBID_9005_SEEPTYPE_2K_4K 0x2
193 #define SUBID_9005_SEEPTYPE_RESERVED 0x3
194 #define SUBID_9005_AUTOTERM(id) \
195 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
196 ? (((id) & 0x400) >> 10) == 0 \
197 : (((id) & 0x40) >> 6) == 0)
198
199 #define SUBID_9005_NUMCHAN(id) \
200 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
201 ? ((id) & 0x300) >> 8 \
202 : ((id) & 0xC00) >> 10)
203
204 #define SUBID_9005_LEGACYCONN(id) \
205 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
206 ? 0 \
207 : ((id) & 0x80) >> 7)
208
209 #define SUBID_9005_MFUNCENB(id) \
210 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
211 ? ((id) & 0x800) >> 11 \
212 : ((id) & 0x1000) >> 12)
213 /*
214 * Informational only. Should use chip register to be
215 * certain, but may be use in identification strings.
216 */
217 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000
218 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000
219 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000
220
221 static ahc_device_setup_t ahc_aic785X_setup;
222 static ahc_device_setup_t ahc_aic7860_setup;
223 static ahc_device_setup_t ahc_apa1480_setup;
224 static ahc_device_setup_t ahc_aic7870_setup;
225 static ahc_device_setup_t ahc_aha394X_setup;
226 static ahc_device_setup_t ahc_aha494X_setup;
227 static ahc_device_setup_t ahc_aha398X_setup;
228 static ahc_device_setup_t ahc_aic7880_setup;
229 static ahc_device_setup_t ahc_aha2940Pro_setup;
230 static ahc_device_setup_t ahc_aha394XU_setup;
231 static ahc_device_setup_t ahc_aha398XU_setup;
232 static ahc_device_setup_t ahc_aic7890_setup;
233 static ahc_device_setup_t ahc_aic7892_setup;
234 static ahc_device_setup_t ahc_aic7895_setup;
235 static ahc_device_setup_t ahc_aic7896_setup;
236 static ahc_device_setup_t ahc_aic7899_setup;
237 static ahc_device_setup_t ahc_aha29160C_setup;
238 static ahc_device_setup_t ahc_raid_setup;
239 static ahc_device_setup_t ahc_aha394XX_setup;
240 static ahc_device_setup_t ahc_aha494XX_setup;
241 static ahc_device_setup_t ahc_aha398XX_setup;
242
243 struct ahc_pci_identity ahc_pci_ident_table [] =
244 {
245 /* aic7850 based controllers */
246 {
247 ID_AHA_2902_04_10_15_20C_30C,
248 ID_ALL_MASK,
249 "Adaptec 2902/04/10/15/20C/30C SCSI adapter",
250 ahc_aic785X_setup
251 },
252 /* aic7860 based controllers */
253 {
254 ID_AHA_2930CU,
255 ID_ALL_MASK,
256 "Adaptec 2930CU SCSI adapter",
257 ahc_aic7860_setup
258 },
259 {
260 ID_AHA_1480A & ID_DEV_VENDOR_MASK,
261 ID_DEV_VENDOR_MASK,
262 "Adaptec 1480A Ultra SCSI adapter",
263 ahc_apa1480_setup
264 },
265 {
266 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK,
267 ID_DEV_VENDOR_MASK,
268 "Adaptec 2940A Ultra SCSI adapter",
269 ahc_aic7860_setup
270 },
271 {
272 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK,
273 ID_DEV_VENDOR_MASK,
274 "Adaptec 2940A/CN Ultra SCSI adapter",
275 ahc_aic7860_setup
276 },
277 {
278 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK,
279 ID_DEV_VENDOR_MASK,
280 "Adaptec 2930C Ultra SCSI adapter (VAR)",
281 ahc_aic7860_setup
282 },
283 /* aic7870 based controllers */
284 {
285 ID_AHA_2940,
286 ID_ALL_MASK,
287 "Adaptec 2940 SCSI adapter",
288 ahc_aic7870_setup
289 },
290 {
291 ID_AHA_3940,
292 ID_ALL_MASK,
293 "Adaptec 3940 SCSI adapter",
294 ahc_aha394X_setup
295 },
296 {
297 ID_AHA_398X,
298 ID_ALL_MASK,
299 "Adaptec 398X SCSI RAID adapter",
300 ahc_aha398X_setup
301 },
302 {
303 ID_AHA_2944,
304 ID_ALL_MASK,
305 "Adaptec 2944 SCSI adapter",
306 ahc_aic7870_setup
307 },
308 {
309 ID_AHA_3944,
310 ID_ALL_MASK,
311 "Adaptec 3944 SCSI adapter",
312 ahc_aha394X_setup
313 },
314 {
315 ID_AHA_4944,
316 ID_ALL_MASK,
317 "Adaptec 4944 SCSI adapter",
318 ahc_aha494X_setup
319 },
320 /* aic7880 based controllers */
321 {
322 ID_AHA_2940U & ID_DEV_VENDOR_MASK,
323 ID_DEV_VENDOR_MASK,
324 "Adaptec 2940 Ultra SCSI adapter",
325 ahc_aic7880_setup
326 },
327 {
328 ID_AHA_3940U & ID_DEV_VENDOR_MASK,
329 ID_DEV_VENDOR_MASK,
330 "Adaptec 3940 Ultra SCSI adapter",
331 ahc_aha394XU_setup
332 },
333 {
334 ID_AHA_2944U & ID_DEV_VENDOR_MASK,
335 ID_DEV_VENDOR_MASK,
336 "Adaptec 2944 Ultra SCSI adapter",
337 ahc_aic7880_setup
338 },
339 {
340 ID_AHA_3944U & ID_DEV_VENDOR_MASK,
341 ID_DEV_VENDOR_MASK,
342 "Adaptec 3944 Ultra SCSI adapter",
343 ahc_aha394XU_setup
344 },
345 {
346 ID_AHA_398XU & ID_DEV_VENDOR_MASK,
347 ID_DEV_VENDOR_MASK,
348 "Adaptec 398X Ultra SCSI RAID adapter",
349 ahc_aha398XU_setup
350 },
351 {
352 /*
353 * XXX Don't know the slot numbers
354 * so we can't identify channels
355 */
356 ID_AHA_4944U & ID_DEV_VENDOR_MASK,
357 ID_DEV_VENDOR_MASK,
358 "Adaptec 4944 Ultra SCSI adapter",
359 ahc_aic7880_setup
360 },
361 {
362 ID_AHA_2930U & ID_DEV_VENDOR_MASK,
363 ID_DEV_VENDOR_MASK,
364 "Adaptec 2930 Ultra SCSI adapter",
365 ahc_aic7880_setup
366 },
367 {
368 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK,
369 ID_DEV_VENDOR_MASK,
370 "Adaptec 2940 Pro Ultra SCSI adapter",
371 ahc_aha2940Pro_setup
372 },
373 {
374 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK,
375 ID_DEV_VENDOR_MASK,
376 "Adaptec 2940/CN Ultra SCSI adapter",
377 ahc_aic7880_setup
378 },
379 /* Ignore all SISL (AAC on MB) based controllers. */
380 {
381 ID_9005_SISL_ID,
382 ID_9005_SISL_MASK,
383 NULL,
384 NULL
385 },
386 /* aic7890 based controllers */
387 {
388 ID_AHA_2930U2,
389 ID_ALL_MASK,
390 "Adaptec 2930 Ultra2 SCSI adapter",
391 ahc_aic7890_setup
392 },
393 {
394 ID_AHA_2940U2B,
395 ID_ALL_MASK,
396 "Adaptec 2940B Ultra2 SCSI adapter",
397 ahc_aic7890_setup
398 },
399 {
400 ID_AHA_2940U2_OEM,
401 ID_ALL_MASK,
402 "Adaptec 2940 Ultra2 SCSI adapter (OEM)",
403 ahc_aic7890_setup
404 },
405 {
406 ID_AHA_2940U2,
407 ID_ALL_MASK,
408 "Adaptec 2940 Ultra2 SCSI adapter",
409 ahc_aic7890_setup
410 },
411 {
412 ID_AHA_2950U2B,
413 ID_ALL_MASK,
414 "Adaptec 2950 Ultra2 SCSI adapter",
415 ahc_aic7890_setup
416 },
417 {
418 ID_AIC7890_ARO,
419 ID_ALL_MASK,
420 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)",
421 ahc_aic7890_setup
422 },
423 {
424 ID_AAA_131U2,
425 ID_ALL_MASK,
426 "Adaptec AAA-131 Ultra2 RAID adapter",
427 ahc_aic7890_setup
428 },
429 /* aic7892 based controllers */
430 {
431 ID_AHA_29160,
432 ID_ALL_MASK,
433 "Adaptec 29160 Ultra160 SCSI adapter",
434 ahc_aic7892_setup
435 },
436 {
437 ID_AHA_29160_CPQ,
438 ID_ALL_MASK,
439 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter",
440 ahc_aic7892_setup
441 },
442 {
443 ID_AHA_29160N,
444 ID_ALL_MASK,
445 "Adaptec 29160N Ultra160 SCSI adapter",
446 ahc_aic7892_setup
447 },
448 {
449 ID_AHA_29160C,
450 ID_ALL_MASK,
451 "Adaptec 29160C Ultra160 SCSI adapter",
452 ahc_aha29160C_setup
453 },
454 {
455 ID_AHA_29160B,
456 ID_ALL_MASK,
457 "Adaptec 29160B Ultra160 SCSI adapter",
458 ahc_aic7892_setup
459 },
460 {
461 ID_AHA_19160B,
462 ID_ALL_MASK,
463 "Adaptec 19160B Ultra160 SCSI adapter",
464 ahc_aic7892_setup
465 },
466 {
467 ID_AIC7892_ARO,
468 ID_ALL_MASK,
469 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)",
470 ahc_aic7892_setup
471 },
472 {
473 ID_AHA_2915_30LP,
474 ID_ALL_MASK,
475 "Adaptec 2915/30LP Ultra160 SCSI adapter",
476 ahc_aic7892_setup
477 },
478 /* aic7895 based controllers */
479 {
480 ID_AHA_2940U_DUAL,
481 ID_ALL_MASK,
482 "Adaptec 2940/DUAL Ultra SCSI adapter",
483 ahc_aic7895_setup
484 },
485 {
486 ID_AHA_3940AU,
487 ID_ALL_MASK,
488 "Adaptec 3940A Ultra SCSI adapter",
489 ahc_aic7895_setup
490 },
491 {
492 ID_AHA_3944AU,
493 ID_ALL_MASK,
494 "Adaptec 3944A Ultra SCSI adapter",
495 ahc_aic7895_setup
496 },
497 {
498 ID_AIC7895_ARO,
499 ID_AIC7895_ARO_MASK,
500 "Adaptec aic7895 Ultra SCSI adapter (ARO)",
501 ahc_aic7895_setup
502 },
503 /* aic7896/97 based controllers */
504 {
505 ID_AHA_3950U2B_0,
506 ID_ALL_MASK,
507 "Adaptec 3950B Ultra2 SCSI adapter",
508 ahc_aic7896_setup
509 },
510 {
511 ID_AHA_3950U2B_1,
512 ID_ALL_MASK,
513 "Adaptec 3950B Ultra2 SCSI adapter",
514 ahc_aic7896_setup
515 },
516 {
517 ID_AHA_3950U2D_0,
518 ID_ALL_MASK,
519 "Adaptec 3950D Ultra2 SCSI adapter",
520 ahc_aic7896_setup
521 },
522 {
523 ID_AHA_3950U2D_1,
524 ID_ALL_MASK,
525 "Adaptec 3950D Ultra2 SCSI adapter",
526 ahc_aic7896_setup
527 },
528 {
529 ID_AIC7896_ARO,
530 ID_ALL_MASK,
531 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)",
532 ahc_aic7896_setup
533 },
534 /* aic7899 based controllers */
535 {
536 ID_AHA_3960D,
537 ID_ALL_MASK,
538 "Adaptec 3960D Ultra160 SCSI adapter",
539 ahc_aic7899_setup
540 },
541 {
542 ID_AHA_3960D_CPQ,
543 ID_ALL_MASK,
544 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter",
545 ahc_aic7899_setup
546 },
547 {
548 ID_AIC7899_ARO,
549 ID_ALL_MASK,
550 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)",
551 ahc_aic7899_setup
552 },
553 /* Generic chip probes for devices we don't know 'exactly' */
554 {
555 ID_AIC7850 & ID_DEV_VENDOR_MASK,
556 ID_DEV_VENDOR_MASK,
557 "Adaptec aic7850 SCSI adapter",
558 ahc_aic785X_setup
559 },
560 {
561 ID_AIC7855 & ID_DEV_VENDOR_MASK,
562 ID_DEV_VENDOR_MASK,
563 "Adaptec aic7855 SCSI adapter",
564 ahc_aic785X_setup
565 },
566 {
567 ID_AIC7859 & ID_DEV_VENDOR_MASK,
568 ID_DEV_VENDOR_MASK,
569 "Adaptec aic7859 SCSI adapter",
570 ahc_aic7860_setup
571 },
572 {
573 ID_AIC7860 & ID_DEV_VENDOR_MASK,
574 ID_DEV_VENDOR_MASK,
575 "Adaptec aic7860 Ultra SCSI adapter",
576 ahc_aic7860_setup
577 },
578 {
579 ID_AIC7870 & ID_DEV_VENDOR_MASK,
580 ID_DEV_VENDOR_MASK,
581 "Adaptec aic7870 SCSI adapter",
582 ahc_aic7870_setup
583 },
584 {
585 ID_AIC7880 & ID_DEV_VENDOR_MASK,
586 ID_DEV_VENDOR_MASK,
587 "Adaptec aic7880 Ultra SCSI adapter",
588 ahc_aic7880_setup
589 },
590 {
591 ID_AIC7890 & ID_9005_GENERIC_MASK,
592 ID_9005_GENERIC_MASK,
593 "Adaptec aic7890/91 Ultra2 SCSI adapter",
594 ahc_aic7890_setup
595 },
596 {
597 ID_AIC7892 & ID_9005_GENERIC_MASK,
598 ID_9005_GENERIC_MASK,
599 "Adaptec aic7892 Ultra160 SCSI adapter",
600 ahc_aic7892_setup
601 },
602 {
603 ID_AIC7895 & ID_DEV_VENDOR_MASK,
604 ID_DEV_VENDOR_MASK,
605 "Adaptec aic7895 Ultra SCSI adapter",
606 ahc_aic7895_setup
607 },
608 {
609 ID_AIC7896 & ID_9005_GENERIC_MASK,
610 ID_9005_GENERIC_MASK,
611 "Adaptec aic7896/97 Ultra2 SCSI adapter",
612 ahc_aic7896_setup
613 },
614 {
615 ID_AIC7899 & ID_9005_GENERIC_MASK,
616 ID_9005_GENERIC_MASK,
617 "Adaptec aic7899 Ultra160 SCSI adapter",
618 ahc_aic7899_setup
619 },
620 {
621 ID_AIC7810 & ID_DEV_VENDOR_MASK,
622 ID_DEV_VENDOR_MASK,
623 "Adaptec aic7810 RAID memory controller",
624 ahc_raid_setup
625 },
626 {
627 ID_AIC7815 & ID_DEV_VENDOR_MASK,
628 ID_DEV_VENDOR_MASK,
629 "Adaptec aic7815 RAID memory controller",
630 ahc_raid_setup
631 }
632 };
633
634 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table);
635
636 #define AHC_394X_SLOT_CHANNEL_A 4
637 #define AHC_394X_SLOT_CHANNEL_B 5
638
639 #define AHC_398X_SLOT_CHANNEL_A 4
640 #define AHC_398X_SLOT_CHANNEL_B 8
641 #define AHC_398X_SLOT_CHANNEL_C 12
642
643 #define AHC_494X_SLOT_CHANNEL_A 4
644 #define AHC_494X_SLOT_CHANNEL_B 5
645 #define AHC_494X_SLOT_CHANNEL_C 6
646 #define AHC_494X_SLOT_CHANNEL_D 7
647
648 #define DEVCONFIG 0x40
649 #define PCIERRGENDIS 0x80000000ul
650 #define SCBSIZE32 0x00010000ul /* aic789X only */
651 #define REXTVALID 0x00001000ul /* ultra cards only */
652 #define MPORTMODE 0x00000400ul /* aic7870+ only */
653 #define RAMPSM 0x00000200ul /* aic7870+ only */
654 #define VOLSENSE 0x00000100ul
655 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/
656 #define SCBRAMSEL 0x00000080ul
657 #define MRDCEN 0x00000040ul
658 #define EXTSCBTIME 0x00000020ul /* aic7870 only */
659 #define EXTSCBPEN 0x00000010ul /* aic7870 only */
660 #define BERREN 0x00000008ul
661 #define DACEN 0x00000004ul
662 #define STPWLEVEL 0x00000002ul
663 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */
664
665 #define CSIZE_LATTIME 0x0c
666 #define CACHESIZE 0x0000003ful /* only 5 bits */
667 #define LATTIME 0x0000ff00ul
668
669 /* PCI STATUS definitions */
670 #define DPE 0x80
671 #define SSE 0x40
672 #define RMA 0x20
673 #define RTA 0x10
674 #define STA 0x08
675 #define DPR 0x01
676
677 static int ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
678 uint16_t subdevice, uint16_t subvendor);
679 static int ahc_ext_scbram_present(struct ahc_softc *ahc);
680 static void ahc_scbram_config(struct ahc_softc *ahc, int enable,
681 int pcheck, int fast, int large);
682 static void ahc_probe_ext_scbram(struct ahc_softc *ahc);
683 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1);
684 static void ahc_parse_pci_eeprom(struct ahc_softc *ahc,
685 struct seeprom_config *sc);
686 static void configure_termination(struct ahc_softc *ahc,
687 struct seeprom_descriptor *sd,
688 u_int adapter_control,
689 u_int *sxfrctl1);
690
691 static void ahc_new_term_detect(struct ahc_softc *ahc,
692 int *enableSEC_low,
693 int *enableSEC_high,
694 int *enablePRI_low,
695 int *enablePRI_high,
696 int *eeprom_present);
697 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
698 int *internal68_present,
699 int *externalcable_present,
700 int *eeprom_present);
701 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
702 int *externalcable_present,
703 int *eeprom_present);
704 static void write_brdctl(struct ahc_softc *ahc, uint8_t value);
705 static uint8_t read_brdctl(struct ahc_softc *ahc);
706 static void ahc_pci_intr(struct ahc_softc *ahc);
707 static int ahc_pci_chip_init(struct ahc_softc *ahc);
708 static int ahc_pci_suspend(struct ahc_softc *ahc);
709 static int ahc_pci_resume(struct ahc_softc *ahc);
710
711 static int
ahc_9005_subdevinfo_valid(uint16_t device,uint16_t vendor,uint16_t subdevice,uint16_t subvendor)712 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
713 uint16_t subdevice, uint16_t subvendor)
714 {
715 int result;
716
717 /* Default to invalid. */
718 result = 0;
719 if (vendor == 0x9005
720 && subvendor == 0x9005
721 && subdevice != device
722 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) {
723 switch (SUBID_9005_TYPE(subdevice)) {
724 case SUBID_9005_TYPE_MB:
725 break;
726 case SUBID_9005_TYPE_CARD:
727 case SUBID_9005_TYPE_LCCARD:
728 /*
729 * Currently only trust Adaptec cards to
730 * get the sub device info correct.
731 */
732 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA)
733 result = 1;
734 break;
735 case SUBID_9005_TYPE_RAID:
736 break;
737 default:
738 break;
739 }
740 }
741 return (result);
742 }
743
744 struct ahc_pci_identity *
ahc_find_pci_device(aic_dev_softc_t pci)745 ahc_find_pci_device(aic_dev_softc_t pci)
746 {
747 uint64_t full_id;
748 uint16_t device;
749 uint16_t vendor;
750 uint16_t subdevice;
751 uint16_t subvendor;
752 struct ahc_pci_identity *entry;
753 u_int i;
754
755 vendor = aic_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
756 device = aic_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
757 subvendor = aic_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
758 subdevice = aic_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
759 full_id = ahc_compose_id(device, vendor, subdevice, subvendor);
760
761 /*
762 * If the second function is not hooked up, ignore it.
763 * Unfortunately, not all MB vendors implement the
764 * subdevice ID as per the Adaptec spec, so do our best
765 * to sanity check it prior to accepting the subdevice
766 * ID as valid.
767 */
768 if (aic_get_pci_function(pci) > 0
769 && ahc_9005_subdevinfo_valid(device, vendor, subdevice, subvendor)
770 && SUBID_9005_MFUNCENB(subdevice) == 0)
771 return (NULL);
772
773 for (i = 0; i < ahc_num_pci_devs; i++) {
774 entry = &ahc_pci_ident_table[i];
775 if (entry->full_id == (full_id & entry->id_mask)) {
776 /* Honor exclusion entries. */
777 if (entry->name == NULL)
778 return (NULL);
779 return (entry);
780 }
781 }
782 return (NULL);
783 }
784
785 int
ahc_pci_config(struct ahc_softc * ahc,struct ahc_pci_identity * entry)786 ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry)
787 {
788 u_int command;
789 u_int our_id;
790 u_int sxfrctl1;
791 u_int scsiseq;
792 u_int dscommand0;
793 uint32_t devconfig;
794 int error;
795 uint8_t sblkctl;
796
797 our_id = 0;
798 error = entry->setup(ahc);
799 if (error != 0)
800 return (error);
801 ahc->chip |= AHC_PCI;
802 ahc->description = entry->name;
803
804 aic_power_state_change(ahc, AIC_POWER_STATE_D0);
805
806 error = ahc_pci_map_registers(ahc);
807 if (error != 0)
808 return (error);
809
810 /*
811 * Before we continue probing the card, ensure that
812 * its interrupts are *disabled*. We don't want
813 * a misstep to hang the machine in an interrupt
814 * storm.
815 */
816 ahc_intr_enable(ahc, FALSE);
817
818 devconfig = aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
819
820 /*
821 * If we need to support high memory, enable dual
822 * address cycles. This bit must be set to enable
823 * high address bit generation even if we are on a
824 * 64bit bus (PCI64BIT set in devconfig).
825 */
826 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
827 if (bootverbose)
828 printf("%s: Enabling 39Bit Addressing\n",
829 ahc_name(ahc));
830 devconfig |= DACEN;
831 }
832
833 /* Ensure that pci error generation, a test feature, is disabled. */
834 devconfig |= PCIERRGENDIS;
835
836 aic_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
837
838 /* Ensure busmastering is enabled */
839 command = aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
840 command |= PCIM_CMD_BUSMASTEREN;
841
842 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
843
844 /* On all PCI adapters, we allow SCB paging */
845 ahc->flags |= AHC_PAGESCBS;
846
847 error = ahc_softc_init(ahc);
848 if (error != 0)
849 return (error);
850
851 /*
852 * Disable PCI parity error checking. Users typically
853 * do this to work around broken PCI chipsets that get
854 * the parity timing wrong and thus generate lots of spurious
855 * errors. The chip only allows us to disable *all* parity
856 * error reporting when doing this, so CIO bus, scb ram, and
857 * scratch ram parity errors will be ignored too.
858 */
859 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0)
860 ahc->seqctl |= FAILDIS;
861
862 ahc->bus_intr = ahc_pci_intr;
863 ahc->bus_chip_init = ahc_pci_chip_init;
864 ahc->bus_suspend = ahc_pci_suspend;
865 ahc->bus_resume = ahc_pci_resume;
866
867 /* Remember how the card was setup in case there is no SEEPROM */
868 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) {
869 ahc_pause(ahc);
870 if ((ahc->features & AHC_ULTRA2) != 0)
871 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
872 else
873 our_id = ahc_inb(ahc, SCSIID) & OID;
874 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN;
875 scsiseq = ahc_inb(ahc, SCSISEQ);
876 } else {
877 sxfrctl1 = STPWEN;
878 our_id = 7;
879 scsiseq = 0;
880 }
881
882 error = ahc_reset(ahc, /*reinit*/FALSE);
883 if (error != 0)
884 return (ENXIO);
885
886 if ((ahc->features & AHC_DT) != 0) {
887 u_int sfunct;
888
889 /* Perform ALT-Mode Setup */
890 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
891 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
892 ahc_outb(ahc, OPTIONMODE,
893 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS);
894 ahc_outb(ahc, SFUNCT, sfunct);
895
896 /* Normal mode setup */
897 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN
898 |TARGCRCENDEN);
899 }
900
901 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
902 dscommand0 |= MPARCKEN|CACHETHEN;
903 if ((ahc->features & AHC_ULTRA2) != 0) {
904 /*
905 * DPARCKEN doesn't work correctly on
906 * some MBs so don't use it.
907 */
908 dscommand0 &= ~DPARCKEN;
909 }
910
911 /*
912 * Handle chips that must have cache line
913 * streaming (dis/en)abled.
914 */
915 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0)
916 dscommand0 |= CACHETHEN;
917
918 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0)
919 dscommand0 &= ~CACHETHEN;
920
921 ahc_outb(ahc, DSCOMMAND0, dscommand0);
922
923 ahc->pci_cachesize =
924 aic_pci_read_config(ahc->dev_softc, CSIZE_LATTIME,
925 /*bytes*/1) & CACHESIZE;
926 ahc->pci_cachesize *= 4;
927
928 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0
929 && ahc->pci_cachesize == 4) {
930 aic_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
931 0, /*bytes*/1);
932 ahc->pci_cachesize = 0;
933 }
934
935 /*
936 * We cannot perform ULTRA speeds without the presence
937 * of the external precision resistor.
938 */
939 if ((ahc->features & AHC_ULTRA) != 0) {
940 uint32_t devconfig;
941
942 devconfig = aic_pci_read_config(ahc->dev_softc,
943 DEVCONFIG, /*bytes*/4);
944 if ((devconfig & REXTVALID) == 0)
945 ahc->features &= ~AHC_ULTRA;
946 }
947
948 /* See if we have a SEEPROM and perform auto-term */
949 check_extport(ahc, &sxfrctl1);
950
951 /*
952 * Take the LED out of diagnostic mode
953 */
954 sblkctl = ahc_inb(ahc, SBLKCTL);
955 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
956
957 if ((ahc->features & AHC_ULTRA2) != 0) {
958 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX);
959 } else {
960 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100);
961 }
962
963 if (ahc->flags & AHC_USEDEFAULTS) {
964 /*
965 * PCI Adapter default setup
966 * Should only be used if the adapter does not have
967 * a SEEPROM.
968 */
969 /* See if someone else set us up already */
970 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0
971 && scsiseq != 0) {
972 printf("%s: Using left over BIOS settings\n",
973 ahc_name(ahc));
974 ahc->flags &= ~AHC_USEDEFAULTS;
975 ahc->flags |= AHC_BIOS_ENABLED;
976 } else {
977 /*
978 * Assume only one connector and always turn
979 * on termination.
980 */
981 our_id = 0x07;
982 sxfrctl1 = STPWEN;
983 }
984 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI);
985
986 ahc->our_id = our_id;
987 }
988
989 /*
990 * Take a look to see if we have external SRAM.
991 * We currently do not attempt to use SRAM that is
992 * shared among multiple controllers.
993 */
994 ahc_probe_ext_scbram(ahc);
995
996 /*
997 * Record our termination setting for the
998 * generic initialization routine.
999 */
1000 if ((sxfrctl1 & STPWEN) != 0)
1001 ahc->flags |= AHC_TERM_ENB_A;
1002
1003 /*
1004 * Save chip register configuration data for chip resets
1005 * that occur during runtime and resume events.
1006 */
1007 ahc->bus_softc.pci_softc.devconfig =
1008 aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1009 ahc->bus_softc.pci_softc.command =
1010 aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1);
1011 ahc->bus_softc.pci_softc.csize_lattime =
1012 aic_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1);
1013 ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1014 ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS);
1015 if ((ahc->features & AHC_DT) != 0) {
1016 u_int sfunct;
1017
1018 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
1019 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
1020 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE);
1021 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT);
1022 ahc_outb(ahc, SFUNCT, sfunct);
1023 ahc->bus_softc.pci_softc.crccontrol1 =
1024 ahc_inb(ahc, CRCCONTROL1);
1025 }
1026 if ((ahc->features & AHC_MULTI_FUNC) != 0)
1027 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR);
1028
1029 if ((ahc->features & AHC_ULTRA2) != 0)
1030 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH);
1031
1032 /* Core initialization */
1033 error = ahc_init(ahc);
1034 if (error != 0)
1035 return (error);
1036
1037 /*
1038 * Allow interrupts now that we are completely setup.
1039 */
1040 error = ahc_pci_map_int(ahc);
1041 if (error != 0)
1042 return (error);
1043
1044 ahc_lock(ahc);
1045 /*
1046 * Link this softc in with all other ahc instances.
1047 */
1048 ahc_softc_insert(ahc);
1049 ahc_unlock(ahc);
1050 return (0);
1051 }
1052
1053 /*
1054 * Test for the presence of external sram in an
1055 * "unshared" configuration.
1056 */
1057 static int
ahc_ext_scbram_present(struct ahc_softc * ahc)1058 ahc_ext_scbram_present(struct ahc_softc *ahc)
1059 {
1060 u_int chip;
1061 int ramps;
1062 int single_user;
1063 uint32_t devconfig;
1064
1065 chip = ahc->chip & AHC_CHIPID_MASK;
1066 devconfig = aic_pci_read_config(ahc->dev_softc,
1067 DEVCONFIG, /*bytes*/4);
1068 single_user = (devconfig & MPORTMODE) != 0;
1069
1070 if ((ahc->features & AHC_ULTRA2) != 0)
1071 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0;
1072 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C)
1073 /*
1074 * External SCBRAM arbitration is flakey
1075 * on these chips. Unfortunately this means
1076 * we don't use the extra SCB ram space on the
1077 * 3940AUW.
1078 */
1079 ramps = 0;
1080 else if (chip >= AHC_AIC7870)
1081 ramps = (devconfig & RAMPSM) != 0;
1082 else
1083 ramps = 0;
1084
1085 if (ramps && single_user)
1086 return (1);
1087 return (0);
1088 }
1089
1090 /*
1091 * Enable external scbram.
1092 */
1093 static void
ahc_scbram_config(struct ahc_softc * ahc,int enable,int pcheck,int fast,int large)1094 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck,
1095 int fast, int large)
1096 {
1097 uint32_t devconfig;
1098
1099 if (ahc->features & AHC_MULTI_FUNC) {
1100 /*
1101 * Set the SCB Base addr (highest address bit)
1102 * depending on which channel we are.
1103 */
1104 ahc_outb(ahc, SCBBADDR, aic_get_pci_function(ahc->dev_softc));
1105 }
1106
1107 ahc->flags &= ~AHC_LSCBS_ENABLED;
1108 if (large)
1109 ahc->flags |= AHC_LSCBS_ENABLED;
1110 devconfig = aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1111 if ((ahc->features & AHC_ULTRA2) != 0) {
1112 u_int dscommand0;
1113
1114 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1115 if (enable)
1116 dscommand0 &= ~INTSCBRAMSEL;
1117 else
1118 dscommand0 |= INTSCBRAMSEL;
1119 if (large)
1120 dscommand0 &= ~USCBSIZE32;
1121 else
1122 dscommand0 |= USCBSIZE32;
1123 ahc_outb(ahc, DSCOMMAND0, dscommand0);
1124 } else {
1125 if (fast)
1126 devconfig &= ~EXTSCBTIME;
1127 else
1128 devconfig |= EXTSCBTIME;
1129 if (enable)
1130 devconfig &= ~SCBRAMSEL;
1131 else
1132 devconfig |= SCBRAMSEL;
1133 if (large)
1134 devconfig &= ~SCBSIZE32;
1135 else
1136 devconfig |= SCBSIZE32;
1137 }
1138 if (pcheck)
1139 devconfig |= EXTSCBPEN;
1140 else
1141 devconfig &= ~EXTSCBPEN;
1142
1143 aic_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
1144 }
1145
1146 /*
1147 * Take a look to see if we have external SRAM.
1148 * We currently do not attempt to use SRAM that is
1149 * shared among multiple controllers.
1150 */
1151 static void
ahc_probe_ext_scbram(struct ahc_softc * ahc)1152 ahc_probe_ext_scbram(struct ahc_softc *ahc)
1153 {
1154 int num_scbs;
1155 int test_num_scbs;
1156 int enable;
1157 int pcheck;
1158 int fast;
1159 int large;
1160
1161 enable = FALSE;
1162 pcheck = FALSE;
1163 fast = FALSE;
1164 large = FALSE;
1165 num_scbs = 0;
1166
1167 if (ahc_ext_scbram_present(ahc) == 0)
1168 goto done;
1169
1170 /*
1171 * Probe for the best parameters to use.
1172 */
1173 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large);
1174 num_scbs = ahc_probe_scbs(ahc);
1175 if (num_scbs == 0) {
1176 /* The SRAM wasn't really present. */
1177 goto done;
1178 }
1179 enable = TRUE;
1180
1181 /*
1182 * Clear any outstanding parity error
1183 * and ensure that parity error reporting
1184 * is enabled.
1185 */
1186 ahc_outb(ahc, SEQCTL, 0);
1187 ahc_outb(ahc, CLRINT, CLRPARERR);
1188 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1189
1190 /* Now see if we can do parity */
1191 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large);
1192 num_scbs = ahc_probe_scbs(ahc);
1193 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1194 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)
1195 pcheck = TRUE;
1196
1197 /* Clear any resulting parity error */
1198 ahc_outb(ahc, CLRINT, CLRPARERR);
1199 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1200
1201 /* Now see if we can do fast timing */
1202 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large);
1203 test_num_scbs = ahc_probe_scbs(ahc);
1204 if (test_num_scbs == num_scbs
1205 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1206 || (ahc_inb(ahc, ERROR) & MPARERR) == 0))
1207 fast = TRUE;
1208
1209 /*
1210 * See if we can use large SCBs and still maintain
1211 * the same overall count of SCBs.
1212 */
1213 if ((ahc->features & AHC_LARGE_SCBS) != 0) {
1214 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE);
1215 test_num_scbs = ahc_probe_scbs(ahc);
1216 if (test_num_scbs >= num_scbs) {
1217 large = TRUE;
1218 num_scbs = test_num_scbs;
1219 if (num_scbs >= 64) {
1220 /*
1221 * We have enough space to move the
1222 * "busy targets table" into SCB space
1223 * and make it qualify all the way to the
1224 * lun level.
1225 */
1226 ahc->flags |= AHC_SCB_BTT;
1227 }
1228 }
1229 }
1230 done:
1231 /*
1232 * Disable parity error reporting until we
1233 * can load instruction ram.
1234 */
1235 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1236 /* Clear any latched parity error */
1237 ahc_outb(ahc, CLRINT, CLRPARERR);
1238 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1239 if (bootverbose && enable) {
1240 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n",
1241 ahc_name(ahc), fast ? "fast" : "slow",
1242 pcheck ? ", parity checking enabled" : "",
1243 large ? 64 : 32);
1244 }
1245 ahc_scbram_config(ahc, enable, pcheck, fast, large);
1246 }
1247
1248 /*
1249 * Perform some simple tests that should catch situations where
1250 * our registers are invalidly mapped.
1251 */
1252 int
ahc_pci_test_register_access(struct ahc_softc * ahc)1253 ahc_pci_test_register_access(struct ahc_softc *ahc)
1254 {
1255 int error;
1256 u_int status1;
1257 uint32_t cmd;
1258 uint8_t hcntrl;
1259
1260 error = EIO;
1261
1262 /*
1263 * Enable PCI error interrupt status, but suppress NMIs
1264 * generated by SERR raised due to target aborts.
1265 */
1266 cmd = aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
1267 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
1268 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
1269
1270 /*
1271 * First a simple test to see if any
1272 * registers can be read. Reading
1273 * HCNTRL has no side effects and has
1274 * at least one bit that is guaranteed to
1275 * be zero so it is a good register to
1276 * use for this test.
1277 */
1278 hcntrl = ahc_inb(ahc, HCNTRL);
1279
1280 if (hcntrl == 0xFF)
1281 goto fail;
1282
1283 if ((hcntrl & CHIPRST) != 0) {
1284 /*
1285 * The chip has not been initialized since
1286 * PCI/EISA/VLB bus reset. Don't trust
1287 * "left over BIOS data".
1288 */
1289 ahc->flags |= AHC_NO_BIOS_INIT;
1290 }
1291
1292 /*
1293 * Next create a situation where write combining
1294 * or read prefetching could be initiated by the
1295 * CPU or host bridge. Our device does not support
1296 * either, so look for data corruption and/or flagged
1297 * PCI errors. First pause without causing another
1298 * chip reset.
1299 */
1300 hcntrl &= ~CHIPRST;
1301 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE);
1302 while (ahc_is_paused(ahc) == 0)
1303 ;
1304
1305 /* Clear any PCI errors that occurred before our driver attached. */
1306 status1 = aic_pci_read_config(ahc->dev_softc,
1307 PCIR_STATUS + 1, /*bytes*/1);
1308 aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1309 status1, /*bytes*/1);
1310 ahc_outb(ahc, CLRINT, CLRPARERR);
1311
1312 ahc_outb(ahc, SEQCTL, PERRORDIS);
1313 ahc_outb(ahc, SCBPTR, 0);
1314 ahc_outl(ahc, SCB_BASE, 0x5aa555aa);
1315 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa)
1316 goto fail;
1317
1318 status1 = aic_pci_read_config(ahc->dev_softc,
1319 PCIR_STATUS + 1, /*bytes*/1);
1320 if ((status1 & STA) != 0)
1321 goto fail;
1322
1323 error = 0;
1324
1325 fail:
1326 /* Silently clear any latched errors. */
1327 status1 = aic_pci_read_config(ahc->dev_softc,
1328 PCIR_STATUS + 1, /*bytes*/1);
1329 aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1330 status1, /*bytes*/1);
1331 ahc_outb(ahc, CLRINT, CLRPARERR);
1332 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1333 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
1334 return (error);
1335 }
1336
1337 /*
1338 * Check the external port logic for a serial eeprom
1339 * and termination/cable detection contrls.
1340 */
1341 static void
check_extport(struct ahc_softc * ahc,u_int * sxfrctl1)1342 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1)
1343 {
1344 struct seeprom_descriptor sd;
1345 struct seeprom_config *sc;
1346 int have_seeprom;
1347 int have_autoterm;
1348
1349 sd.sd_ahc = ahc;
1350 sd.sd_control_offset = SEECTL;
1351 sd.sd_status_offset = SEECTL;
1352 sd.sd_dataout_offset = SEECTL;
1353 sc = ahc->seep_config;
1354
1355 /*
1356 * For some multi-channel devices, the c46 is simply too
1357 * small to work. For the other controller types, we can
1358 * get our information from either SEEPROM type. Set the
1359 * type to start our probe with accordingly.
1360 */
1361 if (ahc->flags & AHC_LARGE_SEEPROM)
1362 sd.sd_chip = C56_66;
1363 else
1364 sd.sd_chip = C46;
1365
1366 sd.sd_MS = SEEMS;
1367 sd.sd_RDY = SEERDY;
1368 sd.sd_CS = SEECS;
1369 sd.sd_CK = SEECK;
1370 sd.sd_DO = SEEDO;
1371 sd.sd_DI = SEEDI;
1372
1373 have_seeprom = ahc_acquire_seeprom(ahc, &sd);
1374 if (have_seeprom) {
1375 if (bootverbose)
1376 printf("%s: Reading SEEPROM...", ahc_name(ahc));
1377
1378 for (;;) {
1379 u_int start_addr;
1380
1381 start_addr = 32 * (ahc->channel - 'A');
1382
1383 have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc,
1384 start_addr,
1385 sizeof(*sc)/2);
1386
1387 if (have_seeprom)
1388 have_seeprom = ahc_verify_cksum(sc);
1389
1390 if (have_seeprom != 0 || sd.sd_chip == C56_66) {
1391 if (bootverbose) {
1392 if (have_seeprom == 0)
1393 printf ("checksum error\n");
1394 else
1395 printf ("done.\n");
1396 }
1397 break;
1398 }
1399 sd.sd_chip = C56_66;
1400 }
1401 ahc_release_seeprom(&sd);
1402
1403 /* Remember the SEEPROM type for later */
1404 if (sd.sd_chip == C56_66)
1405 ahc->flags |= AHC_LARGE_SEEPROM;
1406 }
1407
1408 if (!have_seeprom) {
1409 /*
1410 * Pull scratch ram settings and treat them as
1411 * if they are the contents of an seeprom if
1412 * the 'ADPT' signature is found in SCB2.
1413 * We manually compose the data as 16bit values
1414 * to avoid endian issues.
1415 */
1416 ahc_outb(ahc, SCBPTR, 2);
1417 if (ahc_inb(ahc, SCB_BASE) == 'A'
1418 && ahc_inb(ahc, SCB_BASE + 1) == 'D'
1419 && ahc_inb(ahc, SCB_BASE + 2) == 'P'
1420 && ahc_inb(ahc, SCB_BASE + 3) == 'T') {
1421 uint16_t *sc_data;
1422 int i;
1423
1424 sc_data = (uint16_t *)sc;
1425 for (i = 0; i < 32; i++, sc_data++) {
1426 int j;
1427
1428 j = i * 2;
1429 *sc_data = ahc_inb(ahc, SRAM_BASE + j)
1430 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8;
1431 }
1432 have_seeprom = ahc_verify_cksum(sc);
1433 if (have_seeprom)
1434 ahc->flags |= AHC_SCB_CONFIG_USED;
1435 }
1436 /*
1437 * Clear any SCB parity errors in case this data and
1438 * its associated parity was not initialized by the BIOS
1439 */
1440 ahc_outb(ahc, CLRINT, CLRPARERR);
1441 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1442 }
1443
1444 if (!have_seeprom) {
1445 if (bootverbose)
1446 printf("%s: No SEEPROM available.\n", ahc_name(ahc));
1447 ahc->flags |= AHC_USEDEFAULTS;
1448 free(ahc->seep_config, M_DEVBUF);
1449 ahc->seep_config = NULL;
1450 sc = NULL;
1451 } else {
1452 ahc_parse_pci_eeprom(ahc, sc);
1453 }
1454
1455 /*
1456 * Cards that have the external logic necessary to talk to
1457 * a SEEPROM, are almost certain to have the remaining logic
1458 * necessary for auto-termination control. This assumption
1459 * hasn't failed yet...
1460 */
1461 have_autoterm = have_seeprom;
1462
1463 /*
1464 * Some low-cost chips have SEEPROM and auto-term control built
1465 * in, instead of using a GAL. They can tell us directly
1466 * if the termination logic is enabled.
1467 */
1468 if ((ahc->features & AHC_SPIOCAP) != 0) {
1469 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0)
1470 have_autoterm = FALSE;
1471 }
1472
1473 if (have_autoterm) {
1474 ahc->flags |= AHC_HAS_TERM_LOGIC;
1475 ahc_acquire_seeprom(ahc, &sd);
1476 configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1);
1477 ahc_release_seeprom(&sd);
1478 } else if (have_seeprom) {
1479 *sxfrctl1 &= ~STPWEN;
1480 if ((sc->adapter_control & CFSTERM) != 0)
1481 *sxfrctl1 |= STPWEN;
1482 if (bootverbose)
1483 printf("%s: Low byte termination %sabled\n",
1484 ahc_name(ahc),
1485 (*sxfrctl1 & STPWEN) ? "en" : "dis");
1486 }
1487 }
1488
1489 static void
ahc_parse_pci_eeprom(struct ahc_softc * ahc,struct seeprom_config * sc)1490 ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc)
1491 {
1492 /*
1493 * Put the data we've collected down into SRAM
1494 * where ahc_init will find it.
1495 */
1496 int i;
1497 int max_targ = sc->max_targets & CFMAXTARG;
1498 u_int scsi_conf;
1499 uint16_t discenable;
1500 uint16_t ultraenb;
1501
1502 discenable = 0;
1503 ultraenb = 0;
1504 if ((sc->adapter_control & CFULTRAEN) != 0) {
1505 /*
1506 * Determine if this adapter has a "newstyle"
1507 * SEEPROM format.
1508 */
1509 for (i = 0; i < max_targ; i++) {
1510 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) {
1511 ahc->flags |= AHC_NEWEEPROM_FMT;
1512 break;
1513 }
1514 }
1515 }
1516
1517 for (i = 0; i < max_targ; i++) {
1518 u_int scsirate;
1519 uint16_t target_mask;
1520
1521 target_mask = 0x01 << i;
1522 if (sc->device_flags[i] & CFDISC)
1523 discenable |= target_mask;
1524 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) {
1525 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0)
1526 ultraenb |= target_mask;
1527 } else if ((sc->adapter_control & CFULTRAEN) != 0) {
1528 ultraenb |= target_mask;
1529 }
1530 if ((sc->device_flags[i] & CFXFER) == 0x04
1531 && (ultraenb & target_mask) != 0) {
1532 /* Treat 10MHz as a non-ultra speed */
1533 sc->device_flags[i] &= ~CFXFER;
1534 ultraenb &= ~target_mask;
1535 }
1536 if ((ahc->features & AHC_ULTRA2) != 0) {
1537 u_int offset;
1538
1539 if (sc->device_flags[i] & CFSYNCH)
1540 offset = MAX_OFFSET_ULTRA2;
1541 else
1542 offset = 0;
1543 ahc_outb(ahc, TARG_OFFSET + i, offset);
1544
1545 /*
1546 * The ultra enable bits contain the
1547 * high bit of the ultra2 sync rate
1548 * field.
1549 */
1550 scsirate = (sc->device_flags[i] & CFXFER)
1551 | ((ultraenb & target_mask) ? 0x8 : 0x0);
1552 if (sc->device_flags[i] & CFWIDEB)
1553 scsirate |= WIDEXFER;
1554 } else {
1555 scsirate = (sc->device_flags[i] & CFXFER) << 4;
1556 if (sc->device_flags[i] & CFSYNCH)
1557 scsirate |= SOFS;
1558 if (sc->device_flags[i] & CFWIDEB)
1559 scsirate |= WIDEXFER;
1560 }
1561 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate);
1562 }
1563 ahc->our_id = sc->brtime_id & CFSCSIID;
1564
1565 scsi_conf = (ahc->our_id & 0x7);
1566 if (sc->adapter_control & CFSPARITY)
1567 scsi_conf |= ENSPCHK;
1568 if (sc->adapter_control & CFRESETB)
1569 scsi_conf |= RESET_SCSI;
1570
1571 ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT;
1572
1573 if (sc->bios_control & CFEXTEND)
1574 ahc->flags |= AHC_EXTENDED_TRANS_A;
1575
1576 if (sc->bios_control & CFBIOSEN)
1577 ahc->flags |= AHC_BIOS_ENABLED;
1578 if (ahc->features & AHC_ULTRA
1579 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) {
1580 /* Should we enable Ultra mode? */
1581 if (!(sc->adapter_control & CFULTRAEN))
1582 /* Treat us as a non-ultra card */
1583 ultraenb = 0;
1584 }
1585
1586 if (sc->signature == CFSIGNATURE
1587 || sc->signature == CFSIGNATURE2) {
1588 uint32_t devconfig;
1589
1590 /* Honor the STPWLEVEL settings */
1591 devconfig = aic_pci_read_config(ahc->dev_softc,
1592 DEVCONFIG, /*bytes*/4);
1593 devconfig &= ~STPWLEVEL;
1594 if ((sc->bios_control & CFSTPWLEVEL) != 0)
1595 devconfig |= STPWLEVEL;
1596 aic_pci_write_config(ahc->dev_softc, DEVCONFIG,
1597 devconfig, /*bytes*/4);
1598 }
1599 /* Set SCSICONF info */
1600 ahc_outb(ahc, SCSICONF, scsi_conf);
1601 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff));
1602 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff));
1603 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff);
1604 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff);
1605 }
1606
1607 static void
configure_termination(struct ahc_softc * ahc,struct seeprom_descriptor * sd,u_int adapter_control,u_int * sxfrctl1)1608 configure_termination(struct ahc_softc *ahc,
1609 struct seeprom_descriptor *sd,
1610 u_int adapter_control,
1611 u_int *sxfrctl1)
1612 {
1613 uint8_t brddat;
1614
1615 brddat = 0;
1616
1617 /*
1618 * Update the settings in sxfrctl1 to match the
1619 * termination settings
1620 */
1621 *sxfrctl1 = 0;
1622
1623 /*
1624 * SEECS must be on for the GALS to latch
1625 * the data properly. Be sure to leave MS
1626 * on or we will release the seeprom.
1627 */
1628 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS);
1629 if ((adapter_control & CFAUTOTERM) != 0
1630 || (ahc->features & AHC_NEW_TERMCTL) != 0) {
1631 int internal50_present;
1632 int internal68_present;
1633 int externalcable_present;
1634 int eeprom_present;
1635 int enableSEC_low;
1636 int enableSEC_high;
1637 int enablePRI_low;
1638 int enablePRI_high;
1639 int sum;
1640
1641 enableSEC_low = 0;
1642 enableSEC_high = 0;
1643 enablePRI_low = 0;
1644 enablePRI_high = 0;
1645 if ((ahc->features & AHC_NEW_TERMCTL) != 0) {
1646 ahc_new_term_detect(ahc, &enableSEC_low,
1647 &enableSEC_high,
1648 &enablePRI_low,
1649 &enablePRI_high,
1650 &eeprom_present);
1651 if ((adapter_control & CFSEAUTOTERM) == 0) {
1652 if (bootverbose)
1653 printf("%s: Manual SE Termination\n",
1654 ahc_name(ahc));
1655 enableSEC_low = (adapter_control & CFSELOWTERM);
1656 enableSEC_high =
1657 (adapter_control & CFSEHIGHTERM);
1658 }
1659 if ((adapter_control & CFAUTOTERM) == 0) {
1660 if (bootverbose)
1661 printf("%s: Manual LVD Termination\n",
1662 ahc_name(ahc));
1663 enablePRI_low = (adapter_control & CFSTERM);
1664 enablePRI_high = (adapter_control & CFWSTERM);
1665 }
1666 /* Make the table calculations below happy */
1667 internal50_present = 0;
1668 internal68_present = 1;
1669 externalcable_present = 1;
1670 } else if ((ahc->features & AHC_SPIOCAP) != 0) {
1671 aic785X_cable_detect(ahc, &internal50_present,
1672 &externalcable_present,
1673 &eeprom_present);
1674 /* Can never support a wide connector. */
1675 internal68_present = 0;
1676 } else {
1677 aic787X_cable_detect(ahc, &internal50_present,
1678 &internal68_present,
1679 &externalcable_present,
1680 &eeprom_present);
1681 }
1682
1683 if ((ahc->features & AHC_WIDE) == 0)
1684 internal68_present = 0;
1685
1686 if (bootverbose
1687 && (ahc->features & AHC_ULTRA2) == 0) {
1688 printf("%s: internal 50 cable %s present",
1689 ahc_name(ahc),
1690 internal50_present ? "is":"not");
1691
1692 if ((ahc->features & AHC_WIDE) != 0)
1693 printf(", internal 68 cable %s present",
1694 internal68_present ? "is":"not");
1695 printf("\n%s: external cable %s present\n",
1696 ahc_name(ahc),
1697 externalcable_present ? "is":"not");
1698 }
1699 if (bootverbose)
1700 printf("%s: BIOS eeprom %s present\n",
1701 ahc_name(ahc), eeprom_present ? "is" : "not");
1702
1703 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) {
1704 /*
1705 * The 50 pin connector is a separate bus,
1706 * so force it to always be terminated.
1707 * In the future, perform current sensing
1708 * to determine if we are in the middle of
1709 * a properly terminated bus.
1710 */
1711 internal50_present = 0;
1712 }
1713
1714 /*
1715 * Now set the termination based on what
1716 * we found.
1717 * Flash Enable = BRDDAT7
1718 * Secondary High Term Enable = BRDDAT6
1719 * Secondary Low Term Enable = BRDDAT5 (7890)
1720 * Primary High Term Enable = BRDDAT4 (7890)
1721 */
1722 if ((ahc->features & AHC_ULTRA2) == 0
1723 && (internal50_present != 0)
1724 && (internal68_present != 0)
1725 && (externalcable_present != 0)) {
1726 printf("%s: Illegal cable configuration!!. "
1727 "Only two connectors on the "
1728 "adapter may be used at a "
1729 "time!\n", ahc_name(ahc));
1730
1731 /*
1732 * Pretend there are no cables in the hope
1733 * that having all of the termination on
1734 * gives us a more stable bus.
1735 */
1736 internal50_present = 0;
1737 internal68_present = 0;
1738 externalcable_present = 0;
1739 }
1740
1741 if ((ahc->features & AHC_WIDE) != 0
1742 && ((externalcable_present == 0)
1743 || (internal68_present == 0)
1744 || (enableSEC_high != 0))) {
1745 brddat |= BRDDAT6;
1746 if (bootverbose) {
1747 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1748 printf("%s: 68 pin termination "
1749 "Enabled\n", ahc_name(ahc));
1750 else
1751 printf("%s: %sHigh byte termination "
1752 "Enabled\n", ahc_name(ahc),
1753 enableSEC_high ? "Secondary "
1754 : "");
1755 }
1756 }
1757
1758 sum = internal50_present + internal68_present
1759 + externalcable_present;
1760 if (sum < 2 || (enableSEC_low != 0)) {
1761 if ((ahc->features & AHC_ULTRA2) != 0)
1762 brddat |= BRDDAT5;
1763 else
1764 *sxfrctl1 |= STPWEN;
1765 if (bootverbose) {
1766 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1767 printf("%s: 50 pin termination "
1768 "Enabled\n", ahc_name(ahc));
1769 else
1770 printf("%s: %sLow byte termination "
1771 "Enabled\n", ahc_name(ahc),
1772 enableSEC_low ? "Secondary "
1773 : "");
1774 }
1775 }
1776
1777 if (enablePRI_low != 0) {
1778 *sxfrctl1 |= STPWEN;
1779 if (bootverbose)
1780 printf("%s: Primary Low Byte termination "
1781 "Enabled\n", ahc_name(ahc));
1782 }
1783
1784 /*
1785 * Setup STPWEN before setting up the rest of
1786 * the termination per the tech note on the U160 cards.
1787 */
1788 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1789
1790 if (enablePRI_high != 0) {
1791 brddat |= BRDDAT4;
1792 if (bootverbose)
1793 printf("%s: Primary High Byte "
1794 "termination Enabled\n",
1795 ahc_name(ahc));
1796 }
1797
1798 write_brdctl(ahc, brddat);
1799
1800 } else {
1801 if ((adapter_control & CFSTERM) != 0) {
1802 *sxfrctl1 |= STPWEN;
1803
1804 if (bootverbose)
1805 printf("%s: %sLow byte termination Enabled\n",
1806 ahc_name(ahc),
1807 (ahc->features & AHC_ULTRA2) ? "Primary "
1808 : "");
1809 }
1810
1811 if ((adapter_control & CFWSTERM) != 0
1812 && (ahc->features & AHC_WIDE) != 0) {
1813 brddat |= BRDDAT6;
1814 if (bootverbose)
1815 printf("%s: %sHigh byte termination Enabled\n",
1816 ahc_name(ahc),
1817 (ahc->features & AHC_ULTRA2)
1818 ? "Secondary " : "");
1819 }
1820
1821 /*
1822 * Setup STPWEN before setting up the rest of
1823 * the termination per the tech note on the U160 cards.
1824 */
1825 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1826
1827 if ((ahc->features & AHC_WIDE) != 0)
1828 write_brdctl(ahc, brddat);
1829 }
1830 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */
1831 }
1832
1833 static void
ahc_new_term_detect(struct ahc_softc * ahc,int * enableSEC_low,int * enableSEC_high,int * enablePRI_low,int * enablePRI_high,int * eeprom_present)1834 ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low,
1835 int *enableSEC_high, int *enablePRI_low,
1836 int *enablePRI_high, int *eeprom_present)
1837 {
1838 uint8_t brdctl;
1839
1840 /*
1841 * BRDDAT7 = Eeprom
1842 * BRDDAT6 = Enable Secondary High Byte termination
1843 * BRDDAT5 = Enable Secondary Low Byte termination
1844 * BRDDAT4 = Enable Primary high byte termination
1845 * BRDDAT3 = Enable Primary low byte termination
1846 */
1847 brdctl = read_brdctl(ahc);
1848 *eeprom_present = brdctl & BRDDAT7;
1849 *enableSEC_high = (brdctl & BRDDAT6);
1850 *enableSEC_low = (brdctl & BRDDAT5);
1851 *enablePRI_high = (brdctl & BRDDAT4);
1852 *enablePRI_low = (brdctl & BRDDAT3);
1853 }
1854
1855 static void
aic787X_cable_detect(struct ahc_softc * ahc,int * internal50_present,int * internal68_present,int * externalcable_present,int * eeprom_present)1856 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1857 int *internal68_present, int *externalcable_present,
1858 int *eeprom_present)
1859 {
1860 uint8_t brdctl;
1861
1862 /*
1863 * First read the status of our cables.
1864 * Set the rom bank to 0 since the
1865 * bank setting serves as a multiplexor
1866 * for the cable detection logic.
1867 * BRDDAT5 controls the bank switch.
1868 */
1869 write_brdctl(ahc, 0);
1870
1871 /*
1872 * Now read the state of the internal
1873 * connectors. BRDDAT6 is INT50 and
1874 * BRDDAT7 is INT68.
1875 */
1876 brdctl = read_brdctl(ahc);
1877 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1;
1878 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1;
1879
1880 /*
1881 * Set the rom bank to 1 and determine
1882 * the other signals.
1883 */
1884 write_brdctl(ahc, BRDDAT5);
1885
1886 /*
1887 * Now read the state of the external
1888 * connectors. BRDDAT6 is EXT68 and
1889 * BRDDAT7 is EPROMPS.
1890 */
1891 brdctl = read_brdctl(ahc);
1892 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1893 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0;
1894 }
1895
1896 static void
aic785X_cable_detect(struct ahc_softc * ahc,int * internal50_present,int * externalcable_present,int * eeprom_present)1897 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1898 int *externalcable_present, int *eeprom_present)
1899 {
1900 uint8_t brdctl;
1901 uint8_t spiocap;
1902
1903 spiocap = ahc_inb(ahc, SPIOCAP);
1904 spiocap &= ~SOFTCMDEN;
1905 spiocap |= EXT_BRDCTL;
1906 ahc_outb(ahc, SPIOCAP, spiocap);
1907 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS);
1908 ahc_flush_device_writes(ahc);
1909 aic_delay(500);
1910 ahc_outb(ahc, BRDCTL, 0);
1911 ahc_flush_device_writes(ahc);
1912 aic_delay(500);
1913 brdctl = ahc_inb(ahc, BRDCTL);
1914 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1;
1915 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1916 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0;
1917 }
1918
1919 int
ahc_acquire_seeprom(struct ahc_softc * ahc,struct seeprom_descriptor * sd)1920 ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd)
1921 {
1922 int wait;
1923
1924 if ((ahc->features & AHC_SPIOCAP) != 0
1925 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0)
1926 return (0);
1927
1928 /*
1929 * Request access of the memory port. When access is
1930 * granted, SEERDY will go high. We use a 1 second
1931 * timeout which should be near 1 second more than
1932 * is needed. Reason: after the chip reset, there
1933 * should be no contention.
1934 */
1935 SEEPROM_OUTB(sd, sd->sd_MS);
1936 wait = 1000; /* 1 second timeout in msec */
1937 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) {
1938 aic_delay(1000); /* delay 1 msec */
1939 }
1940 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) {
1941 SEEPROM_OUTB(sd, 0);
1942 return (0);
1943 }
1944 return(1);
1945 }
1946
1947 void
ahc_release_seeprom(struct seeprom_descriptor * sd)1948 ahc_release_seeprom(struct seeprom_descriptor *sd)
1949 {
1950 /* Release access to the memory port and the serial EEPROM. */
1951 SEEPROM_OUTB(sd, 0);
1952 }
1953
1954 static void
write_brdctl(struct ahc_softc * ahc,uint8_t value)1955 write_brdctl(struct ahc_softc *ahc, uint8_t value)
1956 {
1957 uint8_t brdctl;
1958
1959 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1960 brdctl = BRDSTB;
1961 if (ahc->channel == 'B')
1962 brdctl |= BRDCS;
1963 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1964 brdctl = 0;
1965 } else {
1966 brdctl = BRDSTB|BRDCS;
1967 }
1968 ahc_outb(ahc, BRDCTL, brdctl);
1969 ahc_flush_device_writes(ahc);
1970 brdctl |= value;
1971 ahc_outb(ahc, BRDCTL, brdctl);
1972 ahc_flush_device_writes(ahc);
1973 if ((ahc->features & AHC_ULTRA2) != 0)
1974 brdctl |= BRDSTB_ULTRA2;
1975 else
1976 brdctl &= ~BRDSTB;
1977 ahc_outb(ahc, BRDCTL, brdctl);
1978 ahc_flush_device_writes(ahc);
1979 if ((ahc->features & AHC_ULTRA2) != 0)
1980 brdctl = 0;
1981 else
1982 brdctl &= ~BRDCS;
1983 ahc_outb(ahc, BRDCTL, brdctl);
1984 }
1985
1986 static uint8_t
read_brdctl(struct ahc_softc * ahc)1987 read_brdctl(struct ahc_softc *ahc)
1988 {
1989 uint8_t brdctl;
1990 uint8_t value;
1991
1992 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1993 brdctl = BRDRW;
1994 if (ahc->channel == 'B')
1995 brdctl |= BRDCS;
1996 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1997 brdctl = BRDRW_ULTRA2;
1998 } else {
1999 brdctl = BRDRW|BRDCS;
2000 }
2001 ahc_outb(ahc, BRDCTL, brdctl);
2002 ahc_flush_device_writes(ahc);
2003 value = ahc_inb(ahc, BRDCTL);
2004 ahc_outb(ahc, BRDCTL, 0);
2005 return (value);
2006 }
2007
2008 static void
ahc_pci_intr(struct ahc_softc * ahc)2009 ahc_pci_intr(struct ahc_softc *ahc)
2010 {
2011 u_int error;
2012 u_int status1;
2013
2014 error = ahc_inb(ahc, ERROR);
2015 if ((error & PCIERRSTAT) == 0)
2016 return;
2017
2018 status1 = aic_pci_read_config(ahc->dev_softc,
2019 PCIR_STATUS + 1, /*bytes*/1);
2020
2021 if ((status1 & ~DPE) != 0
2022 || (ahc->flags & AHC_DISABLE_PCI_PERR) == 0) {
2023 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n",
2024 ahc_name(ahc),
2025 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
2026 }
2027
2028 if (status1 & DPE
2029 && (ahc->flags & AHC_DISABLE_PCI_PERR) == 0) {
2030 ahc->pci_target_perr_count++;
2031 printf("%s: Data Parity Error Detected during address "
2032 "or write data phase\n", ahc_name(ahc));
2033 }
2034 if (status1 & SSE) {
2035 printf("%s: Signal System Error Detected\n", ahc_name(ahc));
2036 }
2037 if (status1 & RMA) {
2038 printf("%s: Received a Master Abort\n", ahc_name(ahc));
2039 }
2040 if (status1 & RTA) {
2041 printf("%s: Received a Target Abort\n", ahc_name(ahc));
2042 }
2043 if (status1 & STA) {
2044 printf("%s: Signaled a Target Abort\n", ahc_name(ahc));
2045 }
2046 if (status1 & DPR) {
2047 printf("%s: Data Parity Error has been reported via PERR#\n",
2048 ahc_name(ahc));
2049 }
2050
2051 /* Clear latched errors. */
2052 aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
2053 status1, /*bytes*/1);
2054
2055 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) {
2056 printf("%s: Latched PCIERR interrupt with "
2057 "no status bits set\n", ahc_name(ahc));
2058 } else {
2059 ahc_outb(ahc, CLRINT, CLRPARERR);
2060 }
2061
2062 if (ahc->pci_target_perr_count > AHC_PCI_TARGET_PERR_THRESH
2063 && (ahc->flags & AHC_DISABLE_PCI_PERR) == 0) {
2064 printf(
2065 "%s: WARNING WARNING WARNING WARNING\n"
2066 "%s: Too many PCI parity errors observed as a target.\n"
2067 "%s: Some device on this PCI bus is generating bad parity.\n"
2068 "%s: This is an error *observed by*, not *generated by*, %s.\n"
2069 "%s: PCI parity error checking has been disabled.\n"
2070 "%s: WARNING WARNING WARNING WARNING\n",
2071 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc),
2072 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc),
2073 ahc_name(ahc));
2074 ahc->seqctl |= FAILDIS;
2075 ahc->flags |= AHC_DISABLE_PCI_PERR;
2076 ahc_outb(ahc, SEQCTL, ahc->seqctl);
2077 }
2078 ahc_unpause(ahc);
2079 }
2080
2081 static int
ahc_pci_chip_init(struct ahc_softc * ahc)2082 ahc_pci_chip_init(struct ahc_softc *ahc)
2083 {
2084 ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0);
2085 ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus);
2086 if ((ahc->features & AHC_DT) != 0) {
2087 u_int sfunct;
2088
2089 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
2090 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
2091 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode);
2092 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt);
2093 ahc_outb(ahc, SFUNCT, sfunct);
2094 ahc_outb(ahc, CRCCONTROL1,
2095 ahc->bus_softc.pci_softc.crccontrol1);
2096 }
2097 if ((ahc->features & AHC_MULTI_FUNC) != 0)
2098 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr);
2099
2100 if ((ahc->features & AHC_ULTRA2) != 0)
2101 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh);
2102
2103 return (ahc_chip_init(ahc));
2104 }
2105
2106 static int
ahc_pci_suspend(struct ahc_softc * ahc)2107 ahc_pci_suspend(struct ahc_softc *ahc)
2108 {
2109 return (ahc_suspend(ahc));
2110 }
2111
2112 static int
ahc_pci_resume(struct ahc_softc * ahc)2113 ahc_pci_resume(struct ahc_softc *ahc)
2114 {
2115
2116 aic_power_state_change(ahc, AIC_POWER_STATE_D0);
2117
2118 /*
2119 * We assume that the OS has restored our register
2120 * mappings, etc. Just update the config space registers
2121 * that the OS doesn't know about and rely on our chip
2122 * reset handler to handle the rest.
2123 */
2124 aic_pci_write_config(ahc->dev_softc, DEVCONFIG,
2125 ahc->bus_softc.pci_softc.devconfig, /*bytes*/4);
2126 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
2127 ahc->bus_softc.pci_softc.command, /*bytes*/1);
2128 aic_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
2129 ahc->bus_softc.pci_softc.csize_lattime,
2130 /*bytes*/1);
2131 if ((ahc->flags & AHC_HAS_TERM_LOGIC) != 0) {
2132 struct seeprom_descriptor sd;
2133 u_int sxfrctl1;
2134
2135 sd.sd_ahc = ahc;
2136 sd.sd_control_offset = SEECTL;
2137 sd.sd_status_offset = SEECTL;
2138 sd.sd_dataout_offset = SEECTL;
2139
2140 ahc_acquire_seeprom(ahc, &sd);
2141 configure_termination(ahc, &sd,
2142 ahc->seep_config->adapter_control,
2143 &sxfrctl1);
2144 ahc_release_seeprom(&sd);
2145 }
2146 return (ahc_resume(ahc));
2147 }
2148
2149 static int
ahc_aic785X_setup(struct ahc_softc * ahc)2150 ahc_aic785X_setup(struct ahc_softc *ahc)
2151 {
2152 aic_dev_softc_t pci;
2153 uint8_t rev;
2154
2155 pci = ahc->dev_softc;
2156 ahc->channel = 'A';
2157 ahc->chip = AHC_AIC7850;
2158 ahc->features = AHC_AIC7850_FE;
2159 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2160 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2161 if (rev >= 1)
2162 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2163 ahc->instruction_ram_size = 512;
2164 return (0);
2165 }
2166
2167 static int
ahc_aic7860_setup(struct ahc_softc * ahc)2168 ahc_aic7860_setup(struct ahc_softc *ahc)
2169 {
2170 aic_dev_softc_t pci;
2171 uint8_t rev;
2172
2173 pci = ahc->dev_softc;
2174 ahc->channel = 'A';
2175 ahc->chip = AHC_AIC7860;
2176 ahc->features = AHC_AIC7860_FE;
2177 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2178 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2179 if (rev >= 1)
2180 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2181 ahc->instruction_ram_size = 512;
2182 return (0);
2183 }
2184
2185 static int
ahc_apa1480_setup(struct ahc_softc * ahc)2186 ahc_apa1480_setup(struct ahc_softc *ahc)
2187 {
2188 int error;
2189
2190 error = ahc_aic7860_setup(ahc);
2191 if (error != 0)
2192 return (error);
2193 ahc->features |= AHC_REMOVABLE;
2194 return (0);
2195 }
2196
2197 static int
ahc_aic7870_setup(struct ahc_softc * ahc)2198 ahc_aic7870_setup(struct ahc_softc *ahc)
2199 {
2200
2201 ahc->channel = 'A';
2202 ahc->chip = AHC_AIC7870;
2203 ahc->features = AHC_AIC7870_FE;
2204 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2205 ahc->instruction_ram_size = 512;
2206 return (0);
2207 }
2208
2209 static int
ahc_aha394X_setup(struct ahc_softc * ahc)2210 ahc_aha394X_setup(struct ahc_softc *ahc)
2211 {
2212 int error;
2213
2214 error = ahc_aic7870_setup(ahc);
2215 if (error == 0)
2216 error = ahc_aha394XX_setup(ahc);
2217 return (error);
2218 }
2219
2220 static int
ahc_aha398X_setup(struct ahc_softc * ahc)2221 ahc_aha398X_setup(struct ahc_softc *ahc)
2222 {
2223 int error;
2224
2225 error = ahc_aic7870_setup(ahc);
2226 if (error == 0)
2227 error = ahc_aha398XX_setup(ahc);
2228 return (error);
2229 }
2230
2231 static int
ahc_aha494X_setup(struct ahc_softc * ahc)2232 ahc_aha494X_setup(struct ahc_softc *ahc)
2233 {
2234 int error;
2235
2236 error = ahc_aic7870_setup(ahc);
2237 if (error == 0)
2238 error = ahc_aha494XX_setup(ahc);
2239 return (error);
2240 }
2241
2242 static int
ahc_aic7880_setup(struct ahc_softc * ahc)2243 ahc_aic7880_setup(struct ahc_softc *ahc)
2244 {
2245 aic_dev_softc_t pci;
2246 uint8_t rev;
2247
2248 pci = ahc->dev_softc;
2249 ahc->channel = 'A';
2250 ahc->chip = AHC_AIC7880;
2251 ahc->features = AHC_AIC7880_FE;
2252 ahc->bugs |= AHC_TMODE_WIDEODD_BUG;
2253 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2254 if (rev >= 1) {
2255 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2256 } else {
2257 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2258 }
2259 ahc->instruction_ram_size = 512;
2260 return (0);
2261 }
2262
2263 static int
ahc_aha2940Pro_setup(struct ahc_softc * ahc)2264 ahc_aha2940Pro_setup(struct ahc_softc *ahc)
2265 {
2266
2267 ahc->flags |= AHC_INT50_SPEEDFLEX;
2268 return (ahc_aic7880_setup(ahc));
2269 }
2270
2271 static int
ahc_aha394XU_setup(struct ahc_softc * ahc)2272 ahc_aha394XU_setup(struct ahc_softc *ahc)
2273 {
2274 int error;
2275
2276 error = ahc_aic7880_setup(ahc);
2277 if (error == 0)
2278 error = ahc_aha394XX_setup(ahc);
2279 return (error);
2280 }
2281
2282 static int
ahc_aha398XU_setup(struct ahc_softc * ahc)2283 ahc_aha398XU_setup(struct ahc_softc *ahc)
2284 {
2285 int error;
2286
2287 error = ahc_aic7880_setup(ahc);
2288 if (error == 0)
2289 error = ahc_aha398XX_setup(ahc);
2290 return (error);
2291 }
2292
2293 static int
ahc_aic7890_setup(struct ahc_softc * ahc)2294 ahc_aic7890_setup(struct ahc_softc *ahc)
2295 {
2296 aic_dev_softc_t pci;
2297 uint8_t rev;
2298
2299 pci = ahc->dev_softc;
2300 ahc->channel = 'A';
2301 ahc->chip = AHC_AIC7890;
2302 ahc->features = AHC_AIC7890_FE;
2303 ahc->flags |= AHC_NEWEEPROM_FMT;
2304 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2305 if (rev == 0)
2306 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG;
2307 ahc->instruction_ram_size = 768;
2308 return (0);
2309 }
2310
2311 static int
ahc_aic7892_setup(struct ahc_softc * ahc)2312 ahc_aic7892_setup(struct ahc_softc *ahc)
2313 {
2314
2315 ahc->channel = 'A';
2316 ahc->chip = AHC_AIC7892;
2317 ahc->features = AHC_AIC7892_FE;
2318 ahc->flags |= AHC_NEWEEPROM_FMT;
2319 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2320 ahc->instruction_ram_size = 1024;
2321 return (0);
2322 }
2323
2324 static int
ahc_aic7895_setup(struct ahc_softc * ahc)2325 ahc_aic7895_setup(struct ahc_softc *ahc)
2326 {
2327 aic_dev_softc_t pci;
2328 uint8_t rev;
2329
2330 pci = ahc->dev_softc;
2331 ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A';
2332 /*
2333 * The 'C' revision of the aic7895 has a few additional features.
2334 */
2335 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2336 if (rev >= 4) {
2337 ahc->chip = AHC_AIC7895C;
2338 ahc->features = AHC_AIC7895C_FE;
2339 } else {
2340 u_int command;
2341
2342 ahc->chip = AHC_AIC7895;
2343 ahc->features = AHC_AIC7895_FE;
2344
2345 /*
2346 * The BIOS disables the use of MWI transactions
2347 * since it does not have the MWI bug work around
2348 * we have. Disabling MWI reduces performance, so
2349 * turn it on again.
2350 */
2351 command = aic_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1);
2352 command |= PCIM_CMD_MWRICEN;
2353 aic_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1);
2354 ahc->bugs |= AHC_PCI_MWI_BUG;
2355 }
2356 /*
2357 * XXX Does CACHETHEN really not work??? What about PCI retry?
2358 * on C level chips. Need to test, but for now, play it safe.
2359 */
2360 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG
2361 | AHC_CACHETHEN_BUG;
2362
2363 #if 0
2364 uint32_t devconfig;
2365
2366 /*
2367 * Cachesize must also be zero due to stray DAC
2368 * problem when sitting behind some bridges.
2369 */
2370 aic_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1);
2371 devconfig = aic_pci_read_config(pci, DEVCONFIG, /*bytes*/1);
2372 devconfig |= MRDCEN;
2373 aic_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1);
2374 #endif
2375 ahc->flags |= AHC_NEWEEPROM_FMT;
2376 ahc->instruction_ram_size = 512;
2377 return (0);
2378 }
2379
2380 static int
ahc_aic7896_setup(struct ahc_softc * ahc)2381 ahc_aic7896_setup(struct ahc_softc *ahc)
2382 {
2383 aic_dev_softc_t pci;
2384
2385 pci = ahc->dev_softc;
2386 ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A';
2387 ahc->chip = AHC_AIC7896;
2388 ahc->features = AHC_AIC7896_FE;
2389 ahc->flags |= AHC_NEWEEPROM_FMT;
2390 ahc->bugs |= AHC_CACHETHEN_DIS_BUG;
2391 ahc->instruction_ram_size = 768;
2392 return (0);
2393 }
2394
2395 static int
ahc_aic7899_setup(struct ahc_softc * ahc)2396 ahc_aic7899_setup(struct ahc_softc *ahc)
2397 {
2398 aic_dev_softc_t pci;
2399
2400 pci = ahc->dev_softc;
2401 ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A';
2402 ahc->chip = AHC_AIC7899;
2403 ahc->features = AHC_AIC7899_FE;
2404 ahc->flags |= AHC_NEWEEPROM_FMT;
2405 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2406 ahc->instruction_ram_size = 1024;
2407 return (0);
2408 }
2409
2410 static int
ahc_aha29160C_setup(struct ahc_softc * ahc)2411 ahc_aha29160C_setup(struct ahc_softc *ahc)
2412 {
2413 int error;
2414
2415 error = ahc_aic7899_setup(ahc);
2416 if (error != 0)
2417 return (error);
2418 ahc->features |= AHC_REMOVABLE;
2419 return (0);
2420 }
2421
2422 static int
ahc_raid_setup(struct ahc_softc * ahc)2423 ahc_raid_setup(struct ahc_softc *ahc)
2424 {
2425 printf("RAID functionality unsupported\n");
2426 return (ENXIO);
2427 }
2428
2429 static int
ahc_aha394XX_setup(struct ahc_softc * ahc)2430 ahc_aha394XX_setup(struct ahc_softc *ahc)
2431 {
2432 aic_dev_softc_t pci;
2433
2434 pci = ahc->dev_softc;
2435 switch (aic_get_pci_slot(pci)) {
2436 case AHC_394X_SLOT_CHANNEL_A:
2437 ahc->channel = 'A';
2438 break;
2439 case AHC_394X_SLOT_CHANNEL_B:
2440 ahc->channel = 'B';
2441 break;
2442 default:
2443 printf("adapter at unexpected slot %d\n"
2444 "unable to map to a channel\n",
2445 aic_get_pci_slot(pci));
2446 ahc->channel = 'A';
2447 }
2448 return (0);
2449 }
2450
2451 static int
ahc_aha398XX_setup(struct ahc_softc * ahc)2452 ahc_aha398XX_setup(struct ahc_softc *ahc)
2453 {
2454 aic_dev_softc_t pci;
2455
2456 pci = ahc->dev_softc;
2457 switch (aic_get_pci_slot(pci)) {
2458 case AHC_398X_SLOT_CHANNEL_A:
2459 ahc->channel = 'A';
2460 break;
2461 case AHC_398X_SLOT_CHANNEL_B:
2462 ahc->channel = 'B';
2463 break;
2464 case AHC_398X_SLOT_CHANNEL_C:
2465 ahc->channel = 'C';
2466 break;
2467 default:
2468 printf("adapter at unexpected slot %d\n"
2469 "unable to map to a channel\n",
2470 aic_get_pci_slot(pci));
2471 ahc->channel = 'A';
2472 break;
2473 }
2474 ahc->flags |= AHC_LARGE_SEEPROM;
2475 return (0);
2476 }
2477
2478 static int
ahc_aha494XX_setup(struct ahc_softc * ahc)2479 ahc_aha494XX_setup(struct ahc_softc *ahc)
2480 {
2481 aic_dev_softc_t pci;
2482
2483 pci = ahc->dev_softc;
2484 switch (aic_get_pci_slot(pci)) {
2485 case AHC_494X_SLOT_CHANNEL_A:
2486 ahc->channel = 'A';
2487 break;
2488 case AHC_494X_SLOT_CHANNEL_B:
2489 ahc->channel = 'B';
2490 break;
2491 case AHC_494X_SLOT_CHANNEL_C:
2492 ahc->channel = 'C';
2493 break;
2494 case AHC_494X_SLOT_CHANNEL_D:
2495 ahc->channel = 'D';
2496 break;
2497 default:
2498 printf("adapter at unexpected slot %d\n"
2499 "unable to map to a channel\n",
2500 aic_get_pci_slot(pci));
2501 ahc->channel = 'A';
2502 }
2503 ahc->flags |= AHC_LARGE_SEEPROM;
2504 return (0);
2505 }
2506