1 /*-
2 * Product specific probe and attach routines for:
3 * 3940, 2940, aic7895, aic7890, aic7880,
4 * aic7870, aic7860 and aic7850 SCSI controllers
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 *
8 * Copyright (c) 1994-2001 Justin T. Gibbs.
9 * Copyright (c) 2000-2001 Adaptec Inc.
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions, and the following disclaimer,
17 * without modification.
18 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
19 * substantially similar to the "NO WARRANTY" disclaimer below
20 * ("Disclaimer") and any redistribution must be conditioned upon
21 * including a substantially similar Disclaimer requirement for further
22 * binary redistribution.
23 * 3. Neither the names of the above-listed copyright holders nor the names
24 * of any contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * Alternatively, this software may be distributed under the terms of the
28 * GNU General Public License ("GPL") version 2 as published by the Free
29 * Software Foundation.
30 *
31 * NO WARRANTY
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
35 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
36 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
40 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
41 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
42 * POSSIBILITY OF SUCH DAMAGES.
43 *
44 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#78 $
45 */
46
47 #ifdef __linux__
48 #include "aic7xxx_osm.h"
49 #include "aic7xxx_inline.h"
50 #include "aic7xxx_93cx6.h"
51 #else
52 #include <sys/cdefs.h>
53 __FBSDID("$FreeBSD: stable/12/sys/dev/aic7xxx/aic7xxx_pci.c 326255 2017-11-27 14:52:40Z pfg $");
54 #include <dev/aic7xxx/aic7xxx_osm.h>
55 #include <dev/aic7xxx/aic7xxx_inline.h>
56 #include <dev/aic7xxx/aic7xxx_93cx6.h>
57 #endif
58
59 static __inline uint64_t
ahc_compose_id(u_int device,u_int vendor,u_int subdevice,u_int subvendor)60 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
61 {
62 uint64_t id;
63
64 id = subvendor
65 | (subdevice << 16)
66 | ((uint64_t)vendor << 32)
67 | ((uint64_t)device << 48);
68
69 return (id);
70 }
71
72 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
73 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
74 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull
75 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull
76 #define ID_9005_SISL_ID 0x0005900500000000ull
77 #define ID_AIC7850 0x5078900400000000ull
78 #define ID_AHA_2902_04_10_15_20C_30C 0x5078900478509004ull
79 #define ID_AIC7855 0x5578900400000000ull
80 #define ID_AIC7859 0x3860900400000000ull
81 #define ID_AHA_2930CU 0x3860900438699004ull
82 #define ID_AIC7860 0x6078900400000000ull
83 #define ID_AIC7860C 0x6078900478609004ull
84 #define ID_AHA_1480A 0x6075900400000000ull
85 #define ID_AHA_2940AU_0 0x6178900400000000ull
86 #define ID_AHA_2940AU_1 0x6178900478619004ull
87 #define ID_AHA_2940AU_CN 0x2178900478219004ull
88 #define ID_AHA_2930C_VAR 0x6038900438689004ull
89
90 #define ID_AIC7870 0x7078900400000000ull
91 #define ID_AHA_2940 0x7178900400000000ull
92 #define ID_AHA_3940 0x7278900400000000ull
93 #define ID_AHA_398X 0x7378900400000000ull
94 #define ID_AHA_2944 0x7478900400000000ull
95 #define ID_AHA_3944 0x7578900400000000ull
96 #define ID_AHA_4944 0x7678900400000000ull
97
98 #define ID_AIC7880 0x8078900400000000ull
99 #define ID_AIC7880_B 0x8078900478809004ull
100 #define ID_AHA_2940U 0x8178900400000000ull
101 #define ID_AHA_3940U 0x8278900400000000ull
102 #define ID_AHA_2944U 0x8478900400000000ull
103 #define ID_AHA_3944U 0x8578900400000000ull
104 #define ID_AHA_398XU 0x8378900400000000ull
105 #define ID_AHA_4944U 0x8678900400000000ull
106 #define ID_AHA_2940UB 0x8178900478819004ull
107 #define ID_AHA_2930U 0x8878900478889004ull
108 #define ID_AHA_2940U_PRO 0x8778900478879004ull
109 #define ID_AHA_2940U_CN 0x0078900478009004ull
110
111 #define ID_AIC7895 0x7895900478959004ull
112 #define ID_AIC7895_ARO 0x7890900478939004ull
113 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull
114 #define ID_AHA_2940U_DUAL 0x7895900478919004ull
115 #define ID_AHA_3940AU 0x7895900478929004ull
116 #define ID_AHA_3944AU 0x7895900478949004ull
117
118 #define ID_AIC7890 0x001F9005000F9005ull
119 #define ID_AIC7890_ARO 0x00139005000F9005ull
120 #define ID_AAA_131U2 0x0013900500039005ull
121 #define ID_AHA_2930U2 0x0011900501819005ull
122 #define ID_AHA_2940U2B 0x00109005A1009005ull
123 #define ID_AHA_2940U2_OEM 0x0010900521809005ull
124 #define ID_AHA_2940U2 0x00109005A1809005ull
125 #define ID_AHA_2950U2B 0x00109005E1009005ull
126
127 #define ID_AIC7892 0x008F9005FFFF9005ull
128 #define ID_AIC7892_ARO 0x00839005FFFF9005ull
129 #define ID_AHA_29160 0x00809005E2A09005ull
130 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull
131 #define ID_AHA_29160N 0x0080900562A09005ull
132 #define ID_AHA_29160C 0x0080900562209005ull
133 #define ID_AHA_29160B 0x00809005E2209005ull
134 #define ID_AHA_19160B 0x0081900562A19005ull
135 #define ID_AHA_2915_30LP 0x0082900502109005ull
136
137 #define ID_AIC7896 0x005F9005FFFF9005ull
138 #define ID_AIC7896_ARO 0x00539005FFFF9005ull
139 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull
140 #define ID_AHA_3950U2B_1 0x00509005F5009005ull
141 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull
142 #define ID_AHA_3950U2D_1 0x00519005B5009005ull
143
144 #define ID_AIC7899 0x00CF9005FFFF9005ull
145 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull
146 #define ID_AHA_3960D 0x00C09005F6209005ull
147 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull
148
149 #define ID_AIC7810 0x1078900400000000ull
150 #define ID_AIC7815 0x7815900400000000ull
151
152 #define DEVID_9005_TYPE(id) ((id) & 0xF)
153 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
154 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */
155 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */
156 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
157
158 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
159 #define DEVID_9005_MAXRATE_U160 0x0
160 #define DEVID_9005_MAXRATE_ULTRA2 0x1
161 #define DEVID_9005_MAXRATE_ULTRA 0x2
162 #define DEVID_9005_MAXRATE_FAST 0x3
163
164 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6)
165
166 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8)
167 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */
168
169 #define SUBID_9005_TYPE(id) ((id) & 0xF)
170 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */
171 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */
172 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */
173 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */
174
175 #define SUBID_9005_TYPE_KNOWN(id) \
176 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \
177 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \
178 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \
179 || (((id) & 0xF) == SUBID_9005_TYPE_RAID))
180
181 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
182 #define SUBID_9005_MAXRATE_ULTRA2 0x0
183 #define SUBID_9005_MAXRATE_ULTRA 0x1
184 #define SUBID_9005_MAXRATE_U160 0x2
185 #define SUBID_9005_MAXRATE_RESERVED 0x3
186
187 #define SUBID_9005_SEEPTYPE(id) \
188 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
189 ? ((id) & 0xC0) >> 6 \
190 : ((id) & 0x300) >> 8)
191 #define SUBID_9005_SEEPTYPE_NONE 0x0
192 #define SUBID_9005_SEEPTYPE_1K 0x1
193 #define SUBID_9005_SEEPTYPE_2K_4K 0x2
194 #define SUBID_9005_SEEPTYPE_RESERVED 0x3
195 #define SUBID_9005_AUTOTERM(id) \
196 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
197 ? (((id) & 0x400) >> 10) == 0 \
198 : (((id) & 0x40) >> 6) == 0)
199
200 #define SUBID_9005_NUMCHAN(id) \
201 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
202 ? ((id) & 0x300) >> 8 \
203 : ((id) & 0xC00) >> 10)
204
205 #define SUBID_9005_LEGACYCONN(id) \
206 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
207 ? 0 \
208 : ((id) & 0x80) >> 7)
209
210 #define SUBID_9005_MFUNCENB(id) \
211 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
212 ? ((id) & 0x800) >> 11 \
213 : ((id) & 0x1000) >> 12)
214 /*
215 * Informational only. Should use chip register to be
216 * certain, but may be use in identification strings.
217 */
218 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000
219 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000
220 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000
221
222 static ahc_device_setup_t ahc_aic785X_setup;
223 static ahc_device_setup_t ahc_aic7860_setup;
224 static ahc_device_setup_t ahc_apa1480_setup;
225 static ahc_device_setup_t ahc_aic7870_setup;
226 static ahc_device_setup_t ahc_aha394X_setup;
227 static ahc_device_setup_t ahc_aha494X_setup;
228 static ahc_device_setup_t ahc_aha398X_setup;
229 static ahc_device_setup_t ahc_aic7880_setup;
230 static ahc_device_setup_t ahc_aha2940Pro_setup;
231 static ahc_device_setup_t ahc_aha394XU_setup;
232 static ahc_device_setup_t ahc_aha398XU_setup;
233 static ahc_device_setup_t ahc_aic7890_setup;
234 static ahc_device_setup_t ahc_aic7892_setup;
235 static ahc_device_setup_t ahc_aic7895_setup;
236 static ahc_device_setup_t ahc_aic7896_setup;
237 static ahc_device_setup_t ahc_aic7899_setup;
238 static ahc_device_setup_t ahc_aha29160C_setup;
239 static ahc_device_setup_t ahc_raid_setup;
240 static ahc_device_setup_t ahc_aha394XX_setup;
241 static ahc_device_setup_t ahc_aha494XX_setup;
242 static ahc_device_setup_t ahc_aha398XX_setup;
243
244 struct ahc_pci_identity ahc_pci_ident_table [] =
245 {
246 /* aic7850 based controllers */
247 {
248 ID_AHA_2902_04_10_15_20C_30C,
249 ID_ALL_MASK,
250 "Adaptec 2902/04/10/15/20C/30C SCSI adapter",
251 ahc_aic785X_setup
252 },
253 /* aic7860 based controllers */
254 {
255 ID_AHA_2930CU,
256 ID_ALL_MASK,
257 "Adaptec 2930CU SCSI adapter",
258 ahc_aic7860_setup
259 },
260 {
261 ID_AHA_1480A & ID_DEV_VENDOR_MASK,
262 ID_DEV_VENDOR_MASK,
263 "Adaptec 1480A Ultra SCSI adapter",
264 ahc_apa1480_setup
265 },
266 {
267 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK,
268 ID_DEV_VENDOR_MASK,
269 "Adaptec 2940A Ultra SCSI adapter",
270 ahc_aic7860_setup
271 },
272 {
273 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK,
274 ID_DEV_VENDOR_MASK,
275 "Adaptec 2940A/CN Ultra SCSI adapter",
276 ahc_aic7860_setup
277 },
278 {
279 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK,
280 ID_DEV_VENDOR_MASK,
281 "Adaptec 2930C Ultra SCSI adapter (VAR)",
282 ahc_aic7860_setup
283 },
284 /* aic7870 based controllers */
285 {
286 ID_AHA_2940,
287 ID_ALL_MASK,
288 "Adaptec 2940 SCSI adapter",
289 ahc_aic7870_setup
290 },
291 {
292 ID_AHA_3940,
293 ID_ALL_MASK,
294 "Adaptec 3940 SCSI adapter",
295 ahc_aha394X_setup
296 },
297 {
298 ID_AHA_398X,
299 ID_ALL_MASK,
300 "Adaptec 398X SCSI RAID adapter",
301 ahc_aha398X_setup
302 },
303 {
304 ID_AHA_2944,
305 ID_ALL_MASK,
306 "Adaptec 2944 SCSI adapter",
307 ahc_aic7870_setup
308 },
309 {
310 ID_AHA_3944,
311 ID_ALL_MASK,
312 "Adaptec 3944 SCSI adapter",
313 ahc_aha394X_setup
314 },
315 {
316 ID_AHA_4944,
317 ID_ALL_MASK,
318 "Adaptec 4944 SCSI adapter",
319 ahc_aha494X_setup
320 },
321 /* aic7880 based controllers */
322 {
323 ID_AHA_2940U & ID_DEV_VENDOR_MASK,
324 ID_DEV_VENDOR_MASK,
325 "Adaptec 2940 Ultra SCSI adapter",
326 ahc_aic7880_setup
327 },
328 {
329 ID_AHA_3940U & ID_DEV_VENDOR_MASK,
330 ID_DEV_VENDOR_MASK,
331 "Adaptec 3940 Ultra SCSI adapter",
332 ahc_aha394XU_setup
333 },
334 {
335 ID_AHA_2944U & ID_DEV_VENDOR_MASK,
336 ID_DEV_VENDOR_MASK,
337 "Adaptec 2944 Ultra SCSI adapter",
338 ahc_aic7880_setup
339 },
340 {
341 ID_AHA_3944U & ID_DEV_VENDOR_MASK,
342 ID_DEV_VENDOR_MASK,
343 "Adaptec 3944 Ultra SCSI adapter",
344 ahc_aha394XU_setup
345 },
346 {
347 ID_AHA_398XU & ID_DEV_VENDOR_MASK,
348 ID_DEV_VENDOR_MASK,
349 "Adaptec 398X Ultra SCSI RAID adapter",
350 ahc_aha398XU_setup
351 },
352 {
353 /*
354 * XXX Don't know the slot numbers
355 * so we can't identify channels
356 */
357 ID_AHA_4944U & ID_DEV_VENDOR_MASK,
358 ID_DEV_VENDOR_MASK,
359 "Adaptec 4944 Ultra SCSI adapter",
360 ahc_aic7880_setup
361 },
362 {
363 ID_AHA_2930U & ID_DEV_VENDOR_MASK,
364 ID_DEV_VENDOR_MASK,
365 "Adaptec 2930 Ultra SCSI adapter",
366 ahc_aic7880_setup
367 },
368 {
369 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK,
370 ID_DEV_VENDOR_MASK,
371 "Adaptec 2940 Pro Ultra SCSI adapter",
372 ahc_aha2940Pro_setup
373 },
374 {
375 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK,
376 ID_DEV_VENDOR_MASK,
377 "Adaptec 2940/CN Ultra SCSI adapter",
378 ahc_aic7880_setup
379 },
380 /* Ignore all SISL (AAC on MB) based controllers. */
381 {
382 ID_9005_SISL_ID,
383 ID_9005_SISL_MASK,
384 NULL,
385 NULL
386 },
387 /* aic7890 based controllers */
388 {
389 ID_AHA_2930U2,
390 ID_ALL_MASK,
391 "Adaptec 2930 Ultra2 SCSI adapter",
392 ahc_aic7890_setup
393 },
394 {
395 ID_AHA_2940U2B,
396 ID_ALL_MASK,
397 "Adaptec 2940B Ultra2 SCSI adapter",
398 ahc_aic7890_setup
399 },
400 {
401 ID_AHA_2940U2_OEM,
402 ID_ALL_MASK,
403 "Adaptec 2940 Ultra2 SCSI adapter (OEM)",
404 ahc_aic7890_setup
405 },
406 {
407 ID_AHA_2940U2,
408 ID_ALL_MASK,
409 "Adaptec 2940 Ultra2 SCSI adapter",
410 ahc_aic7890_setup
411 },
412 {
413 ID_AHA_2950U2B,
414 ID_ALL_MASK,
415 "Adaptec 2950 Ultra2 SCSI adapter",
416 ahc_aic7890_setup
417 },
418 {
419 ID_AIC7890_ARO,
420 ID_ALL_MASK,
421 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)",
422 ahc_aic7890_setup
423 },
424 {
425 ID_AAA_131U2,
426 ID_ALL_MASK,
427 "Adaptec AAA-131 Ultra2 RAID adapter",
428 ahc_aic7890_setup
429 },
430 /* aic7892 based controllers */
431 {
432 ID_AHA_29160,
433 ID_ALL_MASK,
434 "Adaptec 29160 Ultra160 SCSI adapter",
435 ahc_aic7892_setup
436 },
437 {
438 ID_AHA_29160_CPQ,
439 ID_ALL_MASK,
440 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter",
441 ahc_aic7892_setup
442 },
443 {
444 ID_AHA_29160N,
445 ID_ALL_MASK,
446 "Adaptec 29160N Ultra160 SCSI adapter",
447 ahc_aic7892_setup
448 },
449 {
450 ID_AHA_29160C,
451 ID_ALL_MASK,
452 "Adaptec 29160C Ultra160 SCSI adapter",
453 ahc_aha29160C_setup
454 },
455 {
456 ID_AHA_29160B,
457 ID_ALL_MASK,
458 "Adaptec 29160B Ultra160 SCSI adapter",
459 ahc_aic7892_setup
460 },
461 {
462 ID_AHA_19160B,
463 ID_ALL_MASK,
464 "Adaptec 19160B Ultra160 SCSI adapter",
465 ahc_aic7892_setup
466 },
467 {
468 ID_AIC7892_ARO,
469 ID_ALL_MASK,
470 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)",
471 ahc_aic7892_setup
472 },
473 {
474 ID_AHA_2915_30LP,
475 ID_ALL_MASK,
476 "Adaptec 2915/30LP Ultra160 SCSI adapter",
477 ahc_aic7892_setup
478 },
479 /* aic7895 based controllers */
480 {
481 ID_AHA_2940U_DUAL,
482 ID_ALL_MASK,
483 "Adaptec 2940/DUAL Ultra SCSI adapter",
484 ahc_aic7895_setup
485 },
486 {
487 ID_AHA_3940AU,
488 ID_ALL_MASK,
489 "Adaptec 3940A Ultra SCSI adapter",
490 ahc_aic7895_setup
491 },
492 {
493 ID_AHA_3944AU,
494 ID_ALL_MASK,
495 "Adaptec 3944A Ultra SCSI adapter",
496 ahc_aic7895_setup
497 },
498 {
499 ID_AIC7895_ARO,
500 ID_AIC7895_ARO_MASK,
501 "Adaptec aic7895 Ultra SCSI adapter (ARO)",
502 ahc_aic7895_setup
503 },
504 /* aic7896/97 based controllers */
505 {
506 ID_AHA_3950U2B_0,
507 ID_ALL_MASK,
508 "Adaptec 3950B Ultra2 SCSI adapter",
509 ahc_aic7896_setup
510 },
511 {
512 ID_AHA_3950U2B_1,
513 ID_ALL_MASK,
514 "Adaptec 3950B Ultra2 SCSI adapter",
515 ahc_aic7896_setup
516 },
517 {
518 ID_AHA_3950U2D_0,
519 ID_ALL_MASK,
520 "Adaptec 3950D Ultra2 SCSI adapter",
521 ahc_aic7896_setup
522 },
523 {
524 ID_AHA_3950U2D_1,
525 ID_ALL_MASK,
526 "Adaptec 3950D Ultra2 SCSI adapter",
527 ahc_aic7896_setup
528 },
529 {
530 ID_AIC7896_ARO,
531 ID_ALL_MASK,
532 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)",
533 ahc_aic7896_setup
534 },
535 /* aic7899 based controllers */
536 {
537 ID_AHA_3960D,
538 ID_ALL_MASK,
539 "Adaptec 3960D Ultra160 SCSI adapter",
540 ahc_aic7899_setup
541 },
542 {
543 ID_AHA_3960D_CPQ,
544 ID_ALL_MASK,
545 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter",
546 ahc_aic7899_setup
547 },
548 {
549 ID_AIC7899_ARO,
550 ID_ALL_MASK,
551 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)",
552 ahc_aic7899_setup
553 },
554 /* Generic chip probes for devices we don't know 'exactly' */
555 {
556 ID_AIC7850 & ID_DEV_VENDOR_MASK,
557 ID_DEV_VENDOR_MASK,
558 "Adaptec aic7850 SCSI adapter",
559 ahc_aic785X_setup
560 },
561 {
562 ID_AIC7855 & ID_DEV_VENDOR_MASK,
563 ID_DEV_VENDOR_MASK,
564 "Adaptec aic7855 SCSI adapter",
565 ahc_aic785X_setup
566 },
567 {
568 ID_AIC7859 & ID_DEV_VENDOR_MASK,
569 ID_DEV_VENDOR_MASK,
570 "Adaptec aic7859 SCSI adapter",
571 ahc_aic7860_setup
572 },
573 {
574 ID_AIC7860 & ID_DEV_VENDOR_MASK,
575 ID_DEV_VENDOR_MASK,
576 "Adaptec aic7860 Ultra SCSI adapter",
577 ahc_aic7860_setup
578 },
579 {
580 ID_AIC7870 & ID_DEV_VENDOR_MASK,
581 ID_DEV_VENDOR_MASK,
582 "Adaptec aic7870 SCSI adapter",
583 ahc_aic7870_setup
584 },
585 {
586 ID_AIC7880 & ID_DEV_VENDOR_MASK,
587 ID_DEV_VENDOR_MASK,
588 "Adaptec aic7880 Ultra SCSI adapter",
589 ahc_aic7880_setup
590 },
591 {
592 ID_AIC7890 & ID_9005_GENERIC_MASK,
593 ID_9005_GENERIC_MASK,
594 "Adaptec aic7890/91 Ultra2 SCSI adapter",
595 ahc_aic7890_setup
596 },
597 {
598 ID_AIC7892 & ID_9005_GENERIC_MASK,
599 ID_9005_GENERIC_MASK,
600 "Adaptec aic7892 Ultra160 SCSI adapter",
601 ahc_aic7892_setup
602 },
603 {
604 ID_AIC7895 & ID_DEV_VENDOR_MASK,
605 ID_DEV_VENDOR_MASK,
606 "Adaptec aic7895 Ultra SCSI adapter",
607 ahc_aic7895_setup
608 },
609 {
610 ID_AIC7896 & ID_9005_GENERIC_MASK,
611 ID_9005_GENERIC_MASK,
612 "Adaptec aic7896/97 Ultra2 SCSI adapter",
613 ahc_aic7896_setup
614 },
615 {
616 ID_AIC7899 & ID_9005_GENERIC_MASK,
617 ID_9005_GENERIC_MASK,
618 "Adaptec aic7899 Ultra160 SCSI adapter",
619 ahc_aic7899_setup
620 },
621 {
622 ID_AIC7810 & ID_DEV_VENDOR_MASK,
623 ID_DEV_VENDOR_MASK,
624 "Adaptec aic7810 RAID memory controller",
625 ahc_raid_setup
626 },
627 {
628 ID_AIC7815 & ID_DEV_VENDOR_MASK,
629 ID_DEV_VENDOR_MASK,
630 "Adaptec aic7815 RAID memory controller",
631 ahc_raid_setup
632 }
633 };
634
635 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table);
636
637 #define AHC_394X_SLOT_CHANNEL_A 4
638 #define AHC_394X_SLOT_CHANNEL_B 5
639
640 #define AHC_398X_SLOT_CHANNEL_A 4
641 #define AHC_398X_SLOT_CHANNEL_B 8
642 #define AHC_398X_SLOT_CHANNEL_C 12
643
644 #define AHC_494X_SLOT_CHANNEL_A 4
645 #define AHC_494X_SLOT_CHANNEL_B 5
646 #define AHC_494X_SLOT_CHANNEL_C 6
647 #define AHC_494X_SLOT_CHANNEL_D 7
648
649 #define DEVCONFIG 0x40
650 #define PCIERRGENDIS 0x80000000ul
651 #define SCBSIZE32 0x00010000ul /* aic789X only */
652 #define REXTVALID 0x00001000ul /* ultra cards only */
653 #define MPORTMODE 0x00000400ul /* aic7870+ only */
654 #define RAMPSM 0x00000200ul /* aic7870+ only */
655 #define VOLSENSE 0x00000100ul
656 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/
657 #define SCBRAMSEL 0x00000080ul
658 #define MRDCEN 0x00000040ul
659 #define EXTSCBTIME 0x00000020ul /* aic7870 only */
660 #define EXTSCBPEN 0x00000010ul /* aic7870 only */
661 #define BERREN 0x00000008ul
662 #define DACEN 0x00000004ul
663 #define STPWLEVEL 0x00000002ul
664 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */
665
666 #define CSIZE_LATTIME 0x0c
667 #define CACHESIZE 0x0000003ful /* only 5 bits */
668 #define LATTIME 0x0000ff00ul
669
670 /* PCI STATUS definitions */
671 #define DPE 0x80
672 #define SSE 0x40
673 #define RMA 0x20
674 #define RTA 0x10
675 #define STA 0x08
676 #define DPR 0x01
677
678 static int ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
679 uint16_t subdevice, uint16_t subvendor);
680 static int ahc_ext_scbram_present(struct ahc_softc *ahc);
681 static void ahc_scbram_config(struct ahc_softc *ahc, int enable,
682 int pcheck, int fast, int large);
683 static void ahc_probe_ext_scbram(struct ahc_softc *ahc);
684 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1);
685 static void ahc_parse_pci_eeprom(struct ahc_softc *ahc,
686 struct seeprom_config *sc);
687 static void configure_termination(struct ahc_softc *ahc,
688 struct seeprom_descriptor *sd,
689 u_int adapter_control,
690 u_int *sxfrctl1);
691
692 static void ahc_new_term_detect(struct ahc_softc *ahc,
693 int *enableSEC_low,
694 int *enableSEC_high,
695 int *enablePRI_low,
696 int *enablePRI_high,
697 int *eeprom_present);
698 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
699 int *internal68_present,
700 int *externalcable_present,
701 int *eeprom_present);
702 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
703 int *externalcable_present,
704 int *eeprom_present);
705 static void write_brdctl(struct ahc_softc *ahc, uint8_t value);
706 static uint8_t read_brdctl(struct ahc_softc *ahc);
707 static void ahc_pci_intr(struct ahc_softc *ahc);
708 static int ahc_pci_chip_init(struct ahc_softc *ahc);
709 static int ahc_pci_suspend(struct ahc_softc *ahc);
710 static int ahc_pci_resume(struct ahc_softc *ahc);
711
712 static int
ahc_9005_subdevinfo_valid(uint16_t device,uint16_t vendor,uint16_t subdevice,uint16_t subvendor)713 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
714 uint16_t subdevice, uint16_t subvendor)
715 {
716 int result;
717
718 /* Default to invalid. */
719 result = 0;
720 if (vendor == 0x9005
721 && subvendor == 0x9005
722 && subdevice != device
723 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) {
724
725 switch (SUBID_9005_TYPE(subdevice)) {
726 case SUBID_9005_TYPE_MB:
727 break;
728 case SUBID_9005_TYPE_CARD:
729 case SUBID_9005_TYPE_LCCARD:
730 /*
731 * Currently only trust Adaptec cards to
732 * get the sub device info correct.
733 */
734 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA)
735 result = 1;
736 break;
737 case SUBID_9005_TYPE_RAID:
738 break;
739 default:
740 break;
741 }
742 }
743 return (result);
744 }
745
746 struct ahc_pci_identity *
ahc_find_pci_device(aic_dev_softc_t pci)747 ahc_find_pci_device(aic_dev_softc_t pci)
748 {
749 uint64_t full_id;
750 uint16_t device;
751 uint16_t vendor;
752 uint16_t subdevice;
753 uint16_t subvendor;
754 struct ahc_pci_identity *entry;
755 u_int i;
756
757 vendor = aic_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
758 device = aic_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
759 subvendor = aic_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
760 subdevice = aic_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
761 full_id = ahc_compose_id(device, vendor, subdevice, subvendor);
762
763 /*
764 * If the second function is not hooked up, ignore it.
765 * Unfortunately, not all MB vendors implement the
766 * subdevice ID as per the Adaptec spec, so do our best
767 * to sanity check it prior to accepting the subdevice
768 * ID as valid.
769 */
770 if (aic_get_pci_function(pci) > 0
771 && ahc_9005_subdevinfo_valid(device, vendor, subdevice, subvendor)
772 && SUBID_9005_MFUNCENB(subdevice) == 0)
773 return (NULL);
774
775 for (i = 0; i < ahc_num_pci_devs; i++) {
776 entry = &ahc_pci_ident_table[i];
777 if (entry->full_id == (full_id & entry->id_mask)) {
778 /* Honor exclusion entries. */
779 if (entry->name == NULL)
780 return (NULL);
781 return (entry);
782 }
783 }
784 return (NULL);
785 }
786
787 int
ahc_pci_config(struct ahc_softc * ahc,struct ahc_pci_identity * entry)788 ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry)
789 {
790 u_int command;
791 u_int our_id;
792 u_int sxfrctl1;
793 u_int scsiseq;
794 u_int dscommand0;
795 uint32_t devconfig;
796 int error;
797 uint8_t sblkctl;
798
799 our_id = 0;
800 error = entry->setup(ahc);
801 if (error != 0)
802 return (error);
803 ahc->chip |= AHC_PCI;
804 ahc->description = entry->name;
805
806 aic_power_state_change(ahc, AIC_POWER_STATE_D0);
807
808 error = ahc_pci_map_registers(ahc);
809 if (error != 0)
810 return (error);
811
812 /*
813 * Before we continue probing the card, ensure that
814 * its interrupts are *disabled*. We don't want
815 * a misstep to hang the machine in an interrupt
816 * storm.
817 */
818 ahc_intr_enable(ahc, FALSE);
819
820 devconfig = aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
821
822 /*
823 * If we need to support high memory, enable dual
824 * address cycles. This bit must be set to enable
825 * high address bit generation even if we are on a
826 * 64bit bus (PCI64BIT set in devconfig).
827 */
828 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
829
830 if (bootverbose)
831 printf("%s: Enabling 39Bit Addressing\n",
832 ahc_name(ahc));
833 devconfig |= DACEN;
834 }
835
836 /* Ensure that pci error generation, a test feature, is disabled. */
837 devconfig |= PCIERRGENDIS;
838
839 aic_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
840
841 /* Ensure busmastering is enabled */
842 command = aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
843 command |= PCIM_CMD_BUSMASTEREN;
844
845 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
846
847 /* On all PCI adapters, we allow SCB paging */
848 ahc->flags |= AHC_PAGESCBS;
849
850 error = ahc_softc_init(ahc);
851 if (error != 0)
852 return (error);
853
854 /*
855 * Disable PCI parity error checking. Users typically
856 * do this to work around broken PCI chipsets that get
857 * the parity timing wrong and thus generate lots of spurious
858 * errors. The chip only allows us to disable *all* parity
859 * error reporting when doing this, so CIO bus, scb ram, and
860 * scratch ram parity errors will be ignored too.
861 */
862 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0)
863 ahc->seqctl |= FAILDIS;
864
865 ahc->bus_intr = ahc_pci_intr;
866 ahc->bus_chip_init = ahc_pci_chip_init;
867 ahc->bus_suspend = ahc_pci_suspend;
868 ahc->bus_resume = ahc_pci_resume;
869
870 /* Remember how the card was setup in case there is no SEEPROM */
871 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) {
872 ahc_pause(ahc);
873 if ((ahc->features & AHC_ULTRA2) != 0)
874 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
875 else
876 our_id = ahc_inb(ahc, SCSIID) & OID;
877 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN;
878 scsiseq = ahc_inb(ahc, SCSISEQ);
879 } else {
880 sxfrctl1 = STPWEN;
881 our_id = 7;
882 scsiseq = 0;
883 }
884
885 error = ahc_reset(ahc, /*reinit*/FALSE);
886 if (error != 0)
887 return (ENXIO);
888
889 if ((ahc->features & AHC_DT) != 0) {
890 u_int sfunct;
891
892 /* Perform ALT-Mode Setup */
893 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
894 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
895 ahc_outb(ahc, OPTIONMODE,
896 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS);
897 ahc_outb(ahc, SFUNCT, sfunct);
898
899 /* Normal mode setup */
900 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN
901 |TARGCRCENDEN);
902 }
903
904 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
905 dscommand0 |= MPARCKEN|CACHETHEN;
906 if ((ahc->features & AHC_ULTRA2) != 0) {
907
908 /*
909 * DPARCKEN doesn't work correctly on
910 * some MBs so don't use it.
911 */
912 dscommand0 &= ~DPARCKEN;
913 }
914
915 /*
916 * Handle chips that must have cache line
917 * streaming (dis/en)abled.
918 */
919 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0)
920 dscommand0 |= CACHETHEN;
921
922 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0)
923 dscommand0 &= ~CACHETHEN;
924
925 ahc_outb(ahc, DSCOMMAND0, dscommand0);
926
927 ahc->pci_cachesize =
928 aic_pci_read_config(ahc->dev_softc, CSIZE_LATTIME,
929 /*bytes*/1) & CACHESIZE;
930 ahc->pci_cachesize *= 4;
931
932 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0
933 && ahc->pci_cachesize == 4) {
934
935 aic_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
936 0, /*bytes*/1);
937 ahc->pci_cachesize = 0;
938 }
939
940 /*
941 * We cannot perform ULTRA speeds without the presence
942 * of the external precision resistor.
943 */
944 if ((ahc->features & AHC_ULTRA) != 0) {
945 uint32_t devconfig;
946
947 devconfig = aic_pci_read_config(ahc->dev_softc,
948 DEVCONFIG, /*bytes*/4);
949 if ((devconfig & REXTVALID) == 0)
950 ahc->features &= ~AHC_ULTRA;
951 }
952
953 /* See if we have a SEEPROM and perform auto-term */
954 check_extport(ahc, &sxfrctl1);
955
956 /*
957 * Take the LED out of diagnostic mode
958 */
959 sblkctl = ahc_inb(ahc, SBLKCTL);
960 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
961
962 if ((ahc->features & AHC_ULTRA2) != 0) {
963 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX);
964 } else {
965 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100);
966 }
967
968 if (ahc->flags & AHC_USEDEFAULTS) {
969 /*
970 * PCI Adapter default setup
971 * Should only be used if the adapter does not have
972 * a SEEPROM.
973 */
974 /* See if someone else set us up already */
975 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0
976 && scsiseq != 0) {
977 printf("%s: Using left over BIOS settings\n",
978 ahc_name(ahc));
979 ahc->flags &= ~AHC_USEDEFAULTS;
980 ahc->flags |= AHC_BIOS_ENABLED;
981 } else {
982 /*
983 * Assume only one connector and always turn
984 * on termination.
985 */
986 our_id = 0x07;
987 sxfrctl1 = STPWEN;
988 }
989 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI);
990
991 ahc->our_id = our_id;
992 }
993
994 /*
995 * Take a look to see if we have external SRAM.
996 * We currently do not attempt to use SRAM that is
997 * shared among multiple controllers.
998 */
999 ahc_probe_ext_scbram(ahc);
1000
1001 /*
1002 * Record our termination setting for the
1003 * generic initialization routine.
1004 */
1005 if ((sxfrctl1 & STPWEN) != 0)
1006 ahc->flags |= AHC_TERM_ENB_A;
1007
1008 /*
1009 * Save chip register configuration data for chip resets
1010 * that occur during runtime and resume events.
1011 */
1012 ahc->bus_softc.pci_softc.devconfig =
1013 aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1014 ahc->bus_softc.pci_softc.command =
1015 aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1);
1016 ahc->bus_softc.pci_softc.csize_lattime =
1017 aic_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1);
1018 ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1019 ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS);
1020 if ((ahc->features & AHC_DT) != 0) {
1021 u_int sfunct;
1022
1023 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
1024 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
1025 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE);
1026 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT);
1027 ahc_outb(ahc, SFUNCT, sfunct);
1028 ahc->bus_softc.pci_softc.crccontrol1 =
1029 ahc_inb(ahc, CRCCONTROL1);
1030 }
1031 if ((ahc->features & AHC_MULTI_FUNC) != 0)
1032 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR);
1033
1034 if ((ahc->features & AHC_ULTRA2) != 0)
1035 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH);
1036
1037 /* Core initialization */
1038 error = ahc_init(ahc);
1039 if (error != 0)
1040 return (error);
1041
1042 /*
1043 * Allow interrupts now that we are completely setup.
1044 */
1045 error = ahc_pci_map_int(ahc);
1046 if (error != 0)
1047 return (error);
1048
1049 ahc_lock(ahc);
1050 /*
1051 * Link this softc in with all other ahc instances.
1052 */
1053 ahc_softc_insert(ahc);
1054 ahc_unlock(ahc);
1055 return (0);
1056 }
1057
1058 /*
1059 * Test for the presence of external sram in an
1060 * "unshared" configuration.
1061 */
1062 static int
ahc_ext_scbram_present(struct ahc_softc * ahc)1063 ahc_ext_scbram_present(struct ahc_softc *ahc)
1064 {
1065 u_int chip;
1066 int ramps;
1067 int single_user;
1068 uint32_t devconfig;
1069
1070 chip = ahc->chip & AHC_CHIPID_MASK;
1071 devconfig = aic_pci_read_config(ahc->dev_softc,
1072 DEVCONFIG, /*bytes*/4);
1073 single_user = (devconfig & MPORTMODE) != 0;
1074
1075 if ((ahc->features & AHC_ULTRA2) != 0)
1076 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0;
1077 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C)
1078 /*
1079 * External SCBRAM arbitration is flakey
1080 * on these chips. Unfortunately this means
1081 * we don't use the extra SCB ram space on the
1082 * 3940AUW.
1083 */
1084 ramps = 0;
1085 else if (chip >= AHC_AIC7870)
1086 ramps = (devconfig & RAMPSM) != 0;
1087 else
1088 ramps = 0;
1089
1090 if (ramps && single_user)
1091 return (1);
1092 return (0);
1093 }
1094
1095 /*
1096 * Enable external scbram.
1097 */
1098 static void
ahc_scbram_config(struct ahc_softc * ahc,int enable,int pcheck,int fast,int large)1099 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck,
1100 int fast, int large)
1101 {
1102 uint32_t devconfig;
1103
1104 if (ahc->features & AHC_MULTI_FUNC) {
1105 /*
1106 * Set the SCB Base addr (highest address bit)
1107 * depending on which channel we are.
1108 */
1109 ahc_outb(ahc, SCBBADDR, aic_get_pci_function(ahc->dev_softc));
1110 }
1111
1112 ahc->flags &= ~AHC_LSCBS_ENABLED;
1113 if (large)
1114 ahc->flags |= AHC_LSCBS_ENABLED;
1115 devconfig = aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1116 if ((ahc->features & AHC_ULTRA2) != 0) {
1117 u_int dscommand0;
1118
1119 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1120 if (enable)
1121 dscommand0 &= ~INTSCBRAMSEL;
1122 else
1123 dscommand0 |= INTSCBRAMSEL;
1124 if (large)
1125 dscommand0 &= ~USCBSIZE32;
1126 else
1127 dscommand0 |= USCBSIZE32;
1128 ahc_outb(ahc, DSCOMMAND0, dscommand0);
1129 } else {
1130 if (fast)
1131 devconfig &= ~EXTSCBTIME;
1132 else
1133 devconfig |= EXTSCBTIME;
1134 if (enable)
1135 devconfig &= ~SCBRAMSEL;
1136 else
1137 devconfig |= SCBRAMSEL;
1138 if (large)
1139 devconfig &= ~SCBSIZE32;
1140 else
1141 devconfig |= SCBSIZE32;
1142 }
1143 if (pcheck)
1144 devconfig |= EXTSCBPEN;
1145 else
1146 devconfig &= ~EXTSCBPEN;
1147
1148 aic_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
1149 }
1150
1151 /*
1152 * Take a look to see if we have external SRAM.
1153 * We currently do not attempt to use SRAM that is
1154 * shared among multiple controllers.
1155 */
1156 static void
ahc_probe_ext_scbram(struct ahc_softc * ahc)1157 ahc_probe_ext_scbram(struct ahc_softc *ahc)
1158 {
1159 int num_scbs;
1160 int test_num_scbs;
1161 int enable;
1162 int pcheck;
1163 int fast;
1164 int large;
1165
1166 enable = FALSE;
1167 pcheck = FALSE;
1168 fast = FALSE;
1169 large = FALSE;
1170 num_scbs = 0;
1171
1172 if (ahc_ext_scbram_present(ahc) == 0)
1173 goto done;
1174
1175 /*
1176 * Probe for the best parameters to use.
1177 */
1178 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large);
1179 num_scbs = ahc_probe_scbs(ahc);
1180 if (num_scbs == 0) {
1181 /* The SRAM wasn't really present. */
1182 goto done;
1183 }
1184 enable = TRUE;
1185
1186 /*
1187 * Clear any outstanding parity error
1188 * and ensure that parity error reporting
1189 * is enabled.
1190 */
1191 ahc_outb(ahc, SEQCTL, 0);
1192 ahc_outb(ahc, CLRINT, CLRPARERR);
1193 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1194
1195 /* Now see if we can do parity */
1196 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large);
1197 num_scbs = ahc_probe_scbs(ahc);
1198 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1199 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)
1200 pcheck = TRUE;
1201
1202 /* Clear any resulting parity error */
1203 ahc_outb(ahc, CLRINT, CLRPARERR);
1204 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1205
1206 /* Now see if we can do fast timing */
1207 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large);
1208 test_num_scbs = ahc_probe_scbs(ahc);
1209 if (test_num_scbs == num_scbs
1210 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1211 || (ahc_inb(ahc, ERROR) & MPARERR) == 0))
1212 fast = TRUE;
1213
1214 /*
1215 * See if we can use large SCBs and still maintain
1216 * the same overall count of SCBs.
1217 */
1218 if ((ahc->features & AHC_LARGE_SCBS) != 0) {
1219 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE);
1220 test_num_scbs = ahc_probe_scbs(ahc);
1221 if (test_num_scbs >= num_scbs) {
1222 large = TRUE;
1223 num_scbs = test_num_scbs;
1224 if (num_scbs >= 64) {
1225 /*
1226 * We have enough space to move the
1227 * "busy targets table" into SCB space
1228 * and make it qualify all the way to the
1229 * lun level.
1230 */
1231 ahc->flags |= AHC_SCB_BTT;
1232 }
1233 }
1234 }
1235 done:
1236 /*
1237 * Disable parity error reporting until we
1238 * can load instruction ram.
1239 */
1240 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1241 /* Clear any latched parity error */
1242 ahc_outb(ahc, CLRINT, CLRPARERR);
1243 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1244 if (bootverbose && enable) {
1245 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n",
1246 ahc_name(ahc), fast ? "fast" : "slow",
1247 pcheck ? ", parity checking enabled" : "",
1248 large ? 64 : 32);
1249 }
1250 ahc_scbram_config(ahc, enable, pcheck, fast, large);
1251 }
1252
1253 /*
1254 * Perform some simple tests that should catch situations where
1255 * our registers are invalidly mapped.
1256 */
1257 int
ahc_pci_test_register_access(struct ahc_softc * ahc)1258 ahc_pci_test_register_access(struct ahc_softc *ahc)
1259 {
1260 int error;
1261 u_int status1;
1262 uint32_t cmd;
1263 uint8_t hcntrl;
1264
1265 error = EIO;
1266
1267 /*
1268 * Enable PCI error interrupt status, but suppress NMIs
1269 * generated by SERR raised due to target aborts.
1270 */
1271 cmd = aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
1272 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
1273 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
1274
1275 /*
1276 * First a simple test to see if any
1277 * registers can be read. Reading
1278 * HCNTRL has no side effects and has
1279 * at least one bit that is guaranteed to
1280 * be zero so it is a good register to
1281 * use for this test.
1282 */
1283 hcntrl = ahc_inb(ahc, HCNTRL);
1284
1285 if (hcntrl == 0xFF)
1286 goto fail;
1287
1288 if ((hcntrl & CHIPRST) != 0) {
1289 /*
1290 * The chip has not been initialized since
1291 * PCI/EISA/VLB bus reset. Don't trust
1292 * "left over BIOS data".
1293 */
1294 ahc->flags |= AHC_NO_BIOS_INIT;
1295 }
1296
1297 /*
1298 * Next create a situation where write combining
1299 * or read prefetching could be initiated by the
1300 * CPU or host bridge. Our device does not support
1301 * either, so look for data corruption and/or flagged
1302 * PCI errors. First pause without causing another
1303 * chip reset.
1304 */
1305 hcntrl &= ~CHIPRST;
1306 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE);
1307 while (ahc_is_paused(ahc) == 0)
1308 ;
1309
1310 /* Clear any PCI errors that occurred before our driver attached. */
1311 status1 = aic_pci_read_config(ahc->dev_softc,
1312 PCIR_STATUS + 1, /*bytes*/1);
1313 aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1314 status1, /*bytes*/1);
1315 ahc_outb(ahc, CLRINT, CLRPARERR);
1316
1317 ahc_outb(ahc, SEQCTL, PERRORDIS);
1318 ahc_outb(ahc, SCBPTR, 0);
1319 ahc_outl(ahc, SCB_BASE, 0x5aa555aa);
1320 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa)
1321 goto fail;
1322
1323 status1 = aic_pci_read_config(ahc->dev_softc,
1324 PCIR_STATUS + 1, /*bytes*/1);
1325 if ((status1 & STA) != 0)
1326 goto fail;
1327
1328 error = 0;
1329
1330 fail:
1331 /* Silently clear any latched errors. */
1332 status1 = aic_pci_read_config(ahc->dev_softc,
1333 PCIR_STATUS + 1, /*bytes*/1);
1334 aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1335 status1, /*bytes*/1);
1336 ahc_outb(ahc, CLRINT, CLRPARERR);
1337 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1338 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
1339 return (error);
1340 }
1341
1342 /*
1343 * Check the external port logic for a serial eeprom
1344 * and termination/cable detection contrls.
1345 */
1346 static void
check_extport(struct ahc_softc * ahc,u_int * sxfrctl1)1347 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1)
1348 {
1349 struct seeprom_descriptor sd;
1350 struct seeprom_config *sc;
1351 int have_seeprom;
1352 int have_autoterm;
1353
1354 sd.sd_ahc = ahc;
1355 sd.sd_control_offset = SEECTL;
1356 sd.sd_status_offset = SEECTL;
1357 sd.sd_dataout_offset = SEECTL;
1358 sc = ahc->seep_config;
1359
1360 /*
1361 * For some multi-channel devices, the c46 is simply too
1362 * small to work. For the other controller types, we can
1363 * get our information from either SEEPROM type. Set the
1364 * type to start our probe with accordingly.
1365 */
1366 if (ahc->flags & AHC_LARGE_SEEPROM)
1367 sd.sd_chip = C56_66;
1368 else
1369 sd.sd_chip = C46;
1370
1371 sd.sd_MS = SEEMS;
1372 sd.sd_RDY = SEERDY;
1373 sd.sd_CS = SEECS;
1374 sd.sd_CK = SEECK;
1375 sd.sd_DO = SEEDO;
1376 sd.sd_DI = SEEDI;
1377
1378 have_seeprom = ahc_acquire_seeprom(ahc, &sd);
1379 if (have_seeprom) {
1380
1381 if (bootverbose)
1382 printf("%s: Reading SEEPROM...", ahc_name(ahc));
1383
1384 for (;;) {
1385 u_int start_addr;
1386
1387 start_addr = 32 * (ahc->channel - 'A');
1388
1389 have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc,
1390 start_addr,
1391 sizeof(*sc)/2);
1392
1393 if (have_seeprom)
1394 have_seeprom = ahc_verify_cksum(sc);
1395
1396 if (have_seeprom != 0 || sd.sd_chip == C56_66) {
1397 if (bootverbose) {
1398 if (have_seeprom == 0)
1399 printf ("checksum error\n");
1400 else
1401 printf ("done.\n");
1402 }
1403 break;
1404 }
1405 sd.sd_chip = C56_66;
1406 }
1407 ahc_release_seeprom(&sd);
1408
1409 /* Remember the SEEPROM type for later */
1410 if (sd.sd_chip == C56_66)
1411 ahc->flags |= AHC_LARGE_SEEPROM;
1412 }
1413
1414 if (!have_seeprom) {
1415 /*
1416 * Pull scratch ram settings and treat them as
1417 * if they are the contents of an seeprom if
1418 * the 'ADPT' signature is found in SCB2.
1419 * We manually compose the data as 16bit values
1420 * to avoid endian issues.
1421 */
1422 ahc_outb(ahc, SCBPTR, 2);
1423 if (ahc_inb(ahc, SCB_BASE) == 'A'
1424 && ahc_inb(ahc, SCB_BASE + 1) == 'D'
1425 && ahc_inb(ahc, SCB_BASE + 2) == 'P'
1426 && ahc_inb(ahc, SCB_BASE + 3) == 'T') {
1427 uint16_t *sc_data;
1428 int i;
1429
1430 sc_data = (uint16_t *)sc;
1431 for (i = 0; i < 32; i++, sc_data++) {
1432 int j;
1433
1434 j = i * 2;
1435 *sc_data = ahc_inb(ahc, SRAM_BASE + j)
1436 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8;
1437 }
1438 have_seeprom = ahc_verify_cksum(sc);
1439 if (have_seeprom)
1440 ahc->flags |= AHC_SCB_CONFIG_USED;
1441 }
1442 /*
1443 * Clear any SCB parity errors in case this data and
1444 * its associated parity was not initialized by the BIOS
1445 */
1446 ahc_outb(ahc, CLRINT, CLRPARERR);
1447 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1448 }
1449
1450 if (!have_seeprom) {
1451 if (bootverbose)
1452 printf("%s: No SEEPROM available.\n", ahc_name(ahc));
1453 ahc->flags |= AHC_USEDEFAULTS;
1454 free(ahc->seep_config, M_DEVBUF);
1455 ahc->seep_config = NULL;
1456 sc = NULL;
1457 } else {
1458 ahc_parse_pci_eeprom(ahc, sc);
1459 }
1460
1461 /*
1462 * Cards that have the external logic necessary to talk to
1463 * a SEEPROM, are almost certain to have the remaining logic
1464 * necessary for auto-termination control. This assumption
1465 * hasn't failed yet...
1466 */
1467 have_autoterm = have_seeprom;
1468
1469 /*
1470 * Some low-cost chips have SEEPROM and auto-term control built
1471 * in, instead of using a GAL. They can tell us directly
1472 * if the termination logic is enabled.
1473 */
1474 if ((ahc->features & AHC_SPIOCAP) != 0) {
1475 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0)
1476 have_autoterm = FALSE;
1477 }
1478
1479 if (have_autoterm) {
1480 ahc->flags |= AHC_HAS_TERM_LOGIC;
1481 ahc_acquire_seeprom(ahc, &sd);
1482 configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1);
1483 ahc_release_seeprom(&sd);
1484 } else if (have_seeprom) {
1485 *sxfrctl1 &= ~STPWEN;
1486 if ((sc->adapter_control & CFSTERM) != 0)
1487 *sxfrctl1 |= STPWEN;
1488 if (bootverbose)
1489 printf("%s: Low byte termination %sabled\n",
1490 ahc_name(ahc),
1491 (*sxfrctl1 & STPWEN) ? "en" : "dis");
1492 }
1493 }
1494
1495 static void
ahc_parse_pci_eeprom(struct ahc_softc * ahc,struct seeprom_config * sc)1496 ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc)
1497 {
1498 /*
1499 * Put the data we've collected down into SRAM
1500 * where ahc_init will find it.
1501 */
1502 int i;
1503 int max_targ = sc->max_targets & CFMAXTARG;
1504 u_int scsi_conf;
1505 uint16_t discenable;
1506 uint16_t ultraenb;
1507
1508 discenable = 0;
1509 ultraenb = 0;
1510 if ((sc->adapter_control & CFULTRAEN) != 0) {
1511 /*
1512 * Determine if this adapter has a "newstyle"
1513 * SEEPROM format.
1514 */
1515 for (i = 0; i < max_targ; i++) {
1516 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) {
1517 ahc->flags |= AHC_NEWEEPROM_FMT;
1518 break;
1519 }
1520 }
1521 }
1522
1523 for (i = 0; i < max_targ; i++) {
1524 u_int scsirate;
1525 uint16_t target_mask;
1526
1527 target_mask = 0x01 << i;
1528 if (sc->device_flags[i] & CFDISC)
1529 discenable |= target_mask;
1530 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) {
1531 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0)
1532 ultraenb |= target_mask;
1533 } else if ((sc->adapter_control & CFULTRAEN) != 0) {
1534 ultraenb |= target_mask;
1535 }
1536 if ((sc->device_flags[i] & CFXFER) == 0x04
1537 && (ultraenb & target_mask) != 0) {
1538 /* Treat 10MHz as a non-ultra speed */
1539 sc->device_flags[i] &= ~CFXFER;
1540 ultraenb &= ~target_mask;
1541 }
1542 if ((ahc->features & AHC_ULTRA2) != 0) {
1543 u_int offset;
1544
1545 if (sc->device_flags[i] & CFSYNCH)
1546 offset = MAX_OFFSET_ULTRA2;
1547 else
1548 offset = 0;
1549 ahc_outb(ahc, TARG_OFFSET + i, offset);
1550
1551 /*
1552 * The ultra enable bits contain the
1553 * high bit of the ultra2 sync rate
1554 * field.
1555 */
1556 scsirate = (sc->device_flags[i] & CFXFER)
1557 | ((ultraenb & target_mask) ? 0x8 : 0x0);
1558 if (sc->device_flags[i] & CFWIDEB)
1559 scsirate |= WIDEXFER;
1560 } else {
1561 scsirate = (sc->device_flags[i] & CFXFER) << 4;
1562 if (sc->device_flags[i] & CFSYNCH)
1563 scsirate |= SOFS;
1564 if (sc->device_flags[i] & CFWIDEB)
1565 scsirate |= WIDEXFER;
1566 }
1567 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate);
1568 }
1569 ahc->our_id = sc->brtime_id & CFSCSIID;
1570
1571 scsi_conf = (ahc->our_id & 0x7);
1572 if (sc->adapter_control & CFSPARITY)
1573 scsi_conf |= ENSPCHK;
1574 if (sc->adapter_control & CFRESETB)
1575 scsi_conf |= RESET_SCSI;
1576
1577 ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT;
1578
1579 if (sc->bios_control & CFEXTEND)
1580 ahc->flags |= AHC_EXTENDED_TRANS_A;
1581
1582 if (sc->bios_control & CFBIOSEN)
1583 ahc->flags |= AHC_BIOS_ENABLED;
1584 if (ahc->features & AHC_ULTRA
1585 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) {
1586 /* Should we enable Ultra mode? */
1587 if (!(sc->adapter_control & CFULTRAEN))
1588 /* Treat us as a non-ultra card */
1589 ultraenb = 0;
1590 }
1591
1592 if (sc->signature == CFSIGNATURE
1593 || sc->signature == CFSIGNATURE2) {
1594 uint32_t devconfig;
1595
1596 /* Honor the STPWLEVEL settings */
1597 devconfig = aic_pci_read_config(ahc->dev_softc,
1598 DEVCONFIG, /*bytes*/4);
1599 devconfig &= ~STPWLEVEL;
1600 if ((sc->bios_control & CFSTPWLEVEL) != 0)
1601 devconfig |= STPWLEVEL;
1602 aic_pci_write_config(ahc->dev_softc, DEVCONFIG,
1603 devconfig, /*bytes*/4);
1604 }
1605 /* Set SCSICONF info */
1606 ahc_outb(ahc, SCSICONF, scsi_conf);
1607 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff));
1608 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff));
1609 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff);
1610 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff);
1611 }
1612
1613 static void
configure_termination(struct ahc_softc * ahc,struct seeprom_descriptor * sd,u_int adapter_control,u_int * sxfrctl1)1614 configure_termination(struct ahc_softc *ahc,
1615 struct seeprom_descriptor *sd,
1616 u_int adapter_control,
1617 u_int *sxfrctl1)
1618 {
1619 uint8_t brddat;
1620
1621 brddat = 0;
1622
1623 /*
1624 * Update the settings in sxfrctl1 to match the
1625 * termination settings
1626 */
1627 *sxfrctl1 = 0;
1628
1629 /*
1630 * SEECS must be on for the GALS to latch
1631 * the data properly. Be sure to leave MS
1632 * on or we will release the seeprom.
1633 */
1634 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS);
1635 if ((adapter_control & CFAUTOTERM) != 0
1636 || (ahc->features & AHC_NEW_TERMCTL) != 0) {
1637 int internal50_present;
1638 int internal68_present;
1639 int externalcable_present;
1640 int eeprom_present;
1641 int enableSEC_low;
1642 int enableSEC_high;
1643 int enablePRI_low;
1644 int enablePRI_high;
1645 int sum;
1646
1647 enableSEC_low = 0;
1648 enableSEC_high = 0;
1649 enablePRI_low = 0;
1650 enablePRI_high = 0;
1651 if ((ahc->features & AHC_NEW_TERMCTL) != 0) {
1652 ahc_new_term_detect(ahc, &enableSEC_low,
1653 &enableSEC_high,
1654 &enablePRI_low,
1655 &enablePRI_high,
1656 &eeprom_present);
1657 if ((adapter_control & CFSEAUTOTERM) == 0) {
1658 if (bootverbose)
1659 printf("%s: Manual SE Termination\n",
1660 ahc_name(ahc));
1661 enableSEC_low = (adapter_control & CFSELOWTERM);
1662 enableSEC_high =
1663 (adapter_control & CFSEHIGHTERM);
1664 }
1665 if ((adapter_control & CFAUTOTERM) == 0) {
1666 if (bootverbose)
1667 printf("%s: Manual LVD Termination\n",
1668 ahc_name(ahc));
1669 enablePRI_low = (adapter_control & CFSTERM);
1670 enablePRI_high = (adapter_control & CFWSTERM);
1671 }
1672 /* Make the table calculations below happy */
1673 internal50_present = 0;
1674 internal68_present = 1;
1675 externalcable_present = 1;
1676 } else if ((ahc->features & AHC_SPIOCAP) != 0) {
1677 aic785X_cable_detect(ahc, &internal50_present,
1678 &externalcable_present,
1679 &eeprom_present);
1680 /* Can never support a wide connector. */
1681 internal68_present = 0;
1682 } else {
1683 aic787X_cable_detect(ahc, &internal50_present,
1684 &internal68_present,
1685 &externalcable_present,
1686 &eeprom_present);
1687 }
1688
1689 if ((ahc->features & AHC_WIDE) == 0)
1690 internal68_present = 0;
1691
1692 if (bootverbose
1693 && (ahc->features & AHC_ULTRA2) == 0) {
1694 printf("%s: internal 50 cable %s present",
1695 ahc_name(ahc),
1696 internal50_present ? "is":"not");
1697
1698 if ((ahc->features & AHC_WIDE) != 0)
1699 printf(", internal 68 cable %s present",
1700 internal68_present ? "is":"not");
1701 printf("\n%s: external cable %s present\n",
1702 ahc_name(ahc),
1703 externalcable_present ? "is":"not");
1704 }
1705 if (bootverbose)
1706 printf("%s: BIOS eeprom %s present\n",
1707 ahc_name(ahc), eeprom_present ? "is" : "not");
1708
1709 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) {
1710 /*
1711 * The 50 pin connector is a separate bus,
1712 * so force it to always be terminated.
1713 * In the future, perform current sensing
1714 * to determine if we are in the middle of
1715 * a properly terminated bus.
1716 */
1717 internal50_present = 0;
1718 }
1719
1720 /*
1721 * Now set the termination based on what
1722 * we found.
1723 * Flash Enable = BRDDAT7
1724 * Secondary High Term Enable = BRDDAT6
1725 * Secondary Low Term Enable = BRDDAT5 (7890)
1726 * Primary High Term Enable = BRDDAT4 (7890)
1727 */
1728 if ((ahc->features & AHC_ULTRA2) == 0
1729 && (internal50_present != 0)
1730 && (internal68_present != 0)
1731 && (externalcable_present != 0)) {
1732 printf("%s: Illegal cable configuration!!. "
1733 "Only two connectors on the "
1734 "adapter may be used at a "
1735 "time!\n", ahc_name(ahc));
1736
1737 /*
1738 * Pretend there are no cables in the hope
1739 * that having all of the termination on
1740 * gives us a more stable bus.
1741 */
1742 internal50_present = 0;
1743 internal68_present = 0;
1744 externalcable_present = 0;
1745 }
1746
1747 if ((ahc->features & AHC_WIDE) != 0
1748 && ((externalcable_present == 0)
1749 || (internal68_present == 0)
1750 || (enableSEC_high != 0))) {
1751 brddat |= BRDDAT6;
1752 if (bootverbose) {
1753 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1754 printf("%s: 68 pin termination "
1755 "Enabled\n", ahc_name(ahc));
1756 else
1757 printf("%s: %sHigh byte termination "
1758 "Enabled\n", ahc_name(ahc),
1759 enableSEC_high ? "Secondary "
1760 : "");
1761 }
1762 }
1763
1764 sum = internal50_present + internal68_present
1765 + externalcable_present;
1766 if (sum < 2 || (enableSEC_low != 0)) {
1767 if ((ahc->features & AHC_ULTRA2) != 0)
1768 brddat |= BRDDAT5;
1769 else
1770 *sxfrctl1 |= STPWEN;
1771 if (bootverbose) {
1772 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1773 printf("%s: 50 pin termination "
1774 "Enabled\n", ahc_name(ahc));
1775 else
1776 printf("%s: %sLow byte termination "
1777 "Enabled\n", ahc_name(ahc),
1778 enableSEC_low ? "Secondary "
1779 : "");
1780 }
1781 }
1782
1783 if (enablePRI_low != 0) {
1784 *sxfrctl1 |= STPWEN;
1785 if (bootverbose)
1786 printf("%s: Primary Low Byte termination "
1787 "Enabled\n", ahc_name(ahc));
1788 }
1789
1790 /*
1791 * Setup STPWEN before setting up the rest of
1792 * the termination per the tech note on the U160 cards.
1793 */
1794 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1795
1796 if (enablePRI_high != 0) {
1797 brddat |= BRDDAT4;
1798 if (bootverbose)
1799 printf("%s: Primary High Byte "
1800 "termination Enabled\n",
1801 ahc_name(ahc));
1802 }
1803
1804 write_brdctl(ahc, brddat);
1805
1806 } else {
1807 if ((adapter_control & CFSTERM) != 0) {
1808 *sxfrctl1 |= STPWEN;
1809
1810 if (bootverbose)
1811 printf("%s: %sLow byte termination Enabled\n",
1812 ahc_name(ahc),
1813 (ahc->features & AHC_ULTRA2) ? "Primary "
1814 : "");
1815 }
1816
1817 if ((adapter_control & CFWSTERM) != 0
1818 && (ahc->features & AHC_WIDE) != 0) {
1819 brddat |= BRDDAT6;
1820 if (bootverbose)
1821 printf("%s: %sHigh byte termination Enabled\n",
1822 ahc_name(ahc),
1823 (ahc->features & AHC_ULTRA2)
1824 ? "Secondary " : "");
1825 }
1826
1827 /*
1828 * Setup STPWEN before setting up the rest of
1829 * the termination per the tech note on the U160 cards.
1830 */
1831 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1832
1833 if ((ahc->features & AHC_WIDE) != 0)
1834 write_brdctl(ahc, brddat);
1835 }
1836 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */
1837 }
1838
1839 static void
ahc_new_term_detect(struct ahc_softc * ahc,int * enableSEC_low,int * enableSEC_high,int * enablePRI_low,int * enablePRI_high,int * eeprom_present)1840 ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low,
1841 int *enableSEC_high, int *enablePRI_low,
1842 int *enablePRI_high, int *eeprom_present)
1843 {
1844 uint8_t brdctl;
1845
1846 /*
1847 * BRDDAT7 = Eeprom
1848 * BRDDAT6 = Enable Secondary High Byte termination
1849 * BRDDAT5 = Enable Secondary Low Byte termination
1850 * BRDDAT4 = Enable Primary high byte termination
1851 * BRDDAT3 = Enable Primary low byte termination
1852 */
1853 brdctl = read_brdctl(ahc);
1854 *eeprom_present = brdctl & BRDDAT7;
1855 *enableSEC_high = (brdctl & BRDDAT6);
1856 *enableSEC_low = (brdctl & BRDDAT5);
1857 *enablePRI_high = (brdctl & BRDDAT4);
1858 *enablePRI_low = (brdctl & BRDDAT3);
1859 }
1860
1861 static void
aic787X_cable_detect(struct ahc_softc * ahc,int * internal50_present,int * internal68_present,int * externalcable_present,int * eeprom_present)1862 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1863 int *internal68_present, int *externalcable_present,
1864 int *eeprom_present)
1865 {
1866 uint8_t brdctl;
1867
1868 /*
1869 * First read the status of our cables.
1870 * Set the rom bank to 0 since the
1871 * bank setting serves as a multiplexor
1872 * for the cable detection logic.
1873 * BRDDAT5 controls the bank switch.
1874 */
1875 write_brdctl(ahc, 0);
1876
1877 /*
1878 * Now read the state of the internal
1879 * connectors. BRDDAT6 is INT50 and
1880 * BRDDAT7 is INT68.
1881 */
1882 brdctl = read_brdctl(ahc);
1883 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1;
1884 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1;
1885
1886 /*
1887 * Set the rom bank to 1 and determine
1888 * the other signals.
1889 */
1890 write_brdctl(ahc, BRDDAT5);
1891
1892 /*
1893 * Now read the state of the external
1894 * connectors. BRDDAT6 is EXT68 and
1895 * BRDDAT7 is EPROMPS.
1896 */
1897 brdctl = read_brdctl(ahc);
1898 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1899 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0;
1900 }
1901
1902 static void
aic785X_cable_detect(struct ahc_softc * ahc,int * internal50_present,int * externalcable_present,int * eeprom_present)1903 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1904 int *externalcable_present, int *eeprom_present)
1905 {
1906 uint8_t brdctl;
1907 uint8_t spiocap;
1908
1909 spiocap = ahc_inb(ahc, SPIOCAP);
1910 spiocap &= ~SOFTCMDEN;
1911 spiocap |= EXT_BRDCTL;
1912 ahc_outb(ahc, SPIOCAP, spiocap);
1913 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS);
1914 ahc_flush_device_writes(ahc);
1915 aic_delay(500);
1916 ahc_outb(ahc, BRDCTL, 0);
1917 ahc_flush_device_writes(ahc);
1918 aic_delay(500);
1919 brdctl = ahc_inb(ahc, BRDCTL);
1920 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1;
1921 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1922 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0;
1923 }
1924
1925 int
ahc_acquire_seeprom(struct ahc_softc * ahc,struct seeprom_descriptor * sd)1926 ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd)
1927 {
1928 int wait;
1929
1930 if ((ahc->features & AHC_SPIOCAP) != 0
1931 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0)
1932 return (0);
1933
1934 /*
1935 * Request access of the memory port. When access is
1936 * granted, SEERDY will go high. We use a 1 second
1937 * timeout which should be near 1 second more than
1938 * is needed. Reason: after the chip reset, there
1939 * should be no contention.
1940 */
1941 SEEPROM_OUTB(sd, sd->sd_MS);
1942 wait = 1000; /* 1 second timeout in msec */
1943 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) {
1944 aic_delay(1000); /* delay 1 msec */
1945 }
1946 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) {
1947 SEEPROM_OUTB(sd, 0);
1948 return (0);
1949 }
1950 return(1);
1951 }
1952
1953 void
ahc_release_seeprom(struct seeprom_descriptor * sd)1954 ahc_release_seeprom(struct seeprom_descriptor *sd)
1955 {
1956 /* Release access to the memory port and the serial EEPROM. */
1957 SEEPROM_OUTB(sd, 0);
1958 }
1959
1960 static void
write_brdctl(struct ahc_softc * ahc,uint8_t value)1961 write_brdctl(struct ahc_softc *ahc, uint8_t value)
1962 {
1963 uint8_t brdctl;
1964
1965 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1966 brdctl = BRDSTB;
1967 if (ahc->channel == 'B')
1968 brdctl |= BRDCS;
1969 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1970 brdctl = 0;
1971 } else {
1972 brdctl = BRDSTB|BRDCS;
1973 }
1974 ahc_outb(ahc, BRDCTL, brdctl);
1975 ahc_flush_device_writes(ahc);
1976 brdctl |= value;
1977 ahc_outb(ahc, BRDCTL, brdctl);
1978 ahc_flush_device_writes(ahc);
1979 if ((ahc->features & AHC_ULTRA2) != 0)
1980 brdctl |= BRDSTB_ULTRA2;
1981 else
1982 brdctl &= ~BRDSTB;
1983 ahc_outb(ahc, BRDCTL, brdctl);
1984 ahc_flush_device_writes(ahc);
1985 if ((ahc->features & AHC_ULTRA2) != 0)
1986 brdctl = 0;
1987 else
1988 brdctl &= ~BRDCS;
1989 ahc_outb(ahc, BRDCTL, brdctl);
1990 }
1991
1992 static uint8_t
read_brdctl(struct ahc_softc * ahc)1993 read_brdctl(struct ahc_softc *ahc)
1994 {
1995 uint8_t brdctl;
1996 uint8_t value;
1997
1998 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1999 brdctl = BRDRW;
2000 if (ahc->channel == 'B')
2001 brdctl |= BRDCS;
2002 } else if ((ahc->features & AHC_ULTRA2) != 0) {
2003 brdctl = BRDRW_ULTRA2;
2004 } else {
2005 brdctl = BRDRW|BRDCS;
2006 }
2007 ahc_outb(ahc, BRDCTL, brdctl);
2008 ahc_flush_device_writes(ahc);
2009 value = ahc_inb(ahc, BRDCTL);
2010 ahc_outb(ahc, BRDCTL, 0);
2011 return (value);
2012 }
2013
2014 static void
ahc_pci_intr(struct ahc_softc * ahc)2015 ahc_pci_intr(struct ahc_softc *ahc)
2016 {
2017 u_int error;
2018 u_int status1;
2019
2020 error = ahc_inb(ahc, ERROR);
2021 if ((error & PCIERRSTAT) == 0)
2022 return;
2023
2024 status1 = aic_pci_read_config(ahc->dev_softc,
2025 PCIR_STATUS + 1, /*bytes*/1);
2026
2027 if ((status1 & ~DPE) != 0
2028 || (ahc->flags & AHC_DISABLE_PCI_PERR) == 0) {
2029 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n",
2030 ahc_name(ahc),
2031 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
2032 }
2033
2034 if (status1 & DPE
2035 && (ahc->flags & AHC_DISABLE_PCI_PERR) == 0) {
2036 ahc->pci_target_perr_count++;
2037 printf("%s: Data Parity Error Detected during address "
2038 "or write data phase\n", ahc_name(ahc));
2039 }
2040 if (status1 & SSE) {
2041 printf("%s: Signal System Error Detected\n", ahc_name(ahc));
2042 }
2043 if (status1 & RMA) {
2044 printf("%s: Received a Master Abort\n", ahc_name(ahc));
2045 }
2046 if (status1 & RTA) {
2047 printf("%s: Received a Target Abort\n", ahc_name(ahc));
2048 }
2049 if (status1 & STA) {
2050 printf("%s: Signaled a Target Abort\n", ahc_name(ahc));
2051 }
2052 if (status1 & DPR) {
2053 printf("%s: Data Parity Error has been reported via PERR#\n",
2054 ahc_name(ahc));
2055 }
2056
2057 /* Clear latched errors. */
2058 aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
2059 status1, /*bytes*/1);
2060
2061 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) {
2062 printf("%s: Latched PCIERR interrupt with "
2063 "no status bits set\n", ahc_name(ahc));
2064 } else {
2065 ahc_outb(ahc, CLRINT, CLRPARERR);
2066 }
2067
2068 if (ahc->pci_target_perr_count > AHC_PCI_TARGET_PERR_THRESH
2069 && (ahc->flags & AHC_DISABLE_PCI_PERR) == 0) {
2070 printf(
2071 "%s: WARNING WARNING WARNING WARNING\n"
2072 "%s: Too many PCI parity errors observed as a target.\n"
2073 "%s: Some device on this PCI bus is generating bad parity.\n"
2074 "%s: This is an error *observed by*, not *generated by*, %s.\n"
2075 "%s: PCI parity error checking has been disabled.\n"
2076 "%s: WARNING WARNING WARNING WARNING\n",
2077 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc),
2078 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc),
2079 ahc_name(ahc));
2080 ahc->seqctl |= FAILDIS;
2081 ahc->flags |= AHC_DISABLE_PCI_PERR;
2082 ahc_outb(ahc, SEQCTL, ahc->seqctl);
2083 }
2084 ahc_unpause(ahc);
2085 }
2086
2087 static int
ahc_pci_chip_init(struct ahc_softc * ahc)2088 ahc_pci_chip_init(struct ahc_softc *ahc)
2089 {
2090 ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0);
2091 ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus);
2092 if ((ahc->features & AHC_DT) != 0) {
2093 u_int sfunct;
2094
2095 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
2096 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
2097 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode);
2098 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt);
2099 ahc_outb(ahc, SFUNCT, sfunct);
2100 ahc_outb(ahc, CRCCONTROL1,
2101 ahc->bus_softc.pci_softc.crccontrol1);
2102 }
2103 if ((ahc->features & AHC_MULTI_FUNC) != 0)
2104 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr);
2105
2106 if ((ahc->features & AHC_ULTRA2) != 0)
2107 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh);
2108
2109 return (ahc_chip_init(ahc));
2110 }
2111
2112 static int
ahc_pci_suspend(struct ahc_softc * ahc)2113 ahc_pci_suspend(struct ahc_softc *ahc)
2114 {
2115 return (ahc_suspend(ahc));
2116 }
2117
2118 static int
ahc_pci_resume(struct ahc_softc * ahc)2119 ahc_pci_resume(struct ahc_softc *ahc)
2120 {
2121
2122 aic_power_state_change(ahc, AIC_POWER_STATE_D0);
2123
2124 /*
2125 * We assume that the OS has restored our register
2126 * mappings, etc. Just update the config space registers
2127 * that the OS doesn't know about and rely on our chip
2128 * reset handler to handle the rest.
2129 */
2130 aic_pci_write_config(ahc->dev_softc, DEVCONFIG,
2131 ahc->bus_softc.pci_softc.devconfig, /*bytes*/4);
2132 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
2133 ahc->bus_softc.pci_softc.command, /*bytes*/1);
2134 aic_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
2135 ahc->bus_softc.pci_softc.csize_lattime,
2136 /*bytes*/1);
2137 if ((ahc->flags & AHC_HAS_TERM_LOGIC) != 0) {
2138 struct seeprom_descriptor sd;
2139 u_int sxfrctl1;
2140
2141 sd.sd_ahc = ahc;
2142 sd.sd_control_offset = SEECTL;
2143 sd.sd_status_offset = SEECTL;
2144 sd.sd_dataout_offset = SEECTL;
2145
2146 ahc_acquire_seeprom(ahc, &sd);
2147 configure_termination(ahc, &sd,
2148 ahc->seep_config->adapter_control,
2149 &sxfrctl1);
2150 ahc_release_seeprom(&sd);
2151 }
2152 return (ahc_resume(ahc));
2153 }
2154
2155 static int
ahc_aic785X_setup(struct ahc_softc * ahc)2156 ahc_aic785X_setup(struct ahc_softc *ahc)
2157 {
2158 aic_dev_softc_t pci;
2159 uint8_t rev;
2160
2161 pci = ahc->dev_softc;
2162 ahc->channel = 'A';
2163 ahc->chip = AHC_AIC7850;
2164 ahc->features = AHC_AIC7850_FE;
2165 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2166 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2167 if (rev >= 1)
2168 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2169 ahc->instruction_ram_size = 512;
2170 return (0);
2171 }
2172
2173 static int
ahc_aic7860_setup(struct ahc_softc * ahc)2174 ahc_aic7860_setup(struct ahc_softc *ahc)
2175 {
2176 aic_dev_softc_t pci;
2177 uint8_t rev;
2178
2179 pci = ahc->dev_softc;
2180 ahc->channel = 'A';
2181 ahc->chip = AHC_AIC7860;
2182 ahc->features = AHC_AIC7860_FE;
2183 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2184 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2185 if (rev >= 1)
2186 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2187 ahc->instruction_ram_size = 512;
2188 return (0);
2189 }
2190
2191 static int
ahc_apa1480_setup(struct ahc_softc * ahc)2192 ahc_apa1480_setup(struct ahc_softc *ahc)
2193 {
2194 int error;
2195
2196 error = ahc_aic7860_setup(ahc);
2197 if (error != 0)
2198 return (error);
2199 ahc->features |= AHC_REMOVABLE;
2200 return (0);
2201 }
2202
2203 static int
ahc_aic7870_setup(struct ahc_softc * ahc)2204 ahc_aic7870_setup(struct ahc_softc *ahc)
2205 {
2206
2207 ahc->channel = 'A';
2208 ahc->chip = AHC_AIC7870;
2209 ahc->features = AHC_AIC7870_FE;
2210 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2211 ahc->instruction_ram_size = 512;
2212 return (0);
2213 }
2214
2215 static int
ahc_aha394X_setup(struct ahc_softc * ahc)2216 ahc_aha394X_setup(struct ahc_softc *ahc)
2217 {
2218 int error;
2219
2220 error = ahc_aic7870_setup(ahc);
2221 if (error == 0)
2222 error = ahc_aha394XX_setup(ahc);
2223 return (error);
2224 }
2225
2226 static int
ahc_aha398X_setup(struct ahc_softc * ahc)2227 ahc_aha398X_setup(struct ahc_softc *ahc)
2228 {
2229 int error;
2230
2231 error = ahc_aic7870_setup(ahc);
2232 if (error == 0)
2233 error = ahc_aha398XX_setup(ahc);
2234 return (error);
2235 }
2236
2237 static int
ahc_aha494X_setup(struct ahc_softc * ahc)2238 ahc_aha494X_setup(struct ahc_softc *ahc)
2239 {
2240 int error;
2241
2242 error = ahc_aic7870_setup(ahc);
2243 if (error == 0)
2244 error = ahc_aha494XX_setup(ahc);
2245 return (error);
2246 }
2247
2248 static int
ahc_aic7880_setup(struct ahc_softc * ahc)2249 ahc_aic7880_setup(struct ahc_softc *ahc)
2250 {
2251 aic_dev_softc_t pci;
2252 uint8_t rev;
2253
2254 pci = ahc->dev_softc;
2255 ahc->channel = 'A';
2256 ahc->chip = AHC_AIC7880;
2257 ahc->features = AHC_AIC7880_FE;
2258 ahc->bugs |= AHC_TMODE_WIDEODD_BUG;
2259 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2260 if (rev >= 1) {
2261 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2262 } else {
2263 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2264 }
2265 ahc->instruction_ram_size = 512;
2266 return (0);
2267 }
2268
2269 static int
ahc_aha2940Pro_setup(struct ahc_softc * ahc)2270 ahc_aha2940Pro_setup(struct ahc_softc *ahc)
2271 {
2272
2273 ahc->flags |= AHC_INT50_SPEEDFLEX;
2274 return (ahc_aic7880_setup(ahc));
2275 }
2276
2277 static int
ahc_aha394XU_setup(struct ahc_softc * ahc)2278 ahc_aha394XU_setup(struct ahc_softc *ahc)
2279 {
2280 int error;
2281
2282 error = ahc_aic7880_setup(ahc);
2283 if (error == 0)
2284 error = ahc_aha394XX_setup(ahc);
2285 return (error);
2286 }
2287
2288 static int
ahc_aha398XU_setup(struct ahc_softc * ahc)2289 ahc_aha398XU_setup(struct ahc_softc *ahc)
2290 {
2291 int error;
2292
2293 error = ahc_aic7880_setup(ahc);
2294 if (error == 0)
2295 error = ahc_aha398XX_setup(ahc);
2296 return (error);
2297 }
2298
2299 static int
ahc_aic7890_setup(struct ahc_softc * ahc)2300 ahc_aic7890_setup(struct ahc_softc *ahc)
2301 {
2302 aic_dev_softc_t pci;
2303 uint8_t rev;
2304
2305 pci = ahc->dev_softc;
2306 ahc->channel = 'A';
2307 ahc->chip = AHC_AIC7890;
2308 ahc->features = AHC_AIC7890_FE;
2309 ahc->flags |= AHC_NEWEEPROM_FMT;
2310 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2311 if (rev == 0)
2312 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG;
2313 ahc->instruction_ram_size = 768;
2314 return (0);
2315 }
2316
2317 static int
ahc_aic7892_setup(struct ahc_softc * ahc)2318 ahc_aic7892_setup(struct ahc_softc *ahc)
2319 {
2320
2321 ahc->channel = 'A';
2322 ahc->chip = AHC_AIC7892;
2323 ahc->features = AHC_AIC7892_FE;
2324 ahc->flags |= AHC_NEWEEPROM_FMT;
2325 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2326 ahc->instruction_ram_size = 1024;
2327 return (0);
2328 }
2329
2330 static int
ahc_aic7895_setup(struct ahc_softc * ahc)2331 ahc_aic7895_setup(struct ahc_softc *ahc)
2332 {
2333 aic_dev_softc_t pci;
2334 uint8_t rev;
2335
2336 pci = ahc->dev_softc;
2337 ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A';
2338 /*
2339 * The 'C' revision of the aic7895 has a few additional features.
2340 */
2341 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2342 if (rev >= 4) {
2343 ahc->chip = AHC_AIC7895C;
2344 ahc->features = AHC_AIC7895C_FE;
2345 } else {
2346 u_int command;
2347
2348 ahc->chip = AHC_AIC7895;
2349 ahc->features = AHC_AIC7895_FE;
2350
2351 /*
2352 * The BIOS disables the use of MWI transactions
2353 * since it does not have the MWI bug work around
2354 * we have. Disabling MWI reduces performance, so
2355 * turn it on again.
2356 */
2357 command = aic_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1);
2358 command |= PCIM_CMD_MWRICEN;
2359 aic_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1);
2360 ahc->bugs |= AHC_PCI_MWI_BUG;
2361 }
2362 /*
2363 * XXX Does CACHETHEN really not work??? What about PCI retry?
2364 * on C level chips. Need to test, but for now, play it safe.
2365 */
2366 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG
2367 | AHC_CACHETHEN_BUG;
2368
2369 #if 0
2370 uint32_t devconfig;
2371
2372 /*
2373 * Cachesize must also be zero due to stray DAC
2374 * problem when sitting behind some bridges.
2375 */
2376 aic_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1);
2377 devconfig = aic_pci_read_config(pci, DEVCONFIG, /*bytes*/1);
2378 devconfig |= MRDCEN;
2379 aic_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1);
2380 #endif
2381 ahc->flags |= AHC_NEWEEPROM_FMT;
2382 ahc->instruction_ram_size = 512;
2383 return (0);
2384 }
2385
2386 static int
ahc_aic7896_setup(struct ahc_softc * ahc)2387 ahc_aic7896_setup(struct ahc_softc *ahc)
2388 {
2389 aic_dev_softc_t pci;
2390
2391 pci = ahc->dev_softc;
2392 ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A';
2393 ahc->chip = AHC_AIC7896;
2394 ahc->features = AHC_AIC7896_FE;
2395 ahc->flags |= AHC_NEWEEPROM_FMT;
2396 ahc->bugs |= AHC_CACHETHEN_DIS_BUG;
2397 ahc->instruction_ram_size = 768;
2398 return (0);
2399 }
2400
2401 static int
ahc_aic7899_setup(struct ahc_softc * ahc)2402 ahc_aic7899_setup(struct ahc_softc *ahc)
2403 {
2404 aic_dev_softc_t pci;
2405
2406 pci = ahc->dev_softc;
2407 ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A';
2408 ahc->chip = AHC_AIC7899;
2409 ahc->features = AHC_AIC7899_FE;
2410 ahc->flags |= AHC_NEWEEPROM_FMT;
2411 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2412 ahc->instruction_ram_size = 1024;
2413 return (0);
2414 }
2415
2416 static int
ahc_aha29160C_setup(struct ahc_softc * ahc)2417 ahc_aha29160C_setup(struct ahc_softc *ahc)
2418 {
2419 int error;
2420
2421 error = ahc_aic7899_setup(ahc);
2422 if (error != 0)
2423 return (error);
2424 ahc->features |= AHC_REMOVABLE;
2425 return (0);
2426 }
2427
2428 static int
ahc_raid_setup(struct ahc_softc * ahc)2429 ahc_raid_setup(struct ahc_softc *ahc)
2430 {
2431 printf("RAID functionality unsupported\n");
2432 return (ENXIO);
2433 }
2434
2435 static int
ahc_aha394XX_setup(struct ahc_softc * ahc)2436 ahc_aha394XX_setup(struct ahc_softc *ahc)
2437 {
2438 aic_dev_softc_t pci;
2439
2440 pci = ahc->dev_softc;
2441 switch (aic_get_pci_slot(pci)) {
2442 case AHC_394X_SLOT_CHANNEL_A:
2443 ahc->channel = 'A';
2444 break;
2445 case AHC_394X_SLOT_CHANNEL_B:
2446 ahc->channel = 'B';
2447 break;
2448 default:
2449 printf("adapter at unexpected slot %d\n"
2450 "unable to map to a channel\n",
2451 aic_get_pci_slot(pci));
2452 ahc->channel = 'A';
2453 }
2454 return (0);
2455 }
2456
2457 static int
ahc_aha398XX_setup(struct ahc_softc * ahc)2458 ahc_aha398XX_setup(struct ahc_softc *ahc)
2459 {
2460 aic_dev_softc_t pci;
2461
2462 pci = ahc->dev_softc;
2463 switch (aic_get_pci_slot(pci)) {
2464 case AHC_398X_SLOT_CHANNEL_A:
2465 ahc->channel = 'A';
2466 break;
2467 case AHC_398X_SLOT_CHANNEL_B:
2468 ahc->channel = 'B';
2469 break;
2470 case AHC_398X_SLOT_CHANNEL_C:
2471 ahc->channel = 'C';
2472 break;
2473 default:
2474 printf("adapter at unexpected slot %d\n"
2475 "unable to map to a channel\n",
2476 aic_get_pci_slot(pci));
2477 ahc->channel = 'A';
2478 break;
2479 }
2480 ahc->flags |= AHC_LARGE_SEEPROM;
2481 return (0);
2482 }
2483
2484 static int
ahc_aha494XX_setup(struct ahc_softc * ahc)2485 ahc_aha494XX_setup(struct ahc_softc *ahc)
2486 {
2487 aic_dev_softc_t pci;
2488
2489 pci = ahc->dev_softc;
2490 switch (aic_get_pci_slot(pci)) {
2491 case AHC_494X_SLOT_CHANNEL_A:
2492 ahc->channel = 'A';
2493 break;
2494 case AHC_494X_SLOT_CHANNEL_B:
2495 ahc->channel = 'B';
2496 break;
2497 case AHC_494X_SLOT_CHANNEL_C:
2498 ahc->channel = 'C';
2499 break;
2500 case AHC_494X_SLOT_CHANNEL_D:
2501 ahc->channel = 'D';
2502 break;
2503 default:
2504 printf("adapter at unexpected slot %d\n"
2505 "unable to map to a channel\n",
2506 aic_get_pci_slot(pci));
2507 ahc->channel = 'A';
2508 }
2509 ahc->flags |= AHC_LARGE_SEEPROM;
2510 return (0);
2511 }
2512