1 /* 2 * $OpenBSD: aic7xxx.h,v 1.11 2004/04/12 22:12:32 jmc Exp $ 3 * Core definitions and data structures shareable across OS platforms. 4 * 5 * Copyright (c) 1994-2001 Justin T. Gibbs. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * Alternatively, this software may be distributed under the terms of the 18 * GNU Public License ("GPL"). 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * $Id: aic7xxx.h,v 1.11 2004/04/12 22:12:32 jmc Exp $ 33 * 34 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.h,v 1.40 2001/07/18 21:39:47 gibbs Exp $ 35 */ 36 37 #ifndef _AIC7XXX_H_ 38 #define _AIC7XXX_H_ 39 40 /* Register Definitions */ 41 #include "dev/microcode/aic7xxx/aic7xxx_reg.h" 42 43 #include "dev/ic/aic7xxx_cam.h" 44 45 /************************* Forward Declarations *******************************/ 46 struct ahc_platform_data; 47 struct scb_platform_data; 48 struct seeprom_descriptor; 49 50 /****************************** Useful Macros *********************************/ 51 #ifndef MAX 52 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 53 #endif 54 55 #ifndef MIN 56 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 57 #endif 58 59 #ifndef TRUE 60 #define TRUE 1 61 #endif 62 #ifndef FALSE 63 #define FALSE 0 64 #endif 65 66 #define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 67 68 #define ALL_CHANNELS '\0' 69 #define ALL_TARGETS_MASK 0xFFFF 70 #define INITIATOR_WILDCARD (~0) 71 72 #define SCSIID_TARGET(ahc, scsiid) \ 73 (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \ 74 >> TID_SHIFT) 75 #define SCSIID_OUR_ID(scsiid) \ 76 ((scsiid) & OID) 77 #define SCSIID_CHANNEL(ahc, scsiid) \ 78 ((((ahc)->features & AHC_TWIN) != 0) \ 79 ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \ 80 : 'A') 81 #define SCB_IS_SCSIBUS_B(ahc, scb) \ 82 (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B') 83 #define SCB_GET_OUR_ID(scb) \ 84 SCSIID_OUR_ID((scb)->hscb->scsiid) 85 #define SCB_GET_TARGET(ahc, scb) \ 86 SCSIID_TARGET((ahc), (scb)->hscb->scsiid) 87 #define SCB_GET_CHANNEL(ahc, scb) \ 88 SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) 89 #define SCB_GET_LUN(scb) \ 90 ((scb)->hscb->lun) 91 #define SCB_GET_TARGET_OFFSET(ahc, scb) \ 92 (SCB_GET_TARGET(ahc, scb) + (SCB_IS_SCSIBUS_B(ahc, scb) ? 8 : 0)) 93 #define SCB_GET_TARGET_MASK(ahc, scb) \ 94 (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb))) 95 #ifdef AHC_DEBUG 96 #define SCB_IS_SILENT(scb) \ 97 ((ahc_debug & AHC_SHOW_MASKED_ERRORS) == 0 \ 98 && (((scb)->flags & SCB_SILENT) != 0)) 99 #else 100 #define SCB_IS_SILENT(scb) \ 101 (((scb)->flags & SCB_SILENT) != 0) 102 #endif 103 #define TCL_TARGET_OFFSET(tcl) \ 104 ((((tcl) >> 4) & TID) >> 4) 105 #define TCL_LUN(tcl) \ 106 (tcl & (AHC_NUM_LUNS - 1)) 107 #define BUILD_TCL(scsiid, lun) \ 108 ((lun) | (((scsiid) & TID) << 4)) 109 110 #ifndef AHC_TARGET_MODE 111 #undef AHC_TMODE_ENABLE 112 #define AHC_TMODE_ENABLE 0 113 #endif 114 115 /**************************** Driver Constants ********************************/ 116 /* 117 * The maximum number of supported targets. 118 */ 119 #define AHC_NUM_TARGETS 16 120 121 /* 122 * The maximum number of supported luns. 123 * The identify message only supports 64 luns in SPI3. 124 * You can have 2^64 luns when information unit transfers are enabled, 125 * but it is doubtful this driver will ever support IUTs. 126 */ 127 #define AHC_NUM_LUNS 64 128 129 /* 130 * The maximum transfer per S/G segment. 131 */ 132 #define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 133 134 /* 135 * The maximum amount of SCB storage in hardware on a controller. 136 * This value represents an upper bound. Controllers vary in the number 137 * they actually support. 138 */ 139 #define AHC_SCB_MAX 255 140 141 /* 142 * The maximum number of concurrent transactions supported per driver instance. 143 * Sequencer Control Blocks (SCBs) store per-transaction information. Although 144 * the space for SCBs on the host adapter varies by model, the driver will 145 * page the SCBs between host and controller memory as needed. We are limited 146 * to 253 because: 147 * 1) The 8bit nature of the RISC engine holds us to an 8bit value. 148 * 2) We reserve one value, 255, to represent the invalid element. 149 * 3) Our input queue scheme requires one SCB to always be reserved 150 * in advance of queuing any SCBs. This takes us down to 254. 151 * 4) To handle our output queue correctly on machines that only 152 * support 32bit stores, we must clear the array 4 bytes at a 153 * time. To avoid colliding with a DMA write from the sequencer, 154 * we must be sure that 4 slots are empty when we write to clear 155 * the queue. This reduces us to 253 SCBs: 1 that just completed 156 * and the known three additional empty slots in the queue that 157 * precede it. 158 */ 159 #define AHC_MAX_QUEUE 253 160 161 /* 162 * Ring Buffer of incoming target commands. 163 * We allocate 256 to simplify the logic in the sequencer 164 * by using the natural wrap point of an 8bit counter. 165 */ 166 #define AHC_TMODE_CMDS 256 167 168 /* Reset line assertion time in us */ 169 #define AHC_BUSRESET_DELAY 250 170 171 /******************* Chip Characteristics/Operating Settings *****************/ 172 /* 173 * Chip Type 174 * The chip order is from least sophisticated to most sophisticated. 175 */ 176 typedef enum { 177 AHC_NONE = 0x0000, 178 AHC_CHIPID_MASK = 0x00FF, 179 AHC_AIC7770 = 0x0001, 180 AHC_AIC7850 = 0x0002, 181 AHC_AIC7855 = 0x0003, 182 AHC_AIC7859 = 0x0004, 183 AHC_AIC7860 = 0x0005, 184 AHC_AIC7870 = 0x0006, 185 AHC_AIC7880 = 0x0007, 186 AHC_AIC7895 = 0x0008, 187 AHC_AIC7895C = 0x0009, 188 AHC_AIC7890 = 0x000a, 189 AHC_AIC7896 = 0x000b, 190 AHC_AIC7892 = 0x000c, 191 AHC_AIC7899 = 0x000d, 192 AHC_VL = 0x0100, /* Bus type VL */ 193 AHC_EISA = 0x0200, /* Bus type EISA */ 194 AHC_PCI = 0x0400, /* Bus type PCI */ 195 AHC_BUS_MASK = 0x0F00 196 } ahc_chip; 197 198 /* 199 * Features available in each chip type. 200 */ 201 typedef enum { 202 AHC_FENONE = 0x00000, 203 AHC_ULTRA = 0x00001, /* Supports 20MHz Transfers */ 204 AHC_ULTRA2 = 0x00002, /* Supports 40MHz Transfers */ 205 AHC_WIDE = 0x00004, /* Wide Channel */ 206 AHC_TWIN = 0x00008, /* Twin Channel */ 207 AHC_MORE_SRAM = 0x00010, /* 80 bytes instead of 64 */ 208 AHC_CMD_CHAN = 0x00020, /* Has a Command DMA Channel */ 209 AHC_QUEUE_REGS = 0x00040, /* Has Queue management registers */ 210 AHC_SG_PRELOAD = 0x00080, /* Can perform auto-SG preload */ 211 AHC_SPIOCAP = 0x00100, /* Has a Serial Port I/O Cap Register */ 212 AHC_MULTI_TID = 0x00200, /* Has bitmask of TIDs for select-in */ 213 AHC_HS_MAILBOX = 0x00400, /* Has HS_MAILBOX register */ 214 AHC_DT = 0x00800, /* Double Transition transfers */ 215 AHC_NEW_TERMCTL = 0x01000, /* Newer termination scheme */ 216 AHC_MULTI_FUNC = 0x02000, /* Multi-Function Twin Channel Device */ 217 AHC_LARGE_SCBS = 0x04000, /* 64byte SCBs */ 218 AHC_AUTORATE = 0x08000, /* Automatic update of SCSIRATE/OFFSET*/ 219 AHC_AUTOPAUSE = 0x10000, /* Automatic pause on register access */ 220 AHC_TARGETMODE = 0x20000, /* Has tested target mode support */ 221 AHC_MULTIROLE = 0x40000, /* Space for two roles at a time */ 222 AHC_REMOVABLE = 0x80000, /* Hot-Swap supported */ 223 AHC_AIC7770_FE = AHC_FENONE, 224 /* 225 * The real 7850 does not support Ultra modes, but there are 226 * several cards that use the generic 7850 PCI ID even though 227 * they are using an Ultra capable chip (7859/7860). We start 228 * out with the AHC_ULTRA feature set and then check the DEVSTATUS 229 * register to determine if the capability is really present. 230 */ 231 AHC_AIC7850_FE = AHC_SPIOCAP|AHC_AUTOPAUSE|AHC_TARGETMODE|AHC_ULTRA, 232 AHC_AIC7860_FE = AHC_AIC7850_FE, 233 AHC_AIC7870_FE = AHC_TARGETMODE|AHC_AUTOPAUSE, 234 AHC_AIC7880_FE = AHC_AIC7870_FE|AHC_ULTRA, 235 /* 236 * Although we have space for both the initiator and 237 * target roles on ULTRA2 chips, we currently disable 238 * the initiator role to allow multi-scsi-id target mode 239 * configurations. We can only respond on the same SCSI 240 * ID as our initiator role if we allow initiator operation. 241 * At some point, we should add a configuration knob to 242 * allow both roles to be loaded. 243 */ 244 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2 245 |AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID 246 |AHC_HS_MAILBOX|AHC_NEW_TERMCTL|AHC_LARGE_SCBS 247 |AHC_TARGETMODE, 248 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE, 249 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM|AHC_AUTOPAUSE 250 |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS, 251 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID, 252 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC, 253 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC 254 } ahc_feature; 255 256 /* 257 * Bugs in the silicon that we work around in software. 258 */ 259 typedef enum { 260 AHC_BUGNONE = 0x00, 261 /* 262 * On all chips prior to the U2 product line, 263 * the WIDEODD S/G segment feature does not 264 * work during scsi->HostBus transfers. 265 */ 266 AHC_TMODE_WIDEODD_BUG = 0x01, 267 /* 268 * On the aic7890/91 Rev 0 chips, the autoflush 269 * feature does not work. A manual flush of 270 * the DMA FIFO is required. 271 */ 272 AHC_AUTOFLUSH_BUG = 0x02, 273 /* 274 * On many chips, cacheline streaming does not work. 275 */ 276 AHC_CACHETHEN_BUG = 0x04, 277 /* 278 * On the aic7896/97 chips, cacheline 279 * streaming must be enabled. 280 */ 281 AHC_CACHETHEN_DIS_BUG = 0x08, 282 /* 283 * PCI 2.1 Retry failure on non-empty data fifo. 284 */ 285 AHC_PCI_2_1_RETRY_BUG = 0x10, 286 /* 287 * Controller does not handle cacheline residuals 288 * properly on S/G segments if PCI MWI instructions 289 * are allowed. 290 */ 291 AHC_PCI_MWI_BUG = 0x20, 292 /* 293 * An SCB upload using the SCB channel's 294 * auto array entry copy feature may 295 * corrupt data. This appears to only 296 * occur on 66MHz systems. 297 */ 298 AHC_SCBCHAN_UPLOAD_BUG = 0x40 299 } ahc_bug; 300 301 /* 302 * Configuration specific settings. 303 * The driver determines these settings by probing the 304 * chip/controller's configuration. 305 */ 306 typedef enum { 307 AHC_FNONE = 0x000, 308 AHC_PRIMARY_CHANNEL = 0x003,/* 309 * The channel that should 310 * be probed first. 311 */ 312 AHC_USEDEFAULTS = 0x004,/* 313 * For cards without an seeprom 314 * or a BIOS to initialize the chip's 315 * SRAM, we use the default target 316 * settings. 317 */ 318 AHC_SEQUENCER_DEBUG = 0x008, 319 AHC_SHARED_SRAM = 0x010, 320 AHC_LARGE_SEEPROM = 0x020,/* Uses C56_66 not C46 */ 321 AHC_RESET_BUS_A = 0x040, 322 AHC_RESET_BUS_B = 0x080, 323 AHC_EXTENDED_TRANS_A = 0x100, 324 AHC_EXTENDED_TRANS_B = 0x200, 325 AHC_TERM_ENB_A = 0x400, 326 AHC_TERM_ENB_B = 0x800, 327 AHC_INITIATORROLE = 0x1000,/* 328 * Allow initiator operations on 329 * this controller. 330 */ 331 AHC_TARGETROLE = 0x2000,/* 332 * Allow target operations on this 333 * controller. 334 */ 335 AHC_NEWEEPROM_FMT = 0x4000, 336 AHC_RESOURCE_SHORTAGE = 0x8000, 337 AHC_TQINFIFO_BLOCKED = 0x10000,/* Blocked waiting for ATIOs */ 338 AHC_INT50_SPEEDFLEX = 0x20000,/* 339 * Internal 50pin connector 340 * sits behind an aic3860 341 */ 342 AHC_SCB_BTT = 0x40000,/* 343 * The busy targets table is 344 * stored in SCB space rather 345 * than SRAM. 346 */ 347 AHC_BIOS_ENABLED = 0x80000, 348 AHC_ALL_INTERRUPTS = 0x100000, 349 AHC_PAGESCBS = 0x400000, /* Enable SCB paging */ 350 AHC_EDGE_INTERRUPT = 0x800000, /* Device uses edge triggered ints */ 351 AHC_39BIT_ADDRESSING = 0x1000000, /* Use 39 bit addressing scheme. */ 352 AHC_LSCBS_ENABLED = 0x2000000, /* 64Byte SCBs enabled */ 353 AHC_SCB_CONFIG_USED = 0x4000000, /* No SEEPROM but SCB2 had info. */ 354 AHC_NO_BIOS_INIT = 0x8000000, /* No BIOS left over settings. */ 355 AHC_DISABLE_PCI_PERR = 0x10000000 356 } ahc_flag; 357 358 /************************* Hardware SCB Definition ***************************/ 359 360 /* 361 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 362 * consists of a "hardware SCB" mirroring the fields available on the card 363 * and additional information the kernel stores for each transaction. 364 * 365 * To minimize space utilization, a portion of the hardware scb stores 366 * different data during different portions of a SCSI transaction. 367 * As initialized by the host driver for the initiator role, this area 368 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 369 * the cdb has been presented to the target, this area serves to store 370 * residual transfer information and the SCSI status byte. 371 * For the target role, the contents of this area do not change, but 372 * still serve a different purpose than for the initiator role. See 373 * struct target_data for details. 374 */ 375 376 /* 377 * Status information embedded in the shared portion of 378 * an SCB after passing the cdb to the target. The kernel 379 * driver will only read this data for transactions that 380 * complete abnormally (non-zero status byte). 381 */ 382 struct status_pkt { 383 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 384 uint32_t residual_sg_ptr; /* The next S/G for this transfer */ 385 uint8_t scsi_status; /* Standard SCSI status byte */ 386 }; 387 388 /* 389 * Target mode version of the shared data SCB segment. 390 */ 391 struct target_data { 392 uint8_t target_phases; /* Bitmap of phases to execute */ 393 uint8_t data_phase; /* Data-In or Data-Out */ 394 uint8_t scsi_status; /* SCSI status to give to initiator */ 395 uint8_t initiator_tag; /* Initiator's transaction tag */ 396 }; 397 398 struct hardware_scb { 399 /*0*/ union { 400 /* 401 * If the cdb is 12 bytes or less, we embed it directly 402 * in the SCB. For longer cdbs, we embed the address 403 * of the cdb payload as seen by the chip and a DMA 404 * is used to pull it in. 405 */ 406 uint8_t cdb[12]; 407 uint32_t cdb_ptr; 408 struct status_pkt status; 409 struct target_data tdata; 410 } shared_data; 411 /* 412 * A word about residuals. 413 * The scb is presented to the sequencer with the dataptr and datacnt 414 * fields initialized to the contents of the first S/G element to 415 * transfer. The sgptr field is initialized to the bus address for 416 * the S/G element that follows the first in the in core S/G array 417 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 418 * S/G entry for this transfer (single S/G element transfer with the 419 * first elements address and length preloaded in the dataptr/datacnt 420 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 421 * The SG_FULL_RESID flag ensures that the residual will be correctly 422 * noted even if no data transfers occur. Once the data phase is entered, 423 * the residual sgptr and datacnt are loaded from the sgptr and the 424 * datacnt fields. After each S/G element's dataptr and length are 425 * loaded into the hardware, the residual sgptr is advanced. After 426 * each S/G element is expired, its datacnt field is checked to see 427 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 428 * residual sg ptr and the transfer is considered complete. If the 429 * sequencer determines that there is a residual in the transfer, it 430 * will set the SG_RESID_VALID flag in sgptr and dma the scb back into 431 * host memory. To summarize: 432 * 433 * Sequencer: 434 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 435 * or residual_sgptr does not have SG_LIST_NULL set. 436 * 437 * o We are transfering the last segment if residual_datacnt has 438 * the SG_LAST_SEG flag set. 439 * 440 * Host: 441 * o A residual has occurred if a completed scb has the 442 * SG_RESID_VALID flag set. 443 * 444 * o residual_sgptr and sgptr refer to the "next" sg entry 445 * and so may point beyond the last valid sg entry for the 446 * transfer. 447 */ 448 /*12*/ uint32_t dataptr; 449 /*16*/ uint32_t datacnt; /* 450 * Byte 3 (numbered from 0) of 451 * the datacnt is really the 452 * 4th byte in that data address. 453 */ 454 /*20*/ uint32_t sgptr; 455 #define SG_PTR_MASK 0xFFFFFFF8 456 /*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */ 457 /*25*/ uint8_t scsiid; /* what to load in the SCSIID register */ 458 /*26*/ uint8_t lun; 459 /*27*/ uint8_t tag; /* 460 * Index into our kernel SCB array. 461 * Also used as the tag for tagged I/O 462 */ 463 /*28*/ uint8_t cdb_len; 464 /*29*/ uint8_t scsirate; /* Value for SCSIRATE register */ 465 /*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */ 466 /*31*/ uint8_t next; /* 467 * Used for threading SCBs in the 468 * "Waiting for Selection" and 469 * "Disconnected SCB" lists down 470 * in the sequencer. 471 */ 472 /*32*/ uint8_t cdb32[32]; /* 473 * CDB storage for cdbs of size 474 * 13->32. We store them here 475 * because hardware scbs are 476 * allocated from DMA safe 477 * memory so we are guaranteed 478 * the controller can access 479 * this data. 480 */ 481 }; 482 483 /************************ Kernel SCB Definitions ******************************/ 484 /* 485 * Some fields of the SCB are OS dependent. Here we collect the 486 * definitions for elements that all OS platforms need to include 487 * in there SCB definition. 488 */ 489 490 /* 491 * Definition of a scatter/gather element as transferred to the controller. 492 * The aic7xxx chips only support a 24bit length. We use the top byte of 493 * the length to store additional address bits and a flag to indicate 494 * that a given segment terminates the transfer. This gives us an 495 * addressable range of 512GB on machines with 64bit PCI or with chips 496 * that can support dual address cycles on 32bit PCI busses. 497 */ 498 struct ahc_dma_seg { 499 uint32_t addr; 500 uint32_t len; 501 #define AHC_DMA_LAST_SEG 0x80000000 502 #define AHC_SG_HIGH_ADDR_MASK 0x7F000000 503 #define AHC_SG_LEN_MASK 0x00FFFFFF 504 }; 505 506 struct sg_map_node { 507 bus_dmamap_t sg_dmamap; 508 bus_addr_t sg_physaddr; 509 struct ahc_dma_seg* sg_vaddr; 510 SLIST_ENTRY(sg_map_node) links; 511 #ifdef __OpenBSD__ 512 bus_dma_segment_t sg_dmasegs; 513 int sg_nseg; 514 #endif 515 }; 516 517 struct ahc_pci_busdata { 518 pci_chipset_tag_t pc; 519 pcitag_t tag; 520 u_int dev; 521 u_int func; 522 pcireg_t class; 523 }; 524 525 /* 526 * The current state of this SCB. 527 */ 528 typedef enum { 529 SCB_FREE = 0x0000, 530 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 531 * Another device was active 532 * during the first timeout for 533 * this SCB so we gave ourselves 534 * an additional timeout period 535 * in case it was hogging the 536 * bus. 537 */ 538 SCB_DEVICE_RESET = 0x0004, 539 SCB_SENSE = 0x0008, 540 SCB_CDB32_PTR = 0x0010, 541 SCB_RECOVERY_SCB = 0x0020, 542 SCB_AUTO_NEGOTIATE = 0x0040,/* Negotiate to achieve goal. */ 543 SCB_NEGOTIATE = 0x0080,/* Negotiation forced for command. */ 544 SCB_ABORT = 0x1000, 545 SCB_UNTAGGEDQ = 0x2000, 546 SCB_ACTIVE = 0x4000, 547 SCB_TARGET_IMMEDIATE = 0x8000, 548 SCB_TRANSMISSION_ERROR = 0x1000,/* 549 * We detected a parity or CRC 550 * error that has effected the 551 * payload of the command. This 552 * flag is checked when normal 553 * status is returned to catch 554 * the case of a target not 555 * responding to our attempt 556 * to report the error. 557 */ 558 SCB_TARGET_SCB = 0x2000, 559 SCB_SILENT = 0x4000 /* 560 * Be quiet about transmission type 561 * errors. They are expected and we 562 * don't want to upset the user. This 563 * flag is typically used during DV. 564 */ 565 } scb_flag; 566 567 struct scb { 568 struct hardware_scb *hscb; 569 union { 570 SLIST_ENTRY(scb) sle; 571 TAILQ_ENTRY(scb) tqe; 572 } links; 573 LIST_ENTRY(scb) pending_links; 574 ahc_io_ctx_t io_ctx; 575 struct ahc_softc *ahc_softc; 576 scb_flag flags; 577 #ifndef __linux__ 578 bus_dmamap_t dmamap; 579 #endif 580 struct scb_platform_data *platform_data; 581 struct sg_map_node *sg_map; 582 struct ahc_dma_seg *sg_list; 583 bus_addr_t sg_list_phys; 584 u_int sg_count;/* How full ahc_dma_seg is */ 585 }; 586 587 struct scb_data { 588 SLIST_HEAD(, scb) free_scbs; /* 589 * Pool of SCBs ready to be assigned 590 * commands to execute. 591 */ 592 struct scb *scbindex[AHC_SCB_MAX + 1];/* Mapping from tag to SCB */ 593 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 594 struct scb *scbarray; /* Array of kernel SCBs */ 595 struct scsi_sense_data *sense; /* Per SCB sense data */ 596 597 /* 598 * "Bus" addresses of our data structures. 599 */ 600 bus_dmamap_t hscb_dmamap; 601 bus_addr_t hscb_busaddr; 602 #ifdef __OpenBSD__ 603 bus_dma_segment_t hscb_seg; 604 int hscb_nseg; 605 int hscb_size; 606 #endif 607 bus_dma_tag_t sense_dmat; 608 bus_dmamap_t sense_dmamap; 609 bus_addr_t sense_busaddr; 610 #ifdef __OpenBSD__ 611 bus_dma_segment_t sense_seg; 612 int sense_nseg; 613 int sense_size; 614 #endif 615 SLIST_HEAD(, sg_map_node) sg_maps; 616 uint8_t numscbs; 617 uint8_t maxhscbs; /* Number of SCBs on the card */ 618 uint8_t init_level; /* 619 * How far we've initialized 620 * this structure. 621 */ 622 }; 623 624 /************************ Target Mode Definitions *****************************/ 625 626 /* 627 * Connection desciptor for select-in requests in target mode. 628 */ 629 struct target_cmd { 630 uint8_t scsiid; /* Our ID and the initiator's ID */ 631 uint8_t identify; /* Identify message */ 632 uint8_t bytes[22]; /* 633 * Bytes contains any additional message 634 * bytes terminated by 0xFF. The remainder 635 * is the cdb to execute. 636 */ 637 uint8_t cmd_valid; /* 638 * When a command is complete, the firmware 639 * will set cmd_valid to all bits set. 640 * After the host has seen the command, 641 * the bits are cleared. This allows us 642 * to just peek at host memory to determine 643 * if more work is complete. cmd_valid is on 644 * an 8 byte boundary to simplify setting 645 * it on aic7880 hardware which only has 646 * limited direct access to the DMA FIFO. 647 */ 648 uint8_t pad[7]; 649 }; 650 651 /* 652 * Number of events we can buffer up if we run out 653 * of immediate notify ccbs. 654 */ 655 #define AHC_TMODE_EVENT_BUFFER_SIZE 8 656 struct ahc_tmode_event { 657 uint8_t initiator_id; 658 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 659 #define EVENT_TYPE_BUS_RESET 0xFF 660 uint8_t event_arg; 661 }; 662 663 /* 664 * Per enabled lun target mode state. 665 * As this state is directly influenced by the host OS'es target mode 666 * environment, we let the OS module define it. Forward declare the 667 * structure here so we can store arrays of them, etc. in OS neutral 668 * data structures. 669 */ 670 #ifdef AHC_TARGET_MODE 671 struct ahc_tmode_lstate { 672 struct cam_path *path; 673 struct ccb_hdr_slist accept_tios; 674 struct ccb_hdr_slist immed_notifies; 675 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE]; 676 uint8_t event_r_idx; 677 uint8_t event_w_idx; 678 }; 679 #else 680 struct ahc_tmode_lstate; 681 #endif 682 683 /******************** Transfer Negotiation Datastructures *********************/ 684 #define AHC_TRANS_CUR 0x01 /* Modify current negotiation status */ 685 #define AHC_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 686 #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 687 #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 688 689 /* 690 * Transfer Negotiation Information. 691 */ 692 struct ahc_transinfo { 693 uint8_t protocol_version; /* SCSI Revision level */ 694 uint8_t transport_version; /* SPI Revision level */ 695 uint8_t width; /* Bus width */ 696 uint8_t period; /* Sync rate factor */ 697 uint8_t offset; /* Sync offset */ 698 uint8_t ppr_options; /* Parallel Protocol Request options */ 699 }; 700 701 /* 702 * Per-initiator current, goal and user transfer negotiation information. */ 703 struct ahc_initiator_tinfo { 704 uint8_t scsirate; /* Computed value for SCSIRATE reg */ 705 struct ahc_transinfo curr; 706 struct ahc_transinfo goal; 707 struct ahc_transinfo user; 708 }; 709 710 /* 711 * Per enabled target ID state. 712 * Pointers to lun target state as well as sync/wide negotiation information 713 * for each initiator<->target mapping. For the initiator role we pretend 714 * that we are the target and the targets are the initiators since the 715 * negotiation is the same regardless of role. 716 */ 717 struct ahc_tmode_tstate { 718 struct ahc_tmode_lstate* enabled_luns[AHC_NUM_LUNS]; 719 struct ahc_initiator_tinfo transinfo[AHC_NUM_TARGETS]; 720 721 /* 722 * Per initiator state bitmasks. 723 */ 724 uint16_t auto_negotiate;/* Auto Negotiation Required */ 725 uint16_t ultraenb; /* Using ultra sync rate */ 726 uint16_t discenable; /* Disconnection allowed */ 727 uint16_t tagenable; /* Tagged Queuing allowed */ 728 }; 729 730 /* 731 * Data structure for our table of allowed synchronous transfer rates. 732 */ 733 struct ahc_syncrate { 734 u_int sxfr_u2; /* Value of the SXFR parameter for Ultra2+ Chips */ 735 u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */ 736 #define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */ 737 #define ST_SXFR 0x010 /* Rate Single Transition Only */ 738 #define DT_SXFR 0x040 /* Rate Double Transition Only */ 739 uint8_t period; /* Period to send to SCSI target */ 740 char *rate; 741 }; 742 743 /* 744 * The synchronous transfer rate table. 745 */ 746 extern struct ahc_syncrate ahc_syncrates[]; 747 748 /* Safe and valid period for async negotiations. */ 749 #define AHC_ASYNC_XFER_PERIOD 0x45 750 #define AHC_ULTRA2_XFER_PERIOD 0x0a 751 752 /* 753 * Indexes into our table of synchronous transfer rates. 754 */ 755 #define AHC_SYNCRATE_DT 0 756 #define AHC_SYNCRATE_ULTRA2 1 757 #define AHC_SYNCRATE_ULTRA 3 758 #define AHC_SYNCRATE_FAST 6 759 760 /***************************** Lookup Tables **********************************/ 761 /* 762 * Phase -> name and message out response 763 * to parity errors in each phase table. 764 */ 765 struct ahc_phase_table_entry { 766 uint8_t phase; 767 uint8_t mesg_out; /* Message response to parity errors */ 768 char *phasemsg; 769 }; 770 771 /************************** Serial EEPROM Format ******************************/ 772 773 struct seeprom_config { 774 /* 775 * Per SCSI ID Configuration Flags 776 */ 777 uint16_t device_flags[16]; /* words 0-15 */ 778 #define CFXFER 0x0007 /* synchronous transfer rate */ 779 #define CFSYNCH 0x0008 /* enable synchronous transfer */ 780 #define CFDISC 0x0010 /* enable disconnection */ 781 #define CFWIDEB 0x0020 /* wide bus device */ 782 #define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 783 #define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */ 784 #define CFSTART 0x0100 /* send start unit SCSI command */ 785 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 786 #define CFRNFOUND 0x0400 /* report even if not found */ 787 #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 788 #define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */ 789 #define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */ 790 791 /* 792 * BIOS Control Bits 793 */ 794 uint16_t bios_control; /* word 16 */ 795 #define CFSUPREM 0x0001 /* support all removable drives */ 796 #define CFSUPREMB 0x0002 /* support removable boot drives */ 797 #define CFBIOSEN 0x0004 /* BIOS enabled */ 798 #define CFBIOS_BUSSCAN 0x0008 /* Have the BIOS Scan the Bus */ 799 #define CFSM2DRV 0x0010 /* support more than two drives */ 800 #define CFSTPWLEVEL 0x0010 /* Termination level control */ 801 #define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 802 #define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 803 #define CFTERM_MENU 0x0040 /* BIOS displays termination menu */ 804 #define CFEXTEND 0x0080 /* extended translation enabled */ 805 #define CFSCAMEN 0x0100 /* SCAM enable */ 806 #define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 807 #define CFMSG_VERBOSE 0x0000 808 #define CFMSG_SILENT 0x0200 809 #define CFMSG_DIAG 0x0400 810 #define CFBOOTCD 0x0800 /* Support Bootable CD-ROM */ 811 /* UNUSED 0xff00 */ 812 813 /* 814 * Host Adapter Control Bits 815 */ 816 uint16_t adapter_control; /* word 17 */ 817 #define CFAUTOTERM 0x0001 /* Perform Auto termination */ 818 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 819 #define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 820 #define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 821 #define CFSTERM 0x0004 /* SCSI low byte termination */ 822 #define CFWSTERM 0x0008 /* SCSI high byte termination */ 823 #define CFSPARITY 0x0010 /* SCSI parity */ 824 #define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 825 #define CFMULTILUN 0x0020 826 #define CFRESETB 0x0040 /* reset SCSI bus at boot */ 827 #define CFCLUSTERENB 0x0080 /* Cluster Enable */ 828 #define CFBOOTCHAN 0x0300 /* probe this channel first */ 829 #define CFBOOTCHANSHIFT 8 830 #define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/ 831 #define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */ 832 #define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */ 833 #define CFDOMAINVAL 0x4000 /* Perform Domain Validation*/ 834 835 /* 836 * Bus Release Time, Host Adapter ID 837 */ 838 uint16_t brtime_id; /* word 18 */ 839 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 840 /* UNUSED 0x00f0 */ 841 #define CFBRTIME 0xff00 /* bus release time */ 842 843 /* 844 * Maximum targets 845 */ 846 uint16_t max_targets; /* word 19 */ 847 #define CFMAXTARG 0x00ff /* maximum targets */ 848 #define CFBOOTLUN 0x0f00 /* Lun to boot from */ 849 #define CFBOOTID 0xf000 /* Target to boot from */ 850 uint16_t res_1[10]; /* words 20-29 */ 851 uint16_t signature; /* Signature == 0x250 */ 852 #define CFSIGNATURE 0x250 853 #define CFSIGNATURE2 0x300 854 uint16_t checksum; /* word 31 */ 855 }; 856 857 /**************************** Message Buffer *********************************/ 858 typedef enum { 859 MSG_TYPE_NONE = 0x00, 860 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 861 MSG_TYPE_INITIATOR_MSGIN = 0x02, 862 MSG_TYPE_TARGET_MSGOUT = 0x03, 863 MSG_TYPE_TARGET_MSGIN = 0x04 864 } ahc_msg_type; 865 866 typedef enum { 867 MSGLOOP_IN_PROG, 868 MSGLOOP_MSGCOMPLETE, 869 MSGLOOP_TERMINATED 870 } msg_loop_stat; 871 872 /*********************** Software Configuration Structure *********************/ 873 TAILQ_HEAD(scb_tailq, scb); 874 875 struct ahc_suspend_channel_state { 876 uint8_t scsiseq; 877 uint8_t sxfrctl0; 878 uint8_t sxfrctl1; 879 uint8_t simode0; 880 uint8_t simode1; 881 uint8_t seltimer; 882 uint8_t seqctl; 883 }; 884 885 struct ahc_suspend_state { 886 struct ahc_suspend_channel_state channel[2]; 887 uint8_t optionmode; 888 uint8_t dscommand0; 889 uint8_t dspcistatus; 890 /* hsmailbox */ 891 uint8_t crccontrol1; 892 uint8_t scbbaddr; 893 /* Host and sequencer SCB counts */ 894 uint8_t dff_thrsh; 895 uint8_t *scratch_ram; 896 uint8_t *btt; 897 }; 898 899 typedef void (*ahc_bus_intr_t)(struct ahc_softc *); 900 901 struct ahc_softc { 902 #ifdef __OpenBSD__ 903 struct device sc_dev; 904 #endif 905 bus_space_tag_t tag; 906 bus_space_handle_t bsh; 907 #ifndef __linux__ 908 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 909 #endif 910 struct scb_data *scb_data; 911 912 struct scb *next_queued_scb; 913 914 /* 915 * SCBs that have been sent to the controller 916 */ 917 LIST_HEAD(, scb) pending_scbs; 918 919 /* 920 * Counting lock for deferring the release of additional 921 * untagged transactions from the untagged_queues. When 922 * the lock is decremented to 0, all queues in the 923 * untagged_queues array are run. 924 */ 925 u_int untagged_queue_lock; 926 927 /* 928 * Per-target queue of untagged-transactions. The 929 * transaction at the head of the queue is the 930 * currently pending untagged transaction for the 931 * target. The driver only allows a single untagged 932 * transaction per target. 933 */ 934 struct scb_tailq untagged_queues[AHC_NUM_TARGETS]; 935 936 /* 937 * Platform specific data. 938 */ 939 struct ahc_platform_data *platform_data; 940 941 /* 942 * Platform specific device information. 943 */ 944 ahc_dev_softc_t dev_softc; 945 946 /* 947 * Bus specific device information. 948 */ 949 ahc_bus_intr_t bus_intr; 950 951 /* 952 * Target mode related state kept on a per enabled lun basis. 953 * Targets that are not enabled will have null entries. 954 * As an initiator, we keep one target entry for our initiator 955 * ID to store our sync/wide transfer settings. 956 */ 957 struct ahc_tmode_tstate *enabled_targets[AHC_NUM_TARGETS]; 958 959 /* 960 * The black hole device responsible for handling requests for 961 * disabled luns on enabled targets. 962 */ 963 struct ahc_tmode_lstate *black_hole; 964 965 /* 966 * Device instance currently on the bus awaiting a continue TIO 967 * for a command that was not given the disconnect privilege. 968 */ 969 struct ahc_tmode_lstate *pending_device; 970 971 /* 972 * Card characteristics 973 */ 974 ahc_chip chip; 975 ahc_feature features; 976 ahc_bug bugs; 977 ahc_flag flags; 978 979 struct seeprom_config *seep_config; 980 981 /* Values to store in the SEQCTL register for pause and unpause */ 982 uint8_t unpause; 983 uint8_t pause; 984 985 /* Command Queues */ 986 uint8_t qoutfifonext; 987 uint8_t qinfifonext; 988 uint8_t *qoutfifo; 989 uint8_t *qinfifo; 990 991 /* Critical Section Data */ 992 struct cs *critical_sections; 993 u_int num_critical_sections; 994 995 /* Links for chaining softcs */ 996 TAILQ_ENTRY(ahc_softc) links; 997 998 /* Channel Names ('A', 'B', etc.) */ 999 char channel; 1000 char channel_b; 1001 1002 /* Initiator Bus ID */ 1003 uint8_t our_id; 1004 uint8_t our_id_b; 1005 1006 /* 1007 * PCI error detection. 1008 */ 1009 int unsolicited_ints; 1010 1011 /* 1012 * Target incoming command FIFO. 1013 */ 1014 struct target_cmd *targetcmds; 1015 uint8_t tqinfifonext; 1016 1017 /* 1018 * Incoming and outgoing message handling. 1019 */ 1020 uint8_t send_msg_perror; 1021 ahc_msg_type msg_type; 1022 uint8_t msgout_buf[12];/* Message we are sending */ 1023 uint8_t msgin_buf[12];/* Message we are receiving */ 1024 u_int msgout_len; /* Length of message to send */ 1025 u_int msgout_index; /* Current index in msgout */ 1026 u_int msgin_index; /* Current index in msgin */ 1027 1028 /* 1029 * Mapping information for data structures shared 1030 * between the sequencer and kernel. 1031 */ 1032 bus_dma_tag_t parent_dmat; 1033 bus_dmamap_t shared_data_dmamap; 1034 bus_addr_t shared_data_busaddr; 1035 1036 /* 1037 * Bus address of the one byte buffer used to 1038 * work-around a DMA bug for chips <= aic7880 1039 * in target mode. 1040 */ 1041 bus_addr_t dma_bug_buf; 1042 1043 /* Information saved through suspend/resume cycles */ 1044 struct ahc_suspend_state suspend_state; 1045 1046 /* Number of enabled target mode device on this card */ 1047 u_int enabled_luns; 1048 1049 /* Initialization level of this data structure */ 1050 u_int init_level; 1051 1052 /* PCI cacheline size. */ 1053 u_int pci_cachesize; 1054 1055 /* Per-Unit descriptive information */ 1056 const char *description; 1057 char *name; 1058 int unit; 1059 1060 /* Selection Timer settings */ 1061 int seltime; 1062 int seltime_b; 1063 1064 uint16_t user_discenable;/* Disconnection allowed */ 1065 uint16_t user_tagenable;/* Tagged Queuing allowed */ 1066 1067 struct ahc_pci_busdata *bd; 1068 }; 1069 1070 TAILQ_HEAD(ahc_softc_tailq, ahc_softc); 1071 extern struct ahc_softc_tailq ahc_tailq; 1072 1073 /************************ Active Device Information ***************************/ 1074 typedef enum { 1075 ROLE_UNKNOWN, 1076 ROLE_INITIATOR, 1077 ROLE_TARGET 1078 } role_t; 1079 1080 struct ahc_devinfo { 1081 int our_scsiid; 1082 int target_offset; 1083 uint16_t target_mask; 1084 u_int target; 1085 u_int lun; 1086 char channel; 1087 role_t role; /* 1088 * Only guaranteed to be correct if not 1089 * in the busfree state. 1090 */ 1091 }; 1092 1093 /****************************** PCI Structures ********************************/ 1094 typedef int (ahc_device_setup_t)(struct ahc_softc *); 1095 1096 struct ahc_pci_identity { 1097 uint64_t full_id; 1098 uint64_t id_mask; 1099 char *name; 1100 ahc_device_setup_t *setup; 1101 }; 1102 extern struct ahc_pci_identity ahc_pci_ident_table []; 1103 extern const u_int ahc_num_pci_devs; 1104 1105 /***************************** VL/EISA Declarations ***************************/ 1106 struct aic7770_identity { 1107 uint32_t full_id; 1108 uint32_t id_mask; 1109 char *name; 1110 ahc_device_setup_t *setup; 1111 }; 1112 extern struct aic7770_identity aic7770_ident_table []; 1113 extern const int ahc_num_aic7770_devs; 1114 1115 #define AHC_EISA_SLOT_OFFSET 0xc00 1116 #define AHC_EISA_IOSIZE 0x100 1117 1118 /*************************** Function Declarations ****************************/ 1119 /******************************************************************************/ 1120 u_int ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl); 1121 void ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl); 1122 void ahc_busy_tcl(struct ahc_softc *ahc, 1123 u_int tcl, u_int busyid); 1124 1125 /***************************** PCI Front End *********************************/ 1126 const struct ahc_pci_identity *ahc_find_pci_device(pcireg_t, pcireg_t, u_int); 1127 int ahc_pci_config(struct ahc_softc *, 1128 struct ahc_pci_identity *); 1129 1130 /*************************** EISA/VL Front End ********************************/ 1131 struct aic7770_identity *aic7770_find_device(uint32_t); 1132 int aic7770_config(struct ahc_softc *ahc, 1133 struct aic7770_identity *); 1134 1135 /************************** SCB and SCB queue management **********************/ 1136 int ahc_probe_scbs(struct ahc_softc *); 1137 void ahc_run_untagged_queues(struct ahc_softc *ahc); 1138 void ahc_run_untagged_queue(struct ahc_softc *ahc, 1139 struct scb_tailq *queue); 1140 void ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, 1141 struct scb *scb); 1142 int ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, 1143 int target, char channel, int lun, 1144 u_int tag, role_t role); 1145 1146 /****************************** Initialization ********************************/ 1147 struct ahc_softc *ahc_alloc(void *platform_arg, char *name); 1148 int ahc_softc_init(struct ahc_softc *); 1149 void ahc_controller_info(struct ahc_softc *ahc, char *buf, 1150 size_t buf_len); 1151 int ahc_init(struct ahc_softc *ahc); 1152 void ahc_intr_enable(struct ahc_softc *ahc, int enable); 1153 void ahc_pause_and_flushwork(struct ahc_softc *ahc); 1154 int ahc_suspend(struct ahc_softc *ahc); 1155 int ahc_resume(struct ahc_softc *ahc); 1156 void ahc_softc_insert(struct ahc_softc *); 1157 struct ahc_softc *ahc_find_softc(struct ahc_softc *); 1158 void ahc_set_unit(struct ahc_softc *, int); 1159 void ahc_set_name(struct ahc_softc *, char *); 1160 void ahc_alloc_scbs(struct ahc_softc *ahc); 1161 void ahc_free(struct ahc_softc *ahc); 1162 int ahc_reset(struct ahc_softc *ahc); 1163 void ahc_shutdown(void *arg); 1164 1165 /*************************** Interrupt Services *******************************/ 1166 void ahc_pci_intr(struct ahc_softc *ahc); 1167 void ahc_clear_intstat(struct ahc_softc *ahc); 1168 void ahc_run_qoutfifo(struct ahc_softc *ahc); 1169 #ifdef AHC_TARGET_MODE 1170 void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused); 1171 #endif 1172 void ahc_handle_brkadrint(struct ahc_softc *ahc); 1173 void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat); 1174 void ahc_handle_scsiint(struct ahc_softc *ahc, 1175 u_int intstat); 1176 void ahc_clear_critical_section(struct ahc_softc *ahc); 1177 1178 /***************************** Error Recovery *********************************/ 1179 typedef enum { 1180 SEARCH_COMPLETE, 1181 SEARCH_COUNT, 1182 SEARCH_REMOVE 1183 } ahc_search_action; 1184 int ahc_search_qinfifo(struct ahc_softc *ahc, int target, 1185 char channel, int lun, u_int tag, 1186 role_t role, uint32_t status, 1187 ahc_search_action action); 1188 int ahc_search_untagged_queues(struct ahc_softc *, 1189 struct scsi_xfer *, int, char, int, uint32_t, 1190 ahc_search_action); 1191 int ahc_search_disc_list(struct ahc_softc *ahc, int target, 1192 char channel, int lun, u_int tag, 1193 int stop_on_first, int remove, 1194 int save_state); 1195 void ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb); 1196 int ahc_reset_channel(struct ahc_softc *ahc, char channel, 1197 int initiate_reset); 1198 void ahc_restart(struct ahc_softc *ahc); 1199 void ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb); 1200 /*************************** Utility Functions ********************************/ 1201 struct ahc_phase_table_entry* 1202 ahc_lookup_phase_entry(int phase); 1203 void ahc_compile_devinfo(struct ahc_devinfo *devinfo, 1204 u_int our_id, u_int target, 1205 u_int lun, char channel, 1206 role_t role); 1207 /************************** Transfer Negotiation ******************************/ 1208 struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1209 u_int *ppr_options, u_int maxsync); 1210 u_int ahc_find_period(struct ahc_softc *ahc, 1211 u_int scsirate, u_int maxsync); 1212 void ahc_validate_offset(struct ahc_softc *ahc, 1213 struct ahc_initiator_tinfo *tinfo, 1214 struct ahc_syncrate *syncrate, 1215 u_int *offset, int wide, 1216 role_t role); 1217 void ahc_validate_width(struct ahc_softc *ahc, 1218 struct ahc_initiator_tinfo *tinfo, 1219 u_int *bus_width, 1220 role_t role); 1221 int ahc_update_neg_request(struct ahc_softc*, 1222 struct ahc_devinfo*, 1223 struct ahc_tmode_tstate*, 1224 struct ahc_initiator_tinfo*, 1225 int /*force*/); 1226 void ahc_set_width(struct ahc_softc *ahc, 1227 struct ahc_devinfo *devinfo, 1228 u_int width, u_int type, int paused); 1229 void ahc_set_syncrate(struct ahc_softc *ahc, 1230 struct ahc_devinfo *devinfo, 1231 struct ahc_syncrate *syncrate, 1232 u_int period, u_int offset, 1233 u_int ppr_options, 1234 u_int type, int paused); 1235 typedef enum { 1236 AHC_QUEUE_NONE, 1237 AHC_QUEUE_BASIC, 1238 AHC_QUEUE_TAGGED 1239 } ahc_queue_alg; 1240 1241 void ahc_set_tags(struct ahc_softc *ahc, 1242 struct ahc_devinfo *devinfo, 1243 ahc_queue_alg alg); 1244 1245 /**************************** Target Mode *************************************/ 1246 #ifdef AHC_TARGET_MODE 1247 void ahc_send_lstate_events(struct ahc_softc *, 1248 struct ahc_tmode_lstate *); 1249 void ahc_handle_en_lun(struct ahc_softc *ahc, 1250 struct cam_sim *sim, union ccb *ccb); 1251 cam_status ahc_find_tmode_devs(struct ahc_softc *ahc, 1252 struct cam_sim *sim, union ccb *ccb, 1253 struct ahc_tmode_tstate **tstate, 1254 struct ahc_tmode_lstate **lstate, 1255 int notfound_failure); 1256 #ifndef AHC_TMODE_ENABLE 1257 #define AHC_TMODE_ENABLE 0 1258 #endif 1259 #endif 1260 /******************************* Debug ***************************************/ 1261 void ahc_print_devinfo(struct ahc_softc *, 1262 struct ahc_devinfo *); 1263 void ahc_print_scb(struct scb *scb); 1264 void ahc_dump_card_state(struct ahc_softc *ahc); 1265 int ahc_print_register(ahc_reg_parse_entry_t *, u_int, 1266 const char *, u_int, u_int, u_int *, u_int); 1267 /******************************* SEEPROM *************************************/ 1268 int ahc_acquire_seeprom(struct ahc_softc *, 1269 struct seeprom_descriptor *); 1270 void ahc_release_seeprom(struct seeprom_descriptor *); 1271 1272 void ahc_check_extport(struct ahc_softc *, u_int *); 1273 #endif /* _AIC7XXX_H_ */ 1274