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/freebsd-head/sys/dev/ath/
HDif_ath_rx.h39 #define ath_stoprecv(_sc, _dodelay) \ argument
41 #define ath_startrecv(_sc) \ argument
43 #define ath_rx_flush(_sc) \ argument
45 #define ath_rxbuf_init(_sc, _bf) \ argument
47 #define ath_rxdma_setup(_sc) \ argument
49 #define ath_rxdma_teardown(_sc) \ argument
HDif_ath_tx.h154 #define ath_txdma_setup(_sc) \ argument
156 #define ath_txdma_teardown(_sc) \ argument
158 #define ath_txq_restart_dma(_sc, _txq) \ argument
160 #define ath_tx_handoff(_sc, _txq, _bf) \ argument
162 #define ath_draintxq(_sc, _rtype) \ argument
/freebsd-head/sys/dev/bhnd/cores/pmu/
HDbhnd_pmu_private.h34 #define BHND_PMU_READ_4(_sc, _reg) (_sc)->io->rd4((_reg), (_sc)->io_ctx) argument
35 #define BHND_PMU_WRITE_4(_sc, _reg, _val) \ argument
38 #define BHND_PMU_AND_4(_sc, _reg, _val) \ argument
41 #define BHND_PMU_OR_4(_sc, _reg, _val) \ argument
46 #define BHND_PMU_IND_READ(_sc, _src, _reg) \ argument
49 #define BHND_PMU_IND_WRITE(_sc, _src, _reg, _val, _mask) \ argument
55 #define BHND_PMU_CCTRL_READ(_sc, _reg) \ argument
57 #define BHND_PMU_CCTRL_WRITE(_sc, _reg, _val, _mask) \ argument
61 #define BHND_PMU_REGCTRL_READ(_sc, _reg) \ argument
63 #define BHND_PMU_REGCTRL_WRITE(_sc, _reg, _val, _mask) \ argument
[all …]
/freebsd-head/sys/arm/freescale/vybrid/
HDvf_common.h29 #define READ4(_sc, _reg) \ argument
31 #define WRITE4(_sc, _reg, _val) \ argument
33 #define READ2(_sc, _reg) \ argument
35 #define WRITE2(_sc, _reg, _val) \ argument
37 #define READ1(_sc, _reg) \ argument
39 #define WRITE1(_sc, _reg, _val) \ argument
/freebsd-head/sys/dev/rtwn/
HDif_rtwnvar.h196 #define RTWN_CHIP_HAS_BCNQ1(_sc) \ argument
442 #define rtwn_write_1(_sc, _addr, _val) \ argument
444 #define rtwn_write_2(_sc, _addr, _val) \ argument
446 #define rtwn_write_4(_sc, _addr, _val) \ argument
448 #define rtwn_read_1(_sc, _addr) \ argument
450 #define rtwn_read_2(_sc, _addr) \ argument
452 #define rtwn_read_4(_sc, _addr) \ argument
454 #define rtwn_delay(_sc, _usec) \ argument
456 #define rtwn_tx_start(_sc, _ni, _m, _desc, _type, _id) \ argument
458 #define rtwn_start_xfers(_sc) \ argument
[all …]
/freebsd-head/sys/arm/broadcom/bcm2835/
HDbcm2835_pwm.c72 #define BCM_PWM_MEM_WRITE(_sc, _off, _val) \ argument
74 #define BCM_PWM_MEM_READ(_sc, _off) \ argument
76 #define BCM_PWM_CLK_WRITE(_sc, _off, _val) \ argument
78 #define BCM_PWM_CLK_READ(_sc, _off) \ argument
81 #define W_CTL(_sc, _val) BCM_PWM_MEM_WRITE(_sc, 0x00, _val) argument
82 #define R_CTL(_sc) BCM_PWM_MEM_READ(_sc, 0x00) argument
83 #define W_STA(_sc, _val) BCM_PWM_MEM_WRITE(_sc, 0x04, _val) argument
84 #define R_STA(_sc) BCM_PWM_MEM_READ(_sc, 0x04) argument
85 #define W_RNG(_sc, _val) BCM_PWM_MEM_WRITE(_sc, 0x10, _val) argument
86 #define R_RNG(_sc) BCM_PWM_MEM_READ(_sc, 0x10) argument
[all …]
HDbcm2835_clkman.c65 #define BCM_CLKMAN_WRITE(_sc, _off, _val) \ argument
67 #define BCM_CLKMAN_READ(_sc, _off) \ argument
70 #define W_CMCLK(_sc, unit, _val) BCM_CLKMAN_WRITE(_sc, unit, 0x5a000000 | (_val)) argument
71 #define R_CMCLK(_sc, unit) BCM_CLKMAN_READ(_sc, unit) argument
72 #define W_CMDIV(_sc, unit, _val) BCM_CLKMAN_WRITE(_sc, (unit) + 4, 0x5a000000 | (_val)) argument
73 #define R_CMDIV(_sc, unit) BCM_CLKMAN_READ(_sc, (unit) + 4) argument
HDbcm2835_spivar.h52 #define BCM_SPI_WRITE(_sc, _off, _val) \ argument
54 #define BCM_SPI_READ(_sc, _off) \ argument
57 #define BCM_SPI_LOCK(_sc) \ argument
59 #define BCM_SPI_UNLOCK(_sc) \ argument
/freebsd-head/sys/arm/ti/am335x/
HDam335x_ecap.c57 #define ECAP_READ2(_sc, reg) bus_read_2((_sc)->sc_mem_res, reg); argument
58 #define ECAP_WRITE2(_sc, reg, value) \ argument
60 #define ECAP_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg); argument
61 #define ECAP_WRITE4(_sc, reg, value) \ argument
64 #define PWM_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) argument
65 #define PWM_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) argument
66 #define PWM_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \ argument
68 #define PWM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) argument
HDam335x_rtc.c45 #define RTC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) argument
46 #define RTC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) argument
47 #define RTC_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \ argument
49 #define RTC_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) argument
51 #define RTC_READ4(_sc, reg) \ argument
53 #define RTC_WRITE4(_sc, reg, value) \ argument
/freebsd-head/sys/fs/p9fs/
HDp9fs.h77 #define P9FS_VFID_MTX(_sc) (&(_sc)->vfid_mtx) argument
78 #define P9FS_VFID_LOCK(_sc) mtx_lock(P9FS_VFID_MTX(_sc)) argument
79 #define P9FS_VFID_UNLOCK(_sc) mtx_unlock(P9FS_VFID_MTX(_sc)) argument
80 #define P9FS_VFID_LOCK_INIT(_sc) mtx_init(P9FS_VFID_MTX(_sc), \ argument
82 #define P9FS_VFID_LOCK_DESTROY(_sc) mtx_destroy(P9FS_VFID_MTX(_sc)) argument
84 #define P9FS_VOFID_MTX(_sc) (&(_sc)->vofid_mtx) argument
85 #define P9FS_VOFID_LOCK(_sc) mtx_lock(P9FS_VOFID_MTX(_sc)) argument
86 #define P9FS_VOFID_UNLOCK(_sc) mtx_unlock(P9FS_VOFID_MTX(_sc)) argument
87 #define P9FS_VOFID_LOCK_INIT(_sc) mtx_init(P9FS_VOFID_MTX(_sc), \ argument
89 #define P9FS_VOFID_LOCK_DESTROY(_sc) mtx_destroy(P9FS_VOFID_MTX(_sc)) argument
[all …]
/freebsd-head/sys/dev/syscon/
HDsyscon_generic.c71 #define SYSCON_LOCK(_sc) mtx_lock_spin(&(_sc)->mtx) argument
72 #define SYSCON_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->mtx) argument
73 #define SYSCON_LOCK_INIT(_sc) mtx_init(&(_sc)->mtx, \ argument
75 #define SYSCON_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx); argument
76 #define SYSCON_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED); argument
77 #define SYSCON_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_NOTOWNED); argument
/freebsd-head/sys/dev/wpi/
HDif_wpivar.h256 #define WPI_LOCK_INIT(_sc) \ argument
259 #define WPI_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) argument
260 #define WPI_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) argument
261 #define WPI_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) argument
262 #define WPI_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) argument
264 #define WPI_RXON_LOCK_INIT(_sc) \ argument
266 #define WPI_RXON_LOCK(_sc) mtx_lock(&(_sc)->rxon_mtx) argument
267 #define WPI_RXON_UNLOCK(_sc) mtx_unlock(&(_sc)->rxon_mtx) argument
268 #define WPI_RXON_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rxon_mtx, MA_OWNED) argument
269 #define WPI_RXON_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rxon_mtx) argument
[all …]
/freebsd-head/sys/arm/nvidia/
HDtegra_rtc.c75 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) argument
76 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) argument
78 #define LOCK(_sc) mtx_lock(&(_sc)->mtx) argument
79 #define UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) argument
80 #define SLEEP(_sc, timeout) \ argument
82 #define LOCK_INIT(_sc) \ argument
84 #define LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx) argument
85 #define ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED) argument
86 #define ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED) argument
HDtegra_mc.c97 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) argument
98 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) argument
100 #define LOCK(_sc) mtx_lock(&(_sc)->mtx) argument
101 #define UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) argument
102 #define SLEEP(_sc, timeout) mtx_sleep(sc, &sc->mtx, 0, "tegra_mc", timeout); argument
103 #define LOCK_INIT(_sc) \ argument
105 #define LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx) argument
106 #define ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED) argument
107 #define ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED) argument
HDas3722.c64 #define LOCK(_sc) sx_xlock(&(_sc)->lock) argument
65 #define UNLOCK(_sc) sx_xunlock(&(_sc)->lock) argument
66 #define LOCK_INIT(_sc) sx_init(&(_sc)->lock, "as3722") argument
67 #define LOCK_DESTROY(_sc) sx_destroy(&(_sc)->lock); argument
68 #define ASSERT_LOCKED(_sc) sx_assert(&(_sc)->lock, SA_XLOCKED); argument
69 #define ASSERT_UNLOCKED(_sc) sx_assert(&(_sc)->lock, SA_UNLOCKED); argument
/freebsd-head/sys/dev/bhnd/cores/pci/
HDbhnd_pci_hostb.c174 #define BHND_PCI_SOFTC(_sc) (&((_sc)->common)) argument
176 #define BHND_PCI_READ_2(_sc, _reg) \ argument
179 #define BHND_PCI_READ_4(_sc, _reg) \ argument
182 #define BHND_PCI_WRITE_2(_sc, _reg, _val) \ argument
185 #define BHND_PCI_WRITE_4(_sc, _reg, _val) \ argument
188 #define BHND_PCI_PROTO_READ_4(_sc, _reg) \ argument
191 #define BHND_PCI_PROTO_WRITE_4(_sc, _reg, _val) \ argument
194 #define BHND_PCI_MDIO_READ(_sc, _phy, _reg) \ argument
197 #define BHND_PCI_MDIO_WRITE(_sc, _phy, _reg, _val) \ argument
200 #define BHND_PCI_MDIO_READ_EXT(_sc, _phy, _devaddr, _reg) \ argument
[all …]
/freebsd-head/sys/dev/rtwn/rtl8192c/
HDr92c_var.h65 #define R92C_SOFTC(_sc) ((struct r92c_softc *)((_sc)->sc_priv)) argument
67 #define rtwn_r92c_set_bw20(_sc, _chan) \ argument
69 #define rtwn_r92c_get_txpower(_sc, _chain, _c, _power) \ argument
71 #define rtwn_r92c_set_gain(_sc, _gain) \ argument
73 #define rtwn_r92c_tx_enable_ampdu(_sc, _buf, _enable) \ argument
75 #define rtwn_r92c_tx_setup_hwseq(_sc, _buf) \ argument
77 #define rtwn_r92c_tx_setup_macid(_sc, _buf, _id) \ argument
79 #define rtwn_r92c_set_rom_opts(_sc, _buf) \ argument
/freebsd-head/sys/dev/iicbus/pmic/
HDact8846.c60 #define LOCK(_sc) sx_xlock(&(_sc)->lock) argument
61 #define UNLOCK(_sc) sx_xunlock(&(_sc)->lock) argument
62 #define LOCK_INIT(_sc) sx_init(&(_sc)->lock, "act8846") argument
63 #define LOCK_DESTROY(_sc) sx_destroy(&(_sc)->lock); argument
64 #define ASSERT_LOCKED(_sc) sx_assert(&(_sc)->lock, SA_XLOCKED); argument
65 #define ASSERT_UNLOCKED(_sc) sx_assert(&(_sc)->lock, SA_UNLOCKED); argument
/freebsd-head/sys/dev/flash/
HDcqspi.c80 #define READ4(_sc, _reg) bus_read_4((_sc)->res[0], _reg) argument
81 #define READ2(_sc, _reg) bus_read_2((_sc)->res[0], _reg) argument
82 #define READ1(_sc, _reg) bus_read_1((_sc)->res[0], _reg) argument
83 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->res[0], _reg, _val) argument
84 #define WRITE2(_sc, _reg, _val) bus_write_2((_sc)->res[0], _reg, _val) argument
85 #define WRITE1(_sc, _reg, _val) bus_write_1((_sc)->res[0], _reg, _val) argument
86 #define READ_DATA_4(_sc, _reg) bus_read_4((_sc)->res[1], _reg) argument
87 #define READ_DATA_1(_sc, _reg) bus_read_1((_sc)->res[1], _reg) argument
88 #define WRITE_DATA_4(_sc, _reg, _val) bus_write_4((_sc)->res[1], _reg, _val) argument
89 #define WRITE_DATA_1(_sc, _reg, _val) bus_write_1((_sc)->res[1], _reg, _val) argument
[all …]
/freebsd-head/sys/dev/fdt/
HDsimple_mfd.c64 #define SYSCON_LOCK(_sc) mtx_lock_spin(&(_sc)->mtx) argument
65 #define SYSCON_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->mtx) argument
66 #define SYSCON_LOCK_INIT(_sc) mtx_init(&(_sc)->mtx, \ argument
68 #define SYSCON_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx); argument
69 #define SYSCON_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED); argument
70 #define SYSCON_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_NOTOWNED); argument
/freebsd-head/sys/arm/ti/
HDti_adcvar.h32 #define ADC_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg) argument
33 #define ADC_WRITE4(_sc, reg, value) \ argument
73 #define TI_ADC_LOCK(_sc) \ argument
75 #define TI_ADC_UNLOCK(_sc) \ argument
77 #define TI_ADC_LOCK_INIT(_sc) \ argument
80 #define TI_ADC_LOCK_DESTROY(_sc) \ argument
82 #define TI_ADC_LOCK_ASSERT(_sc) \ argument
/freebsd-head/sys/powerpc/mambo/
HDmambo_disk.c72 #define MBODISK_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) argument
73 #define MBODISK_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) argument
74 #define MBODISK_LOCK_INIT(_sc) \ argument
77 #define MBODISK_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); argument
78 #define MBODISK_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); argument
79 #define MBODISK_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); argument
/freebsd-head/sys/dev/gpio/
HDgpioled.c52 #define GPIOLED_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) argument
53 #define GPIOLED_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) argument
54 #define GPIOLED_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \ argument
56 #define GPIOLED_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) argument
/freebsd-head/sys/dev/rtwn/rtl8812a/
HDr12a_var.h104 #define R12A_SOFTC(_sc) ((struct r12a_softc *)((_sc)->sc_priv)) argument
106 #define rtwn_r12a_fix_spur(_sc, _c) \ argument
108 #define rtwn_r12a_set_band_2ghz(_sc, _rates) \ argument
110 #define rtwn_r12a_set_band_5ghz(_sc, _rates) \ argument
112 #define rtwn_r12a_init_burstlen(_sc) \ argument
114 #define rtwn_r12a_init_ampdu_fwhw(_sc) \ argument
116 #define rtwn_r12a_crystalcap_write(_sc) \ argument
119 #define rtwn_r12a_iq_calib_fw_supported(_sc) \ argument
122 #define rtwn_r12a_iq_calib_sw(_sc) \ argument

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