1 /*-
2 * Copyright(c) 2002-2011 Exar Corp.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification are permitted provided the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the Exar Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31 /*$FreeBSD$*/
32 #include <dev/vxge/vxgehal/vxgehal.h>
33
34
35 /*
36 * __hal_vpath_fw_memo_get - Get the fw memo interface parameters
37 * @pdev: PCI device object.
38 * @regh0: BAR0 mapped memory handle, or simply PCI device @pdev
39 * (Linux and the rest.)
40 * @vp_id: Vpath id
41 * @vpath_reg: Pointer to vpath registers
42 * @action: Action for FW Interface
43 * @param_index: Index of the parameter
44 * @data0: Buffer to return data 0 register contents
45 * @data1: Buffer to return data 1 register contents
46 *
47 * Returns FW memo interface parameters
48 *
49 */
50 vxge_hal_status_e
__hal_vpath_fw_memo_get(pci_dev_h pdev,pci_reg_h regh0,u32 vp_id,vxge_hal_vpath_reg_t * vpath_reg,u32 action,u64 param_index,u64 * data0,u64 * data1)51 __hal_vpath_fw_memo_get(
52 pci_dev_h pdev,
53 pci_reg_h regh0,
54 u32 vp_id,
55 vxge_hal_vpath_reg_t *vpath_reg,
56 u32 action,
57 u64 param_index,
58 u64 *data0,
59 u64 *data1)
60 {
61 u64 val64;
62 vxge_hal_status_e status = VXGE_HAL_OK;
63
64 vxge_assert((vpath_reg != NULL) && (data0 != NULL) && (data1 != NULL));
65
66 vxge_hal_trace_log_driver("==> %s:%s:%d",
67 __FILE__, __func__, __LINE__);
68
69 vxge_hal_trace_log_driver(
70 "pdev = 0x"VXGE_OS_STXFMT", regh0 = 0x"VXGE_OS_STXFMT", "
71 "vp_id = %d, vpath_reg = 0x"VXGE_OS_STXFMT", action = %d, "
72 "param_index = %lld, data0 = 0x"VXGE_OS_STXFMT", "
73 "data1 = 0x"VXGE_OS_STXFMT, (ptr_t) pdev, (ptr_t) regh0,
74 vp_id, (ptr_t) vpath_reg, action, param_index,
75 (ptr_t) data0, (ptr_t) data1);
76
77 vxge_os_pio_mem_write64(pdev,
78 regh0,
79 0,
80 &vpath_reg->rts_access_steer_ctrl);
81
82 vxge_os_wmb();
83
84 vxge_os_pio_mem_write64(pdev,
85 regh0,
86 param_index,
87 &vpath_reg->rts_access_steer_data0);
88
89 vxge_os_pio_mem_write64(pdev,
90 regh0,
91 0,
92 &vpath_reg->rts_access_steer_data1);
93
94 vxge_os_wmb();
95
96 val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(action) |
97 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
98 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
99 VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE |
100 VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(0);
101
102 vxge_hal_pio_mem_write32_lower(pdev,
103 regh0,
104 (u32) bVAL32(val64, 32),
105 &vpath_reg->rts_access_steer_ctrl);
106
107 vxge_os_wmb();
108
109 vxge_hal_pio_mem_write32_upper(pdev,
110 regh0,
111 (u32) bVAL32(val64, 0),
112 &vpath_reg->rts_access_steer_ctrl);
113
114 vxge_os_wmb();
115
116 status = vxge_hal_device_register_poll(pdev, regh0,
117 &vpath_reg->rts_access_steer_ctrl, 0,
118 VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE,
119 WAIT_FACTOR * VXGE_HAL_DEF_DEVICE_POLL_MILLIS);
120
121 if (status != VXGE_HAL_OK) {
122
123 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
124 __FILE__, __func__, __LINE__, status);
125 return (status);
126 }
127
128 val64 = vxge_os_pio_mem_read64(pdev, regh0,
129 &vpath_reg->rts_access_steer_ctrl);
130
131 if (val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
132
133 *data0 = vxge_os_pio_mem_read64(pdev, regh0,
134 &vpath_reg->rts_access_steer_data0);
135
136 *data1 = vxge_os_pio_mem_read64(pdev, regh0,
137 &vpath_reg->rts_access_steer_data1);
138
139 status = VXGE_HAL_OK;
140
141 } else {
142 status = VXGE_HAL_FAIL;
143 }
144
145
146 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
147 __FILE__, __func__, __LINE__, status);
148
149 return (status);
150 }
151
152 /*
153 * __hal_vpath_fw_flash_ver_get - Get the fw version
154 * @pdev: PCI device object.
155 * @regh0: BAR0 mapped memory handle, or simply PCI device @pdev
156 * (Linux and the rest.)
157 * @vp_id: Vpath id
158 * @vpath_reg: Pointer to vpath registers
159 * @fw_version: Buffer to return FW Version (Major)
160 * @fw_date: Buffer to return FW Version (date)
161 * @flash_version: Buffer to return FW Version (Major)
162 * @flash_date: Buffer to return FW Version (date)
163 *
164 * Returns FW Version
165 *
166 */
167 vxge_hal_status_e
__hal_vpath_fw_flash_ver_get(pci_dev_h pdev,pci_reg_h regh0,u32 vp_id,vxge_hal_vpath_reg_t * vpath_reg,vxge_hal_device_version_t * fw_version,vxge_hal_device_date_t * fw_date,vxge_hal_device_version_t * flash_version,vxge_hal_device_date_t * flash_date)168 __hal_vpath_fw_flash_ver_get(
169 pci_dev_h pdev,
170 pci_reg_h regh0,
171 u32 vp_id,
172 vxge_hal_vpath_reg_t *vpath_reg,
173 vxge_hal_device_version_t *fw_version,
174 vxge_hal_device_date_t *fw_date,
175 vxge_hal_device_version_t *flash_version,
176 vxge_hal_device_date_t *flash_date)
177 {
178 u64 data1 = 0ULL;
179 u64 data2 = 0ULL;
180 vxge_hal_status_e status = VXGE_HAL_OK;
181
182 vxge_assert((vpath_reg != NULL) && (fw_version != NULL) &&
183 (fw_date != NULL) && (flash_version != NULL) &&
184 (flash_date != NULL));
185
186 vxge_hal_trace_log_driver("==> %s:%s:%d",
187 __FILE__, __func__, __LINE__);
188
189 vxge_hal_trace_log_driver(
190 "pdev = 0x"VXGE_OS_STXFMT", regh0 = 0x"VXGE_OS_STXFMT", "
191 "vp_id = %d, vpath_reg = 0x"VXGE_OS_STXFMT", "
192 "fw_version = 0x"VXGE_OS_STXFMT", "
193 "fw_date = 0x"VXGE_OS_STXFMT", "
194 "flash_version = 0x"VXGE_OS_STXFMT", "
195 "flash_date = 0x"VXGE_OS_STXFMT,
196 (ptr_t) pdev, (ptr_t) regh0, vp_id, (ptr_t) vpath_reg,
197 (ptr_t) fw_version, (ptr_t) fw_date,
198 (ptr_t) flash_version, (ptr_t) flash_date);
199
200 status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
201 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_VERSION,
202 VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_FW_VERSION,
203 &data1, &data2);
204
205 if (status != VXGE_HAL_OK) {
206
207 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
208 __FILE__, __func__, __LINE__, status);
209 return (status);
210 }
211
212 fw_date->day =
213 (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(data1);
214 fw_date->month =
215 (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(data1);
216 fw_date->year =
217 (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(data1);
218
219 (void) vxge_os_snprintf(fw_date->date, sizeof(fw_date->date),
220 "%2.2d/%2.2d/%4.4d",
221 fw_date->month, fw_date->day, fw_date->year);
222
223 fw_version->major =
224 (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data1);
225 fw_version->minor =
226 (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data1);
227 fw_version->build =
228 (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data1);
229
230 (void) vxge_os_snprintf(fw_version->version,
231 sizeof(fw_version->version),
232 "%d.%d.%d", fw_version->major,
233 fw_version->minor, fw_version->build);
234
235 status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
236 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_CARD_INFO,
237 VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_FLASH_VERSION,
238 &data1, &data2);
239
240 if (status != VXGE_HAL_OK) {
241
242 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
243 __FILE__, __func__, __LINE__, status);
244 return (status);
245 }
246
247 flash_date->day =
248 (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_DAY(data1);
249 flash_date->month =
250 (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_MONTH(data1);
251 flash_date->year =
252 (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_YEAR(data1);
253
254 (void) vxge_os_snprintf(flash_date->date, sizeof(flash_date->date),
255 "%2.2d/%2.2d/%4.4d", flash_date->month, flash_date->day,
256 flash_date->year);
257
258 flash_version->major =
259 (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_MAJOR(data1);
260 flash_version->minor =
261 (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_MINOR(data1);
262 flash_version->build =
263 (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_BUILD(data1);
264
265 (void) vxge_os_snprintf(flash_version->version,
266 sizeof(flash_version->version),
267 "%d.%d.%d", flash_version->major,
268 flash_version->minor, flash_version->build);
269
270 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
271 __FILE__, __func__, __LINE__, status);
272
273 return (status);
274 }
275
276 /*
277 * __hal_vpath_card_info_get - Get the card infor
278 * @pdev: PCI device object.
279 * @regh0: BAR0 mapped memory handle, or simply PCI device @pdev
280 * (Linux and the rest.)
281 * @vp_id: Vpath id
282 * @vpath_reg: Pointer to vpath registers
283 * @serial_number: Buffer to return card serial number
284 * @part_number: Buffer to return card part number
285 * @product_description: Buffer to return card description
286 *
287 * Returns Card Info
288 *
289 */
290 vxge_hal_status_e
__hal_vpath_card_info_get(pci_dev_h pdev,pci_reg_h regh0,u32 vp_id,vxge_hal_vpath_reg_t * vpath_reg,u8 * serial_number,u8 * part_number,u8 * product_description)291 __hal_vpath_card_info_get(
292 pci_dev_h pdev,
293 pci_reg_h regh0,
294 u32 vp_id,
295 vxge_hal_vpath_reg_t *vpath_reg,
296 u8 *serial_number,
297 u8 *part_number,
298 u8 *product_description)
299 {
300 u32 i, j;
301 u64 data1 = 0ULL;
302 u64 data2 = 0ULL;
303 vxge_hal_status_e status = VXGE_HAL_OK;
304
305 vxge_assert((vpath_reg != NULL) && (serial_number != NULL) &&
306 (part_number != NULL) && (product_description != NULL));
307
308 vxge_hal_trace_log_driver("==> %s:%s:%d",
309 __FILE__, __func__, __LINE__);
310
311 vxge_hal_trace_log_driver(
312 "pdev = 0x"VXGE_OS_STXFMT", regh0 = 0x"VXGE_OS_STXFMT", "
313 "vp_id = %d, vpath_reg = 0x"VXGE_OS_STXFMT", "
314 "serial_number = 0x"VXGE_OS_STXFMT", "
315 "part_number = 0x"VXGE_OS_STXFMT", "
316 "product_description = 0x"VXGE_OS_STXFMT,
317 (ptr_t) pdev, (ptr_t) regh0, vp_id, (ptr_t) vpath_reg,
318 (ptr_t) serial_number, (ptr_t) part_number,
319 (ptr_t) product_description);
320
321 *serial_number = 0;
322 *part_number = 0;
323 *product_description = 0;
324
325 status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
326 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_CARD_INFO,
327 VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER,
328 &data1, &data2);
329
330 if (status != VXGE_HAL_OK) {
331
332 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
333 __FILE__, __func__, __LINE__, status);
334 return (status);
335 }
336
337 /* LINTED */
338 ((u64 *) serial_number)[0] = vxge_os_ntohll(data1);
339
340 /* LINTED */
341 ((u64 *) serial_number)[1] = vxge_os_ntohll(data2);
342
343 status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
344 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_CARD_INFO,
345 VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER,
346 &data1, &data2);
347
348 if (status != VXGE_HAL_OK) {
349
350 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
351 __FILE__, __func__, __LINE__, status);
352 return (status);
353 }
354
355 /* LINTED */
356 ((u64 *) part_number)[0] = vxge_os_ntohll(data1);
357
358 /* LINTED */
359 ((u64 *) part_number)[1] = vxge_os_ntohll(data2);
360
361 j = 0;
362
363 for (i = VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_0;
364 i <= VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_3;
365 i++) {
366
367 status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
368 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_CARD_INFO,
369 i,
370 &data1, &data2);
371
372 if (status != VXGE_HAL_OK) {
373
374 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
375 __FILE__, __func__, __LINE__, status);
376 return (status);
377 }
378
379 /* LINTED */
380 ((u64 *) product_description)[j++] = vxge_os_ntohll(data1);
381
382 /* LINTED */
383 ((u64 *) product_description)[j++] = vxge_os_ntohll(data2);
384
385 }
386
387 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
388 __FILE__, __func__, __LINE__, status);
389
390 return (status);
391 }
392
393 /*
394 * __hal_vpath_pmd_info_get - Get the PMD info
395 * @pdev: PCI device object.
396 * @regh0: BAR0 mapped memory handle, or simply PCI device @pdev
397 * (Linux and the rest.)
398 * @vp_id: Vpath id
399 * @vpath_reg: Pointer to vpath registers
400 * @ports: Number of ports supported
401 * @pmd_port0: Buffer to return PMD info for port 0
402 * @pmd_port1: Buffer to return PMD info for port 1
403 *
404 * Returns PMD Info
405 *
406 */
407 vxge_hal_status_e
__hal_vpath_pmd_info_get(pci_dev_h pdev,pci_reg_h regh0,u32 vp_id,vxge_hal_vpath_reg_t * vpath_reg,u32 * ports,vxge_hal_device_pmd_info_t * pmd_port0,vxge_hal_device_pmd_info_t * pmd_port1)408 __hal_vpath_pmd_info_get(
409 pci_dev_h pdev,
410 pci_reg_h regh0,
411 u32 vp_id,
412 vxge_hal_vpath_reg_t *vpath_reg,
413 u32 *ports,
414 vxge_hal_device_pmd_info_t *pmd_port0,
415 vxge_hal_device_pmd_info_t *pmd_port1)
416 {
417 u64 data1 = 0ULL;
418 u64 data2 = 0ULL;
419 vxge_hal_status_e status = VXGE_HAL_OK;
420
421 vxge_assert((vpath_reg != NULL) &&
422 (pmd_port0 != NULL) && (pmd_port1 != NULL));
423
424 vxge_hal_trace_log_driver("==> %s:%s:%d",
425 __FILE__, __func__, __LINE__);
426
427 vxge_hal_trace_log_driver(
428 "pdev = 0x"VXGE_OS_STXFMT", regh0 = 0x"VXGE_OS_STXFMT", "
429 "vp_id = %d, vpath_reg = 0x"VXGE_OS_STXFMT", "
430 "ports = 0x"VXGE_OS_STXFMT", "
431 "pmd_port0 = 0x"VXGE_OS_STXFMT", "
432 "pmd_port1 = 0x"VXGE_OS_STXFMT,
433 (ptr_t) pdev, (ptr_t) regh0, vp_id, (ptr_t) vpath_reg,
434 (ptr_t) ports, (ptr_t) pmd_port0, (ptr_t) pmd_port1);
435
436 status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
437 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_CARD_INFO,
438 VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORTS,
439 &data1, &data2);
440
441 if (status != VXGE_HAL_OK) {
442
443 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
444 __FILE__, __func__, __LINE__, status);
445 return (status);
446 }
447
448 *ports = (u32) data1;
449
450 status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
451 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_CARD_INFO,
452 VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT0_PMD_TYPE,
453 &data1, &data2);
454
455 if (status != VXGE_HAL_OK) {
456
457 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
458 __FILE__, __func__, __LINE__, status);
459 return (status);
460 }
461
462 if (data1) {
463
464 pmd_port0->type = (u32) data1;
465
466 status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
467 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_CARD_INFO,
468 VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT0_PMD_VENDOR,
469 &data1, &data2);
470
471 if (status != VXGE_HAL_OK) {
472
473 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
474 __FILE__, __func__, __LINE__, status);
475 return (status);
476 }
477
478 /* LINTED */
479 ((u64 *) pmd_port0->vendor)[0] = vxge_os_ntohll(data1);
480
481 /* LINTED */
482 ((u64 *) pmd_port0->vendor)[1] = vxge_os_ntohll(data2);
483
484 status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
485 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_CARD_INFO,
486 VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT0_PMD_PARTNO,
487 &data1, &data2);
488
489 if (status != VXGE_HAL_OK) {
490
491 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
492 __FILE__, __func__, __LINE__, status);
493 return (status);
494 }
495
496 /* LINTED */
497 ((u64 *) pmd_port0->part_num)[0] = vxge_os_ntohll(data1);
498
499 /* LINTED */
500 ((u64 *) pmd_port0->part_num)[1] = vxge_os_ntohll(data2);
501
502 status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
503 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_CARD_INFO,
504 VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT0_PMD_SERNO,
505 &data1, &data2);
506
507 if (status != VXGE_HAL_OK) {
508
509 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
510 __FILE__, __func__, __LINE__, status);
511 return (status);
512 }
513
514 /* LINTED */
515 ((u64 *) pmd_port0->ser_num)[0] = vxge_os_ntohll(data1);
516
517 /* LINTED */
518 ((u64 *) pmd_port0->ser_num)[1] = vxge_os_ntohll(data2);
519 } else {
520 vxge_os_memzero(pmd_port0, sizeof(vxge_hal_device_pmd_info_t));
521 }
522
523 status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
524 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_CARD_INFO,
525 VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT1_PMD_TYPE,
526 &data1, &data2);
527
528 if (status != VXGE_HAL_OK) {
529
530 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
531 __FILE__, __func__, __LINE__, status);
532 return (status);
533 }
534
535 if (data1) {
536
537 pmd_port1->type = (u32) data1;
538
539 status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
540 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_CARD_INFO,
541 VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT1_PMD_VENDOR,
542 &data1, &data2);
543
544 if (status != VXGE_HAL_OK) {
545
546 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
547 __FILE__, __func__, __LINE__, status);
548 return (status);
549 }
550
551 /* LINTED */
552 ((u64 *) pmd_port1->vendor)[0] = vxge_os_ntohll(data1);
553
554 /* LINTED */
555 ((u64 *) pmd_port1->vendor)[1] = vxge_os_ntohll(data2);
556
557 status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
558 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_CARD_INFO,
559 VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT1_PMD_PARTNO,
560 &data1, &data2);
561
562 if (status != VXGE_HAL_OK) {
563
564 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
565 __FILE__, __func__, __LINE__, status);
566 return (status);
567 }
568
569 /* LINTED */
570 ((u64 *) pmd_port1->part_num)[0] = vxge_os_ntohll(data1);
571
572 /* LINTED */
573 ((u64 *) pmd_port1->part_num)[1] = vxge_os_ntohll(data2);
574
575 status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
576 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_CARD_INFO,
577 VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT1_PMD_SERNO,
578 &data1, &data2);
579
580 if (status != VXGE_HAL_OK) {
581
582 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
583 __FILE__, __func__, __LINE__, status);
584 return (status);
585 }
586
587 /* LINTED */
588 ((u64 *) pmd_port1->ser_num)[0] = vxge_os_ntohll(data1);
589
590 /* LINTED */
591 ((u64 *) pmd_port1->ser_num)[1] = vxge_os_ntohll(data2);
592
593 } else {
594 vxge_os_memzero(pmd_port1, sizeof(vxge_hal_device_pmd_info_t));
595 }
596
597 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
598 __FILE__, __func__, __LINE__, status);
599
600 return (status);
601 }
602
603 /*
604 * __hal_vpath_pci_func_mode_get - Get the pci mode
605 * @pdev: PCI device object.
606 * @regh0: BAR0 mapped memory handle, or simply PCI device @pdev
607 * (Linux and the rest.)
608 * @vp_id: Vpath id
609 * @vpath_reg: Pointer to vpath registers
610 *
611 * Returns pci function mode
612 *
613 */
614 u64
__hal_vpath_pci_func_mode_get(pci_dev_h pdev,pci_reg_h regh0,u32 vp_id,vxge_hal_vpath_reg_t * vpath_reg)615 __hal_vpath_pci_func_mode_get(
616 pci_dev_h pdev,
617 pci_reg_h regh0,
618 u32 vp_id,
619 vxge_hal_vpath_reg_t *vpath_reg)
620 {
621 u64 data1 = 0ULL;
622 u64 data2 = 0ULL;
623 vxge_hal_status_e status = VXGE_HAL_OK;
624
625 vxge_assert(vpath_reg != NULL);
626
627 vxge_hal_trace_log_driver("==> %s:%s:%d",
628 __FILE__, __func__, __LINE__);
629
630 vxge_hal_trace_log_driver(
631 "pdev = 0x"VXGE_OS_STXFMT", regh0 = 0x"VXGE_OS_STXFMT", "
632 "vp_id = %d, vpath_reg = 0x"VXGE_OS_STXFMT,
633 (ptr_t) pdev, (ptr_t) regh0, vp_id, (ptr_t) vpath_reg);
634
635 status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
636 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_GET_FUNC_MODE,
637 VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PCI_MODE,
638 &data1, &data2);
639
640 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
641 __FILE__, __func__, __LINE__, status);
642
643 return (data1);
644 }
645
646 /*
647 * __hal_vpath_lag_mode_get - Get the LAG mode
648 * @vpath: VIrtual Path
649 *
650 * Returns the LAG mode in use
651 */
652 vxge_hal_device_lag_mode_e
__hal_vpath_lag_mode_get(__hal_virtualpath_t * vpath)653 __hal_vpath_lag_mode_get(__hal_virtualpath_t *vpath)
654 {
655 u64 data1 = 0ULL;
656 u64 data2 = 0ULL;
657 u32 lag_mode = VXGE_HAL_DEVICE_LAG_MODE_UNKNOWN;
658 __hal_device_t *hldev;
659 vxge_hal_status_e status = VXGE_HAL_OK;
660
661 vxge_assert(vpath != NULL);
662
663 hldev = vpath->hldev;
664
665 vxge_hal_trace_log_vpath("==> %s:%s:%d",
666 __FILE__, __func__, __LINE__);
667
668 vxge_hal_trace_log_vpath("vpath = 0x"VXGE_OS_STXFMT,
669 (ptr_t) vpath);
670
671 (void) __hal_vpath_fw_memo_get(hldev->header.pdev, hldev->header.regh0,
672 vpath->vp_id, vpath->vp_reg,
673 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_PORT_INFO,
674 VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_LAG_MODE,
675 &data1, &data2);
676
677 if (VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MEMO_ITEM_STATUS(data1) ==
678 VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_STATUS_SUCCESS) {
679 lag_mode = (u32)
680 VXGE_HAL_RTS_ACCESS_STEER_DATA1_MEMO_ITEM_GET_LAG_MODE(data2);
681 status = VXGE_HAL_OK;
682 } else {
683 status = VXGE_HAL_FAIL;
684 }
685
686 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
687 __FILE__, __func__, __LINE__, status);
688
689 return ((vxge_hal_device_lag_mode_e) lag_mode);
690 }
691
692 /*
693 * __hal_vpath_vpath_map_get - Get the vpath map
694 * @pdev: PCI device object.
695 * @regh0: BAR0 mapped memory handle, or simply PCI device @pdev
696 * (Linux and the rest.)
697 * @vp_id: Vpath id
698 * @vh: Virtual Hierrachy
699 * @func: Function number
700 * @vpath_reg: Pointer to vpath registers
701 *
702 * Returns vpath map for a give hierarchy and function
703 *
704 */
705 u64
__hal_vpath_vpath_map_get(pci_dev_h pdev,pci_reg_h regh0,u32 vp_id,u32 vh,u32 func,vxge_hal_vpath_reg_t * vpath_reg)706 __hal_vpath_vpath_map_get(pci_dev_h pdev, pci_reg_h regh0,
707 u32 vp_id, u32 vh, u32 func,
708 vxge_hal_vpath_reg_t *vpath_reg)
709 {
710 u64 i;
711 u64 val64 = 0ULL;
712 u64 data1 = 0ULL;
713 u64 data2 = 0ULL;
714 vxge_hal_status_e status = VXGE_HAL_OK;
715
716 vxge_assert(vpath_reg != NULL);
717
718 vxge_hal_trace_log_driver("==> %s:%s:%d",
719 __FILE__, __func__, __LINE__);
720
721 vxge_hal_trace_log_driver(
722 "pdev = 0x"VXGE_OS_STXFMT", regh0 = 0x"VXGE_OS_STXFMT", "
723 "vp_id = %d, vh = %d, func = %d, vpath_reg = 0x"VXGE_OS_STXFMT,
724 (ptr_t) pdev, (ptr_t) regh0, vp_id, vh, func, (ptr_t) vpath_reg);
725
726 status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
727 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_VPATH_MAP,
728 VXGE_HAL_RTS_ACCESS_STEER_DATA0_VH(vh) |
729 VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNCTION(func),
730 &data1, &data2);
731
732 for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
733 if (data2 & VXGE_HAL_RTS_ACCESS_STEER_DATA1_IS_VPATH_ASSIGNED(i))
734 val64 |= mBIT(i);
735 }
736
737 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
738 __FILE__, __func__, __LINE__, status);
739
740 return (val64);
741 }
742
743 /*
744 * __hal_vpath_pci_read - Read the content of given address
745 * in pci config space.
746 * @vpath: Virtual Path object.
747 * @offset: Configuration address(offset)to read from
748 * @length: Length of the data (1, 2 or 4 bytes)
749 * @val: Pointer to a buffer to return the content of the address
750 *
751 * Read from the vpath pci config space.
752 *
753 */
754 vxge_hal_status_e
__hal_vpath_pci_read(struct __hal_device_t * hldev,u32 vp_id,u32 offset,u32 length,void * val)755 __hal_vpath_pci_read(struct __hal_device_t *hldev,
756 u32 vp_id, u32 offset,
757 u32 length, void *val)
758 {
759 vxge_hal_status_e status = VXGE_HAL_OK;
760
761 vxge_assert((hldev != NULL) && (val != NULL));
762
763 vxge_hal_trace_log_vpath("==> %s:%s:%d",
764 __FILE__, __func__, __LINE__);
765
766 vxge_hal_trace_log_vpath("hldev = 0x"VXGE_OS_STXFMT", vp_id = %d, "
767 "offset = %d, val = 0x"VXGE_OS_STXFMT,
768 (ptr_t) hldev, vp_id, offset, (ptr_t) val);
769
770 switch (length) {
771 case 1:
772 vxge_os_pci_read8(hldev->header.pdev,
773 hldev->header.cfgh,
774 offset,
775 ((u8 *) val));
776 break;
777 case 2:
778 vxge_os_pci_read16(hldev->header.pdev,
779 hldev->header.cfgh,
780 offset,
781 ((u16 *) val));
782 break;
783 case 4:
784 vxge_os_pci_read32(hldev->header.pdev,
785 hldev->header.cfgh,
786 offset,
787 ((u32 *) val));
788 break;
789 default:
790 status = VXGE_HAL_FAIL;
791 vxge_os_memzero(val, length);
792 break;
793 }
794
795 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
796 __FILE__, __func__, __LINE__, status);
797
798 return (status);
799 }
800
801 /*
802 * __hal_vpath_fw_upgrade - Upgrade the firmware
803 * @pdev: PCI device object.
804 * @regh0: BAR0 mapped memory handle, or simply PCI device @pdev
805 * (Linux and the rest.)
806 * @vp_id: Vpath id
807 * @vpath_reg: Pointer to vpath registers
808 * @buffer: Buffer containing F/W image
809 * @length: Length of F/W image
810 *
811 * Upgrade the firmware
812 *
813 */
814 vxge_hal_status_e
__hal_vpath_fw_upgrade(pci_dev_h pdev,pci_reg_h regh0,u32 vp_id,vxge_hal_vpath_reg_t * vpath_reg,u8 * buffer,u32 length)815 __hal_vpath_fw_upgrade(
816 pci_dev_h pdev,
817 pci_reg_h regh0,
818 u32 vp_id,
819 vxge_hal_vpath_reg_t *vpath_reg,
820 u8 *buffer,
821 u32 length)
822 {
823 u32 i = 0;
824 u64 val64;
825 u32 not_done = TRUE;
826 vxge_hal_status_e status = VXGE_HAL_OK;
827
828 vxge_assert((vpath_reg != NULL) && (buffer != NULL));
829
830 vxge_hal_trace_log_driver("==> %s:%s:%d",
831 __FILE__, __func__, __LINE__);
832
833 vxge_hal_trace_log_driver(
834 "pdev = 0x"VXGE_OS_STXFMT", regh0 = 0x"VXGE_OS_STXFMT", "
835 "vp_id = %d, vpath_reg = 0x"VXGE_OS_STXFMT", "
836 "buffer = 0x"VXGE_OS_STXFMT", length = %d\n",
837 (ptr_t) pdev, (ptr_t) regh0, vp_id, (ptr_t) vpath_reg,
838 (ptr_t) buffer, length);
839
840 vxge_os_pio_mem_write64(pdev,
841 regh0,
842 0,
843 &vpath_reg->rts_access_steer_ctrl);
844
845 vxge_os_wmb();
846
847 vxge_os_pio_mem_write64(pdev,
848 regh0,
849 VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_STREAM_SKIP,
850 &vpath_reg->rts_access_steer_data0);
851
852 vxge_os_pio_mem_write64(pdev,
853 regh0,
854 0,
855 &vpath_reg->rts_access_steer_data1);
856
857 vxge_os_wmb();
858
859 val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(
860 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_UPGRADE) |
861 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
862 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
863 VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE |
864 VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(
865 VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET_FW_UPGRADE_MODE);
866
867 vxge_hal_pio_mem_write32_lower(pdev, regh0,
868 (u32) bVAL32(val64, 32),
869 &vpath_reg->rts_access_steer_ctrl);
870
871 vxge_os_wmb();
872
873 vxge_hal_pio_mem_write32_upper(pdev, regh0,
874 (u32) bVAL32(val64, 0),
875 &vpath_reg->rts_access_steer_ctrl);
876
877 vxge_os_wmb();
878
879 status = __hal_device_register_stall(pdev, regh0,
880 &vpath_reg->rts_access_steer_ctrl, 0,
881 VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE,
882 WAIT_FACTOR * VXGE_HAL_DEF_DEVICE_POLL_MILLIS);
883
884 if (status != VXGE_HAL_OK) {
885
886 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
887 __FILE__, __func__, __LINE__, status);
888 return (status);
889 }
890
891 val64 = vxge_os_pio_mem_read64(pdev, regh0,
892 &vpath_reg->rts_access_steer_ctrl);
893
894 if (!(val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS)) {
895
896 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
897 __FILE__, __func__, __LINE__, VXGE_HAL_FAIL);
898 return (VXGE_HAL_FAIL);
899 }
900
901 while (not_done) {
902 if ((i + 16) > length) {
903 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
904 __FILE__, __func__, __LINE__, VXGE_HAL_FAIL);
905 return (VXGE_HAL_FAIL);
906 }
907 vxge_os_pio_mem_write64(pdev, regh0, ((u64) (buffer[i])) |
908 ((u64) (buffer[i + 1]) << 8) |
909 ((u64) (buffer[i + 2]) << 16) |
910 ((u64) (buffer[i + 3]) << 24) |
911 ((u64) (buffer[i + 4]) << 32) |
912 ((u64) (buffer[i + 5]) << 40) |
913 ((u64) (buffer[i + 6]) << 48) |
914 ((u64) (buffer[i + 7]) << 56),
915 &vpath_reg->rts_access_steer_data0);
916
917 vxge_os_pio_mem_write64(pdev, regh0,
918 ((u64) (buffer[i + 8])) |
919 ((u64) (buffer[i + 9]) << 8) |
920 ((u64) (buffer[i + 10]) << 16) |
921 ((u64) (buffer[i + 11]) << 24) |
922 ((u64) (buffer[i + 12]) << 32) |
923 ((u64) (buffer[i + 13]) << 40) |
924 ((u64) (buffer[i + 14]) << 48) |
925 ((u64) (buffer[i + 15]) << 56),
926 &vpath_reg->rts_access_steer_data1);
927 vxge_os_wmb();
928
929 val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(
930 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_UPGRADE) |
931 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
932 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
933 VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE |
934 VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(
935 VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET_FW_UPGRADE_DATA);
936 vxge_hal_pio_mem_write32_lower(pdev, regh0,
937 (u32) bVAL32(val64, 32),
938 &vpath_reg->rts_access_steer_ctrl);
939
940 vxge_os_wmb();
941
942 vxge_hal_pio_mem_write32_upper(pdev, regh0,
943 (u32) bVAL32(val64, 0), &vpath_reg->rts_access_steer_ctrl);
944 vxge_os_wmb();
945
946 status = __hal_device_register_stall(pdev, regh0,
947 &vpath_reg->rts_access_steer_ctrl, 0,
948 VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE,
949 WAIT_FACTOR * VXGE_HAL_DEF_DEVICE_POLL_MILLIS);
950 if (status != VXGE_HAL_OK) {
951
952 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
953 __FILE__, __func__, __LINE__, status);
954 return (status);
955 }
956
957 val64 = vxge_os_pio_mem_read64(pdev, regh0,
958 &vpath_reg->rts_access_steer_ctrl);
959 if (!(val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS)) {
960 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
961 __FILE__, __func__, __LINE__, VXGE_HAL_FAIL);
962 return (VXGE_HAL_FAIL);
963 }
964
965 val64 = vxge_os_pio_mem_read64(pdev, regh0,
966 &vpath_reg->rts_access_steer_data0);
967 switch (VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_RET_CODE(val64)) {
968 case VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_RET_CODE_OK:
969 i += 16;
970 break;
971 case VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_RET_CODE_DONE:
972 not_done = FALSE;
973 break;
974 case VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_RET_CODE_SKIP:
975 i += 16;
976 i += (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_SKIP_BYTES(val64);
977 break;
978 case VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_RET_CODE_ERROR:
979 default:
980 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
981 __FILE__, __func__, __LINE__, VXGE_HAL_FAIL);
982 return (VXGE_HAL_FAIL);
983 }
984 }
985
986 vxge_os_pio_mem_write64(pdev,
987 regh0,
988 0,
989 &vpath_reg->rts_access_steer_data0);
990
991 vxge_os_pio_mem_write64(pdev,
992 regh0,
993 0,
994 &vpath_reg->rts_access_steer_data1);
995
996 vxge_os_wmb();
997
998 val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(
999 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_UPGRADE) |
1000 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
1001 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
1002 VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE |
1003 VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(
1004 VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET_FW_UPGRADE_COMMIT);
1005
1006 vxge_hal_pio_mem_write32_lower(pdev,
1007 regh0,
1008 (u32) bVAL32(val64, 32),
1009 &vpath_reg->rts_access_steer_ctrl);
1010
1011 vxge_os_wmb();
1012
1013 vxge_hal_pio_mem_write32_upper(pdev,
1014 regh0,
1015 (u32) bVAL32(val64, 0),
1016 &vpath_reg->rts_access_steer_ctrl);
1017
1018 vxge_os_wmb();
1019
1020 status = __hal_device_register_stall(pdev, regh0,
1021 &vpath_reg->rts_access_steer_ctrl, 0,
1022 VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE,
1023 100 * VXGE_HAL_DEF_DEVICE_POLL_MILLIS);
1024
1025 if (status != VXGE_HAL_OK) {
1026
1027 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
1028 __FILE__, __func__, __LINE__, status);
1029 return (status);
1030 }
1031
1032 val64 = vxge_os_pio_mem_read64(pdev, regh0,
1033 &vpath_reg->rts_access_steer_ctrl);
1034
1035 if (!(val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS)) {
1036
1037 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
1038 __FILE__, __func__, __LINE__, VXGE_HAL_FAIL);
1039 return (VXGE_HAL_FAIL);
1040 }
1041
1042 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
1043 __FILE__, __func__, __LINE__, VXGE_HAL_OK);
1044
1045 return (VXGE_HAL_OK);
1046 }
1047
1048 /*
1049 * __hal_vpath_flick_link_led - Flick (blink) link LED.
1050 * @hldev: HAL device.
1051 * @vp_id: Vpath Id
1052 * @port : Port number 0, or 1
1053 * @on_off: TRUE if flickering to be on, FALSE to be off
1054 *
1055 * Flicker the link LED.
1056 */
1057 vxge_hal_status_e
__hal_vpath_flick_link_led(struct __hal_device_t * hldev,u32 vp_id,u32 port,u32 on_off)1058 __hal_vpath_flick_link_led(struct __hal_device_t *hldev,
1059 u32 vp_id, u32 port, u32 on_off)
1060 {
1061 u64 val64;
1062 vxge_hal_status_e status = VXGE_HAL_OK;
1063 vxge_hal_vpath_reg_t *vp_reg;
1064
1065 vxge_assert(hldev != NULL);
1066
1067 vxge_hal_trace_log_vpath("==> %s:%s:%d",
1068 __FILE__, __func__, __LINE__);
1069
1070 vxge_hal_trace_log_vpath(
1071 "hldev = 0x"VXGE_OS_STXFMT", vp_id = %d, port = %d, on_off = %d",
1072 (ptr_t) hldev, vp_id, port, on_off);
1073
1074 vp_reg = hldev->vpath_reg[vp_id];
1075
1076 vxge_os_pio_mem_write64(hldev->header.pdev,
1077 hldev->header.regh0,
1078 0,
1079 &vp_reg->rts_access_steer_ctrl);
1080
1081 vxge_os_wmb();
1082
1083 vxge_os_pio_mem_write64(hldev->header.pdev,
1084 hldev->header.regh0,
1085 (u64) on_off,
1086 &vp_reg->rts_access_steer_data0);
1087
1088 vxge_os_pio_mem_write64(hldev->header.pdev,
1089 hldev->header.regh0,
1090 0,
1091 &vp_reg->rts_access_steer_data1);
1092
1093 vxge_os_wmb();
1094
1095 val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(
1096 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LED_CONTROL) |
1097 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
1098 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
1099 VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE |
1100 VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(0);
1101
1102 vxge_hal_pio_mem_write32_lower(hldev->header.pdev,
1103 hldev->header.regh0,
1104 (u32) bVAL32(val64, 32),
1105 &vp_reg->rts_access_steer_ctrl);
1106
1107 vxge_os_wmb();
1108
1109 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
1110 hldev->header.regh0,
1111 (u32) bVAL32(val64, 0),
1112 &vp_reg->rts_access_steer_ctrl);
1113
1114 vxge_os_wmb();
1115
1116 status = vxge_hal_device_register_poll(hldev->header.pdev,
1117 hldev->header.regh0,
1118 &vp_reg->rts_access_steer_ctrl, 0,
1119 VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE,
1120 WAIT_FACTOR * hldev->header.config.device_poll_millis);
1121
1122 if (status != VXGE_HAL_OK) {
1123
1124 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
1125 __FILE__, __func__, __LINE__, status);
1126 return (status);
1127 }
1128
1129 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
1130 __FILE__, __func__, __LINE__, status);
1131
1132 return (VXGE_HAL_OK);
1133 }
1134
1135 /*
1136 * __hal_vpath_udp_rth_set - Enable or Disable UDP/RTH.
1137 * @hldev: HAL device.
1138 * @vp_id: Vpath Id
1139 * @on_off: TRUE if UDP/RTH to be enabled, FALSE to be disabled
1140 *
1141 * Enable or Disable UDP/RTH.
1142 */
1143 vxge_hal_status_e
__hal_vpath_udp_rth_set(struct __hal_device_t * hldev,u32 vp_id,u32 on_off)1144 __hal_vpath_udp_rth_set(
1145 struct __hal_device_t *hldev,
1146 u32 vp_id,
1147 u32 on_off)
1148 {
1149 u64 val64;
1150 vxge_hal_status_e status = VXGE_HAL_OK;
1151 vxge_hal_vpath_reg_t *vp_reg;
1152
1153 vxge_assert(hldev != NULL);
1154
1155 vxge_hal_trace_log_vpath("==> %s:%s:%d",
1156 __FILE__, __func__, __LINE__);
1157
1158 vxge_hal_trace_log_vpath(
1159 "hldev = 0x"VXGE_OS_STXFMT", vp_id = %d, on_off = %d",
1160 (ptr_t) hldev, vp_id, on_off);
1161
1162 vp_reg = hldev->vpath_reg[vp_id];
1163
1164 vxge_os_pio_mem_write64(hldev->header.pdev,
1165 hldev->header.regh0,
1166 0,
1167 &vp_reg->rts_access_steer_ctrl);
1168
1169 vxge_os_wmb();
1170
1171 vxge_os_pio_mem_write64(hldev->header.pdev,
1172 hldev->header.regh0,
1173 ((on_off) ? VXGE_HAL_RTS_ACCESS_STEER_DATA0_UDP_RTH_ENABLE : 0),
1174 &vp_reg->rts_access_steer_data0);
1175
1176 vxge_os_pio_mem_write64(hldev->header.pdev,
1177 hldev->header.regh0,
1178 0,
1179 &vp_reg->rts_access_steer_data1);
1180
1181 vxge_os_wmb();
1182
1183 val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(
1184 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_UDP_RTH) |
1185 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
1186 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
1187 VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE |
1188 VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(0);
1189
1190 vxge_hal_pio_mem_write32_lower(hldev->header.pdev,
1191 hldev->header.regh0,
1192 (u32) bVAL32(val64, 32),
1193 &vp_reg->rts_access_steer_ctrl);
1194
1195 vxge_os_wmb();
1196
1197 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
1198 hldev->header.regh0,
1199 (u32) bVAL32(val64, 0),
1200 &vp_reg->rts_access_steer_ctrl);
1201
1202 vxge_os_wmb();
1203
1204 status = vxge_hal_device_register_poll(hldev->header.pdev,
1205 hldev->header.regh0,
1206 &vp_reg->rts_access_steer_ctrl, 0,
1207 VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE,
1208 WAIT_FACTOR * hldev->header.config.device_poll_millis);
1209
1210 if (status != VXGE_HAL_OK) {
1211
1212 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
1213 __FILE__, __func__, __LINE__, status);
1214 return (status);
1215 }
1216
1217 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
1218 __FILE__, __func__, __LINE__, status);
1219
1220 return (VXGE_HAL_OK);
1221 }
1222
1223 /*
1224 * __hal_vpath_pcie_func_mode_set - Set PCI-E function mode.
1225 * @hldev: HAL device.
1226 * @vp_id: Vpath Id
1227 * @func_mode: func_mode to be set
1228 *
1229 * Set PCI-E function mode.
1230 */
1231 vxge_hal_status_e
__hal_vpath_pcie_func_mode_set(struct __hal_device_t * hldev,u32 vp_id,u32 func_mode)1232 __hal_vpath_pcie_func_mode_set(struct __hal_device_t *hldev,
1233 u32 vp_id, u32 func_mode)
1234 {
1235 u64 val64;
1236 vxge_hal_status_e status = VXGE_HAL_OK;
1237 vxge_hal_vpath_reg_t *vp_reg;
1238
1239 vxge_assert(hldev != NULL);
1240
1241 vxge_hal_trace_log_vpath("==> %s:%s:%d",
1242 __FILE__, __func__, __LINE__);
1243
1244 vxge_hal_trace_log_vpath(
1245 "hldev = 0x"VXGE_OS_STXFMT", vp_id = %d, func_mode = %d",
1246 (ptr_t) hldev, vp_id, func_mode);
1247
1248 vp_reg = hldev->vpath_reg[vp_id];
1249
1250 vxge_os_pio_mem_write64(hldev->header.pdev,
1251 hldev->header.regh0,
1252 0,
1253 &vp_reg->rts_access_steer_ctrl);
1254
1255 vxge_os_wmb();
1256
1257 vxge_os_pio_mem_write64(hldev->header.pdev,
1258 hldev->header.regh0,
1259 VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE(func_mode),
1260 &vp_reg->rts_access_steer_data0);
1261
1262 vxge_os_pio_mem_write64(hldev->header.pdev,
1263 hldev->header.regh0,
1264 0,
1265 &vp_reg->rts_access_steer_data1);
1266
1267 vxge_os_wmb();
1268
1269 val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(
1270 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FUNC_MODE) |
1271 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
1272 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
1273 VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE |
1274 VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(0);
1275
1276 vxge_hal_pio_mem_write32_lower(hldev->header.pdev,
1277 hldev->header.regh0,
1278 (u32) bVAL32(val64, 32),
1279 &vp_reg->rts_access_steer_ctrl);
1280
1281 vxge_os_wmb();
1282
1283 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
1284 hldev->header.regh0,
1285 (u32) bVAL32(val64, 0),
1286 &vp_reg->rts_access_steer_ctrl);
1287
1288 vxge_os_wmb();
1289
1290 status = vxge_hal_device_register_poll(hldev->header.pdev,
1291 hldev->header.regh0,
1292 &vp_reg->rts_access_steer_ctrl, 0,
1293 VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE,
1294 WAIT_FACTOR * hldev->header.config.device_poll_millis);
1295
1296 if (status != VXGE_HAL_OK) {
1297
1298 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
1299 __FILE__, __func__, __LINE__, status);
1300 return (status);
1301 }
1302
1303 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
1304 hldev->header.regh0,
1305 &vp_reg->rts_access_steer_ctrl);
1306
1307 if (!(val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS)) {
1308 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
1309 __FILE__, __func__, __LINE__, VXGE_HAL_FAIL);
1310 return (VXGE_HAL_FAIL);
1311 }
1312
1313 vxge_os_pio_mem_write64(hldev->header.pdev,
1314 hldev->header.regh0,
1315 0,
1316 &vp_reg->rts_access_steer_ctrl);
1317
1318 vxge_os_wmb();
1319
1320 vxge_os_pio_mem_write64(hldev->header.pdev,
1321 hldev->header.regh0,
1322 0,
1323 &vp_reg->rts_access_steer_data0);
1324
1325 vxge_os_pio_mem_write64(hldev->header.pdev,
1326 hldev->header.regh0,
1327 0,
1328 &vp_reg->rts_access_steer_data1);
1329
1330 vxge_os_wmb();
1331
1332 val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(
1333 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_COMMIT) |
1334 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
1335 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
1336 VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE |
1337 VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(0);
1338
1339 vxge_hal_pio_mem_write32_lower(hldev->header.pdev,
1340 hldev->header.regh0,
1341 (u32) bVAL32(val64, 32),
1342 &vp_reg->rts_access_steer_ctrl);
1343
1344 vxge_os_wmb();
1345
1346 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
1347 hldev->header.regh0,
1348 (u32) bVAL32(val64, 0),
1349 &vp_reg->rts_access_steer_ctrl);
1350
1351 vxge_os_wmb();
1352
1353 status = vxge_hal_device_register_poll(hldev->header.pdev,
1354 hldev->header.regh0,
1355 &vp_reg->rts_access_steer_ctrl, 0,
1356 VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE,
1357 WAIT_FACTOR * hldev->header.config.device_poll_millis);
1358
1359 if (status != VXGE_HAL_OK) {
1360
1361 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
1362 __FILE__, __func__, __LINE__, status);
1363 return (status);
1364 }
1365
1366 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
1367 hldev->header.regh0,
1368 &vp_reg->rts_access_steer_ctrl);
1369
1370 if (val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
1371 status = VXGE_HAL_OK;
1372 } else {
1373 status = VXGE_HAL_FAIL;
1374 }
1375
1376 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
1377 __FILE__, __func__, __LINE__, status);
1378
1379 return (status);
1380 }
1381
1382 /*
1383 * vxge_hal_vpath_udp_rth_disable - Enable UDP/RTH.
1384 * @vpath_handle: Vpath handle.
1385 *
1386 * Disable udp rth
1387 *
1388 */
1389 vxge_hal_status_e
vxge_hal_vpath_udp_rth_disable(vxge_hal_vpath_h vpath_handle)1390 vxge_hal_vpath_udp_rth_disable(vxge_hal_vpath_h vpath_handle)
1391 {
1392 __hal_device_t *hldev;
1393 __hal_virtualpath_t *vpath;
1394 vxge_hal_status_e status = VXGE_HAL_OK;
1395
1396 vxge_assert(vpath_handle != NULL);
1397
1398 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
1399
1400 hldev = vpath->hldev;
1401
1402 vxge_hal_trace_log_vpath("==> %s:%s:%d",
1403 __FILE__, __func__, __LINE__);
1404
1405 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
1406 (ptr_t) vpath_handle);
1407
1408 status = __hal_vpath_udp_rth_set(hldev,
1409 vpath->vp_id,
1410 FALSE);
1411
1412 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
1413 __FILE__, __func__, __LINE__,
1414 status);
1415
1416 return (status);
1417 }
1418
1419 /*
1420 * __hal_vpath_rts_table_get - Get the entries from RTS access tables
1421 * @vpath_handle: Vpath handle.
1422 * @action: Identifies the action to take on the specified entry. The
1423 * interpretation of this field depends on the DATA_STRUCT_SEL field
1424 * DA, VID, ETYPE, PN, RANGE_PN:
1425 * 8'd0 - ADD_ENTRY (Add an entry to the table. This command may be
1426 * rejected by management/administration).
1427 * 8'd1 - DELETE_ENTRY (Add an entry to the table. This command may
1428 * be rejected by management/administration)
1429 * 8'd2 - LIST_FIRST_ENTRY
1430 * 8'd3 - LIST_NEXT_ENTRY
1431 * RTH_GEN_CFG, RTH_IT, RTH_JHASH_CFG, RTH_MASK, RTH_KEY, QOS, DS:
1432 * 8'd0 - READ_ENTRY
1433 * 8'd1 - WRITE_ENTRY
1434 * Note: This field is updated by the H/W during an operation and
1435 * is used to report additional TBD status information back to the
1436 * host.
1437 * @rts_table: Identifies the RTS data structure (i.e. lookup table) to access.
1438 * 0; DA; Destination Address 1; VID; VLAN ID 2; ETYPE; Ethertype
1439 * 3; PN; Layer 4 Port Number 4; Reserved 5; RTH_GEN_CFG; Receive
1440 * Traffic Hashing General Configuration 6; RTH_IT; Receive Traffic
1441 * Hashing Indirection Table 7; RTH_JHASH_CFG; Receive-Traffic
1442 * Hashing Jenkins Hash Configuration 8; RTH_MASK; Receive Traffic
1443 * Hashing Mask 9; RTH_KEY; Receive-Traffic Hashing Key 10; QOS;
1444 * VLAN Quality of Service 11; DS; IP Differentiated Services
1445 * @offset: Applies to RTH_IT, RTH_MASK, RTH_KEY, QOS, DS structures only.
1446 * The interpretation of this field depends on the DATA_STRUCT_SEL
1447 * field:
1448 * RTH_IT - {BUCKET_NUM[0:7]} (Bucket Number)
1449 * RTH_MASK - {5'b0,
1450 * INDEX_8BYTE} (8-byte Index)
1451 * RTH_KEY - {5'b0, INDEX_8BYTE} (8-byte Index)
1452 * QOS - {5'b0, PRI} (Priority)
1453 * DS - {5'b0, CP} (Codepoint)
1454 * @data1: Pointer to the data 1 to be read from the table
1455 * @data2: Pointer to the data 2 to be read from the table
1456 *
1457 * Read from the RTS table
1458 *
1459 */
1460 vxge_hal_status_e
__hal_vpath_rts_table_get(vxge_hal_vpath_h vpath_handle,u32 action,u32 rts_table,u32 offset,u64 * data1,u64 * data2)1461 __hal_vpath_rts_table_get(
1462 vxge_hal_vpath_h vpath_handle,
1463 u32 action,
1464 u32 rts_table,
1465 u32 offset,
1466 u64 *data1,
1467 u64 *data2)
1468 {
1469 u64 val64;
1470 __hal_device_t *hldev;
1471 __hal_virtualpath_t *vpath;
1472 vxge_hal_status_e status = VXGE_HAL_OK;
1473
1474 vxge_assert((vpath_handle != NULL) &&
1475 (data1 != NULL) && (data2 != NULL));
1476
1477 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
1478
1479 hldev = vpath->hldev;
1480
1481 vxge_hal_trace_log_vpath("==> %s:%s:%d",
1482 __FILE__, __func__, __LINE__);
1483
1484 vxge_hal_trace_log_vpath(
1485 "vpath_handle = 0x"VXGE_OS_STXFMT", action = %d, rts_table = %d, "
1486 "offset = %d, data1 = 0x"VXGE_OS_STXFMT", data2 = 0x"VXGE_OS_STXFMT,
1487 (ptr_t) vpath_handle, action, rts_table, offset, (ptr_t) data1,
1488 (ptr_t) data2);
1489
1490 val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(action) |
1491 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(rts_table) |
1492 VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE |
1493 VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(offset);
1494
1495
1496 if ((rts_table ==
1497 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT) ||
1498 (rts_table ==
1499 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT) ||
1500 (rts_table ==
1501 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK) ||
1502 (rts_table ==
1503 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY)) {
1504 val64 |= VXGE_HAL_RTS_ACCESS_STEER_CTRL_TABLE_SEL;
1505 }
1506
1507 vxge_hal_pio_mem_write32_lower(hldev->header.pdev,
1508 hldev->header.regh0,
1509 (u32) bVAL32(val64, 32),
1510 &vpath->vp_reg->rts_access_steer_ctrl);
1511
1512 vxge_os_wmb();
1513
1514 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
1515 hldev->header.regh0,
1516 (u32) bVAL32(val64, 0),
1517 &vpath->vp_reg->rts_access_steer_ctrl);
1518
1519 vxge_os_wmb();
1520
1521 status = vxge_hal_device_register_poll(
1522 hldev->header.pdev,
1523 hldev->header.regh0,
1524 &vpath->vp_reg->rts_access_steer_ctrl, 0,
1525 VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE,
1526 WAIT_FACTOR * hldev->header.config.device_poll_millis);
1527
1528 if (status != VXGE_HAL_OK) {
1529
1530 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
1531 __FILE__, __func__, __LINE__, status);
1532 return (status);
1533 }
1534
1535 val64 = vxge_os_pio_mem_read64(
1536 hldev->header.pdev,
1537 hldev->header.regh0,
1538 &vpath->vp_reg->rts_access_steer_ctrl);
1539
1540 if (!(val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS)) {
1541 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
1542 __FILE__, __func__, __LINE__,
1543 VXGE_HAL_FAIL);
1544 return (VXGE_HAL_FAIL);
1545 }
1546
1547 *data1 = vxge_os_pio_mem_read64(
1548 hldev->header.pdev,
1549 hldev->header.regh0,
1550 &vpath->vp_reg->rts_access_steer_data0);
1551
1552 if ((rts_table ==
1553 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) ||
1554 (rts_table ==
1555 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT)) {
1556 *data2 = vxge_os_pio_mem_read64(
1557 hldev->header.pdev,
1558 hldev->header.regh0,
1559 &vpath->vp_reg->rts_access_steer_data1);
1560 }
1561
1562 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: 0",
1563 __FILE__, __func__, __LINE__);
1564
1565 return (VXGE_HAL_OK);
1566 }
1567
1568 /*
1569 * __hal_vpath_rts_table_set - Set the entries of RTS access tables
1570 * @vpath_handle: Vpath handle.
1571 * @action: Identifies the action to take on the specified entry. The
1572 * interpretation of this field depends on DATA_STRUCT_SEL field
1573 * DA, VID, ETYPE, PN, RANGE_PN:
1574 * 8'd0 - ADD_ENTRY (Add an entry to the table. This command may be
1575 * rejected by management/administration).
1576 * 8'd1 - DELETE_ENTRY (Add an entry to the table. This command may
1577 * be rejected by management/administration)
1578 * 8'd2 - LIST_FIRST_ENTRY
1579 * 8'd3 - LIST_NEXT_ENTRY
1580 * RTH_GEN_CFG, RTH_IT, RTH_JHASH_CFG, RTH_MASK, RTH_KEY, QOS, DS:
1581 * 8'd0 - READ_ENTRY
1582 * 8'd1 - WRITE_ENTRY
1583 * Note: This field is updated by the H/W during an operation and
1584 * is used to report additional TBD status information back to the
1585 * host.
1586 * @rts_table: Identifies the RTS data structure (i.e. lookup table) to access.
1587 * 0; DA; Destination Address 1; VID; VLAN ID 2; ETYPE; Ethertype
1588 * 3; PN; Layer 4 Port Number 4; Reserved 5; RTH_GEN_CFG; Receive
1589 * Traffic Hashing General Configuration 6; RTH_IT; Receive Traffic
1590 * Hashing Indirection Table 7; RTH_JHASH_CFG; Receive-Traffic
1591 * Hashing Jenkins Hash Configuration 8; RTH_MASK; Receive Traffic
1592 * Hashing Mask 9; RTH_KEY; Receive-Traffic Hashing Key 10; QOS;
1593 * VLAN Quality of Service 11; DS; IP Differentiated Services
1594 * @offset: Applies to RTH_IT, RTH_MASK, RTH_KEY, QOS, DS structures only.
1595 * The interpretation of this field depends on the DATA_STRUCT_SEL
1596 * field:
1597 * RTH_IT - {BUCKET_NUM[0:7]} (Bucket Number)
1598 * RTH_MASK - {5'b0,
1599 * INDEX_8BYTE} (8-byte Index)
1600 * RTH_KEY - {5'b0, INDEX_8BYTE} (8-byte Index)
1601 * QOS - {5'b0, PRI} (Priority)
1602 * DS - {5'b0, CP} (Codepoint)
1603 * @data1: data 1 to be written to the table
1604 * @data2: data 2 to be written to the table
1605 *
1606 * Read from the RTS table
1607 *
1608 */
1609 vxge_hal_status_e
__hal_vpath_rts_table_set(vxge_hal_vpath_h vpath_handle,u32 action,u32 rts_table,u32 offset,u64 data1,u64 data2)1610 __hal_vpath_rts_table_set(
1611 vxge_hal_vpath_h vpath_handle,
1612 u32 action,
1613 u32 rts_table,
1614 u32 offset,
1615 u64 data1,
1616 u64 data2)
1617 {
1618 u64 val64;
1619 __hal_device_t *hldev;
1620 __hal_virtualpath_t *vpath;
1621 vxge_hal_status_e status = VXGE_HAL_OK;
1622
1623 vxge_assert(vpath_handle != NULL);
1624
1625 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
1626
1627 hldev = vpath->hldev;
1628
1629 vxge_hal_trace_log_vpath("==> %s:%s:%d",
1630 __FILE__, __func__, __LINE__);
1631
1632 vxge_hal_trace_log_vpath(
1633 "vpath_handle = 0x"VXGE_OS_STXFMT", action = %d, rts_table = %d, "
1634 "offset = %d, data1 = 0x"VXGE_OS_LLXFMT", data2 = 0x"VXGE_OS_LLXFMT,
1635 (ptr_t) vpath_handle, action, rts_table, offset, data1, data2);
1636
1637 vxge_os_pio_mem_write64(hldev->header.pdev,
1638 hldev->header.regh0,
1639 data1,
1640 &vpath->vp_reg->rts_access_steer_data0);
1641 vxge_os_wmb();
1642
1643 if ((rts_table ==
1644 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) ||
1645 (rts_table ==
1646 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT)) {
1647 vxge_os_pio_mem_write64(hldev->header.pdev,
1648 hldev->header.regh0,
1649 data2,
1650 &vpath->vp_reg->rts_access_steer_data1);
1651 vxge_os_wmb();
1652
1653 }
1654
1655 val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(action) |
1656 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(rts_table) |
1657 VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE |
1658 VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(offset);
1659
1660 vxge_hal_pio_mem_write32_lower(hldev->header.pdev,
1661 hldev->header.regh0,
1662 (u32) bVAL32(val64, 32),
1663 &vpath->vp_reg->rts_access_steer_ctrl);
1664
1665 vxge_os_wmb();
1666
1667 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
1668 hldev->header.regh0,
1669 (u32) bVAL32(val64, 0),
1670 &vpath->vp_reg->rts_access_steer_ctrl);
1671
1672 vxge_os_wmb();
1673
1674 status = vxge_hal_device_register_poll(
1675 hldev->header.pdev,
1676 hldev->header.regh0,
1677 &vpath->vp_reg->rts_access_steer_ctrl, 0,
1678 VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE,
1679 WAIT_FACTOR * hldev->header.config.device_poll_millis);
1680
1681 if (status != VXGE_HAL_OK) {
1682
1683 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
1684 __FILE__, __func__, __LINE__, status);
1685 return (status);
1686 }
1687
1688 val64 = vxge_os_pio_mem_read64(
1689 hldev->header.pdev,
1690 hldev->header.regh0,
1691 &vpath->vp_reg->rts_access_steer_ctrl);
1692
1693 if (val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
1694
1695 status = VXGE_HAL_OK;
1696
1697 } else {
1698 status = VXGE_HAL_FAIL;
1699 }
1700
1701
1702 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
1703 __FILE__, __func__, __LINE__, status);
1704 return (status);
1705 }
1706
1707
1708 /*
1709 * vxge_hal_vpath_mac_addr_add - Add the mac address entry for this vpath
1710 * to MAC address table.
1711 * @vpath_handle: Vpath handle.
1712 * @macaddr: MAC address to be added for this vpath into the list
1713 * @macaddr_mask: MAC address mask for macaddr
1714 * @duplicate_mode: Duplicate MAC address add mode. Please see
1715 * vxge_hal_vpath_mac_addr_add_mode_e {}
1716 *
1717 * Adds the given mac address and mac address mask into the list for this
1718 * vpath.
1719 * see also: vxge_hal_vpath_mac_addr_delete, vxge_hal_vpath_mac_addr_get and
1720 * vxge_hal_vpath_mac_addr_get_next
1721 *
1722 */
1723 vxge_hal_status_e
vxge_hal_vpath_mac_addr_add(vxge_hal_vpath_h vpath_handle,macaddr_t macaddr,macaddr_t macaddr_mask,vxge_hal_vpath_mac_addr_add_mode_e duplicate_mode)1724 vxge_hal_vpath_mac_addr_add(
1725 vxge_hal_vpath_h vpath_handle,
1726 macaddr_t macaddr,
1727 macaddr_t macaddr_mask,
1728 vxge_hal_vpath_mac_addr_add_mode_e duplicate_mode)
1729 {
1730 u32 i;
1731 u64 data1 = 0ULL;
1732 u64 data2 = 0ULL;
1733 __hal_device_t *hldev;
1734 __hal_virtualpath_t *vpath;
1735 vxge_hal_status_e status = VXGE_HAL_OK;
1736
1737 vxge_assert(vpath_handle != NULL);
1738
1739 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
1740
1741 hldev = vpath->hldev;
1742
1743 vxge_hal_trace_log_vpath("==> %s:%s:%d",
1744 __FILE__, __func__, __LINE__);
1745
1746 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT", "
1747 "macaddr = %02x-%02x-%02x-%02x-%02x-%02x, "
1748 "macaddr_mask = %02x-%02x-%02x-%02x-%02x-%02x",
1749 (ptr_t) vpath_handle, macaddr[0], macaddr[1], macaddr[2],
1750 macaddr[3], macaddr[4], macaddr[5], macaddr_mask[0],
1751 macaddr_mask[1], macaddr_mask[2], macaddr_mask[3],
1752 macaddr_mask[4], macaddr_mask[5]);
1753
1754 for (i = 0; i < VXGE_HAL_ETH_ALEN; i++) {
1755 data1 <<= 8;
1756 data1 |= (u8) macaddr[i];
1757 }
1758
1759 for (i = 0; i < VXGE_HAL_ETH_ALEN; i++) {
1760 data2 <<= 8;
1761 data2 |= (u8) macaddr_mask[i];
1762 }
1763
1764 switch (duplicate_mode) {
1765 case VXGE_HAL_VPATH_MAC_ADDR_ADD_DUPLICATE:
1766 i = 0;
1767 break;
1768
1769 case VXGE_HAL_VPATH_MAC_ADDR_DISCARD_DUPLICATE:
1770 i = 1;
1771 break;
1772
1773 case VXGE_HAL_VPATH_MAC_ADDR_REPLACE_DUPLICATE:
1774 i = 2;
1775 break;
1776
1777 default:
1778 i = 0;
1779 break;
1780 }
1781
1782 status = __hal_vpath_rts_table_set(vpath_handle,
1783 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_ADD_ENTRY,
1784 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
1785 0,
1786 VXGE_HAL_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(data1),
1787 VXGE_HAL_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MASK(data2) |
1788 VXGE_HAL_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MODE(i));
1789
1790 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
1791 __FILE__, __func__, __LINE__,
1792 status);
1793
1794 return (status);
1795 }
1796
1797 /*
1798 * __hal_vpath_hw_addr_get - Get the hw address entry for this vpath
1799 * from MAC address table.
1800 * @pdev: PCI device object.
1801 * @regh0: BAR0 mapped memory handle, or simply PCI device @pdev
1802 * (Linux and the rest.)
1803 * @vp_id: Vpath id
1804 * @vpath_reg: Pointer to vpath registers
1805 * @macaddr: First MAC address entry for this vpath in the list
1806 * @macaddr_mask: MAC address mask for macaddr
1807 *
1808 * Returns the first mac address and mac address mask in the list for this
1809 * vpath.
1810 * see also: vxge_hal_vpath_mac_addr_get_next
1811 *
1812 */
1813 vxge_hal_status_e
__hal_vpath_hw_addr_get(pci_dev_h pdev,pci_reg_h regh0,u32 vp_id,vxge_hal_vpath_reg_t * vpath_reg,macaddr_t macaddr,macaddr_t macaddr_mask)1814 __hal_vpath_hw_addr_get(
1815 pci_dev_h pdev,
1816 pci_reg_h regh0,
1817 u32 vp_id,
1818 vxge_hal_vpath_reg_t *vpath_reg,
1819 macaddr_t macaddr,
1820 macaddr_t macaddr_mask)
1821 {
1822 u32 i;
1823 u64 val64;
1824 u64 data1 = 0ULL;
1825 u64 data2 = 0ULL;
1826 u64 action = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY;
1827 vxge_hal_status_e status = VXGE_HAL_OK;
1828
1829 vxge_assert((vpath_reg != NULL) && (macaddr != NULL) &&
1830 (macaddr_mask != NULL));
1831
1832 vxge_hal_trace_log_driver("==> %s:%s:%d",
1833 __FILE__, __func__, __LINE__);
1834
1835 vxge_hal_trace_log_driver(
1836 "pdev = 0x"VXGE_OS_STXFMT", regh0 = 0x"VXGE_OS_STXFMT", "
1837 "vp_id = %d, vpath_reg = 0x"VXGE_OS_STXFMT", "
1838 "macaddr = 0x"VXGE_OS_STXFMT", macaddr_mask = 0x"VXGE_OS_STXFMT,
1839 (ptr_t) pdev, (ptr_t) regh0, vp_id, (ptr_t) vpath_reg,
1840 (ptr_t) macaddr, (ptr_t) macaddr_mask);
1841
1842 /* CONSTCOND */
1843 while (TRUE) {
1844
1845 val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(action) |
1846 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
1847 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) |
1848 VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE |
1849 VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(0);
1850
1851 vxge_hal_pio_mem_write32_lower(pdev,
1852 regh0,
1853 (u32) bVAL32(val64, 32),
1854 &vpath_reg->rts_access_steer_ctrl);
1855
1856 vxge_os_wmb();
1857
1858 vxge_hal_pio_mem_write32_upper(pdev,
1859 regh0,
1860 (u32) bVAL32(val64, 0),
1861 &vpath_reg->rts_access_steer_ctrl);
1862
1863 vxge_os_wmb();
1864
1865 status = vxge_hal_device_register_poll(pdev, regh0,
1866 &vpath_reg->rts_access_steer_ctrl, 0,
1867 VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE,
1868 WAIT_FACTOR * VXGE_HAL_DEF_DEVICE_POLL_MILLIS);
1869
1870 if (status != VXGE_HAL_OK) {
1871
1872 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
1873 __FILE__, __func__, __LINE__, status);
1874 return (status);
1875 }
1876
1877 val64 = vxge_os_pio_mem_read64(pdev, regh0,
1878 &vpath_reg->rts_access_steer_ctrl);
1879
1880 if (val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
1881 data1 = vxge_os_pio_mem_read64(pdev, regh0,
1882 &vpath_reg->rts_access_steer_data0);
1883 data2 = vxge_os_pio_mem_read64(pdev, regh0,
1884 &vpath_reg->rts_access_steer_data1);
1885 data1 =
1886 VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data1);
1887 data2 =
1888 VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(data2);
1889
1890 if (VXGE_HAL_IS_UNICAST(data1)) {
1891
1892 for (i = VXGE_HAL_ETH_ALEN; i > 0; i--) {
1893 macaddr[i - 1] = (u8) (data1 & 0xFF);
1894 data1 >>= 8;
1895 }
1896 for (i = VXGE_HAL_ETH_ALEN; i > 0; i--) {
1897 macaddr_mask[i - 1] = (u8) (data2 & 0xFF);
1898 data2 >>= 8;
1899 }
1900 status = VXGE_HAL_OK;
1901 break;
1902 }
1903 action = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY;
1904 } else {
1905 status = VXGE_HAL_FAIL;
1906 break;
1907 }
1908 }
1909
1910 vxge_hal_trace_log_driver("<== %s:%s:%d Result: %d",
1911 __FILE__, __func__, __LINE__, status);
1912
1913 return (status);
1914 }
1915
1916 /*
1917 * vxge_hal_vpath_mac_addr_get - Get the first mac address entry for this vpath
1918 * from MAC address table.
1919 * @vpath_handle: Vpath handle.
1920 * @macaddr: First MAC address entry for this vpath in the list
1921 * @macaddr_mask: MAC address mask for macaddr
1922 *
1923 * Returns the first mac address and mac address mask in the list for this
1924 * vpath.
1925 * see also: vxge_hal_vpath_mac_addr_get_next
1926 *
1927 */
1928 vxge_hal_status_e
vxge_hal_vpath_mac_addr_get(vxge_hal_vpath_h vpath_handle,macaddr_t macaddr,macaddr_t macaddr_mask)1929 vxge_hal_vpath_mac_addr_get(
1930 vxge_hal_vpath_h vpath_handle,
1931 macaddr_t macaddr,
1932 macaddr_t macaddr_mask)
1933 {
1934 u32 i;
1935 u64 data1 = 0ULL;
1936 u64 data2 = 0ULL;
1937 __hal_device_t *hldev;
1938 vxge_hal_status_e status = VXGE_HAL_OK;
1939 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
1940
1941 vxge_assert(vpath_handle != NULL);
1942
1943 hldev = vp->vpath->hldev;
1944
1945 vxge_hal_trace_log_vpath("==> %s:%s:%d",
1946 __FILE__, __func__, __LINE__);
1947
1948 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
1949 (ptr_t) vpath_handle);
1950
1951 status = __hal_vpath_rts_table_get(vpath_handle,
1952 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY,
1953 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
1954 0,
1955 &data1,
1956 &data2);
1957
1958 if (status != VXGE_HAL_OK) {
1959
1960 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
1961 __FILE__, __func__, __LINE__, status);
1962 return (status);
1963 }
1964
1965 data1 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data1);
1966
1967 data2 = VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(data2);
1968
1969 for (i = VXGE_HAL_ETH_ALEN; i > 0; i--) {
1970 macaddr[i - 1] = (u8) (data1 & 0xFF);
1971 data1 >>= 8;
1972 }
1973
1974 for (i = VXGE_HAL_ETH_ALEN; i > 0; i--) {
1975 macaddr_mask[i - 1] = (u8) (data2 & 0xFF);
1976 data2 >>= 8;
1977 }
1978
1979 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
1980 __FILE__, __func__, __LINE__,
1981 status);
1982
1983 return (status);
1984 }
1985
1986 /*
1987 * vxge_hal_vpath_mac_addr_get_next - Get the next mac address entry for vpath
1988 * from MAC address table.
1989 * @vpath_handle: Vpath handle.
1990 * @macaddr: Next MAC address entry for this vpath in the list
1991 * @macaddr_mask: MAC address mask for macaddr
1992 *
1993 * Returns the next mac address and mac address mask in the list for this
1994 * vpath.
1995 * see also: vxge_hal_vpath_mac_addr_get
1996 *
1997 */
1998 vxge_hal_status_e
vxge_hal_vpath_mac_addr_get_next(vxge_hal_vpath_h vpath_handle,macaddr_t macaddr,macaddr_t macaddr_mask)1999 vxge_hal_vpath_mac_addr_get_next(
2000 vxge_hal_vpath_h vpath_handle,
2001 macaddr_t macaddr,
2002 macaddr_t macaddr_mask)
2003 {
2004 u32 i;
2005 u64 data1 = 0ULL;
2006 u64 data2 = 0ULL;
2007 __hal_device_t *hldev;
2008 vxge_hal_status_e status = VXGE_HAL_OK;
2009 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
2010
2011 vxge_assert(vpath_handle != NULL);
2012
2013 hldev = vp->vpath->hldev;
2014
2015 vxge_hal_trace_log_vpath("==> %s:%s:%d",
2016 __FILE__, __func__, __LINE__);
2017
2018 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
2019 (ptr_t) vpath_handle);
2020
2021 status = __hal_vpath_rts_table_get(vpath_handle,
2022 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY,
2023 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
2024 0,
2025 &data1,
2026 &data2);
2027
2028 if (status != VXGE_HAL_OK) {
2029
2030 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
2031 __FILE__, __func__, __LINE__, status);
2032 return (status);
2033 }
2034
2035 data1 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data1);
2036
2037 data2 = VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(data2);
2038
2039 for (i = VXGE_HAL_ETH_ALEN; i > 0; i--) {
2040 macaddr[i - 1] = (u8) (data1 & 0xFF);
2041 data1 >>= 8;
2042 }
2043
2044 for (i = VXGE_HAL_ETH_ALEN; i > 0; i--) {
2045 macaddr_mask[i - 1] = (u8) (data2 & 0xFF);
2046 data2 >>= 8;
2047 }
2048
2049 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
2050 __FILE__, __func__, __LINE__, status);
2051 return (status);
2052 }
2053
2054
2055 /*
2056 * vxge_hal_vpath_mac_addr_delete - Delete the mac address entry for this vpath
2057 * to MAC address table.
2058 * @vpath_handle: Vpath handle.
2059 * @macaddr: MAC address to be added for this vpath into the list
2060 * @macaddr_mask: MAC address mask for macaddr
2061 *
2062 * Delete the given mac address and mac address mask into the list for this
2063 * vpath.
2064 * see also: vxge_hal_vpath_mac_addr_add, vxge_hal_vpath_mac_addr_get and
2065 * vxge_hal_vpath_mac_addr_get_next
2066 *
2067 */
2068 vxge_hal_status_e
vxge_hal_vpath_mac_addr_delete(vxge_hal_vpath_h vpath_handle,macaddr_t macaddr,macaddr_t macaddr_mask)2069 vxge_hal_vpath_mac_addr_delete(
2070 vxge_hal_vpath_h vpath_handle,
2071 macaddr_t macaddr,
2072 macaddr_t macaddr_mask)
2073 {
2074 u32 i;
2075 u64 data1 = 0ULL;
2076 u64 data2 = 0ULL;
2077 __hal_device_t *hldev;
2078 vxge_hal_status_e status = VXGE_HAL_OK;
2079 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
2080
2081 vxge_assert(vpath_handle != NULL);
2082
2083 hldev = vp->vpath->hldev;
2084
2085 vxge_hal_trace_log_vpath("==> %s:%s:%d",
2086 __FILE__, __func__, __LINE__);
2087
2088 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT", "
2089 "macaddr = %02x-%02x-%02x-%02x-%02x-%02x, "
2090 "macaddr_mask = %02x-%02x-%02x-%02x-%02x-%02x",
2091 (ptr_t) vpath_handle, macaddr[0], macaddr[1], macaddr[2],
2092 macaddr[3], macaddr[4], macaddr[5], macaddr_mask[0],
2093 macaddr_mask[1], macaddr_mask[2], macaddr_mask[3],
2094 macaddr_mask[4], macaddr_mask[5]);
2095
2096 for (i = 0; i < VXGE_HAL_ETH_ALEN; i++) {
2097 data1 <<= 8;
2098 data1 |= (u8) macaddr[i];
2099 }
2100
2101 for (i = 0; i < VXGE_HAL_ETH_ALEN; i++) {
2102 data2 <<= 8;
2103 data2 |= (u8) macaddr_mask[i];
2104 }
2105
2106 status = __hal_vpath_rts_table_set(vpath_handle,
2107 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_DELETE_ENTRY,
2108 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
2109 0,
2110 VXGE_HAL_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(data1),
2111 VXGE_HAL_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MASK(data2));
2112
2113 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
2114 __FILE__, __func__, __LINE__, status);
2115 return (status);
2116 }
2117
2118 /*
2119 * vxge_hal_vpath_vid_add - Add the vlan id entry for this vpath
2120 * to vlan id table.
2121 * @vpath_handle: Vpath handle.
2122 * @vid: vlan id to be added for this vpath into the list
2123 *
2124 * Adds the given vlan id into the list for this vpath.
2125 * see also: vxge_hal_vpath_vid_delete, vxge_hal_vpath_vid_get and
2126 * vxge_hal_vpath_vid_get_next
2127 *
2128 */
2129 vxge_hal_status_e
vxge_hal_vpath_vid_add(vxge_hal_vpath_h vpath_handle,u64 vid)2130 vxge_hal_vpath_vid_add(
2131 vxge_hal_vpath_h vpath_handle,
2132 u64 vid)
2133 {
2134 __hal_device_t *hldev;
2135 vxge_hal_status_e status = VXGE_HAL_OK;
2136 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
2137
2138 vxge_assert(vpath_handle != NULL);
2139
2140 hldev = vp->vpath->hldev;
2141
2142 vxge_hal_trace_log_vpath("==> %s:%s:%d",
2143 __FILE__, __func__, __LINE__);
2144
2145 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT", vid = %d",
2146 (ptr_t) vpath_handle, (u32) vid);
2147
2148 status = __hal_vpath_rts_table_set(vpath_handle,
2149 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_ADD_ENTRY,
2150 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID,
2151 0,
2152 VXGE_HAL_RTS_ACCESS_STEER_DATA0_VLAN_ID(vid),
2153 0);
2154
2155 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
2156 __FILE__, __func__, __LINE__, status);
2157 return (status);
2158 }
2159
2160 /*
2161 * vxge_hal_vpath_vid_get - Get the first vid entry for this vpath
2162 * from vlan id table.
2163 * @vpath_handle: Vpath handle.
2164 * @vid: Buffer to return vlan id
2165 *
2166 * Returns the first vlan id in the list for this vpath.
2167 * see also: vxge_hal_vpath_vid_get_next
2168 *
2169 */
2170 vxge_hal_status_e
vxge_hal_vpath_vid_get(vxge_hal_vpath_h vpath_handle,u64 * vid)2171 vxge_hal_vpath_vid_get(
2172 vxge_hal_vpath_h vpath_handle,
2173 u64 *vid)
2174 {
2175 __hal_device_t *hldev;
2176 vxge_hal_status_e status = VXGE_HAL_OK;
2177 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
2178
2179 vxge_assert((vpath_handle != NULL) && (vid != NULL));
2180
2181 hldev = vp->vpath->hldev;
2182
2183 vxge_hal_trace_log_vpath("==> %s:%s:%d",
2184 __FILE__, __func__, __LINE__);
2185
2186 vxge_hal_trace_log_vpath(
2187 "vpath_handle = 0x"VXGE_OS_STXFMT", vid = 0x"VXGE_OS_STXFMT,
2188 (ptr_t) vpath_handle, (ptr_t) vid);
2189
2190 status = __hal_vpath_rts_table_get(vpath_handle,
2191 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY,
2192 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID,
2193 0,
2194 vid,
2195 NULL);
2196
2197 *vid = VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_VLAN_ID(*vid);
2198
2199 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
2200 __FILE__, __func__, __LINE__,
2201 status);
2202
2203 return (status);
2204 }
2205
2206 /*
2207 * vxge_hal_vpath_vid_get_next - Get the next vid entry for this vpath
2208 * from vlan id table.
2209 * @vpath_handle: Vpath handle.
2210 * @vid: Buffer to return vlan id
2211 *
2212 * Returns the next vlan id in the list for this vpath.
2213 * see also: vxge_hal_vpath_vid_get
2214 *
2215 */
2216 vxge_hal_status_e
vxge_hal_vpath_vid_get_next(vxge_hal_vpath_h vpath_handle,u64 * vid)2217 vxge_hal_vpath_vid_get_next(
2218 vxge_hal_vpath_h vpath_handle,
2219 u64 *vid)
2220 {
2221 __hal_device_t *hldev;
2222 vxge_hal_status_e status = VXGE_HAL_OK;
2223 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
2224
2225 vxge_assert((vpath_handle != NULL) && (vid != NULL));
2226
2227 hldev = vp->vpath->hldev;
2228
2229 vxge_hal_trace_log_vpath("==> %s:%s:%d",
2230 __FILE__, __func__, __LINE__);
2231
2232 vxge_hal_trace_log_vpath(
2233 "vpath_handle = 0x"VXGE_OS_STXFMT", vid = 0x"VXGE_OS_STXFMT,
2234 (ptr_t) vpath_handle, (ptr_t) vid);
2235
2236 status = __hal_vpath_rts_table_get(vpath_handle,
2237 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY,
2238 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID,
2239 0,
2240 vid,
2241 NULL);
2242
2243 *vid = VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_VLAN_ID(*vid);
2244
2245 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
2246 __FILE__, __func__, __LINE__, status);
2247
2248 return (status);
2249 }
2250
2251 /*
2252 * vxge_hal_vpath_vid_delete - Delete the vlan id entry for this vpath
2253 * to vlan id table.
2254 * @vpath_handle: Vpath handle.
2255 * @vid: vlan id to be added for this vpath into the list
2256 *
2257 * Adds the given vlan id into the list for this vpath.
2258 * see also: vxge_hal_vpath_vid_add, vxge_hal_vpath_vid_get and
2259 * vxge_hal_vpath_vid_get_next
2260 *
2261 */
2262 vxge_hal_status_e
vxge_hal_vpath_vid_delete(vxge_hal_vpath_h vpath_handle,u64 vid)2263 vxge_hal_vpath_vid_delete(
2264 vxge_hal_vpath_h vpath_handle,
2265 u64 vid)
2266 {
2267 __hal_device_t *hldev;
2268 vxge_hal_status_e status = VXGE_HAL_OK;
2269 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
2270
2271 vxge_assert(vpath_handle != NULL);
2272
2273 hldev = vp->vpath->hldev;
2274
2275 vxge_hal_trace_log_vpath("==> %s:%s:%d",
2276 __FILE__, __func__, __LINE__);
2277
2278 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT", vid = %d",
2279 (ptr_t) vpath_handle, (u32) vid);
2280
2281 status = __hal_vpath_rts_table_set(vpath_handle,
2282 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_DELETE_ENTRY,
2283 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID,
2284 0,
2285 VXGE_HAL_RTS_ACCESS_STEER_DATA0_VLAN_ID(vid),
2286 0);
2287
2288 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
2289 __FILE__, __func__, __LINE__,
2290 status);
2291
2292 return (status);
2293 }
2294
2295 /*
2296 * vxge_hal_vpath_etype_add - Add the Ethertype entry for this vpath
2297 * to Ethertype table.
2298 * @vpath_handle: Vpath handle.
2299 * @etype: ethertype to be added for this vpath into the list
2300 *
2301 * Adds the given Ethertype into the list for this vpath.
2302 * see also: vxge_hal_vpath_etype_delete, vxge_hal_vpath_etype_get and
2303 * vxge_hal_vpath_etype_get_next
2304 *
2305 */
2306 vxge_hal_status_e
vxge_hal_vpath_etype_add(vxge_hal_vpath_h vpath_handle,u64 etype)2307 vxge_hal_vpath_etype_add(
2308 vxge_hal_vpath_h vpath_handle,
2309 u64 etype)
2310 {
2311 __hal_device_t *hldev;
2312 vxge_hal_status_e status = VXGE_HAL_OK;
2313 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
2314
2315 vxge_assert(vpath_handle != NULL);
2316
2317 hldev = vp->vpath->hldev;
2318
2319 vxge_hal_trace_log_vpath("==> %s:%s:%d",
2320 __FILE__, __func__, __LINE__);
2321
2322 vxge_hal_trace_log_vpath("vpath_handle = 0x"
2323 VXGE_OS_STXFMT", etype = %d",
2324 (ptr_t) vpath_handle, (u32) etype);
2325
2326 status = __hal_vpath_rts_table_set(vpath_handle,
2327 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_ADD_ENTRY,
2328 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_ETYPE,
2329 0,
2330 VXGE_HAL_RTS_ACCESS_STEER_DATA0_ETYPE(etype),
2331 0);
2332
2333 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
2334 __FILE__, __func__, __LINE__, status);
2335
2336 return (status);
2337 }
2338
2339 /*
2340 * vxge_hal_vpath_etype_get - Get the first ethertype entry for this vpath
2341 * from Ethertype table.
2342 * @vpath_handle: Vpath handle.
2343 * @etype: Buffer to return Ethertype
2344 *
2345 * Returns the first ethype entry in the list for this vpath.
2346 * see also: vxge_hal_vpath_etype_get_next
2347 *
2348 */
2349 vxge_hal_status_e
vxge_hal_vpath_etype_get(vxge_hal_vpath_h vpath_handle,u64 * etype)2350 vxge_hal_vpath_etype_get(
2351 vxge_hal_vpath_h vpath_handle,
2352 u64 *etype)
2353 {
2354 __hal_device_t *hldev;
2355 vxge_hal_status_e status = VXGE_HAL_OK;
2356 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
2357
2358 vxge_assert((vpath_handle != NULL) && (etype != NULL));
2359
2360 hldev = vp->vpath->hldev;
2361
2362 vxge_hal_trace_log_vpath("==> %s:%s:%d",
2363 __FILE__, __func__, __LINE__);
2364
2365 vxge_hal_trace_log_vpath(
2366 "vpath_handle = 0x"VXGE_OS_STXFMT", etype = 0x"VXGE_OS_STXFMT,
2367 (ptr_t) vpath_handle, (ptr_t) etype);
2368
2369 status = __hal_vpath_rts_table_get(vpath_handle,
2370 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY,
2371 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_ETYPE,
2372 0,
2373 etype,
2374 NULL);
2375
2376 *etype = VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_ETYPE(*etype);
2377
2378 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
2379 __FILE__, __func__, __LINE__, status);
2380 return (status);
2381 }
2382
2383 /*
2384 * vxge_hal_vpath_etype_get_next - Get the next Ethertype entry for this vpath
2385 * from Ethertype table.
2386 * @vpath_handle: Vpath handle.
2387 * @etype: Buffer to return Ethwrtype
2388 *
2389 * Returns the next Ethwrtype in the list for this vpath.
2390 * see also: vxge_hal_vpath_etype_get
2391 *
2392 */
2393 vxge_hal_status_e
vxge_hal_vpath_etype_get_next(vxge_hal_vpath_h vpath_handle,u64 * etype)2394 vxge_hal_vpath_etype_get_next(
2395 vxge_hal_vpath_h vpath_handle,
2396 u64 *etype)
2397 {
2398 __hal_device_t *hldev;
2399 vxge_hal_status_e status = VXGE_HAL_OK;
2400 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
2401
2402 vxge_assert((vpath_handle != NULL) && (etype != NULL));
2403
2404 hldev = vp->vpath->hldev;
2405
2406 vxge_hal_trace_log_vpath("==> %s:%s:%d",
2407 __FILE__, __func__, __LINE__);
2408
2409 vxge_hal_trace_log_vpath(
2410 "vpath_handle = 0x"VXGE_OS_STXFMT", etype = 0x"VXGE_OS_STXFMT,
2411 (ptr_t) vpath_handle, (ptr_t) etype);
2412
2413 status = __hal_vpath_rts_table_get(vpath_handle,
2414 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY,
2415 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_ETYPE,
2416 0,
2417 etype,
2418 NULL);
2419
2420 *etype = VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_ETYPE(*etype);
2421
2422 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
2423 __FILE__, __func__, __LINE__,
2424 status);
2425
2426 return (status);
2427 }
2428
2429 /*
2430 * vxge_hal_vpath_etype_delete - Delete the Ethertype entry for this vpath
2431 * to Ethertype table.
2432 * @vpath_handle: Vpath handle.
2433 * @etype: ethertype to be added for this vpath into the list
2434 *
2435 * Adds the given Ethertype into the list for this vpath.
2436 * see also: vxge_hal_vpath_etype_add, vxge_hal_vpath_etype_get and
2437 * vxge_hal_vpath_etype_get_next
2438 *
2439 */
2440 vxge_hal_status_e
vxge_hal_vpath_etype_delete(vxge_hal_vpath_h vpath_handle,u64 etype)2441 vxge_hal_vpath_etype_delete(vxge_hal_vpath_h vpath_handle, u64 etype)
2442 {
2443 __hal_device_t *hldev;
2444 vxge_hal_status_e status = VXGE_HAL_OK;
2445 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
2446
2447 vxge_assert(vpath_handle != NULL);
2448
2449 hldev = vp->vpath->hldev;
2450
2451 vxge_hal_trace_log_vpath("==> %s:%s:%d",
2452 __FILE__, __func__, __LINE__);
2453
2454 vxge_hal_trace_log_vpath("vpath_handle = 0x"
2455 VXGE_OS_STXFMT", etype = %d",
2456 (ptr_t) vpath_handle, (u32) etype);
2457
2458 status = __hal_vpath_rts_table_set(vpath_handle,
2459 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_DELETE_ENTRY,
2460 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_ETYPE,
2461 0,
2462 VXGE_HAL_RTS_ACCESS_STEER_DATA0_ETYPE(etype),
2463 0);
2464
2465 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
2466 __FILE__, __func__, __LINE__, status);
2467
2468 return (status);
2469 }
2470
2471 /*
2472 * vxge_hal_vpath_port_add - Add the port entry for this vpath
2473 * to port number table.
2474 * @vpath_handle: Vpath handle.
2475 * @port_type: if 0 - Src port or 1 - Dest port
2476 * @protocol: if 0 - TCP or 1 - UDP
2477 * @port: port to be added for this vpath into the list
2478 *
2479 * Adds the given port into the list for this vpath.
2480 * see also: vxge_hal_vpath_port_delete, vxge_hal_vpath_port_get and
2481 * vxge_hal_vpath_port_get_next
2482 *
2483 */
2484 vxge_hal_status_e
vxge_hal_vpath_port_add(vxge_hal_vpath_h vpath_handle,u32 port_type,u32 protocol,u32 port)2485 vxge_hal_vpath_port_add(
2486 vxge_hal_vpath_h vpath_handle,
2487 u32 port_type,
2488 u32 protocol,
2489 u32 port)
2490 {
2491 u64 val64;
2492 __hal_device_t *hldev;
2493 vxge_hal_status_e status = VXGE_HAL_OK;
2494 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
2495
2496 vxge_assert(vpath_handle != NULL);
2497
2498 hldev = vp->vpath->hldev;
2499
2500 vxge_hal_trace_log_vpath("==> %s:%s:%d",
2501 __FILE__, __func__, __LINE__);
2502
2503 vxge_hal_trace_log_vpath(
2504 "vpath_handle = 0x"VXGE_OS_STXFMT", port_type = %d, "
2505 "protocol = %d, port = %d", (ptr_t) vpath_handle, port_type,
2506 protocol, port);
2507
2508 val64 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_PORT_NUM(port);
2509
2510 if (port_type)
2511 val64 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_SRC_DEST_SEL;
2512
2513 if (protocol)
2514 val64 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_TCP_UDP_SEL;
2515
2516 status = __hal_vpath_rts_table_set(vpath_handle,
2517 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_ADD_ENTRY,
2518 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_PN,
2519 0,
2520 val64,
2521 0);
2522
2523 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
2524 __FILE__, __func__, __LINE__,
2525 status);
2526
2527 return (status);
2528 }
2529
2530 /*
2531 * vxge_hal_vpath_port_get
2532 * Get the first port number entry for this vpath from port number table.
2533 * @vpath_handle: Vpath handle.
2534 * @port_type: Buffer to return if 0 - Src port or 1 - Dest port
2535 * @protocol: Buffer to return if 0 - TCP or 1 - UDP
2536 * @port: Buffer to return port number
2537 *
2538 * Returns the first port number entry in the list for this vpath.
2539 * see also: vxge_hal_vpath_port_get_next
2540 *
2541 */
2542 vxge_hal_status_e
vxge_hal_vpath_port_get(vxge_hal_vpath_h vpath_handle,u32 * port_type,u32 * protocol,u32 * port)2543 vxge_hal_vpath_port_get(
2544 vxge_hal_vpath_h vpath_handle,
2545 u32 *port_type,
2546 u32 *protocol,
2547 u32 *port)
2548 {
2549 u64 val64;
2550 __hal_device_t *hldev;
2551 vxge_hal_status_e status = VXGE_HAL_OK;
2552 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
2553
2554 vxge_assert((vpath_handle != NULL) && (port_type != NULL) &&
2555 (protocol != NULL) && (port != NULL));
2556
2557 hldev = vp->vpath->hldev;
2558
2559 vxge_hal_trace_log_vpath("==> %s:%s:%d",
2560 __FILE__, __func__, __LINE__);
2561
2562 vxge_hal_trace_log_vpath(
2563 "vpath_handle = 0x"VXGE_OS_STXFMT", port_type = 0x"VXGE_OS_STXFMT
2564 ", protocol = 0x"VXGE_OS_STXFMT", port = 0x"VXGE_OS_STXFMT,
2565 (ptr_t) vpath_handle, (ptr_t) port_type, (ptr_t) protocol,
2566 (ptr_t) port);
2567
2568 status = __hal_vpath_rts_table_get(vpath_handle,
2569 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY,
2570 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_PN,
2571 0,
2572 &val64,
2573 NULL);
2574
2575 *port_type =
2576 (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_SRC_DEST_SEL(val64);
2577 *protocol =
2578 (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_TCP_UDP_SEL(val64);
2579 *port = (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_PORT_NUM(val64);
2580
2581 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
2582 __FILE__, __func__, __LINE__,
2583 status);
2584
2585 return (status);
2586 }
2587
2588 /*
2589 * vxge_hal_vpath_port_get_next
2590 * Get the next port number entry for this vpath from port number table.
2591 * @vpath_handle: Vpath handle.
2592 * @port_type: Buffer to return if 0 - Src port or 1 - Dest port
2593 * @protocol: Buffer to return if 0 - TCP or 1 - UDP
2594 * @port: Buffer to return port number
2595 *
2596 * Returns the next port number entry in the list for this vpath.
2597 * see also: vxge_hal_vpath_port_get
2598 */
2599 vxge_hal_status_e
vxge_hal_vpath_port_get_next(vxge_hal_vpath_h vpath_handle,u32 * port_type,u32 * protocol,u32 * port)2600 vxge_hal_vpath_port_get_next(
2601 vxge_hal_vpath_h vpath_handle,
2602 u32 *port_type,
2603 u32 *protocol,
2604 u32 *port)
2605 {
2606 u64 val64;
2607 __hal_device_t *hldev;
2608 vxge_hal_status_e status = VXGE_HAL_OK;
2609 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
2610
2611 vxge_assert((vpath_handle != NULL) && (port_type != NULL) &&
2612 (protocol != NULL) && (port != NULL));
2613
2614 hldev = vp->vpath->hldev;
2615
2616 vxge_hal_trace_log_vpath("==> %s:%s:%d",
2617 __FILE__, __func__, __LINE__);
2618
2619 vxge_hal_trace_log_vpath(
2620 "vpath_handle = 0x"VXGE_OS_STXFMT", port_type = 0x"VXGE_OS_STXFMT
2621 ", protocol = 0x"VXGE_OS_STXFMT", port = 0x"VXGE_OS_STXFMT,
2622 (ptr_t) vpath_handle, (ptr_t) port_type, (ptr_t) protocol,
2623 (ptr_t) port);
2624
2625 status = __hal_vpath_rts_table_get(vpath_handle,
2626 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY,
2627 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_PN,
2628 0,
2629 &val64,
2630 NULL);
2631
2632 *port_type =
2633 (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_SRC_DEST_SEL(val64);
2634
2635 *protocol =
2636 (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_TCP_UDP_SEL(val64);
2637
2638 *port = (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_PORT_NUM(val64);
2639
2640 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
2641 __FILE__, __func__, __LINE__,
2642 status);
2643
2644 return (status);
2645 }
2646
2647 /*
2648 * vxge_hal_vpath_port_delete
2649 * Delete the port entry for this vpath to port number table.
2650 * @vpath_handle: Vpath handle.
2651 * @port_type: if 0 - Src port or 1 - Dest port
2652 * @protocol: if 0 - TCP or 1 - UDP
2653 * @port: port to be added for this vpath into the list
2654 *
2655 * Adds the given port into the list for this vpath.
2656 * see also: vxge_hal_vpath_port_add, vxge_hal_vpath_port_get and
2657 * vxge_hal_vpath_port_get_next
2658 *
2659 */
2660 vxge_hal_status_e
vxge_hal_vpath_port_delete(vxge_hal_vpath_h vpath_handle,u32 port_type,u32 protocol,u32 port)2661 vxge_hal_vpath_port_delete(
2662 vxge_hal_vpath_h vpath_handle,
2663 u32 port_type,
2664 u32 protocol,
2665 u32 port)
2666 {
2667 u64 val64;
2668 __hal_device_t *hldev;
2669 vxge_hal_status_e status = VXGE_HAL_OK;
2670 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
2671
2672 vxge_assert(vpath_handle != NULL);
2673
2674 hldev = vp->vpath->hldev;
2675
2676 vxge_hal_trace_log_vpath("==> %s:%s:%d",
2677 __FILE__, __func__, __LINE__);
2678
2679 vxge_hal_trace_log_vpath(
2680 "vpath_handle = 0x"VXGE_OS_STXFMT", port_type = %d, "
2681 "protocol = %d, port = %d", (ptr_t) vpath_handle, port_type,
2682 protocol, port);
2683
2684 val64 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_PORT_NUM(port);
2685
2686 if (port_type)
2687 val64 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_SRC_DEST_SEL;
2688
2689 if (protocol)
2690 val64 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_TCP_UDP_SEL;
2691
2692 status = __hal_vpath_rts_table_set(vpath_handle,
2693 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_DELETE_ENTRY,
2694 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_PN,
2695 0,
2696 val64,
2697 0);
2698
2699 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
2700 __FILE__, __func__, __LINE__, status);
2701
2702 return (status);
2703 }
2704
2705 /*
2706 * vxge_hal_vpath_rts_rth_set - Set/configure RTS hashing.
2707 * @vpath_handle: Virtual Path handle.
2708 * @algorithm: Algorithm Select
2709 * @hash_type: Hash Type
2710 * @bucket_size: no of least significant bits to be used for hashing.
2711 * @it_switch: Itable switch required
2712 *
2713 * Used to set/configure all RTS hashing related stuff.
2714 *
2715 * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_itable_set().
2716 */
2717 vxge_hal_status_e
vxge_hal_vpath_rts_rth_set(vxge_hal_vpath_h vpath_handle,vxge_hal_rth_algoritms_t algorithm,vxge_hal_rth_hash_types_t * hash_type,u16 bucket_size,u16 it_switch)2718 vxge_hal_vpath_rts_rth_set(vxge_hal_vpath_h vpath_handle,
2719 vxge_hal_rth_algoritms_t algorithm,
2720 vxge_hal_rth_hash_types_t *hash_type,
2721 u16 bucket_size,
2722 u16 it_switch)
2723 {
2724 u64 data0, data1;
2725 __hal_device_t *hldev;
2726 __hal_vpath_handle_t *vp;
2727
2728 vxge_hal_status_e status = VXGE_HAL_OK;
2729
2730 vxge_assert(vpath_handle != NULL);
2731
2732 vp = (__hal_vpath_handle_t *) vpath_handle;
2733 hldev = vp->vpath->hldev;
2734
2735 vxge_hal_trace_log_vpath("==> %s:%s:%d",
2736 __FILE__, __func__, __LINE__);
2737
2738 vxge_hal_trace_log_vpath(
2739 "vpath_handle = 0x"VXGE_OS_STXFMT", algorithm = %d, "
2740 "hash_type = 0x"VXGE_OS_STXFMT", bucket_size = %d",
2741 (ptr_t) vpath_handle, algorithm, (ptr_t) hash_type,
2742 bucket_size);
2743
2744 (void) __hal_vpath_rts_table_get(vpath_handle,
2745 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
2746 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG,
2747 0,
2748 &data0,
2749 &data1);
2750
2751 if (algorithm == RTH_ALG_NONE) {
2752
2753 data0 &= ~VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_EN;
2754
2755 } else {
2756
2757 if (it_switch) {
2758
2759 if (VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(
2760 data0))
2761 data0 = 0;
2762 else
2763 data0 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE;
2764
2765 } else {
2766 data0 &= VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE;
2767
2768 }
2769
2770 data0 |= VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_EN |
2771 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(bucket_size) |
2772 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(algorithm);
2773
2774 if (hash_type->hash_type_tcpipv4_en)
2775 data0 |=
2776 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV4_EN;
2777
2778 if (hash_type->hash_type_ipv4_en)
2779 data0 |= VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV4_EN;
2780
2781 if (hash_type->hash_type_tcpipv6_en)
2782 data0 |=
2783 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EN;
2784
2785 if (hash_type->hash_type_ipv6_en)
2786 data0 |= VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EN;
2787
2788 if (hash_type->hash_type_tcpipv6ex_en)
2789 data0 |=
2790 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EX_EN;
2791
2792 if (hash_type->hash_type_ipv6ex_en)
2793 data0 |= VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EX_EN;
2794
2795 }
2796
2797 status = __hal_vpath_rts_table_set(vpath_handle,
2798 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY,
2799 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG,
2800 0,
2801 data0,
2802 0);
2803
2804 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
2805 __FILE__, __func__, __LINE__, status);
2806
2807 return (status);
2808 }
2809
2810 /*
2811 * vxge_hal_vpath_rts_rth_get - Read RTS hashing.
2812 * @vpath_handle: Virtual Path handle.
2813 * @algorithm: Buffer to return Algorithm Select
2814 * @hash_type: Buffer to return Hash Type
2815 * @table_select: Buffer to return active Table
2816 * @bucket_size: Buffer to return no of least significant bits used for hashing.
2817 *
2818 * Used to read all RTS hashing related stuff.
2819 *
2820 * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_itable_set(),
2821 * vxge_hal_vpath_rts_rth_set().
2822 */
2823 vxge_hal_status_e
vxge_hal_vpath_rts_rth_get(vxge_hal_vpath_h vpath_handle,vxge_hal_rth_algoritms_t * algorithm,vxge_hal_rth_hash_types_t * hash_type,u8 * table_select,u16 * bucket_size)2824 vxge_hal_vpath_rts_rth_get(vxge_hal_vpath_h vpath_handle,
2825 vxge_hal_rth_algoritms_t *algorithm,
2826 vxge_hal_rth_hash_types_t *hash_type,
2827 u8 *table_select,
2828 u16 *bucket_size)
2829 {
2830 u64 val64;
2831 __hal_device_t *hldev;
2832 vxge_hal_status_e status = VXGE_HAL_OK;
2833 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
2834
2835 vxge_assert(vpath_handle != NULL);
2836
2837 hldev = vp->vpath->hldev;
2838
2839 vxge_hal_trace_log_vpath("==> %s:%s:%d",
2840 __FILE__, __func__, __LINE__);
2841
2842 vxge_hal_trace_log_vpath(
2843 "vpath_handle = 0x"VXGE_OS_STXFMT", algorithm = 0x"VXGE_OS_STXFMT
2844 ", hash_type = 0x"VXGE_OS_STXFMT", "
2845 "table_select = 0x"VXGE_OS_STXFMT", "
2846 "bucket_size = 0x"VXGE_OS_STXFMT, (ptr_t) vpath_handle,
2847 (ptr_t) algorithm, (ptr_t) hash_type,
2848 (ptr_t) table_select, (ptr_t) bucket_size);
2849
2850 status = __hal_vpath_rts_table_get(vpath_handle,
2851 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
2852 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG,
2853 0,
2854 &val64,
2855 NULL);
2856
2857 *algorithm = (vxge_hal_rth_algoritms_t)
2858 VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ALG_SEL(val64);
2859
2860 hash_type->hash_type_tcpipv4_en = ((u32)
2861 VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV4_EN(val64))
2862 ? 1 : 0;
2863
2864 hash_type->hash_type_ipv4_en = ((u32)
2865 VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV4_EN(val64))
2866 ? 1 : 0;
2867
2868 hash_type->hash_type_tcpipv6_en = ((u32)
2869 VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EN(val64))
2870 ? 1 : 0;
2871
2872 hash_type->hash_type_ipv6_en = ((u32)
2873 VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EN(val64))
2874 ? 1 : 0;
2875
2876 hash_type->hash_type_tcpipv6ex_en = ((u32)
2877 VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EX_EN(
2878 val64)) ? 1 : 0;
2879
2880 hash_type->hash_type_ipv6ex_en = ((u32)
2881 VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EX_EN(val64))
2882 ? 1 : 0;
2883
2884 *table_select = ((u32)
2885 VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(val64))
2886 ? 1 : 0;
2887
2888 *bucket_size = (u16)
2889 VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_BUCKET_SIZE(val64);
2890
2891 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
2892 __FILE__, __func__, __LINE__, status);
2893
2894 return (status);
2895 }
2896
2897 /*
2898 * vxge_hal_vpath_rts_rth_key_set - Configure 40byte secret for hash calc.
2899 *
2900 * @vpath_handle: Virtual Path ahandle.
2901 * @KeySize: Number of 64-bit words
2902 * @Key: up to 40-byte array of 64-bit values
2903 * This function configures the 40-byte secret which is used for hash
2904 * calculation.
2905 *
2906 * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set().
2907 */
2908 vxge_hal_status_e
vxge_hal_vpath_rts_rth_key_set(vxge_hal_vpath_h vpath_handle,u8 KeySize,u64 * Key)2909 vxge_hal_vpath_rts_rth_key_set(vxge_hal_vpath_h vpath_handle,
2910 u8 KeySize, u64 *Key)
2911 {
2912 u32 i;
2913 __hal_device_t *hldev;
2914 vxge_hal_status_e status = VXGE_HAL_OK;
2915 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
2916
2917 vxge_assert((vpath_handle != NULL) && (Key != NULL));
2918
2919 hldev = vp->vpath->hldev;
2920
2921 vxge_hal_trace_log_vpath("==> %s:%s:%d",
2922 __FILE__, __func__, __LINE__);
2923
2924 vxge_hal_trace_log_vpath(
2925 "vpath_handle = 0x"VXGE_OS_STXFMT", KeySize = %d"
2926 ", Key = 0x"VXGE_OS_STXFMT, (ptr_t) vpath_handle, KeySize,
2927 (ptr_t) Key);
2928
2929 for (i = 0; i < KeySize; i++) {
2930
2931 status = __hal_vpath_rts_table_set(vpath_handle,
2932 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY,
2933 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY,
2934 i,
2935 vxge_os_htonll(*Key++),
2936 0);
2937
2938 if (status != VXGE_HAL_OK)
2939 break;
2940 }
2941
2942 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
2943 __FILE__, __func__, __LINE__, status);
2944
2945 return (status);
2946 }
2947
2948 /*
2949 * vxge_hal_vpath_rts_rth_key_get - Read 40byte secret for hash calc.
2950 *
2951 * @vpath_handle: Virtual Path ahandle.
2952 * @KeySize: Number of 64-bit words
2953 * @Key: Buffer to return the key
2954 * This function reads the 40-byte secret which is used for hash
2955 * calculation.
2956 *
2957 * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set(),
2958 * vxge_hal_vpath_rts_rth_key_set().
2959 */
2960 vxge_hal_status_e
vxge_hal_vpath_rts_rth_key_get(vxge_hal_vpath_h vpath_handle,u8 KeySize,u64 * Key)2961 vxge_hal_vpath_rts_rth_key_get(vxge_hal_vpath_h vpath_handle,
2962 u8 KeySize, u64 *Key)
2963 {
2964 u32 i;
2965 __hal_device_t *hldev;
2966 vxge_hal_status_e status = VXGE_HAL_OK;
2967 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
2968
2969 vxge_assert((vpath_handle != NULL) && (Key != NULL));
2970
2971 hldev = vp->vpath->hldev;
2972
2973 vxge_hal_trace_log_vpath("==> %s:%s:%d",
2974 __FILE__, __func__, __LINE__);
2975
2976 vxge_hal_trace_log_vpath(
2977 "vpath_handle = 0x"VXGE_OS_STXFMT", KeySize = %d"
2978 ", Key = 0x"VXGE_OS_STXFMT, (ptr_t) vpath_handle, KeySize,
2979 (ptr_t) Key);
2980
2981 for (i = 0; i < KeySize; i++) {
2982
2983 status = __hal_vpath_rts_table_get(vpath_handle,
2984 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
2985 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY,
2986 i,
2987 Key++,
2988 NULL);
2989
2990 if (status != VXGE_HAL_OK)
2991 break;
2992 }
2993
2994 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
2995 __FILE__, __func__, __LINE__, status);
2996
2997 return (status);
2998 }
2999
3000 /*
3001 * vxge_hal_vpath_rts_rth_jhash_cfg_set - Configure JHASH algorithm
3002 *
3003 * @vpath_handle: Virtual Path ahandle.
3004 * @golden_ratio: Golden ratio
3005 * @init_value: Initial value
3006 * This function configures JENKIN's HASH algorithm
3007 *
3008 * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set().
3009 */
3010 vxge_hal_status_e
vxge_hal_vpath_rts_rth_jhash_cfg_set(vxge_hal_vpath_h vpath_handle,u32 golden_ratio,u32 init_value)3011 vxge_hal_vpath_rts_rth_jhash_cfg_set(vxge_hal_vpath_h vpath_handle,
3012 u32 golden_ratio, u32 init_value)
3013 {
3014 __hal_device_t *hldev;
3015 vxge_hal_status_e status = VXGE_HAL_OK;
3016 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
3017
3018 vxge_assert(vpath_handle != NULL);
3019
3020 hldev = vp->vpath->hldev;
3021
3022 vxge_hal_trace_log_vpath("==> %s:%s:%d",
3023 __FILE__, __func__, __LINE__);
3024
3025 vxge_hal_trace_log_vpath(
3026 "vpath_handle = 0x"VXGE_OS_STXFMT", golden_ratio = %d"
3027 ", init_value = %d", (ptr_t) vpath_handle, golden_ratio,
3028 init_value);
3029
3030 status = __hal_vpath_rts_table_set(vpath_handle,
3031 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY,
3032 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_JHASH_CFG,
3033 0,
3034 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_JHASH_CFG_GOLDEN_RATIO(
3035 golden_ratio) |
3036 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_JHASH_CFG_INIT_VALUE(
3037 init_value),
3038 0);
3039
3040 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
3041 __FILE__, __func__, __LINE__, status);
3042
3043 return (status);
3044 }
3045
3046 /*
3047 * vxge_hal_vpath_rts_rth_jhash_cfg_get - Read JHASH algorithm
3048 *
3049 * @vpath_handle: Virtual Path ahandle.
3050 * @golden_ratio: Buffer to return Golden ratio
3051 * @init_value: Buffer to return Initial value
3052 * This function reads JENKIN's HASH algorithm
3053 *
3054 * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set(),
3055 * vxge_hal_vpath_rts_rth_jhash_cfg_set().
3056 */
3057 vxge_hal_status_e
vxge_hal_vpath_rts_rth_jhash_cfg_get(vxge_hal_vpath_h vpath_handle,u32 * golden_ratio,u32 * init_value)3058 vxge_hal_vpath_rts_rth_jhash_cfg_get(vxge_hal_vpath_h vpath_handle,
3059 u32 * golden_ratio, u32 *init_value)
3060 {
3061 u64 val64;
3062 __hal_device_t *hldev;
3063 vxge_hal_status_e status = VXGE_HAL_OK;
3064 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
3065
3066 vxge_assert(vpath_handle != NULL);
3067
3068 hldev = vp->vpath->hldev;
3069
3070 vxge_hal_trace_log_vpath("==> %s:%s:%d",
3071 __FILE__, __func__, __LINE__);
3072
3073 vxge_hal_trace_log_vpath(
3074 "vpath_handle = 0x"VXGE_OS_STXFMT", "
3075 "golden_ratio = 0x"VXGE_OS_STXFMT", init_value = 0x"VXGE_OS_STXFMT,
3076 (ptr_t) vpath_handle, (ptr_t) golden_ratio, (ptr_t) init_value);
3077
3078 status = __hal_vpath_rts_table_get(vpath_handle,
3079 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
3080 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_JHASH_CFG,
3081 0,
3082 &val64,
3083 NULL);
3084
3085 if (status != VXGE_HAL_OK) {
3086 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
3087 __FILE__, __func__, __LINE__, status);
3088 return (status);
3089 }
3090
3091 *golden_ratio = (u32)
3092 VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_GOLDEN_RATIO(
3093 val64);
3094
3095 *init_value = (u32)
3096 VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_INIT_VALUE(
3097 val64);
3098
3099 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
3100 __FILE__, __func__, __LINE__, status);
3101
3102 return (status);
3103 }
3104
3105 /*
3106 * vxge_hal_vpath_rts_rth_mask_set - Set/configure JHASH mask.
3107 * @vpath_handle: Virtual Path ahandle.
3108 * @table_size: Size of the mask table
3109 * @hash_mask_ipv6sa: IPv6SA Hash Mask
3110 * @hash_mask_ipv6da: IPv6DA Hash Mask
3111 * @hash_mask_ipv4sa: IPv4SA Hash Mask
3112 * @hash_mask_ipv4da: IPv4DA Hash Mask
3113 * @hash_mask_l4sp: L4SP Hash Mask
3114 * @hash_mask_l4dp: L4DP Hash Mask
3115 *
3116 * Used to set/configure indirection table.
3117 * It enables the required no of entries in the IT.
3118 * It adds entries to the IT.
3119 *
3120 * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set().
3121 */
3122 vxge_hal_status_e
vxge_hal_vpath_rts_rth_mask_set(vxge_hal_vpath_h vpath_handle,u32 table_size,u32 * hash_mask_ipv6sa,u32 * hash_mask_ipv6da,u32 * hash_mask_ipv4sa,u32 * hash_mask_ipv4da,u32 * hash_mask_l4sp,u32 * hash_mask_l4dp)3123 vxge_hal_vpath_rts_rth_mask_set(vxge_hal_vpath_h vpath_handle,
3124 u32 table_size,
3125 u32 *hash_mask_ipv6sa,
3126 u32 *hash_mask_ipv6da,
3127 u32 *hash_mask_ipv4sa,
3128 u32 *hash_mask_ipv4da,
3129 u32 *hash_mask_l4sp,
3130 u32 *hash_mask_l4dp)
3131 {
3132 u32 i;
3133 u64 val64;
3134 __hal_device_t *hldev;
3135 vxge_hal_status_e status = VXGE_HAL_OK;
3136 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
3137
3138 vxge_assert((vpath_handle != NULL) && (hash_mask_ipv6sa != NULL) &&
3139 (hash_mask_ipv6da != NULL) && (hash_mask_ipv4sa != NULL) &&
3140 (hash_mask_ipv4da != NULL) && (hash_mask_l4sp != NULL) &&
3141 (hash_mask_l4dp != NULL));
3142
3143 hldev = vp->vpath->hldev;
3144
3145 vxge_hal_trace_log_vpath("==> %s:%s:%d",
3146 __FILE__, __func__, __LINE__);
3147
3148 vxge_hal_trace_log_vpath(
3149 "vpath_handle = 0x"VXGE_OS_STXFMT", "
3150 "table_size = %d, hash_mask_ipv6sa = 0x"VXGE_OS_STXFMT
3151 ", hash_mask_ipv6da = 0x"VXGE_OS_STXFMT
3152 ", hash_mask_ipv4sa = 0x"VXGE_OS_STXFMT
3153 ", hash_mask_ipv4da = 0x"VXGE_OS_STXFMT
3154 ", hash_mask_l4sp = 0x"VXGE_OS_STXFMT
3155 ", hash_mask_l4dp = 0x"VXGE_OS_STXFMT,
3156 (ptr_t) vpath_handle, table_size, (ptr_t) hash_mask_ipv6sa,
3157 (ptr_t) hash_mask_ipv6da, (ptr_t) hash_mask_ipv4sa,
3158 (ptr_t) hash_mask_ipv4da, (ptr_t) hash_mask_l4sp,
3159 (ptr_t) hash_mask_l4dp);
3160
3161 for (i = 0; i < table_size; i++) {
3162
3163 val64 =
3164 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_SA_MASK(
3165 *hash_mask_ipv6sa++) |
3166 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_DA_MASK(
3167 *hash_mask_ipv6da++) |
3168 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_SA_MASK(
3169 *hash_mask_ipv4sa++) |
3170 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_DA_MASK(
3171 *hash_mask_ipv4da++) |
3172 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4SP_MASK(
3173 *hash_mask_l4sp++) |
3174 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4DP_MASK(
3175 *hash_mask_l4dp++);
3176
3177 status = __hal_vpath_rts_table_set(vpath_handle,
3178 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY,
3179 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK,
3180 i,
3181 val64,
3182 0);
3183
3184 if (status != VXGE_HAL_OK)
3185 break;
3186 }
3187
3188 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
3189 __FILE__, __func__, __LINE__, status);
3190
3191 return (status);
3192 }
3193
3194 /*
3195 * vxge_hal_vpath_rts_rth_mask_get - Read JHASH mask.
3196 * @vpath_handle: Virtual Path ahandle.
3197 * @table_size: Size of the mask table
3198 * @hash_mask_ipv6sa: Buffer to return IPv6SA Hash Mask
3199 * @hash_mask_ipv6da: Buffer to return IPv6DA Hash Mask
3200 * @hash_mask_ipv4sa: Buffer to return IPv4SA Hash Mask
3201 * @hash_mask_ipv4da: Buffer to return IPv4DA Hash Mask
3202 * @hash_mask_l4sp: Buffer to return L4SP Hash Mask
3203 * @hash_mask_l4dp: Buffer to return L4DP Hash Mask
3204 *
3205 * Used to read rth mask.
3206 *
3207 * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set(),
3208 * vxge_hal_vpath_rts_rth_mask_set().
3209 */
3210 vxge_hal_status_e
vxge_hal_vpath_rts_rth_mask_get(vxge_hal_vpath_h vpath_handle,u32 table_size,u32 * hash_mask_ipv6sa,u32 * hash_mask_ipv6da,u32 * hash_mask_ipv4sa,u32 * hash_mask_ipv4da,u32 * hash_mask_l4sp,u32 * hash_mask_l4dp)3211 vxge_hal_vpath_rts_rth_mask_get(vxge_hal_vpath_h vpath_handle,
3212 u32 table_size,
3213 u32 *hash_mask_ipv6sa,
3214 u32 *hash_mask_ipv6da,
3215 u32 *hash_mask_ipv4sa,
3216 u32 *hash_mask_ipv4da,
3217 u32 *hash_mask_l4sp,
3218 u32 *hash_mask_l4dp)
3219 {
3220 u32 i;
3221 u64 val64;
3222 __hal_device_t *hldev;
3223 vxge_hal_status_e status = VXGE_HAL_OK;
3224 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
3225
3226 vxge_assert((vpath_handle != NULL) && (hash_mask_ipv6sa != NULL) &&
3227 (hash_mask_ipv6da != NULL) && (hash_mask_ipv4sa != NULL) &&
3228 (hash_mask_ipv4da != NULL) && (hash_mask_l4sp != NULL) &&
3229 (hash_mask_l4dp != NULL));
3230
3231 hldev = vp->vpath->hldev;
3232
3233 vxge_hal_trace_log_vpath("==> %s:%s:%d",
3234 __FILE__, __func__, __LINE__);
3235
3236 vxge_hal_trace_log_vpath(
3237 "vpath_handle = 0x"VXGE_OS_STXFMT", "
3238 "table_size = %d, hash_mask_ipv6sa = 0x"VXGE_OS_STXFMT
3239 ", hash_mask_ipv6da = 0x"VXGE_OS_STXFMT
3240 ", hash_mask_ipv4sa = 0x"VXGE_OS_STXFMT
3241 ", hash_mask_ipv4da = 0x"VXGE_OS_STXFMT
3242 ", hash_mask_l4sp = 0x"VXGE_OS_STXFMT
3243 ", hash_mask_l4dp = 0x"VXGE_OS_STXFMT,
3244 (ptr_t) vpath_handle, table_size, (ptr_t) hash_mask_ipv6sa,
3245 (ptr_t) hash_mask_ipv6da, (ptr_t) hash_mask_ipv4sa,
3246 (ptr_t) hash_mask_ipv4da, (ptr_t) hash_mask_l4sp,
3247 (ptr_t) hash_mask_l4dp);
3248
3249 for (i = 0; i < table_size; i++) {
3250
3251 status = __hal_vpath_rts_table_get(vpath_handle,
3252 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
3253 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK,
3254 i,
3255 &val64,
3256 NULL);
3257
3258 if (status != VXGE_HAL_OK)
3259 break;
3260
3261 *hash_mask_ipv6sa++ = (u32)
3262 VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV6_SA_MASK(
3263 val64);
3264
3265 *hash_mask_ipv6da++ = (u32)
3266 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_DA_MASK(
3267 val64);
3268
3269 *hash_mask_ipv4sa++ = (u32)
3270 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_SA_MASK(
3271 val64);
3272
3273 *hash_mask_ipv4da++ = (u32)
3274 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_DA_MASK(
3275 val64);
3276
3277 *hash_mask_l4sp++ = (u32)
3278 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4SP_MASK(val64);
3279
3280 *hash_mask_l4dp++ = (u32)
3281 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4DP_MASK(val64);
3282
3283 }
3284
3285 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
3286 __FILE__, __func__, __LINE__, status);
3287
3288 return (status);
3289 }
3290
3291 /*
3292 * vxge_hal_vpath_rts_rth_itable_set - Set/configure indirection table (IT).
3293 * @vpath_handles: Virtual Path handles.
3294 * @vpath_count: Number of vpath handles passed in vpath_handles
3295 * @itable: Pointer to indirection table
3296 * @itable_size: Number of entries in itable
3297 *
3298 * Used to set/configure indirection table.
3299 * It enables the required no of entries in the IT.
3300 * It adds entries to the IT.
3301 *
3302 * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set().
3303 */
3304 vxge_hal_status_e
vxge_hal_vpath_rts_rth_itable_set(vxge_hal_vpath_h * vpath_handles,u32 vpath_count,u8 * itable,u32 itable_size)3305 vxge_hal_vpath_rts_rth_itable_set(vxge_hal_vpath_h *vpath_handles,
3306 u32 vpath_count,
3307 u8 *itable,
3308 u32 itable_size)
3309 {
3310 u32 i, j, k, l, items[4];
3311 u64 data0;
3312 u64 data1;
3313 __hal_device_t *hldev;
3314 vxge_hal_status_e status = VXGE_HAL_OK;
3315 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handles[0];
3316
3317 vxge_assert((vpath_handles != NULL) && (itable != NULL));
3318
3319 hldev = vp->vpath->hldev;
3320
3321 vxge_hal_trace_log_vpath("==> %s:%s:%d",
3322 __FILE__, __func__, __LINE__);
3323
3324 vxge_hal_trace_log_vpath(
3325 "vpath_handle = 0x"VXGE_OS_STXFMT", vpath_count = %d, "
3326 "itable = 0x"VXGE_OS_STXFMT", itable_size = %d",
3327 (ptr_t) vpath_handles, vpath_count, (ptr_t) itable, itable_size);
3328
3329 if (hldev->header.config.rth_it_type == VXGE_HAL_RTH_IT_TYPE_SOLO_IT) {
3330
3331 for (j = 0; j < itable_size; j++) {
3332
3333 data1 = 0;
3334
3335 data0 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(
3336 itable[j]);
3337
3338 status = __hal_vpath_rts_table_set(vpath_handles[0],
3339 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY,
3340 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT,
3341 j,
3342 data0,
3343 data1);
3344
3345 if (status != VXGE_HAL_OK) {
3346 vxge_hal_trace_log_vpath(
3347 "<== %s:%s:%d Result: %d",
3348 __FILE__, __func__, __LINE__,
3349 status);
3350
3351 return (status);
3352 }
3353 }
3354
3355 for (j = 0; j < itable_size; j++) {
3356
3357 data1 = 0;
3358
3359 data0 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_ENTRY_EN |
3360 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(itable[j]);
3361
3362 status = __hal_vpath_rts_table_set(vpath_handles[itable[j]],
3363 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY,
3364 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT,
3365 j, data0, data1);
3366
3367 if (status != VXGE_HAL_OK) {
3368 vxge_hal_trace_log_vpath(
3369 "<== %s:%s:%d Result: %d",
3370 __FILE__, __func__, __LINE__,
3371 status);
3372 return (status);
3373 }
3374 }
3375
3376 } else {
3377 for (i = 0; i < vpath_count; i++) {
3378
3379 for (k = 0, j = 0; k < itable_size; k++) {
3380
3381 if (itable[k] != i)
3382 continue;
3383
3384 for (l = j; l < 4; l++)
3385 items[l] = k;
3386
3387 if ((j++ == 3) || (k == (itable_size - 1))) {
3388
3389 data0 =
3390 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(
3391 items[0]) |
3392 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_ENTRY_EN |
3393 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_DATA(
3394 itable[items[0]]) |
3395 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(
3396 items[1]) |
3397 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_ENTRY_EN |
3398 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_DATA(
3399 itable[items[1]]);
3400
3401 data1 =
3402 VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(
3403 items[2]) |
3404 VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_ENTRY_EN |
3405 VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_DATA(
3406 itable[items[2]]) |
3407 VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(
3408 items[3]) |
3409 VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_ENTRY_EN |
3410 VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_DATA(
3411 itable[items[3]]);
3412
3413 status =
3414 __hal_vpath_rts_table_set(vpath_handles[i],
3415 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY,
3416 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT,
3417 0,
3418 data0,
3419 data1);
3420
3421 if (status != VXGE_HAL_OK) {
3422 vxge_hal_trace_log_vpath(
3423 "<== %s:%s:%d Result: %d",
3424 __FILE__, __func__,
3425 __LINE__, status);
3426
3427 return (status);
3428 }
3429
3430 j = 0;
3431 }
3432 }
3433 }
3434 }
3435
3436 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
3437 __FILE__, __func__, __LINE__, status);
3438
3439 return (status);
3440 }
3441
3442 /*
3443 * vxge_hal_vpath_rts_rth_itable_get - Read indirection table(IT).
3444 * @vpath_handles: Virtual Path handles.
3445 * @vpath_count: Number of vpath handles passed in vpath_handles
3446 * @itable: Pointer to the buffer to return indirection table
3447 * @itable_size: pointer to buffer to return Number of entries in itable
3448 *
3449 * Used to read indirection table.
3450 *
3451 * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set(),
3452 * vxge_hal_vpath_rts_rth_itable_set().
3453 */
3454 vxge_hal_status_e
vxge_hal_vpath_rts_rth_itable_get(vxge_hal_vpath_h * vpath_handles,u32 vpath_count,u8 * itable,u32 itable_size)3455 vxge_hal_vpath_rts_rth_itable_get(vxge_hal_vpath_h *vpath_handles,
3456 u32 vpath_count,
3457 u8 *itable,
3458 u32 itable_size)
3459 {
3460 u32 i, j;
3461 u64 data0;
3462 u64 data1;
3463 __hal_device_t *hldev;
3464 vxge_hal_status_e status = VXGE_HAL_OK;
3465 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handles[0];
3466
3467 vxge_assert((vpath_handles != NULL) && (itable != NULL));
3468
3469 hldev = vp->vpath->hldev;
3470
3471 vxge_hal_trace_log_vpath("==> %s:%s:%d",
3472 __FILE__, __func__, __LINE__);
3473
3474 vxge_hal_trace_log_vpath(
3475 "vpath_handle = 0x"VXGE_OS_STXFMT", vpath_count = %d, "
3476 "itable = 0x"VXGE_OS_STXFMT", itable_size = %d",
3477 (ptr_t) vpath_handles, vpath_count, (ptr_t) itable, itable_size);
3478
3479 if (hldev->header.config.rth_it_type == VXGE_HAL_RTH_IT_TYPE_SOLO_IT) {
3480
3481 for (i = 0; i < vpath_count; i++) {
3482
3483 for (j = 0; j < itable_size; j++) {
3484
3485 status = __hal_vpath_rts_table_get(vpath_handles[i],
3486 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
3487 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT,
3488 j,
3489 &data0,
3490 &data1);
3491
3492 if (status != VXGE_HAL_OK) {
3493 vxge_hal_trace_log_vpath(
3494 "<== %s:%s:%d Result: %d",
3495 __FILE__, __func__, __LINE__,
3496 status);
3497
3498 return (status);
3499 }
3500
3501 if ((u8) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_SOLO_IT_ENTRY_EN(data0)) {
3502 itable[j] = (u8) i;
3503 }
3504 }
3505 }
3506 } else {
3507
3508 for (i = 0; i < vpath_count; i++) {
3509
3510 for (j = 0; j < itable_size; ) {
3511
3512 data0 = 0;
3513 data1 = 0;
3514
3515 if (j < itable_size)
3516 data0 =
3517 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(j);
3518
3519 if (j + 1 < itable_size)
3520 data0 |= VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(j + 1);
3521
3522 if (j + 2 < itable_size)
3523 data1 = VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(j + 2);
3524
3525 if (j + 3 < itable_size)
3526 data1 |= VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(j + 3);
3527
3528 status = __hal_vpath_rts_table_get(
3529 vpath_handles[i],
3530 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
3531 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT,
3532 0, &data0, &data1);
3533
3534 if (status != VXGE_HAL_OK) {
3535 vxge_hal_trace_log_vpath(
3536 "<== %s:%s:%d Result: %d",
3537 __FILE__, __func__, __LINE__,
3538 status);
3539
3540 return (status);
3541 }
3542
3543 if (j < itable_size) {
3544 if ((u8)
3545 VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_ENTRY_EN(data0)) {
3546 itable[j] = (u8) i;
3547 }
3548
3549 j++;
3550 }
3551
3552 if (j < itable_size) {
3553 if ((u8)
3554 VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_ENTRY_EN(data0)) {
3555 itable[j] = (u8) i;
3556 }
3557 j++;
3558 }
3559
3560 if (j < itable_size) {
3561 if ((u8)
3562 VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_ENTRY_EN(data1)) {
3563 itable[j] = (u8) i;
3564 }
3565 j++;
3566 }
3567
3568 if (j < itable_size) {
3569 if ((u8)
3570 VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_ENTRY_EN(data1)) {
3571 itable[j] = (u8) i;
3572 }
3573 j++;
3574 }
3575 }
3576 }
3577 }
3578
3579 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
3580 __FILE__, __func__, __LINE__, status);
3581
3582 return (status);
3583 }
3584
3585 /*
3586 * vxge_hal_vpath_rts_rth_clr - Clear RTS hashing.
3587 * @vpath_handles: Virtual Path handles.
3588 * @vpath_count: Number of vpath handles passed in vpath_handles
3589 *
3590 * This function is used to clear all RTS hashing related stuff.
3591 *
3592 * See also: vxge_hal_vpath_rts_rth_set(), vxge_hal_vpath_rts_rth_itable_set().
3593 */
3594 vxge_hal_status_e
vxge_hal_vpath_rts_rth_clr(vxge_hal_vpath_h * vpath_handles,u32 vpath_count)3595 vxge_hal_vpath_rts_rth_clr(
3596 vxge_hal_vpath_h *vpath_handles,
3597 u32 vpath_count)
3598 {
3599 u64 data0, data1;
3600 u32 i, j;
3601 __hal_device_t *hldev;
3602 __hal_vpath_handle_t *vp;
3603 vxge_hal_status_e status = VXGE_HAL_OK;
3604
3605 vxge_assert(vpath_handles != NULL);
3606
3607 vp = (__hal_vpath_handle_t *) vpath_handles[0];
3608
3609 hldev = vp->vpath->hldev;
3610
3611 vxge_hal_trace_log_vpath("==> %s:%s:%d",
3612 __FILE__, __func__, __LINE__);
3613
3614 vxge_hal_trace_log_vpath(
3615 "vpath_handles = 0x"VXGE_OS_STXFMT", vpath_count = %d",
3616 (ptr_t) vpath_handles, vpath_count);
3617
3618 if (hldev->header.config.rth_it_type == VXGE_HAL_RTH_IT_TYPE_SOLO_IT) {
3619
3620 for (j = 0; j < VXGE_HAL_MAX_ITABLE_ENTRIES; j++) {
3621
3622 data0 = 0;
3623 data1 = 0;
3624
3625 status = __hal_vpath_rts_table_set(vpath_handles[0],
3626 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY,
3627 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT,
3628 j,
3629 data0,
3630 data1);
3631
3632 if (status != VXGE_HAL_OK) {
3633 vxge_hal_trace_log_vpath(
3634 "<== %s:%s:%d Result: %d",
3635 __FILE__, __func__, __LINE__,
3636 status);
3637
3638 return (status);
3639 }
3640 }
3641 } else {
3642 for (i = 0; i < vpath_count; i++) {
3643
3644 for (j = 0; j < VXGE_HAL_MAX_ITABLE_ENTRIES; j += 4) {
3645
3646 data0 =
3647 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(j) |
3648 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(j + 1);
3649
3650 data1 =
3651 VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(j + 2) |
3652 VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(j + 3);
3653
3654 status = __hal_vpath_rts_table_set(vpath_handles[i],
3655 VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY,
3656 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT,
3657 0,
3658 data0,
3659 data1);
3660
3661 if (status != VXGE_HAL_OK) {
3662 vxge_hal_trace_log_vpath(
3663 "<== %s:%s:%d Result: %d",
3664 __FILE__, __func__, __LINE__,
3665 status);
3666 return (status);
3667 }
3668 }
3669 }
3670 }
3671
3672 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
3673 __FILE__, __func__, __LINE__, status);
3674 return (VXGE_HAL_OK);
3675 }
3676
3677 /*
3678 * vxge_hal_vpath_promisc_enable - Enable promiscuous mode.
3679 * @vpath_handle: Vpath handle.
3680 *
3681 * Enable promiscuous mode of X3100 operation.
3682 *
3683 * See also: vxge_hal_vpath_promisc_disable().
3684 */
3685 vxge_hal_status_e
vxge_hal_vpath_promisc_enable(vxge_hal_vpath_h vpath_handle)3686 vxge_hal_vpath_promisc_enable(vxge_hal_vpath_h vpath_handle)
3687 {
3688 u64 val64;
3689 __hal_device_t *hldev;
3690 __hal_virtualpath_t *vpath;
3691
3692 vxge_assert(vpath_handle != NULL);
3693
3694 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
3695
3696 hldev = vpath->hldev;
3697
3698 vxge_hal_trace_log_vpath("==> %s:%s:%d",
3699 __FILE__, __func__, __LINE__);
3700
3701 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
3702 (ptr_t) vpath_handle);
3703
3704 if (vpath->ringh == NULL) {
3705 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
3706 __FILE__, __func__, __LINE__,
3707 VXGE_HAL_ERR_INVALID_HANDLE);
3708 return (VXGE_HAL_ERR_INVALID_HANDLE);
3709 }
3710
3711 if (vpath->promisc_en == VXGE_HAL_VP_PROMISC_ENABLE) {
3712
3713 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
3714 __FILE__, __func__, __LINE__);
3715 return (VXGE_HAL_OK);
3716 }
3717
3718 val64 = vxge_os_pio_mem_read64(
3719 hldev->header.pdev,
3720 hldev->header.regh0,
3721 &vpath->vp_reg->rxmac_vcfg0);
3722
3723 val64 |= VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN |
3724 VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN |
3725 VXGE_HAL_RXMAC_VCFG0_BCAST_EN |
3726 VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN;
3727
3728 vxge_os_pio_mem_write64(
3729 hldev->header.pdev,
3730 hldev->header.regh0,
3731 val64,
3732 &vpath->vp_reg->rxmac_vcfg0);
3733
3734 vpath->promisc_en = VXGE_HAL_VP_PROMISC_ENABLE;
3735
3736 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
3737 __FILE__, __func__, __LINE__);
3738 return (VXGE_HAL_OK);
3739 }
3740
3741 /*
3742 * vxge_hal_vpath_promisc_disable - Disable promiscuous mode.
3743 * @vpath_handle: Vpath handle.
3744 *
3745 * Disable promiscuous mode of X3100 operation.
3746 *
3747 * See also: vxge_hal_vpath_promisc_enable().
3748 */
3749 vxge_hal_status_e
vxge_hal_vpath_promisc_disable(vxge_hal_vpath_h vpath_handle)3750 vxge_hal_vpath_promisc_disable(vxge_hal_vpath_h vpath_handle)
3751 {
3752 u64 val64;
3753 __hal_device_t *hldev;
3754 __hal_virtualpath_t *vpath;
3755
3756 vxge_assert(vpath_handle != NULL);
3757
3758 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
3759
3760 hldev = vpath->hldev;
3761
3762 vxge_hal_trace_log_vpath("==> %s:%s:%d",
3763 __FILE__, __func__, __LINE__);
3764
3765 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
3766 (ptr_t) vpath_handle);
3767
3768 if (vpath->ringh == NULL) {
3769 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
3770 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
3771 return (VXGE_HAL_ERR_INVALID_HANDLE);
3772 }
3773
3774 if (vpath->promisc_en == VXGE_HAL_VP_PROMISC_DISABLE) {
3775
3776 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
3777 __FILE__, __func__, __LINE__);
3778 return (VXGE_HAL_OK);
3779 }
3780
3781 val64 = vxge_os_pio_mem_read64(
3782 hldev->header.pdev,
3783 hldev->header.regh0,
3784 &vpath->vp_reg->rxmac_vcfg0);
3785
3786 if (vpath->vp_config->rpa_ucast_all_addr_en ==
3787 VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_DISABLE) {
3788 val64 &= ~VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN;
3789 }
3790
3791 if (vpath->vp_config->rpa_mcast_all_addr_en ==
3792 VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_DISABLE) {
3793 val64 &= ~VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN;
3794 }
3795
3796 if (vpath->vp_config->rpa_bcast_en ==
3797 VXGE_HAL_VPATH_RPA_BCAST_DISABLE) {
3798 val64 &= ~VXGE_HAL_RXMAC_VCFG0_BCAST_EN;
3799 }
3800
3801 if (vpath->vp_config->rpa_all_vid_en ==
3802 VXGE_HAL_VPATH_RPA_ALL_VID_DISABLE) {
3803 val64 &= ~VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN;
3804 }
3805
3806 vxge_os_pio_mem_write64(
3807 hldev->header.pdev,
3808 hldev->header.regh0,
3809 val64,
3810 &vpath->vp_reg->rxmac_vcfg0);
3811
3812 vpath->promisc_en = VXGE_HAL_VP_PROMISC_DISABLE;
3813
3814 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
3815 __FILE__, __func__, __LINE__);
3816
3817 return (VXGE_HAL_OK);
3818 }
3819
3820 /*
3821 * vxge_hal_vpath_bcast_enable - Enable broadcast
3822 * @vpath_handle: Vpath handle.
3823 *
3824 * Enable receiving broadcasts.
3825 */
3826 vxge_hal_status_e
vxge_hal_vpath_bcast_enable(vxge_hal_vpath_h vpath_handle)3827 vxge_hal_vpath_bcast_enable(vxge_hal_vpath_h vpath_handle)
3828 {
3829 u64 val64;
3830 __hal_device_t *hldev;
3831 __hal_virtualpath_t *vpath;
3832
3833 vxge_assert(vpath_handle != NULL);
3834
3835 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
3836
3837 hldev = vpath->hldev;
3838
3839 vxge_hal_trace_log_vpath("==> %s:%s:%d",
3840 __FILE__, __func__, __LINE__);
3841
3842 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
3843 (ptr_t) vpath_handle);
3844
3845 if (vpath->ringh == NULL) {
3846 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
3847 __FILE__, __func__, __LINE__,
3848 VXGE_HAL_ERR_INVALID_HANDLE);
3849
3850 return (VXGE_HAL_ERR_INVALID_HANDLE);
3851 }
3852
3853 if (vpath->vp_config->rpa_bcast_en ==
3854 VXGE_HAL_VPATH_RPA_BCAST_ENABLE) {
3855
3856 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
3857 __FILE__, __func__, __LINE__);
3858 return (VXGE_HAL_OK);
3859 }
3860
3861 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3862 hldev->header.regh0,
3863 &vpath->vp_reg->rxmac_vcfg0);
3864
3865 val64 |= VXGE_HAL_RXMAC_VCFG0_BCAST_EN;
3866
3867 vxge_os_pio_mem_write64(hldev->header.pdev,
3868 hldev->header.regh0,
3869 val64,
3870 &vpath->vp_reg->rxmac_vcfg0);
3871
3872 vpath->vp_config->rpa_bcast_en = VXGE_HAL_VPATH_RPA_BCAST_ENABLE;
3873
3874 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
3875 __FILE__, __func__, __LINE__);
3876
3877 return (VXGE_HAL_OK);
3878 }
3879
3880 /*
3881 * vxge_hal_vpath_bcast_disable - Disable broadcast
3882 * @vpath_handle: Vpath handle.
3883 *
3884 * Disable receiving broadcasts.
3885 */
3886 vxge_hal_status_e
vxge_hal_vpath_bcast_disable(vxge_hal_vpath_h vpath_handle)3887 vxge_hal_vpath_bcast_disable(vxge_hal_vpath_h vpath_handle)
3888 {
3889 u64 val64;
3890 __hal_device_t *hldev;
3891 __hal_virtualpath_t *vpath;
3892
3893 vxge_assert(vpath_handle != NULL);
3894
3895 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
3896
3897 hldev = vpath->hldev;
3898
3899 vxge_hal_trace_log_vpath("==> %s:%s:%d",
3900 __FILE__, __func__, __LINE__);
3901
3902 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
3903 (ptr_t) vpath_handle);
3904
3905 if (vpath->ringh == NULL) {
3906 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
3907 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
3908 return (VXGE_HAL_ERR_INVALID_HANDLE);
3909 }
3910
3911 if (vpath->vp_config->rpa_bcast_en ==
3912 VXGE_HAL_VPATH_RPA_BCAST_DISABLE) {
3913
3914 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
3915 __FILE__, __func__, __LINE__);
3916 return (VXGE_HAL_OK);
3917 }
3918
3919 val64 = vxge_os_pio_mem_read64(
3920 hldev->header.pdev,
3921 hldev->header.regh0,
3922 &vpath->vp_reg->rxmac_vcfg0);
3923
3924 val64 &= ~VXGE_HAL_RXMAC_VCFG0_BCAST_EN;
3925
3926 vxge_os_pio_mem_write64(
3927 hldev->header.pdev,
3928 hldev->header.regh0,
3929 val64,
3930 &vpath->vp_reg->rxmac_vcfg0);
3931
3932 vpath->vp_config->rpa_bcast_en = VXGE_HAL_VPATH_RPA_BCAST_DISABLE;
3933
3934 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
3935 __FILE__, __func__, __LINE__);
3936
3937 return (VXGE_HAL_OK);
3938 }
3939
3940 /*
3941 * vxge_hal_vpath_mcast_enable - Enable multicast addresses.
3942 * @vpath_handle: Vpath handle.
3943 *
3944 * Enable X3100 multicast addresses.
3945 * Returns: VXGE_HAL_OK on success.
3946 *
3947 */
3948 vxge_hal_status_e
vxge_hal_vpath_mcast_enable(vxge_hal_vpath_h vpath_handle)3949 vxge_hal_vpath_mcast_enable(vxge_hal_vpath_h vpath_handle)
3950 {
3951 u64 val64;
3952 __hal_device_t *hldev;
3953 __hal_virtualpath_t *vpath;
3954
3955 vxge_assert(vpath_handle != NULL);
3956
3957 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
3958
3959 hldev = vpath->hldev;
3960
3961 vxge_hal_trace_log_vpath("==> %s:%s:%d",
3962 __FILE__, __func__, __LINE__);
3963
3964 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
3965 (ptr_t) vpath_handle);
3966
3967 if (vpath->ringh == NULL) {
3968 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
3969 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
3970 return (VXGE_HAL_ERR_INVALID_HANDLE);
3971 }
3972
3973 if (vpath->vp_config->rpa_mcast_all_addr_en ==
3974 VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_ENABLE) {
3975 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
3976 __FILE__, __func__, __LINE__);
3977 return (VXGE_HAL_OK);
3978 }
3979
3980 val64 = vxge_os_pio_mem_read64(
3981 hldev->header.pdev,
3982 hldev->header.regh0,
3983 &vpath->vp_reg->rxmac_vcfg0);
3984
3985 val64 |= VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN;
3986
3987 vxge_os_pio_mem_write64(
3988 hldev->header.pdev,
3989 hldev->header.regh0,
3990 val64,
3991 &vpath->vp_reg->rxmac_vcfg0);
3992
3993 vpath->vp_config->rpa_mcast_all_addr_en =
3994 VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_ENABLE;
3995
3996 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
3997 __FILE__, __func__, __LINE__);
3998
3999 return (VXGE_HAL_OK);
4000 }
4001
4002 /*
4003 * vxge_hal_vpath_mcast_disable - Disable multicast addresses.
4004 * @vpath_handle: Vpath handle.
4005 *
4006 * Disable X3100 multicast addresses.
4007 * Returns: VXGE_HAL_OK - success.
4008 * VXGE_HAL_INF_MEM_STROBE_CMD_EXECUTING - Failed to disable mcast
4009 * feature within the time(timeout).
4010 *
4011 */
4012 vxge_hal_status_e
vxge_hal_vpath_mcast_disable(vxge_hal_vpath_h vpath_handle)4013 vxge_hal_vpath_mcast_disable(vxge_hal_vpath_h vpath_handle)
4014 {
4015 u64 val64;
4016 __hal_device_t *hldev;
4017 __hal_virtualpath_t *vpath;
4018
4019 vxge_assert(vpath_handle != NULL);
4020
4021 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
4022
4023 hldev = vpath->hldev;
4024
4025 vxge_hal_trace_log_vpath("==> %s:%s:%d",
4026 __FILE__, __func__, __LINE__);
4027
4028 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
4029 (ptr_t) vpath_handle);
4030
4031 if (vpath->ringh == NULL) {
4032 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
4033 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
4034 return (VXGE_HAL_ERR_INVALID_HANDLE);
4035 }
4036
4037 if (vpath->vp_config->rpa_mcast_all_addr_en ==
4038 VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_DISABLE) {
4039
4040 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
4041 __FILE__, __func__, __LINE__);
4042 return (VXGE_HAL_OK);
4043 }
4044
4045 val64 = vxge_os_pio_mem_read64(
4046 hldev->header.pdev,
4047 hldev->header.regh0,
4048 &vpath->vp_reg->rxmac_vcfg0);
4049
4050 val64 &= ~VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN;
4051
4052 vxge_os_pio_mem_write64(
4053 hldev->header.pdev,
4054 hldev->header.regh0,
4055 val64,
4056 &vpath->vp_reg->rxmac_vcfg0);
4057
4058 vpath->vp_config->rpa_mcast_all_addr_en =
4059 VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_DISABLE;
4060
4061 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
4062 __FILE__, __func__, __LINE__);
4063
4064 return (VXGE_HAL_OK);
4065 }
4066
4067 /*
4068 * vxge_hal_vpath_ucast_enable - Enable unicast addresses.
4069 * @vpath_handle: Vpath handle.
4070 *
4071 * Enable X3100 unicast addresses.
4072 * Returns: VXGE_HAL_OK on success.
4073 *
4074 */
4075 vxge_hal_status_e
vxge_hal_vpath_ucast_enable(vxge_hal_vpath_h vpath_handle)4076 vxge_hal_vpath_ucast_enable(vxge_hal_vpath_h vpath_handle)
4077 {
4078 u64 val64;
4079 __hal_device_t *hldev;
4080 __hal_virtualpath_t *vpath;
4081
4082 vxge_assert(vpath_handle != NULL);
4083
4084 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
4085
4086 hldev = vpath->hldev;
4087
4088 vxge_hal_trace_log_vpath("==> %s:%s:%d",
4089 __FILE__, __func__, __LINE__);
4090
4091 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
4092 (ptr_t) vpath_handle);
4093
4094 if (vpath->ringh == NULL) {
4095 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
4096 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
4097 return (VXGE_HAL_ERR_INVALID_HANDLE);
4098 }
4099
4100 if (vpath->vp_config->rpa_ucast_all_addr_en ==
4101 VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_ENABLE) {
4102 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
4103 __FILE__, __func__, __LINE__);
4104 return (VXGE_HAL_OK);
4105 }
4106
4107 val64 = vxge_os_pio_mem_read64(
4108 hldev->header.pdev,
4109 hldev->header.regh0,
4110 &vpath->vp_reg->rxmac_vcfg0);
4111
4112 val64 |= VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN;
4113
4114 vxge_os_pio_mem_write64(
4115 hldev->header.pdev,
4116 hldev->header.regh0,
4117 val64,
4118 &vpath->vp_reg->rxmac_vcfg0);
4119
4120 vpath->vp_config->rpa_ucast_all_addr_en =
4121 VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_ENABLE;
4122
4123 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
4124 __FILE__, __func__, __LINE__);
4125 return (VXGE_HAL_OK);
4126 }
4127
4128 /*
4129 * vxge_hal_vpath_ucast_disable - Disable unicast addresses.
4130 * @vpath_handle: Vpath handle.
4131 *
4132 * Disable X3100 unicast addresses.
4133 * Returns: VXGE_HAL_OK - success.
4134 * VXGE_HAL_INF_MEM_STROBE_CMD_EXECUTING - Failed to disable mcast
4135 * feature within the time(timeout).
4136 *
4137 */
4138 vxge_hal_status_e
vxge_hal_vpath_ucast_disable(vxge_hal_vpath_h vpath_handle)4139 vxge_hal_vpath_ucast_disable(vxge_hal_vpath_h vpath_handle)
4140 {
4141 u64 val64;
4142 __hal_device_t *hldev;
4143 __hal_virtualpath_t *vpath;
4144
4145 vxge_assert(vpath_handle != NULL);
4146
4147 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
4148
4149 hldev = vpath->hldev;
4150
4151 vxge_hal_trace_log_vpath("==> %s:%s:%d",
4152 __FILE__, __func__, __LINE__);
4153
4154 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
4155 (ptr_t) vpath_handle);
4156
4157 if (vpath->ringh == NULL) {
4158 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
4159 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
4160 return (VXGE_HAL_ERR_INVALID_HANDLE);
4161 }
4162
4163 if (vpath->vp_config->rpa_ucast_all_addr_en ==
4164 VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_DISABLE) {
4165
4166 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
4167 __FILE__, __func__, __LINE__);
4168 return (VXGE_HAL_OK);
4169 }
4170
4171 val64 = vxge_os_pio_mem_read64(
4172 hldev->header.pdev,
4173 hldev->header.regh0,
4174 &vpath->vp_reg->rxmac_vcfg0);
4175
4176 val64 &= ~VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN;
4177
4178 vxge_os_pio_mem_write64(
4179 hldev->header.pdev,
4180 hldev->header.regh0,
4181 val64,
4182 &vpath->vp_reg->rxmac_vcfg0);
4183
4184 vpath->vp_config->rpa_ucast_all_addr_en =
4185 VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_DISABLE;
4186
4187 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
4188 __FILE__, __func__, __LINE__);
4189
4190 return (VXGE_HAL_OK);
4191 }
4192
4193 /*
4194 * vxge_hal_vpath_all_vid_enable - Enable all Vlan Ids.
4195 * @vpath_handle: Vpath handle.
4196 *
4197 * Enable X3100 vlan ids.
4198 * Returns: VXGE_HAL_OK on success.
4199 *
4200 */
4201 vxge_hal_status_e
vxge_hal_vpath_all_vid_enable(vxge_hal_vpath_h vpath_handle)4202 vxge_hal_vpath_all_vid_enable(vxge_hal_vpath_h vpath_handle)
4203 {
4204 u64 val64;
4205 __hal_device_t *hldev;
4206 __hal_virtualpath_t *vpath;
4207
4208 vxge_assert(vpath_handle != NULL);
4209
4210 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
4211
4212 hldev = vpath->hldev;
4213
4214 vxge_hal_trace_log_vpath("==> %s:%s:%d",
4215 __FILE__, __func__, __LINE__);
4216
4217 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
4218 (ptr_t) vpath_handle);
4219
4220 if (vpath->ringh == NULL) {
4221 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
4222 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
4223 return (VXGE_HAL_ERR_INVALID_HANDLE);
4224 }
4225
4226 if (vpath->vp_config->rpa_all_vid_en ==
4227 VXGE_HAL_VPATH_RPA_ALL_VID_ENABLE) {
4228 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
4229 __FILE__, __func__, __LINE__);
4230 return (VXGE_HAL_OK);
4231 }
4232
4233 val64 = vxge_os_pio_mem_read64(
4234 hldev->header.pdev,
4235 hldev->header.regh0,
4236 &vpath->vp_reg->rxmac_vcfg0);
4237
4238 val64 |= VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN;
4239
4240 vxge_os_pio_mem_write64(
4241 hldev->header.pdev,
4242 hldev->header.regh0,
4243 val64,
4244 &vpath->vp_reg->rxmac_vcfg0);
4245
4246 vpath->vp_config->rpa_all_vid_en = VXGE_HAL_VPATH_RPA_ALL_VID_ENABLE;
4247
4248 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
4249 __FILE__, __func__, __LINE__);
4250
4251 return (VXGE_HAL_OK);
4252 }
4253
4254 /*
4255 * vxge_hal_vpath_all_vid_disable - Disable all Vlan Ids.
4256 * @vpath_handle: Vpath handle.
4257 *
4258 * Disable X3100 vlan ids.
4259 * Returns: VXGE_HAL_OK - success.
4260 *
4261 */
4262 vxge_hal_status_e
vxge_hal_vpath_all_vid_disable(vxge_hal_vpath_h vpath_handle)4263 vxge_hal_vpath_all_vid_disable(vxge_hal_vpath_h vpath_handle)
4264 {
4265 u64 val64;
4266 __hal_device_t *hldev;
4267 __hal_virtualpath_t *vpath;
4268
4269 vxge_assert(vpath_handle != NULL);
4270
4271 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
4272
4273 hldev = vpath->hldev;
4274
4275 vxge_hal_trace_log_vpath("==> %s:%s:%d",
4276 __FILE__, __func__, __LINE__);
4277
4278 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
4279 (ptr_t) vpath_handle);
4280
4281 if (vpath->ringh == NULL) {
4282 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
4283 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
4284 return (VXGE_HAL_ERR_INVALID_HANDLE);
4285 }
4286
4287 if (vpath->vp_config->rpa_all_vid_en ==
4288 VXGE_HAL_VPATH_RPA_ALL_VID_DISABLE) {
4289
4290 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
4291 __FILE__, __func__, __LINE__);
4292 return (VXGE_HAL_OK);
4293 }
4294
4295 val64 = vxge_os_pio_mem_read64(
4296 hldev->header.pdev,
4297 hldev->header.regh0,
4298 &vpath->vp_reg->rxmac_vcfg0);
4299
4300 val64 &= ~VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN;
4301
4302 vxge_os_pio_mem_write64(
4303 hldev->header.pdev,
4304 hldev->header.regh0,
4305 val64,
4306 &vpath->vp_reg->rxmac_vcfg0);
4307
4308 vpath->vp_config->rpa_all_vid_en = VXGE_HAL_VPATH_RPA_ALL_VID_DISABLE;
4309
4310 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
4311 __FILE__, __func__, __LINE__);
4312
4313 return (VXGE_HAL_OK);
4314 }
4315
4316 /*
4317 * vxge_hal_vpath_strip_vlan_tag_enable - Enable strip vlan tag.
4318 * @vpath_handle: Vpath handle.
4319 *
4320 * Enable X3100 strip vlan tag.
4321 * Returns: VXGE_HAL_OK on success.
4322 *
4323 */
4324 vxge_hal_status_e
vxge_hal_vpath_strip_vlan_tag_enable(vxge_hal_vpath_h vpath_handle)4325 vxge_hal_vpath_strip_vlan_tag_enable(vxge_hal_vpath_h vpath_handle)
4326 {
4327 u64 val64;
4328 __hal_device_t *hldev;
4329 __hal_virtualpath_t *vpath;
4330
4331 vxge_assert(vpath_handle != NULL);
4332
4333 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
4334
4335 hldev = vpath->hldev;
4336
4337 vxge_hal_trace_log_vpath("==> %s:%s:%d",
4338 __FILE__, __func__, __LINE__);
4339
4340 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
4341 (ptr_t) vpath_handle);
4342
4343 if (vpath->ringh == NULL) {
4344 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
4345 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
4346 return (VXGE_HAL_ERR_INVALID_HANDLE);
4347 }
4348
4349 if (vpath->vp_config->rpa_strip_vlan_tag ==
4350 VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_ENABLE) {
4351 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
4352 __FILE__, __func__, __LINE__);
4353 return (VXGE_HAL_OK);
4354 }
4355
4356 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4357 hldev->header.regh0,
4358 &vpath->vp_reg->xmac_rpa_vcfg);
4359
4360 val64 |= VXGE_HAL_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
4361
4362 vxge_os_pio_mem_write64(hldev->header.pdev,
4363 hldev->header.regh0,
4364 val64,
4365 &vpath->vp_reg->xmac_rpa_vcfg);
4366
4367 vpath->vp_config->rpa_strip_vlan_tag =
4368 VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_ENABLE;
4369
4370 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
4371 __FILE__, __func__, __LINE__);
4372
4373 return (VXGE_HAL_OK);
4374 }
4375
4376 /*
4377 * vxge_hal_vpath_strip_vlan_tag_disable - Disable strip vlan tag.
4378 * @vpath_handle: Vpath handle.
4379 *
4380 * Disable X3100 strip vlan tag.
4381 * Returns: VXGE_HAL_OK - success.
4382 *
4383 */
4384 vxge_hal_status_e
vxge_hal_vpath_strip_vlan_tag_disable(vxge_hal_vpath_h vpath_handle)4385 vxge_hal_vpath_strip_vlan_tag_disable(vxge_hal_vpath_h vpath_handle)
4386 {
4387 u64 val64;
4388 __hal_device_t *hldev;
4389 __hal_virtualpath_t *vpath;
4390
4391 vxge_assert(vpath_handle != NULL);
4392
4393 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
4394
4395 hldev = vpath->hldev;
4396
4397 vxge_hal_trace_log_vpath("==> %s:%s:%d",
4398 __FILE__, __func__, __LINE__);
4399
4400 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
4401 (ptr_t) vpath_handle);
4402
4403 if (vpath->ringh == NULL) {
4404 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
4405 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
4406 return (VXGE_HAL_ERR_INVALID_HANDLE);
4407 }
4408
4409 if (vpath->vp_config->rpa_strip_vlan_tag ==
4410 VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_DISABLE) {
4411 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
4412 __FILE__, __func__, __LINE__);
4413 return (VXGE_HAL_OK);
4414 }
4415
4416 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4417 hldev->header.regh0,
4418 &vpath->vp_reg->xmac_rpa_vcfg);
4419
4420 val64 &= ~VXGE_HAL_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
4421
4422 vxge_os_pio_mem_write64(hldev->header.pdev,
4423 hldev->header.regh0,
4424 val64,
4425 &vpath->vp_reg->xmac_rpa_vcfg);
4426
4427 vpath->vp_config->rpa_strip_vlan_tag =
4428 VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_DISABLE;
4429
4430 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
4431 __FILE__, __func__, __LINE__);
4432
4433 return (VXGE_HAL_OK);
4434 }
4435
4436 /*
4437 * vxge_hal_vpath_tpa_set - Set tpa parameters.
4438 * @vpath_handle: Virtual Path ahandle.
4439 * @params: vxge_hal_vpath_tpa_params {} structure with parameters
4440 *
4441 * The function sets the tpa parametrs for the vpath.
4442 *
4443 * See also: vxge_hal_vpath_tpa_params {}
4444 */
4445 vxge_hal_status_e
vxge_hal_vpath_tpa_set(vxge_hal_vpath_h vpath_handle,vxge_hal_vpath_tpa_params * params)4446 vxge_hal_vpath_tpa_set(vxge_hal_vpath_h vpath_handle,
4447 vxge_hal_vpath_tpa_params *params)
4448 {
4449 u64 val64;
4450 __hal_device_t *hldev;
4451 __hal_virtualpath_t *vpath;
4452
4453 vxge_assert((vpath_handle != NULL) && (params != NULL));
4454
4455 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
4456
4457 hldev = vpath->hldev;
4458
4459 vxge_hal_trace_log_vpath("==> %s:%s:%d",
4460 __FILE__, __func__, __LINE__);
4461
4462 vxge_hal_trace_log_vpath(
4463 "vpath_handle = 0x"VXGE_OS_STXFMT", params = 0x"VXGE_OS_STXFMT,
4464 (ptr_t) vpath_handle, (ptr_t) params);
4465
4466 if (vpath->fifoh == NULL) {
4467 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
4468 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
4469 return (VXGE_HAL_ERR_INVALID_HANDLE);
4470 }
4471
4472 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4473 hldev->header.regh0,
4474 &vpath->vp_reg->tpa_cfg);
4475
4476 if (params->tpa_ignore_frame_error != VXGE_HAL_DEFAULT_32) {
4477 if (params->tpa_ignore_frame_error)
4478 val64 |= VXGE_HAL_TPA_CFG_IGNORE_FRAME_ERR;
4479 else
4480 val64 &= ~VXGE_HAL_TPA_CFG_IGNORE_FRAME_ERR;
4481 }
4482
4483 if (params->tpa_ipv6_keep_searching != VXGE_HAL_DEFAULT_32) {
4484 if (params->tpa_ipv6_keep_searching)
4485 val64 &= ~VXGE_HAL_TPA_CFG_IPV6_STOP_SEARCHING;
4486 else
4487 val64 |= VXGE_HAL_TPA_CFG_IPV6_STOP_SEARCHING;
4488 }
4489
4490 if (params->tpa_l4_pshdr_present != VXGE_HAL_DEFAULT_32) {
4491 if (params->tpa_l4_pshdr_present)
4492 val64 |= VXGE_HAL_TPA_CFG_L4_PSHDR_PRESENT;
4493 else
4494 val64 &= ~VXGE_HAL_TPA_CFG_L4_PSHDR_PRESENT;
4495 }
4496
4497 if (params->tpa_support_mobile_ipv6_hdrs != VXGE_HAL_DEFAULT_32) {
4498 if (params->tpa_support_mobile_ipv6_hdrs)
4499 val64 |= VXGE_HAL_TPA_CFG_SUPPORT_MOBILE_IPV6_HDRS;
4500 else
4501 val64 &= ~VXGE_HAL_TPA_CFG_SUPPORT_MOBILE_IPV6_HDRS;
4502 }
4503
4504 vxge_os_pio_mem_write64(hldev->header.pdev,
4505 hldev->header.regh0,
4506 val64,
4507 &vpath->vp_reg->tpa_cfg);
4508
4509 vpath->vp_config->tpa_ignore_frame_error =
4510 params->tpa_ignore_frame_error;
4511 vpath->vp_config->tpa_l4_pshdr_present =
4512 params->tpa_l4_pshdr_present;
4513 vpath->vp_config->tpa_support_mobile_ipv6_hdrs =
4514 params->tpa_support_mobile_ipv6_hdrs;
4515
4516 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4517 hldev->header.regh0,
4518 &vpath->vp_reg->tx_protocol_assist_cfg);
4519
4520 if (params->tpa_lsov2_en != VXGE_HAL_DEFAULT_32) {
4521 if (params->tpa_lsov2_en)
4522 val64 |= VXGE_HAL_TX_PROTOCOL_ASSIST_CFG_LSOV2_EN;
4523 else
4524 val64 &= ~VXGE_HAL_TX_PROTOCOL_ASSIST_CFG_LSOV2_EN;
4525 }
4526
4527 if (params->tpa_ipv6_keep_searching != VXGE_HAL_DEFAULT_32) {
4528 if (params->tpa_ipv6_keep_searching)
4529 val64 |=
4530 VXGE_HAL_TX_PROTOCOL_ASSIST_CFG_IPV6_KEEP_SEARCHING;
4531 else
4532 val64 &=
4533 ~VXGE_HAL_TX_PROTOCOL_ASSIST_CFG_IPV6_KEEP_SEARCHING;
4534 }
4535
4536 vxge_os_pio_mem_write64(hldev->header.pdev,
4537 hldev->header.regh0,
4538 val64,
4539 &vpath->vp_reg->tx_protocol_assist_cfg);
4540
4541 vpath->vp_config->tpa_lsov2_en = params->tpa_lsov2_en;
4542 vpath->vp_config->tpa_ipv6_keep_searching =
4543 params->tpa_ipv6_keep_searching;
4544
4545 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
4546 __FILE__, __func__, __LINE__);
4547
4548 return (VXGE_HAL_OK);
4549 }
4550
4551 /*
4552 * vxge_hal_vpath_rpa_set - Set rpa parameters.
4553 * @vpath_handle: Virtual Path ahandle.
4554 * @params: vxge_hal_vpath_rpa_params {} structure with parameters
4555 *
4556 * The function sets the rpa parametrs for the vpath.
4557 *
4558 * See also: vxge_hal_vpath_rpa_params {}
4559 */
4560 vxge_hal_status_e
vxge_hal_vpath_rpa_set(vxge_hal_vpath_h vpath_handle,vxge_hal_vpath_rpa_params * params)4561 vxge_hal_vpath_rpa_set(vxge_hal_vpath_h vpath_handle,
4562 vxge_hal_vpath_rpa_params *params)
4563 {
4564 u64 val64;
4565 __hal_device_t *hldev;
4566 __hal_virtualpath_t *vpath;
4567
4568 vxge_assert((vpath_handle != NULL) && (params != NULL));
4569
4570 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
4571
4572 hldev = vpath->hldev;
4573
4574 vxge_hal_trace_log_vpath("==> %s:%s:%d",
4575 __FILE__, __func__, __LINE__);
4576
4577 vxge_hal_trace_log_vpath(
4578 "vpath_handle = 0x"VXGE_OS_STXFMT", params = 0x"VXGE_OS_STXFMT,
4579 (ptr_t) vpath_handle, (ptr_t) params);
4580
4581 if (vpath->ringh == NULL) {
4582 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
4583 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
4584 return (VXGE_HAL_ERR_INVALID_HANDLE);
4585 }
4586
4587 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4588 hldev->header.regh0,
4589 &vpath->vp_reg->xmac_rpa_vcfg);
4590
4591 if (params->rpa_ipv4_tcp_incl_ph != VXGE_HAL_DEFAULT_32) {
4592 if (params->rpa_ipv4_tcp_incl_ph)
4593 val64 |= VXGE_HAL_XMAC_RPA_VCFG_IPV4_TCP_INCL_PH;
4594 else
4595 val64 &= ~VXGE_HAL_XMAC_RPA_VCFG_IPV4_TCP_INCL_PH;
4596 }
4597
4598 if (params->rpa_ipv6_tcp_incl_ph != VXGE_HAL_DEFAULT_32) {
4599 if (params->rpa_ipv6_tcp_incl_ph)
4600 val64 |= VXGE_HAL_XMAC_RPA_VCFG_IPV6_TCP_INCL_PH;
4601 else
4602 val64 &= ~VXGE_HAL_XMAC_RPA_VCFG_IPV6_TCP_INCL_PH;
4603 }
4604
4605 if (params->rpa_ipv4_udp_incl_ph != VXGE_HAL_DEFAULT_32) {
4606 if (params->rpa_ipv4_udp_incl_ph)
4607 val64 |= VXGE_HAL_XMAC_RPA_VCFG_IPV4_UDP_INCL_PH;
4608 else
4609 val64 &= ~VXGE_HAL_XMAC_RPA_VCFG_IPV4_UDP_INCL_PH;
4610 }
4611
4612 if (params->rpa_ipv6_udp_incl_ph != VXGE_HAL_DEFAULT_32) {
4613 if (params->rpa_ipv6_udp_incl_ph)
4614 val64 |= VXGE_HAL_XMAC_RPA_VCFG_IPV6_UDP_INCL_PH;
4615 else
4616 val64 &= ~VXGE_HAL_XMAC_RPA_VCFG_IPV6_UDP_INCL_PH;
4617 }
4618
4619 if (params->rpa_l4_incl_cf != VXGE_HAL_DEFAULT_32) {
4620 if (params->rpa_l4_incl_cf)
4621 val64 |= VXGE_HAL_XMAC_RPA_VCFG_L4_INCL_CF;
4622 else
4623 val64 &= ~VXGE_HAL_XMAC_RPA_VCFG_L4_INCL_CF;
4624 }
4625
4626 if (params->rpa_strip_vlan_tag != VXGE_HAL_DEFAULT_32) {
4627 if (params->rpa_strip_vlan_tag)
4628 val64 |= VXGE_HAL_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
4629 else
4630 val64 &= ~VXGE_HAL_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
4631 }
4632
4633 vxge_os_pio_mem_write64(hldev->header.pdev,
4634 hldev->header.regh0,
4635 val64,
4636 &vpath->vp_reg->xmac_rpa_vcfg);
4637
4638 vpath->vp_config->rpa_ipv4_tcp_incl_ph = params->rpa_ipv4_tcp_incl_ph;
4639 vpath->vp_config->rpa_ipv6_tcp_incl_ph = params->rpa_ipv6_tcp_incl_ph;
4640 vpath->vp_config->rpa_ipv4_udp_incl_ph = params->rpa_ipv4_udp_incl_ph;
4641 vpath->vp_config->rpa_ipv6_udp_incl_ph = params->rpa_ipv6_udp_incl_ph;
4642 vpath->vp_config->rpa_l4_incl_cf = params->rpa_l4_incl_cf;
4643 vpath->vp_config->rpa_strip_vlan_tag = params->rpa_strip_vlan_tag;
4644
4645 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4646 hldev->header.regh0,
4647 &vpath->vp_reg->rxmac_vcfg0);
4648
4649 if (params->rpa_ucast_all_addr_en != VXGE_HAL_DEFAULT_32) {
4650 if (params->rpa_ucast_all_addr_en)
4651 val64 |= VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN;
4652 else
4653 val64 &= ~VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN;
4654 }
4655
4656 if (params->rpa_mcast_all_addr_en != VXGE_HAL_DEFAULT_32) {
4657 if (params->rpa_mcast_all_addr_en)
4658 val64 |= VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN;
4659 else
4660 val64 &= ~VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN;
4661 }
4662
4663 if (params->rpa_bcast_en != VXGE_HAL_DEFAULT_32) {
4664 if (params->rpa_bcast_en)
4665 val64 |= VXGE_HAL_RXMAC_VCFG0_BCAST_EN;
4666 else
4667 val64 &= ~VXGE_HAL_RXMAC_VCFG0_BCAST_EN;
4668 }
4669
4670 if (params->rpa_all_vid_en != VXGE_HAL_DEFAULT_32) {
4671 if (params->rpa_all_vid_en)
4672 val64 |= VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN;
4673 else
4674 val64 &= ~VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN;
4675 }
4676
4677 vxge_os_pio_mem_write64(hldev->header.pdev,
4678 hldev->header.regh0,
4679 val64,
4680 &vpath->vp_reg->rxmac_vcfg0);
4681
4682 vpath->vp_config->rpa_ucast_all_addr_en = params->rpa_ucast_all_addr_en;
4683 vpath->vp_config->rpa_mcast_all_addr_en = params->rpa_mcast_all_addr_en;
4684 vpath->vp_config->rpa_bcast_en = params->rpa_bcast_en;
4685 vpath->vp_config->rpa_all_vid_en = params->rpa_all_vid_en;
4686
4687 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4688 hldev->header.regh0,
4689 &vpath->vp_reg->fau_rpa_vcfg);
4690
4691 if (params->rpa_l4_comp_csum != VXGE_HAL_DEFAULT_32) {
4692 if (params->rpa_l4_comp_csum)
4693 val64 |= VXGE_HAL_FAU_RPA_VCFG_L4_COMP_CSUM;
4694 else
4695 val64 &= ~VXGE_HAL_FAU_RPA_VCFG_L4_COMP_CSUM;
4696 }
4697
4698 if (params->rpa_l3_incl_cf != VXGE_HAL_DEFAULT_32) {
4699 if (params->rpa_l3_incl_cf)
4700 val64 |= VXGE_HAL_FAU_RPA_VCFG_L3_INCL_CF;
4701 else
4702 val64 &= ~VXGE_HAL_FAU_RPA_VCFG_L3_INCL_CF;
4703 }
4704
4705 if (params->rpa_l3_comp_csum != VXGE_HAL_DEFAULT_32) {
4706 if (params->rpa_l3_comp_csum)
4707 val64 |= VXGE_HAL_FAU_RPA_VCFG_L3_COMP_CSUM;
4708 else
4709 val64 &= ~VXGE_HAL_FAU_RPA_VCFG_L3_COMP_CSUM;
4710 }
4711
4712 vxge_os_pio_mem_write64(hldev->header.pdev,
4713 hldev->header.regh0,
4714 val64,
4715 &vpath->vp_reg->fau_rpa_vcfg);
4716
4717 vpath->vp_config->rpa_l4_comp_csum = params->rpa_l4_comp_csum;
4718 vpath->vp_config->rpa_l3_incl_cf = params->rpa_l3_incl_cf;
4719 vpath->vp_config->rpa_l3_comp_csum = params->rpa_l3_comp_csum;
4720
4721 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
4722 __FILE__, __func__, __LINE__);
4723
4724 return (VXGE_HAL_OK);
4725 }
4726
4727 /*
4728 * __hal_vpath_intr_enable - Enable vpath interrupts.
4729 * @vpath: Virtual Path.
4730 * @op: One of the vxge_hal_vpath_intr_e enumerated values specifying
4731 * the type(s) of interrupts to enable.
4732 *
4733 * Enable vpath interrupts. The function is to be executed the last in
4734 * vpath initialization sequence.
4735 *
4736 * See also: __hal_vpath_intr_disable()
4737 */
4738 vxge_hal_status_e
__hal_vpath_intr_enable(__hal_virtualpath_t * vpath)4739 __hal_vpath_intr_enable(__hal_virtualpath_t *vpath)
4740 {
4741 u64 val64;
4742 __hal_device_t *hldev;
4743
4744 vxge_assert(vpath != NULL);
4745
4746 hldev = vpath->hldev;
4747
4748 vxge_hal_trace_log_vpath("==> %s:%s:%d",
4749 __FILE__, __func__, __LINE__);
4750
4751 vxge_hal_trace_log_vpath("vpath = 0x"VXGE_OS_STXFMT,
4752 (ptr_t) vpath);
4753
4754 if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
4755 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
4756 __FILE__, __func__, __LINE__,
4757 VXGE_HAL_ERR_VPATH_NOT_OPEN);
4758 return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
4759 }
4760
4761 vxge_os_pio_mem_write64(hldev->header.pdev,
4762 hldev->header.regh0,
4763 VXGE_HAL_INTR_MASK_ALL,
4764 &vpath->vp_reg->kdfcctl_errors_reg);
4765
4766 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
4767 hldev->header.regh0,
4768 (u32) VXGE_HAL_INTR_MASK_ALL,
4769 &vpath->vp_reg->general_errors_reg);
4770
4771 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
4772 hldev->header.regh0,
4773 (u32) VXGE_HAL_INTR_MASK_ALL,
4774 &vpath->vp_reg->pci_config_errors_reg);
4775
4776 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
4777 hldev->header.regh0,
4778 (u32) VXGE_HAL_INTR_MASK_ALL,
4779 &vpath->vp_reg->mrpcim_to_vpath_alarm_reg);
4780
4781 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
4782 hldev->header.regh0,
4783 (u32) VXGE_HAL_INTR_MASK_ALL,
4784 &vpath->vp_reg->srpcim_to_vpath_alarm_reg);
4785
4786 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
4787 hldev->header.regh0,
4788 (u32) VXGE_HAL_INTR_MASK_ALL,
4789 &vpath->vp_reg->vpath_ppif_int_status);
4790
4791 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
4792 hldev->header.regh0,
4793 (u32) VXGE_HAL_INTR_MASK_ALL,
4794 &vpath->vp_reg->srpcim_msg_to_vpath_reg);
4795
4796 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
4797 hldev->header.regh0,
4798 (u32) VXGE_HAL_INTR_MASK_ALL,
4799 &vpath->vp_reg->vpath_pcipif_int_status);
4800
4801 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
4802 hldev->header.regh0,
4803 (u32) VXGE_HAL_INTR_MASK_ALL,
4804 &vpath->vp_reg->prc_alarm_reg);
4805
4806 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
4807 hldev->header.regh0,
4808 (u32) VXGE_HAL_INTR_MASK_ALL,
4809 &vpath->vp_reg->wrdma_alarm_status);
4810
4811 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
4812 hldev->header.regh0,
4813 (u32) VXGE_HAL_INTR_MASK_ALL,
4814 &vpath->vp_reg->asic_ntwk_vp_err_reg);
4815
4816 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
4817 hldev->header.regh0,
4818 (u32) VXGE_HAL_INTR_MASK_ALL,
4819 &vpath->vp_reg->xgmac_vp_int_status);
4820
4821 vxge_os_pio_mem_read64(hldev->header.pdev,
4822 hldev->header.regh0,
4823 &vpath->vp_reg->vpath_general_int_status);
4824
4825 /* Unmask the individual interrupts. */
4826 vxge_os_pio_mem_write64(hldev->header.pdev,
4827 hldev->header.regh0,
4828 0,
4829 &vpath->vp_reg->kdfcctl_errors_mask);
4830
4831 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
4832 hldev->header.regh0,
4833 0,
4834 &vpath->vp_reg->general_errors_mask);
4835
4836 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
4837 hldev->header.regh0,
4838 (u32) VXGE_HAL_INTR_MASK_ALL,
4839 &vpath->vp_reg->pci_config_errors_mask);
4840
4841 if (hldev->first_vp_id != vpath->vp_id) {
4842 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
4843 hldev->header.regh0,
4844 (u32) VXGE_HAL_INTR_MASK_ALL,
4845 &vpath->vp_reg->mrpcim_to_vpath_alarm_mask);
4846
4847 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
4848 hldev->header.regh0,
4849 (u32) VXGE_HAL_INTR_MASK_ALL,
4850 &vpath->vp_reg->srpcim_to_vpath_alarm_mask);
4851 } else {
4852 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
4853 hldev->header.regh0,
4854 0,
4855 &vpath->vp_reg->mrpcim_to_vpath_alarm_mask);
4856
4857 if (hldev->access_rights &
4858 VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM) {
4859 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
4860 hldev->header.regh0,
4861 0,
4862 &vpath->vp_reg->srpcim_to_vpath_alarm_mask);
4863 }
4864 }
4865
4866 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
4867 hldev->header.regh0,
4868 0,
4869 &vpath->vp_reg->vpath_ppif_int_mask);
4870
4871 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
4872 hldev->header.regh0,
4873 (u32) VXGE_HAL_INTR_MASK_ALL,
4874 &vpath->vp_reg->srpcim_msg_to_vpath_mask);
4875
4876 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
4877 hldev->header.regh0,
4878 0,
4879 &vpath->vp_reg->vpath_pcipif_int_mask);
4880
4881 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
4882 hldev->header.regh0,
4883 (u32) bVAL32(VXGE_HAL_PRC_ALARM_REG_PRC_RING_BUMP, 0),
4884 &vpath->vp_reg->prc_alarm_mask);
4885
4886 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
4887 hldev->header.regh0,
4888 0,
4889 &vpath->vp_reg->wrdma_alarm_mask);
4890
4891 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
4892 hldev->header.regh0,
4893 0,
4894 &vpath->vp_reg->xgmac_vp_int_mask);
4895
4896 if (hldev->first_vp_id != vpath->vp_id) {
4897 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
4898 hldev->header.regh0,
4899 (u32) VXGE_HAL_INTR_MASK_ALL,
4900 &vpath->vp_reg->asic_ntwk_vp_err_mask);
4901 } else {
4902 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
4903 hldev->header.regh0, (u32) bVAL32((
4904 VXGE_HAL_ASIC_NTWK_VP_ERR_REG_REAF_FAULT |
4905 VXGE_HAL_ASIC_NTWK_VP_ERR_REG_REAF_OK), 0),
4906 &vpath->vp_reg->asic_ntwk_vp_err_mask);
4907 }
4908
4909 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4910 hldev->header.regh0,
4911 &hldev->common_reg->tim_int_en);
4912
4913 /* val64 |= VXGE_HAL_TIM_SET_INT_EN_VP(1 << (16 - vpath->vp_id)); */
4914
4915 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
4916 hldev->header.regh0,
4917 (u32) bVAL32(val64, 0),
4918 &hldev->common_reg->tim_set_int_en);
4919
4920 vxge_hal_pio_mem_write32_upper(
4921 hldev->header.pdev,
4922 hldev->header.regh0,
4923 0,
4924 &vpath->vp_reg->vpath_general_int_mask);
4925
4926 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
4927 __FILE__, __func__, __LINE__);
4928
4929 return (VXGE_HAL_OK);
4930
4931 }
4932
4933 /*
4934 * vxge_hal_vpath_intr_enable - Enable vpath interrupts.
4935 * @vpath_handle: Virtual Path handle.
4936 * @op: One of the vxge_hal_vpath_intr_e enumerated values specifying
4937 * the type(s) of interrupts to enable.
4938 *
4939 * Enable vpath interrupts. The function is to be executed the last in
4940 * vpath initialization sequence.
4941 *
4942 * See also: vxge_hal_vpath_intr_disable()
4943 */
4944 vxge_hal_status_e
vxge_hal_vpath_intr_enable(vxge_hal_vpath_h vpath_handle)4945 vxge_hal_vpath_intr_enable(vxge_hal_vpath_h vpath_handle)
4946 {
4947 vxge_hal_status_e status;
4948
4949 __hal_device_t *hldev;
4950 __hal_vpath_handle_t *vp;
4951
4952 vxge_assert(vpath_handle != NULL);
4953
4954 vp = (__hal_vpath_handle_t *) vpath_handle;
4955 hldev = vp->vpath->hldev;
4956
4957 vxge_hal_trace_log_vpath("==> %s:%s:%d",
4958 __FILE__, __func__, __LINE__);
4959
4960 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
4961 (ptr_t) vpath_handle);
4962
4963 status = __hal_vpath_intr_enable((__hal_virtualpath_t *) vp->vpath);
4964
4965 vxge_hal_vpath_unmask_all(vpath_handle);
4966
4967 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = %d",
4968 __FILE__, __func__, __LINE__, status);
4969
4970 return (status);
4971
4972 }
4973
4974 /*
4975 * __hal_vpath_intr_disable - Disable vpath interrupts.
4976 * @vpath: Virtual Path.
4977 * @op: One of the vxge_hal_vpath_intr_e enumerated values specifying
4978 * the type(s) of interrupts to enable.
4979 *
4980 * Disable vpath interrupts. The function is to be executed the last in
4981 * vpath initialization sequence.
4982 *
4983 * See also: __hal_vpath_intr_enable()
4984 */
4985 vxge_hal_status_e
__hal_vpath_intr_disable(__hal_virtualpath_t * vpath)4986 __hal_vpath_intr_disable(__hal_virtualpath_t *vpath)
4987 {
4988 u64 val64;
4989 __hal_device_t *hldev;
4990
4991 vxge_assert(vpath != NULL);
4992
4993 hldev = vpath->hldev;
4994
4995 vxge_hal_trace_log_vpath("==> %s:%s:%d",
4996 __FILE__, __func__, __LINE__);
4997
4998 vxge_hal_trace_log_vpath("vpath = 0x"VXGE_OS_STXFMT,
4999 (ptr_t) vpath);
5000
5001 if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
5002 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
5003 __FILE__, __func__, __LINE__,
5004 VXGE_HAL_ERR_VPATH_NOT_OPEN);
5005
5006 return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
5007 }
5008
5009 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
5010 hldev->header.regh0,
5011 (u32) VXGE_HAL_INTR_MASK_ALL,
5012 &vpath->vp_reg->vpath_general_int_mask);
5013
5014 val64 = VXGE_HAL_TIM_CLR_INT_EN_VP(1 << (16 - vpath->vp_id));
5015
5016 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
5017 hldev->header.regh0,
5018 (u32) bVAL32(val64, 0),
5019 &hldev->common_reg->tim_clr_int_en);
5020
5021 vxge_os_pio_mem_write64(hldev->header.pdev,
5022 hldev->header.regh0,
5023 VXGE_HAL_INTR_MASK_ALL,
5024 &vpath->vp_reg->kdfcctl_errors_mask);
5025
5026 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
5027 hldev->header.regh0,
5028 (u32) VXGE_HAL_INTR_MASK_ALL,
5029 &vpath->vp_reg->general_errors_mask);
5030
5031 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
5032 hldev->header.regh0,
5033 (u32) VXGE_HAL_INTR_MASK_ALL,
5034 &vpath->vp_reg->pci_config_errors_mask);
5035
5036 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
5037 hldev->header.regh0,
5038 (u32) VXGE_HAL_INTR_MASK_ALL,
5039 &vpath->vp_reg->mrpcim_to_vpath_alarm_mask);
5040
5041 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
5042 hldev->header.regh0,
5043 (u32) VXGE_HAL_INTR_MASK_ALL,
5044 &vpath->vp_reg->srpcim_to_vpath_alarm_mask);
5045
5046 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
5047 hldev->header.regh0,
5048 (u32) VXGE_HAL_INTR_MASK_ALL,
5049 &vpath->vp_reg->vpath_ppif_int_mask);
5050
5051 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
5052 hldev->header.regh0,
5053 (u32) VXGE_HAL_INTR_MASK_ALL,
5054 &vpath->vp_reg->srpcim_msg_to_vpath_mask);
5055
5056 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
5057 hldev->header.regh0,
5058 (u32) VXGE_HAL_INTR_MASK_ALL,
5059 &vpath->vp_reg->vpath_pcipif_int_mask);
5060
5061 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
5062 hldev->header.regh0,
5063 (u32) VXGE_HAL_INTR_MASK_ALL,
5064 &vpath->vp_reg->prc_alarm_mask);
5065
5066 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
5067 hldev->header.regh0,
5068 (u32) VXGE_HAL_INTR_MASK_ALL,
5069 &vpath->vp_reg->wrdma_alarm_mask);
5070
5071 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
5072 hldev->header.regh0,
5073 (u32) VXGE_HAL_INTR_MASK_ALL,
5074 &vpath->vp_reg->asic_ntwk_vp_err_mask);
5075
5076 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
5077 hldev->header.regh0,
5078 (u32) VXGE_HAL_INTR_MASK_ALL,
5079 &vpath->vp_reg->xgmac_vp_int_mask);
5080
5081 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
5082 __FILE__, __func__, __LINE__);
5083
5084 return (VXGE_HAL_OK);
5085
5086 }
5087 /*
5088 * vxge_hal_vpath_intr_disable - Disable vpath interrupts.
5089 * @vpath_handle: Virtual Path handle.
5090 * @op: One of the vxge_hal_vpath_intr_e enumerated values specifying
5091 * the type(s) of interrupts to disable.
5092 *
5093 * Disable vpath interrupts.
5094 *
5095 * See also: vxge_hal_vpath_intr_enable()
5096 */
5097 vxge_hal_status_e
vxge_hal_vpath_intr_disable(vxge_hal_vpath_h vpath_handle)5098 vxge_hal_vpath_intr_disable(vxge_hal_vpath_h vpath_handle)
5099 {
5100 __hal_device_t *hldev;
5101 __hal_virtualpath_t *vpath;
5102
5103 vxge_assert(vpath_handle != NULL);
5104
5105 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
5106 hldev = vpath->hldev;
5107
5108 vxge_hal_trace_log_vpath("==> %s:%s:%d",
5109 __FILE__, __func__, __LINE__);
5110
5111 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
5112 (ptr_t) vpath_handle);
5113
5114 vxge_hal_vpath_mask_all(vpath_handle);
5115
5116 (void) __hal_vpath_intr_disable(vpath);
5117
5118 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
5119 __FILE__, __func__, __LINE__);
5120
5121 return (VXGE_HAL_OK);
5122 }
5123
5124 /*
5125 * vxge_hal_vpath_mask_all - Mask all vpath interrupts.
5126 * @vpath_handle: Virtual Path handle.
5127 *
5128 * Mask all vpath interrupts.
5129 *
5130 * See also: vxge_hal_vpath_unmask_all()
5131 */
5132 void
vxge_hal_vpath_mask_all(vxge_hal_vpath_h vpath_handle)5133 vxge_hal_vpath_mask_all(vxge_hal_vpath_h vpath_handle)
5134 {
5135 u64 val64;
5136
5137 __hal_device_t *hldev;
5138 __hal_vpath_handle_t *vp;
5139
5140 vxge_assert(vpath_handle != NULL);
5141
5142 vp = (__hal_vpath_handle_t *) vpath_handle;
5143 hldev = vp->vpath->hldev;
5144
5145 vxge_hal_trace_log_vpath("==> %s:%s:%d",
5146 __FILE__, __func__, __LINE__);
5147
5148 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
5149 (ptr_t) vpath_handle);
5150
5151 val64 = VXGE_HAL_VPATH_GENERAL_INT_MASK_PIC_INT |
5152 VXGE_HAL_VPATH_GENERAL_INT_MASK_PCI_INT |
5153 VXGE_HAL_VPATH_GENERAL_INT_MASK_WRDMA_INT |
5154 VXGE_HAL_VPATH_GENERAL_INT_MASK_XMAC_INT;
5155
5156 vxge_hal_pio_mem_write32_upper(
5157 hldev->header.pdev,
5158 hldev->header.regh0,
5159 (u32) bVAL32(val64, 0),
5160 &vp->vpath->vp_reg->vpath_general_int_mask);
5161
5162 if (vp->vpath->vp_id < 16) {
5163
5164 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5165 hldev->header.regh0,
5166 &hldev->common_reg->tim_int_mask0);
5167
5168 val64 |= vBIT(0xf, (vp->vpath->vp_id * 4), 4);
5169
5170 vxge_os_pio_mem_write64(hldev->header.pdev,
5171 hldev->header.regh0,
5172 val64,
5173 &hldev->common_reg->tim_int_mask0);
5174
5175 } else {
5176
5177 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
5178 hldev->header.regh0,
5179 (u32) bVAL32(VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(0xf), 0),
5180 &hldev->common_reg->tim_int_mask1);
5181
5182 }
5183
5184 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
5185 __FILE__, __func__, __LINE__);
5186 }
5187
5188 /*
5189 * vxge_hal_vpath_unmask_all - Unmask all vpath interrupts.
5190 * @vpath_handle: Virtual Path handle.
5191 *
5192 * Unmask all vpath interrupts.
5193 *
5194 * See also: vxge_hal_vpath_mask_all()
5195 */
5196 void
vxge_hal_vpath_unmask_all(vxge_hal_vpath_h vpath_handle)5197 vxge_hal_vpath_unmask_all(vxge_hal_vpath_h vpath_handle)
5198 {
5199 u64 val64;
5200 __hal_device_t *hldev;
5201 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
5202
5203 vxge_assert(vpath_handle != NULL);
5204
5205 hldev = vp->vpath->hldev;
5206
5207 vxge_hal_trace_log_vpath("==> %s:%s:%d",
5208 __FILE__, __func__, __LINE__);
5209
5210 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
5211 (ptr_t) vpath_handle);
5212
5213 if (vp == NULL) {
5214 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
5215 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
5216 return;
5217 }
5218
5219 vxge_hal_pio_mem_write32_upper(
5220 hldev->header.pdev,
5221 hldev->header.regh0,
5222 0,
5223 &vp->vpath->vp_reg->vpath_general_int_mask);
5224
5225 if (vp->vpath->vp_id < 16) {
5226
5227 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5228 hldev->header.regh0,
5229 &hldev->common_reg->tim_int_mask0);
5230
5231 val64 &= ~(vBIT(0xf, (vp->vpath->vp_id * 4), 4));
5232
5233 vxge_os_pio_mem_write64(hldev->header.pdev,
5234 hldev->header.regh0,
5235 val64,
5236 &hldev->common_reg->tim_int_mask0);
5237
5238 } else {
5239
5240 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
5241 hldev->header.regh0,
5242 0,
5243 &hldev->common_reg->tim_int_mask1);
5244
5245 }
5246
5247 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
5248 __FILE__, __func__, __LINE__);
5249 }
5250
5251 /*
5252 * __hal_vpath_link_state_test - Test for the link state.
5253 * @vpath: Virtual Path.
5254 *
5255 * Test link state.
5256 * Returns: link state.
5257 */
5258 vxge_hal_device_link_state_e
__hal_vpath_link_state_test(__hal_virtualpath_t * vpath)5259 __hal_vpath_link_state_test(__hal_virtualpath_t *vpath)
5260 {
5261 __hal_device_t *hldev;
5262
5263 vxge_assert(vpath != NULL);
5264 hldev = vpath->hldev;
5265
5266 vxge_hal_trace_log_vpath("==> %s:%s:%d",
5267 __FILE__, __func__, __LINE__);
5268
5269 vxge_hal_trace_log_vpath("vpath = 0x"VXGE_OS_STXFMT,
5270 (ptr_t) vpath);
5271
5272 vxge_os_pio_mem_write64(hldev->header.pdev,
5273 hldev->header.regh0,
5274 VXGE_HAL_ASIC_NTWK_VP_CTRL_REQ_TEST_NTWK,
5275 &vpath->vp_reg->asic_ntwk_vp_ctrl);
5276
5277 (void) vxge_hal_device_register_poll(hldev->header.pdev,
5278 hldev->header.regh0,
5279 &vpath->vp_reg->asic_ntwk_vp_ctrl,
5280 0,
5281 VXGE_HAL_ASIC_NTWK_VP_CTRL_REQ_TEST_NTWK,
5282 hldev->header.config.device_poll_millis);
5283
5284 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
5285 __FILE__, __func__, __LINE__);
5286
5287 return (hldev->header.link_state);
5288 }
5289
5290 /*
5291 * __hal_vpath_link_state_poll - Poll for the link state.
5292 * @vpath: Virtual Path.
5293 *
5294 * Get link state.
5295 * Returns: link state.
5296 */
5297 vxge_hal_device_link_state_e
__hal_vpath_link_state_poll(__hal_virtualpath_t * vpath)5298 __hal_vpath_link_state_poll(__hal_virtualpath_t *vpath)
5299 {
5300 u64 val64;
5301 __hal_device_t *hldev;
5302
5303 vxge_assert(vpath != NULL);
5304
5305 hldev = vpath->hldev;
5306
5307 vxge_hal_trace_log_vpath("==> %s:%s:%d",
5308 __FILE__, __func__, __LINE__);
5309
5310 vxge_hal_trace_log_vpath("vpath = 0x"VXGE_OS_STXFMT,
5311 (ptr_t) vpath);
5312
5313 if (vpath == NULL) {
5314 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
5315 __FILE__, __func__, __LINE__, VXGE_HAL_LINK_NONE);
5316 return (VXGE_HAL_LINK_NONE);
5317 }
5318
5319 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5320 hldev->header.regh0,
5321 &vpath->vpmgmt_reg->xgmac_gen_status_vpmgmt_clone);
5322
5323 if (val64 & VXGE_HAL_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_OK) {
5324
5325 (void) __hal_device_handle_link_up_ind(vpath->hldev);
5326
5327 if (val64 &
5328 VXGE_HAL_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_DATA_RATE) {
5329 VXGE_HAL_DEVICE_DATA_RATE_SET(vpath->hldev,
5330 VXGE_HAL_DATA_RATE_10G);
5331
5332 } else {
5333 VXGE_HAL_DEVICE_DATA_RATE_SET(vpath->hldev,
5334 VXGE_HAL_DATA_RATE_1G);
5335
5336 }
5337 } else {
5338 (void) __hal_device_handle_link_down_ind(vpath->hldev);
5339 }
5340
5341 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
5342 __FILE__, __func__, __LINE__);
5343
5344 return (vpath->hldev->header.link_state);
5345 }
5346
5347 /*
5348 * __hal_vpath_data_rate_poll - Poll for the data rate.
5349 * @vpath: Virtual Path.
5350 *
5351 * Get data rate.
5352 * Returns: data rate.
5353 */
5354 vxge_hal_device_data_rate_e
__hal_vpath_data_rate_poll(__hal_virtualpath_t * vpath)5355 __hal_vpath_data_rate_poll(
5356 __hal_virtualpath_t *vpath)
5357 {
5358 u64 val64;
5359 __hal_device_t *hldev;
5360
5361 vxge_assert(vpath != NULL);
5362
5363 hldev = vpath->hldev;
5364
5365 vxge_hal_trace_log_vpath("==> %s:%s:%d",
5366 __FILE__, __func__, __LINE__);
5367
5368 vxge_hal_trace_log_vpath("vpath = 0x"VXGE_OS_STXFMT,
5369 (ptr_t) vpath);
5370
5371 if (vpath == NULL) {
5372 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
5373 __FILE__, __func__, __LINE__, VXGE_HAL_DATA_RATE_UNKNOWN);
5374 return (VXGE_HAL_DATA_RATE_UNKNOWN);
5375 }
5376
5377 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5378 hldev->header.regh0,
5379 &vpath->vpmgmt_reg->xgmac_gen_status_vpmgmt_clone);
5380
5381 if (val64 &
5382 VXGE_HAL_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_DATA_RATE) {
5383
5384 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
5385 __FILE__, __func__, __LINE__);
5386
5387 return (VXGE_HAL_DATA_RATE_10G);
5388
5389 } else {
5390
5391 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
5392 __FILE__, __func__, __LINE__);
5393
5394 return (VXGE_HAL_DATA_RATE_1G);
5395
5396 }
5397 }
5398
5399 /*
5400 * __hal_vpath_alarm_process - Process Alarms.
5401 * @vpath: Virtual Path.
5402 * @skip_alarms: Do not clear the alarms
5403 *
5404 * Process vpath alarms.
5405 *
5406 */
5407 vxge_hal_status_e
__hal_vpath_alarm_process(__hal_virtualpath_t * vpath,u32 skip_alarms)5408 __hal_vpath_alarm_process(__hal_virtualpath_t *vpath, u32 skip_alarms)
5409 {
5410 u64 val64;
5411 u64 alarm_status;
5412 u64 pic_status = 0;
5413 u64 pif_status;
5414 u64 wrdma_status;
5415 u64 xgmac_status;
5416 __hal_device_t *hldev;
5417 vxge_hal_status_e status;
5418
5419 vxge_assert(vpath != NULL);
5420
5421 hldev = vpath->hldev;
5422
5423 vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
5424 __FILE__, __func__, __LINE__);
5425
5426 vxge_hal_trace_log_vpath_irq("vpath = 0x"VXGE_OS_STXFMT,
5427 (ptr_t) vpath);
5428
5429 alarm_status = vxge_os_pio_mem_read64(hldev->header.pdev,
5430 hldev->header.regh0,
5431 &vpath->vp_reg->vpath_general_int_status);
5432
5433 vxge_hal_info_log_vpath_irq(
5434 "alarm_status = 0x"VXGE_OS_STXFMT, (ptr_t) alarm_status);
5435
5436 if (vxge_os_unlikely(!alarm_status)) {
5437 status = VXGE_HAL_ERR_WRONG_IRQ;
5438 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = %d",
5439 __FILE__, __func__, __LINE__, status);
5440 return (status);
5441 }
5442
5443 if (alarm_status & VXGE_HAL_VPATH_GENERAL_INT_STATUS_PIC_INT) {
5444
5445 pic_status = vxge_os_pio_mem_read64(hldev->header.pdev,
5446 hldev->header.regh0,
5447 &vpath->vp_reg->vpath_ppif_int_status);
5448
5449 vxge_hal_info_log_vpath_irq(
5450 "pic_status = 0x"VXGE_OS_STXFMT, (ptr_t) pic_status);
5451
5452 if (pic_status &
5453 VXGE_HAL_VPATH_PPIF_INT_STATUS_GENERAL_ERRORS_INT) {
5454 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5455 hldev->header.regh0,
5456 &vpath->vp_reg->general_errors_reg);
5457
5458 vxge_hal_info_log_vpath_irq(
5459 "general_errors_reg = 0x"VXGE_OS_STXFMT,
5460 (ptr_t) val64);
5461 if (val64 & VXGE_HAL_GENERAL_ERRORS_REG_INI_SERR_DET) {
5462
5463 vpath->sw_stats->error_stats.ini_serr_det++;
5464 vxge_hal_info_log_vpath_irq("%s:"
5465 "VXGE_HAL_GENERAL_ERRORS_REG_INI_SERR_DET",
5466 __func__);
5467
5468 __hal_device_handle_error(hldev, vpath->vp_id,
5469 VXGE_HAL_EVENT_SERR);
5470
5471 if (!skip_alarms) {
5472 vxge_os_pio_mem_write64(hldev->header.pdev,
5473 hldev->header.regh0,
5474 VXGE_HAL_GENERAL_ERRORS_REG_INI_SERR_DET,
5475 &vpath->vp_reg->general_errors_reg);
5476 }
5477
5478 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d \
5479 Result = 0", __FILE__, __func__, __LINE__);
5480
5481 return (VXGE_HAL_ERR_EVENT_SERR);
5482 }
5483 }
5484
5485 if (pic_status & VXGE_HAL_VPATH_PPIF_INT_STATUS_PCI_CONFIG_ERRORS_INT) {
5486 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5487 hldev->header.regh0,
5488 &vpath->vp_reg->pci_config_errors_reg);
5489
5490 vxge_hal_info_log_vpath_irq(
5491 "pci_config_errors_reg = 0x"VXGE_OS_STXFMT,
5492 (ptr_t) val64);
5493
5494 if (val64 &
5495 VXGE_HAL_PCI_CONFIG_ERRORS_REG_STATUS_ERR) {
5496 vpath->sw_stats->error_stats.pci_config_status_err++;
5497 vxge_hal_info_log_vpath_irq("%s: \
5498 VXGE_HAL_PCI_CONFIG_ERRORS_REG_STATUS_ERR",
5499 __func__);
5500 }
5501
5502 if (val64 & VXGE_HAL_PCI_CONFIG_ERRORS_REG_UNCOR_ERR) {
5503 vpath->sw_stats->error_stats.pci_config_uncor_err++;
5504 vxge_hal_info_log_vpath_irq("%s: \
5505 VXGE_HAL_PCI_CONFIG_ERRORS_REG_UNCOR_ERR",
5506 __func__);
5507 }
5508
5509 if (val64 & VXGE_HAL_PCI_CONFIG_ERRORS_REG_COR_ERR) {
5510 vpath->sw_stats->error_stats.pci_config_cor_err++;
5511 vxge_hal_info_log_vpath_irq("%s: \
5512 VXGE_HAL_PCI_CONFIG_ERRORS_REG_COR_ERR",
5513 __func__);
5514 }
5515
5516 if (!skip_alarms)
5517 vxge_os_pio_mem_write64(hldev->header.pdev,
5518 hldev->header.regh0, VXGE_HAL_INTR_MASK_ALL,
5519 &vpath->vp_reg->pci_config_errors_reg);
5520 }
5521
5522 if (pic_status &
5523 VXGE_HAL_VPATH_PPIF_INT_STATUS_MRPCIM_TO_VPATH_ALARM_INT) {
5524
5525 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5526 hldev->header.regh0,
5527 &vpath->vp_reg->mrpcim_to_vpath_alarm_reg);
5528
5529 vxge_hal_info_log_vpath_irq(
5530 "mrpcim_to_vpath_alarm_reg = 0x"VXGE_OS_STXFMT,
5531 (ptr_t) val64);
5532
5533 if (val64 &
5534 VXGE_HAL_MRPCIM_TO_VPATH_ALARM_REG_ALARM) {
5535
5536 vpath->sw_stats->error_stats.mrpcim_to_vpath_alarms++;
5537 hldev->stats.sw_dev_err_stats.mrpcim_alarms++;
5538 vxge_hal_info_log_vpath_irq(
5539 "%s:VXGE_HAL_MRPCIM_TO_VPATH_ALARM_REG_ALARM",
5540 __func__);
5541
5542 __hal_device_handle_error(hldev, vpath->vp_id,
5543 VXGE_HAL_EVENT_MRPCIM_CRITICAL);
5544
5545 if (!skip_alarms)
5546 vxge_os_pio_mem_write64(hldev->header.pdev,
5547 hldev->header.regh0,
5548 VXGE_HAL_MRPCIM_TO_VPATH_ALARM_REG_ALARM,
5549 &vpath->vp_reg->mrpcim_to_vpath_alarm_reg);
5550 return (VXGE_HAL_ERR_EVENT_MRPCIM_CRITICAL);
5551 }
5552
5553 if (!skip_alarms)
5554 vxge_os_pio_mem_write64(hldev->header.pdev,
5555 hldev->header.regh0,
5556 VXGE_HAL_INTR_MASK_ALL,
5557 &vpath->vp_reg->mrpcim_to_vpath_alarm_reg);
5558 }
5559
5560 if (pic_status &
5561 VXGE_HAL_VPATH_PPIF_INT_STATUS_SRPCIM_TO_VPATH_ALARM_INT) {
5562
5563 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5564 hldev->header.regh0,
5565 &vpath->vp_reg->srpcim_to_vpath_alarm_reg);
5566
5567 vxge_hal_info_log_vpath_irq(
5568 "srpcim_to_vpath_alarm_reg = 0x"VXGE_OS_STXFMT,
5569 (ptr_t) val64);
5570
5571 vpath->sw_stats->error_stats.srpcim_to_vpath_alarms++;
5572 hldev->stats.sw_dev_err_stats.srpcim_alarms++;
5573
5574 vxge_hal_info_log_vpath_irq(
5575 "%s:VXGE_HAL_SRPCIM_TO_VPATH_ALARM_REG_GET_ALARM",
5576 __func__);
5577
5578 status = vxge_hal_srpcim_alarm_process(
5579 (vxge_hal_device_h) hldev, skip_alarms);
5580
5581 if (!skip_alarms)
5582 vxge_os_pio_mem_write64(hldev->header.pdev,
5583 hldev->header.regh0,
5584 VXGE_HAL_INTR_MASK_ALL,
5585 &vpath->vp_reg->srpcim_to_vpath_alarm_reg);
5586
5587 if (status == VXGE_HAL_ERR_EVENT_SRPCIM_CRITICAL)
5588 return (status);
5589 }
5590 }
5591
5592 if (alarm_status & VXGE_HAL_VPATH_GENERAL_INT_STATUS_WRDMA_INT) {
5593
5594 wrdma_status = vxge_os_pio_mem_read64(hldev->header.pdev,
5595 hldev->header.regh0,
5596 &vpath->vp_reg->wrdma_alarm_status);
5597
5598 vxge_hal_info_log_vpath_irq(
5599 "wrdma_alarm_status = 0x"VXGE_OS_STXFMT,
5600 (ptr_t) wrdma_status);
5601
5602 if (wrdma_status &
5603 VXGE_HAL_WRDMA_ALARM_STATUS_PRC_ALARM_PRC_INT) {
5604 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5605 hldev->header.regh0,
5606 &vpath->vp_reg->prc_alarm_reg);
5607
5608 vxge_hal_info_log_vpath_irq(
5609 "prc_alarm_reg = 0x"VXGE_OS_STXFMT, (ptr_t) val64);
5610
5611 if (val64 & VXGE_HAL_PRC_ALARM_REG_PRC_RING_BUMP) {
5612 vpath->sw_stats->error_stats.prc_ring_bumps++;
5613 vxge_hal_info_log_vpath_irq(
5614 "%s:VXGE_HAL_PRC_ALARM_REG_PRC_RING_BUMP",
5615 __func__);
5616 }
5617
5618 if (val64 & VXGE_HAL_PRC_ALARM_REG_PRC_RXDCM_SC_ERR) {
5619 vpath->sw_stats->error_stats.prc_rxdcm_sc_err++;
5620 vxge_hal_info_log_vpath_irq("%s:" \
5621 "VXGE_HAL_PRC_ALARM_REG_PRC_RXDCM_SC_ERR",
5622 __func__);
5623 __hal_device_handle_error(hldev,
5624 vpath->vp_id,
5625 VXGE_HAL_EVENT_CRITICAL);
5626
5627 if (!skip_alarms) {
5628 vxge_os_pio_mem_write64(hldev->header.pdev,
5629 hldev->header.regh0,
5630 VXGE_HAL_PRC_ALARM_REG_PRC_RXDCM_SC_ERR,
5631 &vpath->vp_reg->prc_alarm_reg);
5632 }
5633
5634 vxge_hal_trace_log_vpath_irq(
5635 "<== %s:%s:%d Result = %d",
5636 __FILE__, __func__, __LINE__,
5637 VXGE_HAL_ERR_EVENT_CRITICAL);
5638
5639 return (VXGE_HAL_ERR_EVENT_CRITICAL);
5640 }
5641
5642 if (val64 & VXGE_HAL_PRC_ALARM_REG_PRC_RXDCM_SC_ABORT) {
5643 vpath->sw_stats->error_stats.prc_rxdcm_sc_abort++;
5644 vxge_hal_info_log_vpath_irq("%s: \
5645 VXGE_HAL_PRC_ALARM_REG_PRC_RXDCM_SC_ABORT",
5646 __func__);
5647
5648 __hal_device_handle_error(hldev, vpath->vp_id,
5649 VXGE_HAL_EVENT_CRITICAL);
5650
5651 if (!skip_alarms)
5652 vxge_os_pio_mem_write64(hldev->header.pdev,
5653 hldev->header.regh0,
5654 VXGE_HAL_PRC_ALARM_REG_PRC_RXDCM_SC_ABORT,
5655 &vpath->vp_reg->prc_alarm_reg);
5656
5657 vxge_hal_trace_log_vpath_irq(
5658 "<== %s:%s:%d Result = %d",
5659 __FILE__, __func__, __LINE__,
5660 VXGE_HAL_ERR_EVENT_CRITICAL);
5661
5662 return (VXGE_HAL_ERR_EVENT_CRITICAL);
5663 }
5664
5665 if (val64 & VXGE_HAL_PRC_ALARM_REG_PRC_QUANTA_SIZE_ERR) {
5666 vpath->sw_stats->error_stats.prc_quanta_size_err++;
5667 vxge_hal_info_log_vpath_irq("%s: \
5668 VXGE_HAL_PRC_ALARM_REG_PRC_QUANTA_SIZE_ERR",
5669 __func__);
5670 }
5671
5672 if (!skip_alarms)
5673 vxge_os_pio_mem_write64(hldev->header.pdev,
5674 hldev->header.regh0, VXGE_HAL_INTR_MASK_ALL,
5675 &vpath->vp_reg->prc_alarm_reg);
5676 }
5677 }
5678
5679 if (alarm_status & VXGE_HAL_VPATH_GENERAL_INT_STATUS_PIC_INT) {
5680
5681 if (pic_status &
5682 VXGE_HAL_VPATH_PPIF_INT_STATUS_GENERAL_ERRORS_INT) {
5683
5684 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5685 hldev->header.regh0,
5686 &vpath->vp_reg->general_errors_reg);
5687
5688 vxge_hal_info_log_vpath_irq(
5689 "general_errors_reg = 0x"VXGE_OS_STXFMT,
5690 (ptr_t) val64);
5691
5692 if (val64 &
5693 VXGE_HAL_GENERAL_ERRORS_REG_DBLGEN_FIFO0_OVRFLOW) {
5694
5695 vpath->sw_stats->error_stats.dblgen_fifo0_overflow++;
5696 vxge_hal_info_log_vpath_irq(
5697 "%s:"
5698 "VXGE_HAL_GENERAL_ERRORS_REG_DBLGEN_FIFO0_OVRFLOW",
5699 __func__);
5700
5701 __hal_device_handle_error(hldev, vpath->vp_id,
5702 VXGE_HAL_EVENT_KDFCCTL);
5703
5704 if (!skip_alarms) {
5705 vxge_os_pio_mem_write64(hldev->header.pdev,
5706 hldev->header.regh0,
5707 VXGE_HAL_GENERAL_ERRORS_REG_DBLGEN_FIFO0_OVRFLOW,
5708 &vpath->vp_reg->general_errors_reg);
5709 }
5710
5711 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d \
5712 Result = %d",
5713 __FILE__, __func__, __LINE__,
5714 VXGE_HAL_ERR_EVENT_KDFCCTL);
5715 return (VXGE_HAL_ERR_EVENT_KDFCCTL);
5716 }
5717
5718 if (val64 & VXGE_HAL_GENERAL_ERRORS_REG_DBLGEN_FIFO1_OVRFLOW) {
5719 vpath->sw_stats->error_stats.dblgen_fifo1_overflow++;
5720 vxge_hal_info_log_vpath_irq("%s:" \
5721 "VXGE_HAL_GENERAL_ERRORS_REG_DBLGEN_FIFO1_OVRFLOW",
5722 __func__);
5723
5724 }
5725
5726 if (val64 &
5727 VXGE_HAL_GENERAL_ERRORS_REG_DBLGEN_FIFO2_OVRFLOW) {
5728 vpath->sw_stats->error_stats.dblgen_fifo2_overflow++;
5729 vxge_hal_info_log_vpath_irq("%s:" \
5730 "VXGE_HAL_GENERAL_ERRORS_REG_DBLGEN_FIFO2_OVRFLOW",
5731 __func__);
5732 }
5733
5734 if (val64 &
5735 VXGE_HAL_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR) {
5736 vpath->sw_stats->error_stats.statsb_pif_chain_error++;
5737 vxge_hal_info_log_vpath_irq("%s:" \
5738 "VXGE_HAL_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR",
5739 __func__);
5740 }
5741
5742 if (val64 &
5743 VXGE_HAL_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT) {
5744 vpath->sw_stats->error_stats.statsb_drop_timeout++;
5745 vxge_hal_info_log_vpath_irq("%s:" \
5746 "VXGE_HAL_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT",
5747 __func__);
5748 }
5749
5750 if (val64 & VXGE_HAL_GENERAL_ERRORS_REG_TGT_ILLEGAL_ACCESS) {
5751 vpath->sw_stats->error_stats.target_illegal_access++;
5752 vxge_hal_info_log_vpath_irq("%s:" \
5753 "VXGE_HAL_GENERAL_ERRORS_REG_TGT_ILLEGAL_ACCESS",
5754 __func__);
5755 }
5756
5757 if (!skip_alarms)
5758 vxge_os_pio_mem_write64(hldev->header.pdev,
5759 hldev->header.regh0,
5760 VXGE_HAL_INTR_MASK_ALL,
5761 &vpath->vp_reg->general_errors_reg);
5762 }
5763
5764 if (pic_status &
5765 VXGE_HAL_VPATH_PPIF_INT_STATUS_KDFCCTL_ERRORS_INT) {
5766 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5767 hldev->header.regh0,
5768 &vpath->vp_reg->kdfcctl_errors_reg);
5769
5770 vxge_hal_info_log_vpath_irq(
5771 "kdfcctl_errors_reg = 0x"VXGE_OS_STXFMT,
5772 (ptr_t) val64);
5773
5774 if (val64 &
5775 VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_OVRWR) {
5776 vpath->sw_stats->error_stats.kdfcctl_fifo0_overwrite++;
5777 vxge_hal_info_log_vpath_irq("%s:" \
5778 "VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_OVRWR",
5779 __func__);
5780 __hal_device_handle_error(hldev, vpath->vp_id,
5781 VXGE_HAL_EVENT_KDFCCTL);
5782
5783 if (!skip_alarms) {
5784 vxge_os_pio_mem_write64(hldev->header.pdev,
5785 hldev->header.regh0,
5786 VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_OVRWR,
5787 &vpath->vp_reg->kdfcctl_errors_reg);
5788 }
5789
5790 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d \
5791 Result = %d", __FILE__, __func__, __LINE__,
5792 VXGE_HAL_ERR_EVENT_KDFCCTL);
5793 return (VXGE_HAL_ERR_EVENT_KDFCCTL);
5794 }
5795
5796 if (val64 &
5797 VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_OVRWR) {
5798 vpath->sw_stats->error_stats.kdfcctl_fifo1_overwrite++;
5799 vxge_hal_info_log_vpath_irq("%s:" \
5800 "VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_OVRWR",
5801 __func__);
5802
5803 }
5804
5805 if (val64 &
5806 VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_OVRWR) {
5807 vpath->sw_stats->error_stats.kdfcctl_fifo2_overwrite++;
5808 vxge_hal_info_log_vpath_irq("%s:" \
5809 "VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_OVRWR",
5810 __func__);
5811 }
5812
5813 if (val64 &
5814 VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_POISON) {
5815 vpath->sw_stats->error_stats.kdfcctl_fifo0_poison++;
5816 vxge_hal_info_log_vpath_irq("%s:" \
5817 "VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_POISON",
5818 __func__);
5819 __hal_device_handle_error(hldev, vpath->vp_id,
5820 VXGE_HAL_EVENT_KDFCCTL);
5821
5822 if (!skip_alarms) {
5823 vxge_os_pio_mem_write64(hldev->header.pdev,
5824 hldev->header.regh0,
5825 VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_POISON,
5826 &vpath->vp_reg->kdfcctl_errors_reg);
5827 }
5828
5829 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d \
5830 Result = %d", __FILE__, __func__, __LINE__,
5831 VXGE_HAL_ERR_EVENT_KDFCCTL);
5832 return (VXGE_HAL_ERR_EVENT_KDFCCTL);
5833 }
5834
5835 if (val64 &
5836 VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_POISON) {
5837 vpath->sw_stats->error_stats.kdfcctl_fifo1_poison++;
5838 vxge_hal_info_log_vpath_irq("%s:" \
5839 "VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_POISON",
5840 __func__);
5841
5842 }
5843
5844 if (val64 &
5845 VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_POISON) {
5846 vpath->sw_stats->error_stats.kdfcctl_fifo2_poison++;
5847 vxge_hal_info_log_vpath_irq("%s:" \
5848 "VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_POISON",
5849 __func__);
5850 }
5851
5852 if (val64 &
5853 VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_DMA_ERR) {
5854 vpath->sw_stats->error_stats.kdfcctl_fifo0_dma_error++;
5855 vxge_hal_info_log_vpath_irq("%s:" \
5856 "VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_DMA_ERR",
5857 __func__);
5858
5859 __hal_device_handle_error(hldev, vpath->vp_id,
5860 VXGE_HAL_EVENT_KDFCCTL);
5861
5862 if (!skip_alarms) {
5863 vxge_os_pio_mem_write64(hldev->header.pdev,
5864 hldev->header.regh0,
5865 VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_DMA_ERR,
5866 &vpath->vp_reg->kdfcctl_errors_reg);
5867 }
5868
5869 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d \
5870 Result = %d", __FILE__, __func__, __LINE__,
5871 VXGE_HAL_ERR_EVENT_KDFCCTL);
5872 return (VXGE_HAL_ERR_EVENT_KDFCCTL);
5873 }
5874
5875 if (val64 &
5876 VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_DMA_ERR) {
5877 vpath->sw_stats->error_stats.kdfcctl_fifo1_dma_error++;
5878 vxge_hal_info_log_vpath_irq("%s:"
5879 "VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_DMA_ERR",
5880 __func__);
5881 }
5882
5883 if (val64 &
5884 VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_DMA_ERR) {
5885 vpath->sw_stats->error_stats.kdfcctl_fifo2_dma_error++;
5886 vxge_hal_info_log_vpath_irq("%s:" \
5887 "VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_DMA_ERR",
5888 __func__);
5889 }
5890
5891 if (!skip_alarms) {
5892 vxge_os_pio_mem_write64(hldev->header.pdev,
5893 hldev->header.regh0,
5894 VXGE_HAL_INTR_MASK_ALL,
5895 &vpath->vp_reg->kdfcctl_errors_reg);
5896 }
5897 }
5898 }
5899
5900 if (alarm_status & VXGE_HAL_VPATH_GENERAL_INT_STATUS_PCI_INT) {
5901
5902 pif_status = vxge_os_pio_mem_read64(hldev->header.pdev,
5903 hldev->header.regh0,
5904 &vpath->vp_reg->vpath_pcipif_int_status);
5905
5906 vxge_hal_info_log_vpath_irq(
5907 "vpath_pcipif_int_status = 0x"VXGE_OS_STXFMT,
5908 (ptr_t) pif_status);
5909
5910 if (pif_status &
5911 VXGE_HAL_VPATH_PCIPIF_INT_STATUS_SRPCIM_MSG_TO_VPATH_INT) {
5912
5913 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5914 hldev->header.regh0,
5915 &vpath->vp_reg->srpcim_msg_to_vpath_reg);
5916
5917 vxge_hal_info_log_vpath_irq(
5918 "srpcim_msg_to_vpath_reg = 0x"VXGE_OS_STXFMT,
5919 (ptr_t) val64);
5920
5921 if (val64 &
5922 VXGE_HAL_SRPCIM_MSG_TO_VPATH_REG_INT) {
5923
5924 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5925 hldev->header.regh0,
5926 &vpath->vpmgmt_reg->srpcim_to_vpath_wmsg);
5927
5928 __hal_ifmsg_wmsg_process(vpath, val64);
5929
5930 vpath->sw_stats->error_stats.srpcim_msg_to_vpath++;
5931
5932 vxge_os_pio_mem_write64(hldev->header.pdev,
5933 hldev->header.regh0,
5934 0,
5935 &vpath->vpmgmt_reg->srpcim_to_vpath_wmsg);
5936
5937 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
5938 hldev->header.regh0,
5939 (u32) VXGE_HAL_INTR_MASK_ALL,
5940 &vpath->vp_reg->srpcim_msg_to_vpath_mask);
5941
5942 vxge_hal_info_log_vpath_irq("%s:"
5943 "VXGE_HAL_SRPCIM_MSG_TO_VPATH_REG_INT",
5944 __func__);
5945 }
5946
5947 vxge_os_pio_mem_write64(hldev->header.pdev,
5948 hldev->header.regh0,
5949 VXGE_HAL_INTR_MASK_ALL,
5950 &vpath->vp_reg->srpcim_msg_to_vpath_reg);
5951 }
5952 }
5953
5954 if (alarm_status & VXGE_HAL_VPATH_GENERAL_INT_STATUS_XMAC_INT) {
5955
5956 xgmac_status = vxge_os_pio_mem_read64(hldev->header.pdev,
5957 hldev->header.regh0,
5958 &vpath->vp_reg->xgmac_vp_int_status);
5959
5960 vxge_hal_info_log_vpath_irq("xgmac_status = 0x"VXGE_OS_STXFMT,
5961 (ptr_t) xgmac_status);
5962
5963 if (xgmac_status &
5964 VXGE_HAL_XGMAC_VP_INT_STATUS_ASIC_NTWK_VP_ERR_INT) {
5965
5966 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5967 hldev->header.regh0,
5968 &vpath->vp_reg->asic_ntwk_vp_err_reg);
5969
5970 vxge_hal_info_log_vpath_irq(
5971 "asic_ntwk_vp_err_reg = 0x"VXGE_OS_STXFMT,
5972 (ptr_t) val64);
5973
5974 if (((val64 & VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_FAULT) &&
5975 (!(val64 & VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_OK))) ||
5976 ((val64 & VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_FAULT_OCCURRED) &&
5977 (!(val64 & VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_OK_OCCURRED)))) {
5978 vpath->sw_stats->error_stats.network_sustained_fault++;
5979 vxge_hal_info_log_vpath_irq("%s:" \
5980 "VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_FAULT",
5981 __func__);
5982 vxge_os_pio_mem_write64(vpath->hldev->header.pdev,
5983 hldev->header.regh0,
5984 VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_FAULT,
5985 &vpath->vp_reg->asic_ntwk_vp_err_mask);
5986
5987 (void) __hal_device_handle_link_down_ind(hldev);
5988 }
5989
5990 if (((val64 & VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_OK) &&
5991 (!(val64 & VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_FAULT))) ||
5992 ((val64 & VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_OK_OCCURRED) &&
5993 (!(val64 & VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_FAULT_OCCURRED)))) {
5994 vpath->sw_stats->error_stats.network_sustained_ok++;
5995 vxge_hal_info_log_vpath_irq(
5996 "%s:VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_OK",
5997 __func__);
5998
5999 vxge_os_pio_mem_write64(hldev->header.pdev,
6000 hldev->header.regh0,
6001 VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_OK,
6002 &vpath->vp_reg->asic_ntwk_vp_err_mask);
6003
6004 (void) __hal_device_handle_link_up_ind(hldev);
6005 }
6006
6007 vxge_os_pio_mem_write64(hldev->header.pdev,
6008 hldev->header.regh0,
6009 VXGE_HAL_INTR_MASK_ALL,
6010 &vpath->vp_reg->asic_ntwk_vp_err_reg);
6011 return (VXGE_HAL_INF_LINK_UP_DOWN);
6012 }
6013 }
6014
6015 if (alarm_status & ~(
6016 VXGE_HAL_VPATH_GENERAL_INT_STATUS_PIC_INT |
6017 VXGE_HAL_VPATH_GENERAL_INT_STATUS_PCI_INT |
6018 VXGE_HAL_VPATH_GENERAL_INT_STATUS_WRDMA_INT |
6019 VXGE_HAL_VPATH_GENERAL_INT_STATUS_XMAC_INT)) {
6020
6021 vpath->sw_stats->error_stats.unknown_alarms++;
6022 vxge_hal_info_log_vpath_irq(
6023 "%s:%s:%d Unknown Alarm", __FILE__, __func__, __LINE__);
6024
6025 __hal_device_handle_error(hldev, vpath->vp_id,
6026 VXGE_HAL_EVENT_UNKNOWN);
6027 status = VXGE_HAL_ERR_EVENT_UNKNOWN;
6028
6029 } else {
6030 hldev->stats.sw_dev_err_stats.vpath_alarms++;
6031 status = VXGE_HAL_OK;
6032 }
6033
6034 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
6035 __FILE__, __func__, __LINE__);
6036
6037 return (status);
6038 }
6039
6040 /*
6041 * vxge_hal_vpath_begin_irq - Begin IRQ processing.
6042 * @vpath_handle: Virtual Path handle.
6043 * @skip_alarms: Do not clear the alarms
6044 * @reason: "Reason" for the interrupt, the value of vpath's
6045 * general_int_status register.
6046 *
6047 * The function performs two actions, It first checks whether (shared IRQ) the
6048 * interrupt was raised by the device. Next, it masks the device interrupts.
6049 *
6050 * Note:
6051 * vxge_hal_vpath_begin_irq() does not flush MMIO writes through the
6052 * bridge. Therefore, two back-to-back interrupts are potentially possible.
6053 * It is the responsibility of the ULD to make sure that only one
6054 * vxge_hal_vpath_continue_irq() runs at a time.
6055 *
6056 * Returns: 0, if the interrupt is not "ours" (note that in this case the
6057 * vpath remain enabled).
6058 * Otherwise, vxge_hal_vpath_begin_irq() returns 64bit general adapter
6059 * status.
6060 * See also: vxge_hal_vpath_handle_irq()
6061 */
6062 vxge_hal_status_e
vxge_hal_vpath_begin_irq(vxge_hal_vpath_h vpath_handle,u32 skip_alarms,u64 * reason)6063 vxge_hal_vpath_begin_irq(vxge_hal_vpath_h vpath_handle,
6064 u32 skip_alarms, u64 *reason)
6065 {
6066 u64 val64;
6067 u64 adapter_status;
6068 __hal_device_t *hldev;
6069 __hal_virtualpath_t *vpath;
6070 vxge_hal_status_e ret_val = VXGE_HAL_OK;
6071
6072 vxge_assert((vpath_handle != NULL) && (reason != NULL));
6073
6074 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
6075
6076 hldev = vpath->hldev;
6077
6078 vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
6079 __FILE__, __func__, __LINE__);
6080
6081 vxge_hal_trace_log_vpath_irq(
6082 "vpath_handle = 0x"VXGE_OS_STXFMT", skip_alarms = %d, "
6083 "reason = 0x"VXGE_OS_STXFMT, (ptr_t) vpath_handle,
6084 skip_alarms, (ptr_t) reason);
6085
6086 if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
6087 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result: %d",
6088 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
6089 return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
6090 }
6091
6092 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6093 hldev->header.regh0,
6094 &hldev->common_reg->titan_general_int_status);
6095
6096 if (vxge_os_unlikely(!val64)) {
6097 /* not Titan interrupt */
6098 *reason = 0;
6099 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = %d",
6100 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_WRONG_IRQ);
6101 return (VXGE_HAL_ERR_WRONG_IRQ);
6102 }
6103
6104 if (vxge_os_unlikely(val64 == VXGE_HAL_ALL_FOXES)) {
6105
6106 adapter_status = vxge_os_pio_mem_read64(hldev->header.pdev,
6107 hldev->header.regh0,
6108 &hldev->common_reg->adapter_status);
6109
6110 if (adapter_status == VXGE_HAL_ALL_FOXES) {
6111 __hal_device_handle_error(hldev,
6112 vpath->vp_id,
6113 VXGE_HAL_EVENT_SLOT_FREEZE);
6114
6115 *reason = 0;
6116 ret_val = VXGE_HAL_ERR_SLOT_FREEZE;
6117 goto exit;
6118 }
6119 }
6120
6121 if (val64 &
6122 VXGE_HAL_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT(
6123 1 << (16 - vpath->vp_id))) {
6124
6125 if (vpath->vp_id < 16) {
6126
6127 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6128 hldev->header.regh0,
6129 &hldev->common_reg->tim_int_mask0);
6130
6131 *reason = bVAL4(val64, (vpath->vp_id * 4));
6132 } else {
6133
6134 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6135 hldev->header.regh0,
6136 &hldev->common_reg->tim_int_mask1);
6137
6138 *reason = bVAL4(val64, 0);
6139 }
6140
6141 return (VXGE_HAL_OK);
6142 }
6143
6144 *reason = VXGE_HAL_INTR_ALARM;
6145
6146 if (vxge_os_unlikely(val64 &
6147 VXGE_HAL_TITAN_GENERAL_INT_STATUS_MRPCIM_ALARM_INT)) {
6148 vxge_hal_info_log_vpath_irq(
6149 "%s:VXGE_HAL_TITAN_GENERAL_INT_STATUS_MRPCIM_ALARM_INT",
6150 __func__);
6151 ret_val = VXGE_HAL_ERR_CRITICAL;
6152 goto exit;
6153 }
6154
6155 if (vxge_os_unlikely(val64 &
6156 VXGE_HAL_TITAN_GENERAL_INT_STATUS_SRPCIM_ALARM_INT)) {
6157 vxge_hal_info_log_vpath_irq(
6158 "%s:VXGE_HAL_TITAN_GENERAL_INT_STATUS_SRPCIM_ALARM_INT",
6159 __func__);
6160 ret_val = VXGE_HAL_ERR_CRITICAL;
6161 goto exit;
6162 }
6163
6164 if (vxge_os_unlikely(val64 &
6165 VXGE_HAL_TITAN_GENERAL_INT_STATUS_VPATH_ALARM_INT)) {
6166 vxge_hal_info_log_vpath_irq(
6167 "%s:VXGE_HAL_TITAN_GENERAL_INT_STATUS_VPATH_ALARM_INT",
6168 __func__);
6169 ret_val = __hal_vpath_alarm_process(vpath, skip_alarms);
6170 }
6171
6172 exit:
6173 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
6174 __FILE__, __func__, __LINE__);
6175
6176 return (ret_val);
6177
6178 }
6179
6180 /*
6181 * vxge_hal_vpath_continue_irq - Continue handling IRQ: process all
6182 * completed descriptors.
6183 * @vpath_handle: Virtual Path handle.
6184 *
6185 * Process completed descriptors and unmask the vpath interrupts.
6186 *
6187 * The vxge_hal_vpath_continue_irq() calls upper-layer driver (ULD)
6188 * via supplied completion callback.
6189 *
6190 * Note that the vxge_hal_vpath_continue_irq is part of the _fast_ path.
6191 * To optimize the processing, the function does _not_ check for
6192 * errors and alarms.
6193 *
6194 * Returns: VXGE_HAL_OK.
6195 *
6196 * See also: vxge_hal_vpath_handle_irq()
6197 * vxge_hal_ring_rxd_next_completed(),
6198 * vxge_hal_fifo_txdl_next_completed(), vxge_hal_ring_callback_f {},
6199 * vxge_hal_fifo_callback_f {}.
6200 */
6201 vxge_hal_status_e
vxge_hal_vpath_continue_irq(vxge_hal_vpath_h vpath_handle)6202 vxge_hal_vpath_continue_irq(vxge_hal_vpath_h vpath_handle)
6203 {
6204 u32 got_rx = 1, got_tx = 1;
6205 __hal_device_t *hldev;
6206 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
6207 u32 isr_polling_cnt;
6208
6209 vxge_assert(vpath_handle != NULL);
6210
6211 hldev = vp->vpath->hldev;
6212
6213 vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
6214 __FILE__, __func__, __LINE__);
6215
6216 vxge_hal_trace_log_vpath_irq("vpath_handle = 0x"VXGE_OS_STXFMT,
6217 (ptr_t) vpath_handle);
6218
6219 isr_polling_cnt = hldev->header.config.isr_polling_cnt;
6220
6221 do {
6222 if (got_rx && (vp->vpath->ringh != NULL))
6223 (void) vxge_hal_vpath_poll_rx(vpath_handle, &got_rx);
6224
6225 if (got_tx && (vp->vpath->fifoh != NULL))
6226 (void) vxge_hal_vpath_poll_tx(vpath_handle, &got_tx);
6227
6228 if (!got_rx && !got_tx)
6229 break;
6230
6231 } while (isr_polling_cnt--);
6232
6233 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
6234 __FILE__, __func__, __LINE__);
6235
6236 return (VXGE_HAL_OK);
6237 }
6238
6239 /*
6240 * vxge_hal_vpath_handle_irq - Handle vpath IRQ.
6241 * @vpath_handle: Virtual Path handle.
6242 * @skip_alarms: Do not clear the alarms
6243 *
6244 * Perform the complete handling of the line interrupt. The function
6245 * performs two calls.
6246 * First it uses vxge_hal_vpath_begin_irq() to check the reason for
6247 * the interrupt and mask the vpath interrupts.
6248 * Second, it calls vxge_hal_vpath_continue_irq() to process all
6249 * completed descriptors and re-enable the interrupts.
6250 *
6251 * Returns: VXGE_HAL_OK - success;
6252 * VXGE_HAL_ERR_WRONG_IRQ - (shared) IRQ produced by other device.
6253 *
6254 * See also: vxge_hal_vpath_begin_irq(), vxge_hal_vpath_continue_irq().
6255 */
6256 vxge_hal_status_e
vxge_hal_vpath_handle_irq(vxge_hal_vpath_h vpath_handle,u32 skip_alarms)6257 vxge_hal_vpath_handle_irq(vxge_hal_vpath_h vpath_handle, u32 skip_alarms)
6258 {
6259 u64 reason;
6260 vxge_hal_status_e status;
6261 __hal_device_t *hldev;
6262 __hal_virtualpath_t *vpath;
6263
6264 vxge_assert(vpath_handle != NULL);
6265
6266 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
6267
6268 hldev = vpath->hldev;
6269
6270 vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
6271 __FILE__, __func__, __LINE__);
6272
6273 vxge_hal_trace_log_vpath_irq("vpath_handle = 0x"VXGE_OS_STXFMT,
6274 (ptr_t) vpath_handle);
6275
6276 if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
6277 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result: %d",
6278 __FILE__, __func__, __LINE__,
6279 VXGE_HAL_ERR_VPATH_NOT_OPEN);
6280 return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
6281 }
6282
6283 vxge_hal_vpath_mask_all(vpath_handle);
6284
6285 status = vxge_hal_vpath_begin_irq(vpath_handle,
6286 skip_alarms, &reason);
6287
6288 if (status != VXGE_HAL_OK) {
6289 vxge_hal_vpath_unmask_all(vpath_handle);
6290 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = %d",
6291 __FILE__, __func__, __LINE__, status);
6292 return (status);
6293 }
6294
6295 if (reason & VXGE_HAL_INTR_ALARM) {
6296 if (skip_alarms) {
6297 /* ULD needs to unmask explicitely */
6298 vxge_hal_trace_log_vpath_irq(
6299 "<== %s:%s:%d Result = %d",
6300 __FILE__, __func__, __LINE__,
6301 VXGE_HAL_ERR_CRITICAL);
6302 return (VXGE_HAL_ERR_CRITICAL);
6303 } else {
6304 vxge_hal_vpath_unmask_all(vpath_handle);
6305 vxge_hal_trace_log_vpath_irq(
6306 "<== %s:%s:%d Result = %d",
6307 __FILE__, __func__, __LINE__, status);
6308 return (status);
6309 }
6310 }
6311
6312 if (reason & VXGE_HAL_INTR_RX)
6313 vxge_hal_vpath_clear_rx(vpath_handle);
6314
6315 status = vxge_hal_vpath_continue_irq(vpath_handle);
6316
6317 vxge_hal_vpath_clear_tx(vpath_handle);
6318
6319 vxge_hal_vpath_unmask_all(vpath_handle);
6320
6321 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
6322 __FILE__, __func__, __LINE__);
6323 return (status);
6324 }
6325
6326 /*
6327 * vxge_hal_vpath_mask_tx - Mask Tx interrupts.
6328 * @vpath_handle: Virtual Path handle.
6329 *
6330 * Mask Tx device interrupts.
6331 *
6332 * See also: vxge_hal_vpath_unmask_tx(), vxge_hal_vpath_mask_rx(),
6333 * vxge_hal_vpath_clear_tx().
6334 */
6335 void
vxge_hal_vpath_mask_tx(vxge_hal_vpath_h vpath_handle)6336 vxge_hal_vpath_mask_tx(vxge_hal_vpath_h vpath_handle)
6337 {
6338 u64 val64;
6339 __hal_device_t *hldev;
6340 __hal_virtualpath_t *vpath;
6341
6342 vxge_assert(vpath_handle != NULL);
6343
6344 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
6345
6346 hldev = vpath->hldev;
6347
6348 vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
6349 __FILE__, __func__, __LINE__);
6350
6351 vxge_hal_trace_log_vpath_irq("vpath_handle = 0x"VXGE_OS_STXFMT,
6352 (ptr_t) vpath_handle);
6353
6354 if (vpath->fifoh == NULL) {
6355 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result: %d",
6356 __FILE__, __func__, __LINE__,
6357 VXGE_HAL_ERR_INVALID_HANDLE);
6358 return;
6359 }
6360
6361 if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
6362 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result: %d",
6363 __FILE__, __func__, __LINE__,
6364 VXGE_HAL_ERR_VPATH_NOT_OPEN);
6365 return;
6366 }
6367
6368 if (vpath->vp_id < 16) {
6369
6370 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6371 hldev->header.regh0,
6372 &hldev->common_reg->tim_int_mask0);
6373
6374 val64 |= vBIT(VXGE_HAL_INTR_TX, (vpath->vp_id * 4), 4);
6375
6376 vxge_os_pio_mem_write64(hldev->header.pdev,
6377 hldev->header.regh0,
6378 val64,
6379 &hldev->common_reg->tim_int_mask0);
6380
6381 } else {
6382
6383 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6384 hldev->header.regh0,
6385 &hldev->common_reg->tim_int_mask1);
6386
6387 val64 |= VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(VXGE_HAL_INTR_TX);
6388
6389 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
6390 hldev->header.regh0,
6391 (u32) bVAL32(val64, 0),
6392 &hldev->common_reg->tim_int_mask1);
6393 }
6394
6395 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
6396 __FILE__, __func__, __LINE__);
6397 }
6398
6399 /*
6400 * vxge_hal_vpath_clear_tx - Acknowledge (that is, clear) the
6401 * condition that has caused the TX interrupt.
6402 * @vpath_handle: Virtual Path handle.
6403 *
6404 * Acknowledge (that is, clear) the condition that has caused
6405 * the Tx interrupt.
6406 * See also: vxge_hal_vpath_begin_irq(), vxge_hal_vpath_continue_irq(),
6407 * vxge_hal_vpath_clear_rx(), vxge_hal_vpath_mask_tx().
6408 */
6409 void
vxge_hal_vpath_clear_tx(vxge_hal_vpath_h vpath_handle)6410 vxge_hal_vpath_clear_tx(vxge_hal_vpath_h vpath_handle)
6411 {
6412 __hal_device_t *hldev;
6413 __hal_virtualpath_t *vpath;
6414
6415 vxge_assert(vpath_handle != NULL);
6416
6417 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
6418
6419 hldev = vpath->hldev;
6420
6421 vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
6422 __FILE__, __func__, __LINE__);
6423
6424 vxge_hal_trace_log_vpath_irq("vpath_handle = 0x"VXGE_OS_STXFMT,
6425 (ptr_t) vpath_handle);
6426
6427 if (vpath->fifoh == NULL) {
6428 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result: %d",
6429 __FILE__, __func__, __LINE__,
6430 VXGE_HAL_ERR_INVALID_HANDLE);
6431 return;
6432 }
6433
6434 if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
6435 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result: %d",
6436 __FILE__, __func__, __LINE__,
6437 VXGE_HAL_ERR_VPATH_NOT_OPEN);
6438 return;
6439 }
6440
6441 if (vpath->vp_id < 16) {
6442
6443 vxge_os_pio_mem_write64(hldev->header.pdev,
6444 hldev->header.regh0,
6445 vBIT(VXGE_HAL_INTR_TX, (vpath->vp_id * 4), 4),
6446 &hldev->common_reg->tim_int_status0);
6447
6448 } else {
6449
6450 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
6451 hldev->header.regh0, (u32) bVAL32(
6452 vBIT(VXGE_HAL_INTR_TX, 0, 4),
6453 0),
6454 &hldev->common_reg->tim_int_status1);
6455
6456 }
6457
6458 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
6459 __FILE__, __func__, __LINE__);
6460 }
6461
6462 /*
6463 * vxge_hal_vpath_unmask_tx - Unmask Tx interrupts.
6464 * @vpath_handle: Virtual Path handle.
6465 *
6466 * Unmask Tx vpath interrupts.
6467 *
6468 * See also: vxge_hal_vpath_mask_tx(), vxge_hal_vpath_clear_tx().
6469 */
6470 void
vxge_hal_vpath_unmask_tx(vxge_hal_vpath_h vpath_handle)6471 vxge_hal_vpath_unmask_tx(vxge_hal_vpath_h vpath_handle)
6472 {
6473 u64 val64;
6474 __hal_device_t *hldev;
6475 __hal_virtualpath_t *vpath;
6476
6477 vxge_assert(vpath_handle != NULL);
6478
6479 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
6480
6481 hldev = vpath->hldev;
6482
6483 vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
6484 __FILE__, __func__, __LINE__);
6485
6486 vxge_hal_trace_log_vpath_irq("vpath_handle = 0x"VXGE_OS_STXFMT,
6487 (ptr_t) vpath_handle);
6488
6489 if (vpath->fifoh == NULL) {
6490 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result: %d",
6491 __FILE__, __func__, __LINE__,
6492 VXGE_HAL_ERR_INVALID_HANDLE);
6493 return;
6494 }
6495
6496 if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
6497 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result: %d",
6498 __FILE__, __func__, __LINE__,
6499 VXGE_HAL_ERR_VPATH_NOT_AVAILABLE);
6500 return;
6501 }
6502
6503 if (vpath->vp_id < 16) {
6504
6505 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6506 hldev->header.regh0,
6507 &hldev->common_reg->tim_int_mask0);
6508
6509 val64 &= ~vBIT(VXGE_HAL_INTR_TX, (vpath->vp_id * 4), 4);
6510
6511 vxge_os_pio_mem_write64(hldev->header.pdev,
6512 hldev->header.regh0,
6513 val64,
6514 &hldev->common_reg->tim_int_mask0);
6515
6516 } else {
6517
6518 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6519 hldev->header.regh0,
6520 &hldev->common_reg->tim_int_mask1);
6521
6522 val64 &=
6523 ~VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(VXGE_HAL_INTR_TX);
6524
6525 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
6526 hldev->header.regh0,
6527 (u32) bVAL32(val64, 0),
6528 &hldev->common_reg->tim_int_mask1);
6529
6530 }
6531
6532 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
6533 __FILE__, __func__, __LINE__);
6534 }
6535
6536 /*
6537 * vxge_hal_vpath_mask_rx - Mask Rx interrupts.
6538 * @vpath_handle: Virtual Path handle.
6539 *
6540 * Mask Rx vpath interrupts.
6541 *
6542 * See also: vxge_hal_vpath_unmask_rx(), vxge_hal_vpath_mask_tx(),
6543 * vxge_hal_vpath_clear_rx().
6544 */
6545 void
vxge_hal_vpath_mask_rx(vxge_hal_vpath_h vpath_handle)6546 vxge_hal_vpath_mask_rx(vxge_hal_vpath_h vpath_handle)
6547 {
6548 u64 val64;
6549 __hal_device_t *hldev;
6550 __hal_virtualpath_t *vpath;
6551
6552 vxge_assert(vpath_handle != NULL);
6553
6554 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
6555
6556 hldev = vpath->hldev;
6557
6558 vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
6559 __FILE__, __func__, __LINE__);
6560
6561 vxge_hal_trace_log_vpath_irq("vpath_handle = 0x"VXGE_OS_STXFMT,
6562 (ptr_t) vpath_handle);
6563
6564 if (vpath->ringh == NULL) {
6565 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result: %d",
6566 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
6567 return;
6568 }
6569
6570 if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
6571 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result: %d",
6572 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
6573 return;
6574 }
6575
6576 if (vpath->vp_id < 16) {
6577
6578 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6579 hldev->header.regh0,
6580 &hldev->common_reg->tim_int_mask0);
6581
6582 val64 |= vBIT(VXGE_HAL_INTR_RX, (vpath->vp_id * 4), 4);
6583
6584 vxge_os_pio_mem_write64(hldev->header.pdev,
6585 hldev->header.regh0,
6586 val64,
6587 &hldev->common_reg->tim_int_mask0);
6588
6589 } else {
6590
6591 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6592 hldev->header.regh0,
6593 &hldev->common_reg->tim_int_mask1);
6594
6595 val64 |= VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(VXGE_HAL_INTR_RX);
6596
6597 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
6598 hldev->header.regh0,
6599 (u32) bVAL32(val64, 0),
6600 &hldev->common_reg->tim_int_mask1);
6601
6602 }
6603
6604 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
6605 __FILE__, __func__, __LINE__);
6606 }
6607
6608
6609 /*
6610 * vxge_hal_vpath_clear_rx - Acknowledge (that is, clear) the
6611 * condition that has caused the RX interrupt.
6612 * @vpath_handle: Virtual Path handle.
6613 *
6614 * Acknowledge (that is, clear) the condition that has caused
6615 * the Rx interrupt.
6616 * See also: vxge_hal_vpath_begin_irq(), vxge_hal_vpath_continue_irq(),
6617 * vxge_hal_vpath_clear_tx(), vxge_hal_vpath_mask_rx().
6618 */
6619 void
vxge_hal_vpath_clear_rx(vxge_hal_vpath_h vpath_handle)6620 vxge_hal_vpath_clear_rx(vxge_hal_vpath_h vpath_handle)
6621 {
6622 __hal_device_t *hldev;
6623 __hal_virtualpath_t *vpath;
6624
6625 vxge_assert(vpath_handle != NULL);
6626
6627 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
6628
6629 hldev = vpath->hldev;
6630
6631 vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
6632 __FILE__, __func__, __LINE__);
6633
6634 vxge_hal_trace_log_vpath_irq("vpath_handle = 0x"VXGE_OS_STXFMT,
6635 (ptr_t) vpath_handle);
6636
6637 if (vpath->ringh == NULL) {
6638 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result: %d",
6639 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
6640 return;
6641 }
6642
6643 if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
6644 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result: %d",
6645 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
6646 return;
6647 }
6648
6649 if (vpath->vp_id < 16) {
6650
6651 vxge_os_pio_mem_write64(hldev->header.pdev,
6652 hldev->header.regh0,
6653 vBIT(VXGE_HAL_INTR_RX, (vpath->vp_id * 4), 4),
6654 &hldev->common_reg->tim_int_status0);
6655
6656 } else {
6657
6658 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
6659 hldev->header.regh0,
6660 (u32) bVAL32(vBIT(VXGE_HAL_INTR_RX, 0, 4), 0),
6661 &hldev->common_reg->tim_int_status1);
6662
6663 }
6664
6665
6666 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
6667 __FILE__, __func__, __LINE__);
6668 }
6669
6670 /*
6671 * vxge_hal_vpath_unmask_rx - Unmask Rx interrupts.
6672 * @vpath_handle: Virtual Path handle.
6673 *
6674 * Unmask Rx vpath interrupts.
6675 *
6676 * See also: vxge_hal_vpath_mask_rx(), vxge_hal_vpath_clear_rx().
6677 */
6678 void
vxge_hal_vpath_unmask_rx(vxge_hal_vpath_h vpath_handle)6679 vxge_hal_vpath_unmask_rx(vxge_hal_vpath_h vpath_handle)
6680 {
6681 u64 val64;
6682 __hal_device_t *hldev;
6683 __hal_virtualpath_t *vpath;
6684
6685 vxge_assert(vpath_handle != NULL);
6686
6687 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
6688
6689 hldev = vpath->hldev;
6690
6691 vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
6692 __FILE__, __func__, __LINE__);
6693
6694 vxge_hal_trace_log_vpath_irq("vpath_handle = 0x"VXGE_OS_STXFMT,
6695 (ptr_t) vpath_handle);
6696
6697 if (vpath->ringh == NULL) {
6698 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result: %d",
6699 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
6700 return;
6701 }
6702
6703 if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
6704 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result: %d",
6705 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
6706 return;
6707 }
6708
6709 if (vpath->vp_id < 16) {
6710
6711 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6712 hldev->header.regh0,
6713 &hldev->common_reg->tim_int_mask0);
6714
6715 val64 &= ~vBIT(VXGE_HAL_INTR_RX, (vpath->vp_id * 4), 4);
6716
6717 vxge_os_pio_mem_write64(hldev->header.pdev,
6718 hldev->header.regh0,
6719 val64,
6720 &hldev->common_reg->tim_int_mask0);
6721
6722 } else {
6723
6724 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6725 hldev->header.regh0,
6726 &hldev->common_reg->tim_int_mask1);
6727
6728 val64 &=
6729 ~VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(VXGE_HAL_INTR_RX);
6730
6731 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
6732 hldev->header.regh0,
6733 (u32) bVAL32(val64, 0),
6734 &hldev->common_reg->tim_int_mask1);
6735
6736 }
6737
6738
6739 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
6740 __FILE__, __func__, __LINE__);
6741 }
6742
6743 /*
6744 * vxge_hal_vpath_mask_tx_rx - Mask Tx and Rx interrupts.
6745 * @vpath_handle: Virtual Path handle.
6746 *
6747 * Mask Tx and Rx vpath interrupts.
6748 *
6749 * See also: vxge_hal_vpath_unmask_tx_rx(), vxge_hal_vpath_clear_tx_rx().
6750 */
6751 void
vxge_hal_vpath_mask_tx_rx(vxge_hal_vpath_h vpath_handle)6752 vxge_hal_vpath_mask_tx_rx(vxge_hal_vpath_h vpath_handle)
6753 {
6754 u64 val64;
6755 __hal_device_t *hldev;
6756 __hal_virtualpath_t *vpath;
6757
6758 vxge_assert(vpath_handle != NULL);
6759
6760 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
6761
6762 hldev = vpath->hldev;
6763
6764 vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
6765 __FILE__, __func__, __LINE__);
6766
6767 vxge_hal_trace_log_vpath_irq("vpath_handle = 0x"VXGE_OS_STXFMT,
6768 (ptr_t) vpath_handle);
6769
6770 if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
6771 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result: %d",
6772 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
6773 return;
6774 }
6775
6776 if (vpath->vp_id < 16) {
6777
6778 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6779 hldev->header.regh0,
6780 &hldev->common_reg->tim_int_mask0);
6781
6782 val64 |= vBIT(VXGE_HAL_INTR_TX, (vpath->vp_id * 4), 4) |
6783 vBIT(VXGE_HAL_INTR_RX, (vpath->vp_id * 4), 4);
6784
6785 vxge_os_pio_mem_write64(hldev->header.pdev,
6786 hldev->header.regh0,
6787 val64,
6788 &hldev->common_reg->tim_int_mask0);
6789
6790 } else {
6791
6792 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6793 hldev->header.regh0,
6794 &hldev->common_reg->tim_int_mask1);
6795
6796 val64 |=
6797 VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(VXGE_HAL_INTR_TX) |
6798 VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(VXGE_HAL_INTR_RX);
6799
6800 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
6801 hldev->header.regh0,
6802 (u32) bVAL32(val64, 0),
6803 &hldev->common_reg->tim_int_mask1);
6804
6805 }
6806
6807 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
6808 __FILE__, __func__, __LINE__);
6809 }
6810
6811
6812 /*
6813 * vxge_hal_vpath_clear_tx_rx - Acknowledge (that is, clear) the
6814 * condition that has caused the Tx and RX interrupt.
6815 * @vpath_handle: Virtual Path handle.
6816 *
6817 * Acknowledge (that is, clear) the condition that has caused
6818 * the Tx and Rx interrupt.
6819 * See also: vxge_hal_vpath_begin_irq(), vxge_hal_vpath_continue_irq(),
6820 * vxge_hal_vpath_clear_tx_rx(), vxge_hal_vpath_mask_tx_rx().
6821 */
6822 void
vxge_hal_vpath_clear_tx_rx(vxge_hal_vpath_h vpath_handle)6823 vxge_hal_vpath_clear_tx_rx(vxge_hal_vpath_h vpath_handle)
6824 {
6825 u64 val64;
6826 __hal_device_t *hldev;
6827 __hal_virtualpath_t *vpath;
6828
6829 vxge_assert(vpath_handle != NULL);
6830
6831 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
6832
6833 hldev = vpath->hldev;
6834
6835 vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
6836 __FILE__, __func__, __LINE__);
6837
6838 vxge_hal_trace_log_vpath_irq("vpath_handle = 0x"VXGE_OS_STXFMT,
6839 (ptr_t) vpath_handle);
6840
6841 if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
6842 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result: %d",
6843 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
6844 return;
6845 }
6846
6847 val64 = 0;
6848
6849 if (vpath->vp_id < 16) {
6850
6851 if (vpath->fifoh != NULL)
6852 val64 |= vBIT(VXGE_HAL_INTR_TX, (vpath->vp_id * 4), 4);
6853 else
6854 val64 &= ~vBIT(VXGE_HAL_INTR_TX, (vpath->vp_id * 4), 4);
6855
6856 if (vpath->ringh != NULL)
6857 val64 |= vBIT(VXGE_HAL_INTR_RX, (vpath->vp_id * 4), 4);
6858 else
6859 val64 &= ~vBIT(VXGE_HAL_INTR_RX, (vpath->vp_id * 4), 4);
6860
6861 vxge_os_pio_mem_write64(hldev->header.pdev,
6862 hldev->header.regh0,
6863 val64,
6864 &hldev->common_reg->tim_int_status0);
6865
6866 } else {
6867
6868 if (vpath->fifoh != NULL)
6869 val64 |= vBIT(VXGE_HAL_INTR_TX, 0, 4);
6870
6871 if (vpath->ringh != NULL)
6872 val64 |= vBIT(VXGE_HAL_INTR_RX, 0, 4);
6873 else
6874 val64 &= ~vBIT(VXGE_HAL_INTR_RX, 0, 4);
6875
6876 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
6877 hldev->header.regh0,
6878 (u32) bVAL32(val64, 0),
6879 &hldev->common_reg->tim_int_status1);
6880
6881 }
6882
6883 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
6884 __FILE__, __func__, __LINE__);
6885 }
6886
6887 /*
6888 * vxge_hal_vpath_unmask_tx_rx - Unmask Tx and Rx interrupts.
6889 * @vpath_handle: Virtual Path handle.
6890 *
6891 * Unmask Tx and Rx vpath interrupts.
6892 *
6893 * See also: vxge_hal_vpath_mask_tx_rx(), vxge_hal_vpath_clear_tx_rx().
6894 */
6895 void
vxge_hal_vpath_unmask_tx_rx(vxge_hal_vpath_h vpath_handle)6896 vxge_hal_vpath_unmask_tx_rx(vxge_hal_vpath_h vpath_handle)
6897 {
6898 u64 val64;
6899 __hal_device_t *hldev;
6900 __hal_virtualpath_t *vpath;
6901
6902 vxge_assert(vpath_handle != NULL);
6903
6904 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
6905
6906 hldev = vpath->hldev;
6907
6908 vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
6909 __FILE__, __func__, __LINE__);
6910
6911 vxge_hal_trace_log_vpath_irq("vpath_handle = 0x"VXGE_OS_STXFMT,
6912 (ptr_t) vpath_handle);
6913
6914 if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
6915 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result: %d",
6916 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
6917 return;
6918 }
6919
6920 if (vpath->vp_id < 16) {
6921
6922 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6923 hldev->header.regh0,
6924 &hldev->common_reg->tim_int_mask0);
6925
6926 if (vpath->fifoh != NULL)
6927 val64 &= ~vBIT(VXGE_HAL_INTR_TX, (vpath->vp_id * 4), 4);
6928 else
6929 val64 |= vBIT(VXGE_HAL_INTR_TX, (vpath->vp_id * 4), 4);
6930
6931 if (vpath->ringh != NULL)
6932 val64 &= ~vBIT(VXGE_HAL_INTR_RX, (vpath->vp_id * 4), 4);
6933 else
6934 val64 |= vBIT(VXGE_HAL_INTR_RX, (vpath->vp_id * 4), 4);
6935
6936 vxge_os_pio_mem_write64(hldev->header.pdev,
6937 hldev->header.regh0,
6938 val64,
6939 &hldev->common_reg->tim_int_mask0);
6940
6941 } else {
6942
6943 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6944 hldev->header.regh0,
6945 &hldev->common_reg->tim_int_mask1);
6946
6947 if (vpath->fifoh != NULL)
6948 val64 &= ~VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(
6949 VXGE_HAL_INTR_TX);
6950 else
6951 val64 |= VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(
6952 VXGE_HAL_INTR_TX);
6953
6954 if (vpath->ringh != NULL)
6955 val64 &= ~VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(
6956 VXGE_HAL_INTR_RX);
6957 else
6958 val64 |= VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(
6959 VXGE_HAL_INTR_RX);
6960
6961 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
6962 hldev->header.regh0,
6963 (u32) bVAL32(val64, 0),
6964 &hldev->common_reg->tim_int_mask1);
6965
6966 }
6967
6968 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
6969 __FILE__, __func__, __LINE__);
6970 }
6971
6972 /*
6973 * vxge_hal_vpath_alarm_process - Process Alarms.
6974 * @vpath: Virtual Path.
6975 * @skip_alarms: Do not clear the alarms
6976 *
6977 * Process vpath alarms.
6978 *
6979 */
6980 vxge_hal_status_e
vxge_hal_vpath_alarm_process(vxge_hal_vpath_h vpath_handle,u32 skip_alarms)6981 vxge_hal_vpath_alarm_process(vxge_hal_vpath_h vpath_handle, u32 skip_alarms)
6982 {
6983 vxge_hal_status_e status;
6984 __hal_device_t *hldev;
6985 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
6986
6987 vxge_assert(vpath_handle != NULL);
6988
6989 hldev = vp->vpath->hldev;
6990
6991 vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
6992 __FILE__, __func__, __LINE__);
6993
6994 vxge_hal_trace_log_vpath_irq("vpath_handle = 0x"VXGE_OS_STXFMT,
6995 (ptr_t) vpath_handle);
6996
6997 status = __hal_vpath_alarm_process(
6998 vp->vpath,
6999 skip_alarms);
7000
7001 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = %d",
7002 __FILE__, __func__, __LINE__, status);
7003
7004 return (status);
7005 }
7006
7007 /*
7008 * vxge_hal_vpath_msix_mode - Is MSIX enabled?
7009 * @vpath_handle: Virtual Path handle.
7010 *
7011 * Returns 0 if MSI is enabled for the specified device,
7012 * non-zero otherwise.
7013 */
7014 u32
vxge_hal_vpath_msix_mode(vxge_hal_vpath_h vpath_handle)7015 vxge_hal_vpath_msix_mode(vxge_hal_vpath_h vpath_handle)
7016 {
7017 __hal_device_t *hldev;
7018 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
7019
7020 vxge_assert(vpath_handle != NULL);
7021
7022 hldev = vp->vpath->hldev;
7023
7024 vxge_hal_trace_log_vpath("==> %s:%s:%d",
7025 __FILE__, __func__, __LINE__);
7026
7027 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
7028 (ptr_t) vpath_handle);
7029
7030 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
7031 __FILE__, __func__, __LINE__);
7032
7033 return (hldev->header.msix_enabled);
7034 }
7035
7036 /*
7037 * vxge_hal_vpath_msix_set
7038 * Associate MSIX vectors with TIM interrupts and alrms
7039 * @vpath_handle: Virtual Path handle.
7040 * @tim_msix_id: MSIX vectors associated with VXGE_HAL_VPATH_MSIX_MAX number of
7041 * interrupts(Can be repeated). If fifo or ring are not enabled
7042 * the MSIX vector for that should be set to 0
7043 * @alarm_msix_id: MSIX vector for alarm.
7044 *
7045 * This API will associate a given MSIX vector numbers with the four TIM
7046 * interrupts and alarm interrupt.
7047 */
7048 vxge_hal_status_e
vxge_hal_vpath_msix_set(vxge_hal_vpath_h vpath_handle,int * tim_msix_id,int alarm_msix_id)7049 vxge_hal_vpath_msix_set(vxge_hal_vpath_h vpath_handle,
7050 int *tim_msix_id,
7051 int alarm_msix_id)
7052 {
7053 u32 i;
7054 u32 j;
7055 u32 rvp_id;
7056 u32 msix_id;
7057 u64 val64;
7058 __hal_device_t *hldev;
7059 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
7060
7061 vxge_assert(vp != NULL);
7062
7063 hldev = vp->vpath->hldev;
7064
7065 vxge_hal_trace_log_vpath("==> %s:%s:%d",
7066 __FILE__, __func__, __LINE__);
7067
7068 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT", "
7069 "tim_msix_id0 = %d, tim_msix_id1 = %d, tim_msix_id2 = %d, "
7070 "tim_msix_id3 = %d, alarm_msix_id = %d", (ptr_t) vpath_handle,
7071 tim_msix_id[0], tim_msix_id[1], tim_msix_id[2], tim_msix_id[3],
7072 alarm_msix_id);
7073
7074 for (i = 0; i < VXGE_HAL_VPATH_MSIX_MAX + 1; i++) {
7075
7076 if (i == VXGE_HAL_VPATH_MSIX_MAX)
7077 msix_id = alarm_msix_id;
7078 else
7079 msix_id = tim_msix_id[i];
7080
7081 rvp_id = msix_id / VXGE_HAL_VPATH_MSIX_MAX;
7082
7083 for (j = 0; j < VXGE_HAL_MAX_VIRTUAL_PATHS; j++) {
7084
7085 if (!(hldev->vpath_assignments & mBIT(j)))
7086 continue;
7087
7088 if (rvp_id-- == 0) {
7089 hldev->msix_map[msix_id].vp_id = j;
7090 hldev->msix_map[msix_id].int_num =
7091 msix_id % VXGE_HAL_VPATH_MSIX_MAX;
7092 break;
7093 }
7094 }
7095 }
7096
7097 val64 = VXGE_HAL_INTERRUPT_CFG0_GROUP0_MSIX_FOR_TXTI(
7098 hldev->msix_map[tim_msix_id[0]].vp_id * VXGE_HAL_VPATH_MSIX_MAX +
7099 hldev->msix_map[tim_msix_id[0]].int_num) |
7100 VXGE_HAL_INTERRUPT_CFG0_GROUP1_MSIX_FOR_TXTI(
7101 hldev->msix_map[tim_msix_id[1]].vp_id * VXGE_HAL_VPATH_MSIX_MAX +
7102 hldev->msix_map[tim_msix_id[1]].int_num) |
7103 VXGE_HAL_INTERRUPT_CFG0_GROUP2_MSIX_FOR_TXTI(
7104 hldev->msix_map[tim_msix_id[2]].vp_id * VXGE_HAL_VPATH_MSIX_MAX +
7105 hldev->msix_map[tim_msix_id[2]].int_num) |
7106 VXGE_HAL_INTERRUPT_CFG0_GROUP3_MSIX_FOR_TXTI(
7107 hldev->msix_map[tim_msix_id[3]].vp_id * VXGE_HAL_VPATH_MSIX_MAX +
7108 hldev->msix_map[tim_msix_id[3]].int_num);
7109
7110 vxge_os_pio_mem_write64(hldev->header.pdev,
7111 hldev->header.regh0,
7112 val64,
7113 &vp->vpath->vp_reg->interrupt_cfg0);
7114
7115 vxge_os_pio_mem_write64(hldev->header.pdev,
7116 hldev->header.regh0,
7117 VXGE_HAL_INTERRUPT_CFG2_ALARM_MAP_TO_MSG(
7118 hldev->msix_map[alarm_msix_id].vp_id * VXGE_HAL_VPATH_MSIX_MAX +
7119 hldev->msix_map[alarm_msix_id].int_num),
7120 &vp->vpath->vp_reg->interrupt_cfg2);
7121
7122 if (hldev->header.config.intr_mode ==
7123 VXGE_HAL_INTR_MODE_MSIX_ONE_SHOT) {
7124
7125 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
7126 hldev->header.regh0, (u32) bVAL32(
7127 VXGE_HAL_ONE_SHOT_VECT0_EN_ONE_SHOT_VECT0_EN, 0),
7128 &vp->vpath->vp_reg->one_shot_vect0_en);
7129
7130 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
7131 hldev->header.regh0, (u32) bVAL32(
7132 VXGE_HAL_ONE_SHOT_VECT1_EN_ONE_SHOT_VECT1_EN, 0),
7133 &vp->vpath->vp_reg->one_shot_vect1_en);
7134
7135 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
7136 hldev->header.regh0, (u32) bVAL32(
7137 VXGE_HAL_ONE_SHOT_VECT2_EN_ONE_SHOT_VECT2_EN, 0),
7138 &vp->vpath->vp_reg->one_shot_vect2_en);
7139
7140 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
7141 hldev->header.regh0, (u32) bVAL32(
7142 VXGE_HAL_ONE_SHOT_VECT3_EN_ONE_SHOT_VECT3_EN, 0),
7143 &vp->vpath->vp_reg->one_shot_vect3_en);
7144
7145 } else if (hldev->header.config.intr_mode ==
7146 VXGE_HAL_INTR_MODE_EMULATED_INTA) {
7147 /* For emulated-INTA we are only using MSI-X 1 to be one shot */
7148 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
7149 hldev->header.regh0, (u32) bVAL32(
7150 VXGE_HAL_ONE_SHOT_VECT1_EN_ONE_SHOT_VECT1_EN, 0),
7151 &vp->vpath->vp_reg->one_shot_vect1_en);
7152
7153 }
7154
7155 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
7156 __FILE__, __func__, __LINE__);
7157
7158 return (VXGE_HAL_OK);
7159 }
7160
7161 /*
7162 * vxge_hal_vpath_msix_mask - Mask MSIX Vector.
7163 * @vpath_handle: Virtual Path handle.
7164 * @msix_id: MSIX ID
7165 *
7166 * The function masks the msix interrupt for the given msix_id
7167 *
7168 * Note:
7169 *
7170 * Returns: 0,
7171 * Otherwise, VXGE_HAL_ERR_WRONG_IRQ if the msix index is out of range
7172 * status.
7173 * See also:
7174 */
7175 void
vxge_hal_vpath_msix_mask(vxge_hal_vpath_h vpath_handle,int msix_id)7176 vxge_hal_vpath_msix_mask(vxge_hal_vpath_h vpath_handle, int msix_id)
7177 {
7178 __hal_device_t *hldev;
7179 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
7180
7181 vxge_assert(vpath_handle != NULL);
7182
7183 hldev = vp->vpath->hldev;
7184
7185 vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
7186 __FILE__, __func__, __LINE__);
7187
7188 vxge_hal_trace_log_vpath_irq(
7189 "vpath_handle = 0x"VXGE_OS_STXFMT", msix_id = %d",
7190 (ptr_t) vpath_handle, msix_id);
7191
7192 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
7193 hldev->header.regh0,
7194 (u32) bVAL32(mBIT(hldev->msix_map[msix_id].vp_id), 0),
7195 &hldev->common_reg->set_msix_mask_vect[
7196 hldev->msix_map[msix_id].int_num]);
7197
7198 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
7199 __FILE__, __func__, __LINE__);
7200 }
7201
7202 /*
7203 * vxge_hal_vpath_msix_clear - Clear MSIX Vector.
7204 * @vpath_handle: Virtual Path handle.
7205 * @msix_id: MSI ID
7206 *
7207 * The function clears the msix interrupt for the given msix_id
7208 *
7209 * Note:
7210 *
7211 * Returns: 0,
7212 * Otherwise, VXGE_HAL_ERR_WRONG_IRQ if the msix index is out of range
7213 * status.
7214 * See also:
7215 */
7216 void
vxge_hal_vpath_msix_clear(vxge_hal_vpath_h vpath_handle,int msix_id)7217 vxge_hal_vpath_msix_clear(vxge_hal_vpath_h vpath_handle, int msix_id)
7218 {
7219 __hal_device_t *hldev;
7220 __hal_vpath_handle_t *vp;
7221
7222 vxge_assert(vpath_handle != NULL);
7223
7224 vp = (__hal_vpath_handle_t *) vpath_handle;
7225 hldev = vp->vpath->hldev;
7226
7227 vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
7228 __FILE__, __func__, __LINE__);
7229
7230 vxge_hal_trace_log_vpath_irq(
7231 "vpath_handle = 0x"VXGE_OS_STXFMT", msix_id = %d",
7232 (ptr_t) vpath_handle, msix_id);
7233
7234 if ((hldev->header.config.intr_mode ==
7235 VXGE_HAL_INTR_MODE_MSIX_ONE_SHOT) ||
7236 (hldev->header.config.intr_mode ==
7237 VXGE_HAL_INTR_MODE_EMULATED_INTA)) {
7238 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
7239 hldev->header.regh0,
7240 (u32) bVAL32(mBIT(hldev->msix_map[msix_id].vp_id), 0),
7241 &hldev->common_reg->clr_msix_one_shot_vec[
7242 hldev->msix_map[msix_id].int_num]);
7243
7244 if (hldev->header.config.intr_mode ==
7245 VXGE_HAL_INTR_MODE_EMULATED_INTA) {
7246 /* Adding read to flush the write,
7247 * for HP-ISS platform
7248 */
7249 vxge_os_pio_mem_read64(hldev->header.pdev,
7250 hldev->header.regh0,
7251 &hldev->common_reg->titan_general_int_status);
7252 }
7253 } else {
7254 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
7255 hldev->header.regh0,
7256 (u32) bVAL32(mBIT(hldev->msix_map[msix_id].vp_id), 0),
7257 &hldev->common_reg->clear_msix_mask_vect[
7258 hldev->msix_map[msix_id].int_num]);
7259 }
7260
7261 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
7262 __FILE__, __func__, __LINE__);
7263 }
7264
7265 /* NEW CODE BEGIN */
7266
7267 vxge_hal_status_e
vxge_hal_vpath_mf_msix_set(vxge_hal_vpath_h vpath_handle,int * tim_msix_id,int alarm_msix_id)7268 vxge_hal_vpath_mf_msix_set(vxge_hal_vpath_h vpath_handle,
7269 int *tim_msix_id,
7270 int alarm_msix_id)
7271 {
7272
7273 u64 val64;
7274 __hal_device_t *hldev;
7275 __hal_vpath_handle_t *vp;
7276
7277 vxge_assert(vpath_handle != NULL);
7278
7279 vp = (__hal_vpath_handle_t *) vpath_handle;
7280 hldev = vp->vpath->hldev;
7281
7282 /* Write the internal msi-x vectors numbers */
7283 val64 = VXGE_HAL_INTERRUPT_CFG0_GROUP0_MSIX_FOR_TXTI(tim_msix_id[0]) |
7284 VXGE_HAL_INTERRUPT_CFG0_GROUP1_MSIX_FOR_TXTI(tim_msix_id[1]);
7285
7286 #if defined(VXGE_EMULATED_INTA)
7287 if (hldev->config.intr_mode ==
7288 VXGE_HAL_INTR_MODE_EMULATED_INTA)
7289 val64 |= VXGE_HAL_INTERRUPT_CFG0_GROUP2_MSIX_FOR_TXTI(
7290 (vp->vpath->vp_id * 4) + tim_msix_id[2]);
7291 #endif
7292
7293 vxge_os_pio_mem_write64(hldev->header.pdev,
7294 hldev->header.regh0,
7295 val64,
7296 &vp->vpath->vp_reg->interrupt_cfg0);
7297
7298 vxge_os_pio_mem_read64(hldev->header.pdev,
7299 hldev->header.regh0,
7300 &vp->vpath->vp_reg->interrupt_cfg0);
7301
7302 vxge_os_pio_mem_write64(hldev->header.pdev,
7303 hldev->header.regh0,
7304 VXGE_HAL_INTERRUPT_CFG2_ALARM_MAP_TO_MSG(
7305 (hldev->first_vp_id * 4) + alarm_msix_id),
7306 &vp->vpath->vp_reg->interrupt_cfg2);
7307
7308 if (
7309 #if defined(VXGE_EMULATED_INTA)
7310 (hldev->header.config.intr_mode ==
7311 VXGE_HAL_INTR_MODE_EMULATED_INTA) ||
7312 #endif
7313 (hldev->header.config.intr_mode ==
7314 VXGE_HAL_INTR_MODE_MSIX_ONE_SHOT)) {
7315 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
7316 hldev->header.regh0, (u32) bVAL32(
7317 VXGE_HAL_ONE_SHOT_VECT1_EN_ONE_SHOT_VECT1_EN, 0),
7318 &vp->vpath->vp_reg->one_shot_vect1_en);
7319 }
7320
7321 if (hldev->header.config.intr_mode ==
7322 VXGE_HAL_INTR_MODE_MSIX_ONE_SHOT) {
7323 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
7324 hldev->header.regh0, (u32) bVAL32(
7325 VXGE_HAL_ONE_SHOT_VECT2_EN_ONE_SHOT_VECT2_EN, 0),
7326 &vp->vpath->vp_reg->one_shot_vect2_en);
7327
7328 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
7329 hldev->header.regh0, (u32) bVAL32(
7330 VXGE_HAL_ONE_SHOT_VECT3_EN_ONE_SHOT_VECT3_EN, 0),
7331 &vp->vpath->vp_reg->one_shot_vect3_en);
7332 }
7333
7334 return (VXGE_HAL_OK);
7335 }
7336
7337 /*
7338 * vxge_hal_vpath_mf_msix_mask - Mask MSIX Vector.
7339 * @vp: Virtual Path handle.
7340 * @msix_id: MSIX ID
7341 *
7342 * The function masks the msix interrupt for the given msix_id
7343 *
7344 * Returns: 0,
7345 * Otherwise, VXGE_HW_ERR_WRONG_IRQ if the msix index is out of range
7346 * status.
7347 * See also:
7348 */
7349 void
vxge_hal_vpath_mf_msix_mask(vxge_hal_vpath_h vpath_handle,int msix_id)7350 vxge_hal_vpath_mf_msix_mask(vxge_hal_vpath_h vpath_handle, int msix_id)
7351 {
7352 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
7353
7354 vxge_hal_pio_mem_write32_upper(vp->vpath->hldev->header.pdev,
7355 vp->vpath->hldev->header.regh0, (u32) bVAL32(mBIT(msix_id >> 2), 0),
7356 &vp->vpath->hldev->common_reg->set_msix_mask_vect[msix_id % 4]);
7357 }
7358
7359 /*
7360 * vxge_hal_vpath_mf_msix_clear - Clear MSIX Vector.
7361 * @vp: Virtual Path handle.
7362 * @msix_id: MSI ID
7363 *
7364 * The function clears the msix interrupt for the given msix_id
7365 *
7366 * Returns: 0,
7367 * Otherwise, VXGE_HW_ERR_WRONG_IRQ if the msix index is out of range
7368 * status.
7369 * See also:
7370 */
7371 void
vxge_hal_vpath_mf_msix_clear(vxge_hal_vpath_h vpath_handle,int msix_id)7372 vxge_hal_vpath_mf_msix_clear(vxge_hal_vpath_h vpath_handle, int msix_id)
7373 {
7374 __hal_device_t *hldev;
7375 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
7376
7377 vxge_assert(vpath_handle != NULL);
7378
7379 hldev = vp->vpath->hldev;
7380
7381 if (
7382 #if defined(VXGE_EMULATED_INTA)
7383 (hldev->header.config.intr_mode ==
7384 VXGE_HAL_INTR_MODE_EMULATED_INTA) ||
7385 #endif
7386 (hldev->header.config.intr_mode ==
7387 VXGE_HAL_INTR_MODE_MSIX_ONE_SHOT)) {
7388 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
7389 hldev->header.regh0,
7390 (u32) bVAL32(mBIT((msix_id >> 2)), 0),
7391 &hldev->common_reg->clr_msix_one_shot_vec[msix_id % 4]);
7392 } else {
7393 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
7394 hldev->header.regh0,
7395 (u32) bVAL32(mBIT((msix_id >> 2)), 0),
7396 &hldev->common_reg->clear_msix_mask_vect[msix_id % 4]);
7397 }
7398 }
7399
7400 /*
7401 * vxge_hal_vpath_mf_msix_unmask - Unmask the MSIX Vector.
7402 * @vp: Virtual Path handle.
7403 * @msix_id: MSI ID
7404 *
7405 * The function unmasks the msix interrupt for the given msix_id
7406 *
7407 * Returns: 0,
7408 * Otherwise, VXGE_HW_ERR_WRONG_IRQ if the msix index is out of range
7409 * status.
7410 * See also:
7411 */
7412 void
vxge_hal_vpath_mf_msix_unmask(vxge_hal_vpath_h vpath_handle,int msix_id)7413 vxge_hal_vpath_mf_msix_unmask(vxge_hal_vpath_h vpath_handle, int msix_id)
7414 {
7415 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
7416 vxge_hal_pio_mem_write32_upper(vp->vpath->hldev->header.pdev,
7417 vp->vpath->hldev->header.regh0,
7418 (u32) bVAL32(mBIT(msix_id >> 2), 0),
7419 &vp->vpath->hldev->common_reg->
7420 clear_msix_mask_vect[msix_id % 4]);
7421 }
7422
7423 /* NEW CODE ENDS */
7424
7425 /*
7426 * vxge_hal_vpath_msix_unmask - Unmask the MSIX Vector.
7427 * @vpath_handle: Virtual Path handle.
7428 * @msix_id: MSI ID
7429 *
7430 * The function unmasks the msix interrupt for the given msix_id
7431 *
7432 * Note:
7433 *
7434 * Returns: 0,
7435 * Otherwise, VXGE_HAL_ERR_WRONG_IRQ if the msix index is out of range
7436 * status.
7437 * See also:
7438 */
7439 void
vxge_hal_vpath_msix_unmask(vxge_hal_vpath_h vpath_handle,int msix_id)7440 vxge_hal_vpath_msix_unmask(vxge_hal_vpath_h vpath_handle, int msix_id)
7441 {
7442 __hal_device_t *hldev;
7443 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
7444
7445 vxge_assert(vpath_handle != NULL);
7446
7447 hldev = vp->vpath->hldev;
7448
7449 vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
7450 __FILE__, __func__, __LINE__);
7451
7452 vxge_hal_trace_log_vpath_irq(
7453 "vpath_handle = 0x"VXGE_OS_STXFMT", msix_id = %d",
7454 (ptr_t) vpath_handle, msix_id);
7455
7456 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
7457 hldev->header.regh0,
7458 (u32) bVAL32(mBIT(hldev->msix_map[msix_id].vp_id), 0),
7459 &hldev->common_reg->clear_msix_mask_vect[
7460 hldev->msix_map[msix_id].int_num]);
7461
7462 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
7463 __FILE__, __func__, __LINE__);
7464 }
7465
7466 /*
7467 * vxge_hal_vpath_msix_mask_all - Mask all MSIX vectors for the vpath.
7468 * @vpath_handle: Virtual Path handle.
7469 *
7470 * The function masks all msix interrupt for the given vpath
7471 *
7472 */
7473 void
vxge_hal_vpath_msix_mask_all(vxge_hal_vpath_h vpath_handle)7474 vxge_hal_vpath_msix_mask_all(vxge_hal_vpath_h vpath_handle)
7475 {
7476 __hal_device_t *hldev;
7477 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
7478
7479 vxge_assert(vpath_handle != NULL);
7480
7481 hldev = vp->vpath->hldev;
7482
7483 vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
7484 __FILE__, __func__, __LINE__);
7485
7486 vxge_hal_trace_log_vpath_irq(
7487 "vpath_handle = 0x"VXGE_OS_STXFMT, (ptr_t) vpath_handle);
7488
7489 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
7490 hldev->header.regh0,
7491 (u32) bVAL32(mBIT(vp->vpath->vp_id), 0),
7492 &hldev->common_reg->set_msix_mask_all_vect);
7493
7494 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
7495 __FILE__, __func__, __LINE__);
7496
7497 }
7498
7499 /*
7500 * vxge_hal_vpath_msix_unmask_all - Unmask all MSIX vectors for the vpath.
7501 * @vpath_handle: Virtual Path handle.
7502 *
7503 * The function unmasks the msix interrupt for the given vpath
7504 *
7505 */
7506 void
vxge_hal_vpath_msix_unmask_all(vxge_hal_vpath_h vpath_handle)7507 vxge_hal_vpath_msix_unmask_all(vxge_hal_vpath_h vpath_handle)
7508 {
7509 __hal_device_t *hldev;
7510 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
7511
7512 vxge_assert(vpath_handle != NULL);
7513
7514 hldev = vp->vpath->hldev;
7515
7516 vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
7517 __FILE__, __func__, __LINE__);
7518
7519 vxge_hal_trace_log_vpath_irq("vpath_handle = 0x"VXGE_OS_STXFMT,
7520 (ptr_t) vpath_handle);
7521
7522 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
7523 hldev->header.regh0,
7524 (u32) bVAL32(mBIT(vp->vpath->vp_id), 0),
7525 &hldev->common_reg->clear_msix_mask_all_vect);
7526
7527 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
7528 __FILE__, __func__, __LINE__);
7529 }
7530
7531 /*
7532 * vxge_hal_vpath_poll_rx - Poll Rx Virtual Path for completed
7533 * descriptors and process the same.
7534 * @vpath_handle: Virtual Path ahandle.
7535 * @got_rx: Buffer to return the flag set if receive interrupt is occurred
7536 *
7537 * The function polls the Rx for the completed descriptors and calls
7538 * the upper-layer driver (ULD) via supplied completion callback.
7539 *
7540 * Returns: VXGE_HAL_OK, if the polling is completed successful.
7541 * VXGE_HAL_COMPLETIONS_REMAIN: There are still more completed
7542 * descriptors available which are yet to be processed.
7543 *
7544 * See also: vxge_hal_vpath_poll_tx()
7545 */
7546 vxge_hal_status_e
vxge_hal_vpath_poll_rx(vxge_hal_vpath_h vpath_handle,u32 * got_rx)7547 vxge_hal_vpath_poll_rx(vxge_hal_vpath_h vpath_handle, u32 *got_rx)
7548 {
7549 u8 t_code;
7550 vxge_hal_status_e status = VXGE_HAL_OK;
7551 vxge_hal_rxd_h first_rxdh;
7552 void *rxd_priv;
7553 __hal_device_t *hldev;
7554 __hal_virtualpath_t *vpath;
7555 __hal_ring_t *ring;
7556
7557 vxge_assert((vpath_handle != NULL) && (got_rx != NULL));
7558
7559 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
7560
7561 hldev = vpath->hldev;
7562
7563 vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
7564 __FILE__, __func__, __LINE__);
7565
7566 vxge_hal_trace_log_vpath_irq(
7567 "vpathh = 0x"VXGE_OS_STXFMT", got_rx = 0x"VXGE_OS_STXFMT,
7568 (ptr_t) vpath_handle, (ptr_t) got_rx);
7569
7570 ring = (__hal_ring_t *) vpath->ringh;
7571 if (ring == NULL) {
7572 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result: %d",
7573 __FILE__, __func__, __LINE__, status);
7574 return (status);
7575 }
7576
7577 ring->cmpl_cnt = 0;
7578 ring->channel.poll_bytes = 0;
7579 *got_rx = 0;
7580
7581 if ((status = vxge_hal_ring_rxd_next_completed(vpath_handle,
7582 &first_rxdh, &rxd_priv, &t_code)) == VXGE_HAL_OK) {
7583 if (ring->callback(vpath_handle, first_rxdh, rxd_priv,
7584 t_code, ring->channel.userdata) != VXGE_HAL_OK) {
7585 status = VXGE_HAL_COMPLETIONS_REMAIN;
7586 }
7587
7588 (*got_rx)++;
7589 }
7590
7591 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result: %d",
7592 __FILE__, __func__, __LINE__, status);
7593 return (status);
7594 }
7595
7596 /*
7597 * vxge_hal_vpath_poll_tx - Poll Tx for completed descriptors and process
7598 * the same.
7599 * @vpath_handle: Virtual Path ahandle.
7600 * @got_tx: Buffer to return the flag set if transmit interrupt is occurred
7601 *
7602 * The function polls the Tx for the completed descriptors and calls
7603 * the upper-layer driver (ULD) via supplied completion callback.
7604 *
7605 * Returns: VXGE_HAL_OK, if the polling is completed successful.
7606 * VXGE_HAL_COMPLETIONS_REMAIN: There are still more completed
7607 * descriptors available which are yet to be processed.
7608 *
7609 * See also: vxge_hal_vpath_poll_rx().
7610 */
7611 vxge_hal_status_e
vxge_hal_vpath_poll_tx(vxge_hal_vpath_h vpath_handle,u32 * got_tx)7612 vxge_hal_vpath_poll_tx(vxge_hal_vpath_h vpath_handle, u32 *got_tx)
7613 {
7614 vxge_hal_fifo_tcode_e t_code;
7615 vxge_hal_txdl_h first_txdlh;
7616 void *txdl_priv;
7617 __hal_virtualpath_t *vpath;
7618 __hal_fifo_t *fifo;
7619 __hal_device_t *hldev;
7620 vxge_hal_status_e status = VXGE_HAL_OK;
7621
7622 vxge_assert((vpath_handle != NULL) && (got_tx != NULL));
7623
7624 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
7625
7626 hldev = vpath->hldev;
7627
7628 vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
7629 __FILE__, __func__, __LINE__);
7630
7631 vxge_hal_trace_log_vpath_irq(
7632 "vpathh = 0x"VXGE_OS_STXFMT", got_tx = 0x"VXGE_OS_STXFMT,
7633 (ptr_t) vpath_handle, (ptr_t) got_tx);
7634
7635 fifo = (__hal_fifo_t *) vpath->fifoh;
7636 if (fifo == NULL) {
7637 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result: %d",
7638 __FILE__, __func__, __LINE__, status);
7639 return (status);
7640 }
7641
7642 fifo->channel.poll_bytes = 0;
7643 *got_tx = 0;
7644
7645 if ((status = vxge_hal_fifo_txdl_next_completed(vpath_handle,
7646 &first_txdlh, &txdl_priv, &t_code)) == VXGE_HAL_OK) {
7647 if (fifo->callback(vpath_handle, first_txdlh, txdl_priv,
7648 t_code, fifo->channel.userdata) != VXGE_HAL_OK) {
7649 status = VXGE_HAL_COMPLETIONS_REMAIN;
7650 }
7651
7652 (*got_tx)++;
7653 }
7654
7655 vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result: %d",
7656 __FILE__, __func__, __LINE__, status);
7657 return (status);
7658 }
7659
7660
7661 /*
7662 * __hal_vpath_mgmt_read
7663 * @hldev: HAL device
7664 * @vpath: Virtual path structure
7665 *
7666 * This routine reads the vpath_mgmt registers
7667 */
7668 vxge_hal_status_e
__hal_vpath_mgmt_read(__hal_device_t * hldev,__hal_virtualpath_t * vpath)7669 __hal_vpath_mgmt_read(
7670 __hal_device_t *hldev,
7671 __hal_virtualpath_t *vpath)
7672 {
7673 u32 i, mtu;
7674 u64 val64;
7675 vxge_hal_status_e status = VXGE_HAL_OK;
7676
7677 vxge_assert((hldev != NULL) && (vpath != NULL));
7678
7679 vxge_hal_trace_log_vpath("==> %s:%s:%d",
7680 __FILE__, __func__, __LINE__);
7681
7682 vxge_hal_trace_log_vpath(
7683 "hldev = 0x"VXGE_OS_STXFMT", vpath = 0x"VXGE_OS_STXFMT,
7684 (ptr_t) hldev, (ptr_t) vpath);
7685
7686 vpath->sess_grps_available = vxge_os_pio_mem_read64(hldev->header.pdev,
7687 hldev->header.regh0,
7688 &vpath->vpmgmt_reg->sgrp_own);
7689
7690 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
7691 hldev->header.regh0,
7692 &vpath->vpmgmt_reg->vpath_is_first);
7693
7694 vpath->is_first_vpath =
7695 (u32) VXGE_HAL_VPATH_IS_FIRST_GET_VPATH_IS_FIRST(val64);
7696
7697 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
7698 hldev->header.regh0,
7699 &vpath->vpmgmt_reg->tim_vpath_assignment);
7700
7701 vpath->bmap_root_assigned =
7702 (u32) VXGE_HAL_TIM_VPATH_ASSIGNMENT_GET_BMAP_ROOT(val64);
7703
7704 mtu = 0;
7705
7706 for (i = 0; i < VXGE_HAL_MAC_MAX_WIRE_PORTS; i++) {
7707
7708 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
7709 hldev->header.regh0,
7710 &vpath->vpmgmt_reg->rxmac_cfg0_port_vpmgmt_clone[i]);
7711
7712 if (mtu < (u32)
7713 VXGE_HAL_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN(
7714 val64)) {
7715 mtu = (u32)
7716 VXGE_HAL_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN(
7717 val64);
7718 }
7719 }
7720
7721 vpath->max_mtu = mtu + VXGE_HAL_MAC_HEADER_MAX_SIZE;
7722
7723 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
7724 hldev->header.regh0,
7725 &vpath->vpmgmt_reg->xmac_vsport_choices_vp);
7726
7727 vpath->vsport_choices =
7728 (u32) VXGE_HAL_XMAC_VSPORT_CHOICES_VP_GET_VSPORT_VECTOR(val64);
7729
7730 for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
7731
7732 if (val64 & mBIT(i))
7733 vpath->vsport_number = i;
7734
7735 }
7736
7737 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
7738 hldev->header.regh0,
7739 &vpath->vpmgmt_reg->xgmac_gen_status_vpmgmt_clone);
7740
7741 if (val64 & VXGE_HAL_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_OK) {
7742
7743 VXGE_HAL_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HAL_LINK_UP);
7744
7745 } else {
7746
7747 VXGE_HAL_DEVICE_LINK_STATE_SET(vpath->hldev,
7748 VXGE_HAL_LINK_DOWN);
7749
7750 }
7751
7752 if (val64 &
7753 VXGE_HAL_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_DATA_RATE) {
7754
7755 VXGE_HAL_DEVICE_DATA_RATE_SET(vpath->hldev,
7756 VXGE_HAL_DATA_RATE_10G);
7757
7758 } else {
7759
7760 VXGE_HAL_DEVICE_DATA_RATE_SET(vpath->hldev,
7761 VXGE_HAL_DATA_RATE_1G);
7762
7763 }
7764
7765 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
7766 __FILE__, __func__, __LINE__, status);
7767
7768 return (status);
7769 }
7770
7771 /*
7772 * __hal_vpath_reset_check - Check if resetting the vpath completed
7773 *
7774 * @vpath: Virtual Path
7775 *
7776 * This routine checks the vpath_rst_in_prog register to see if adapter
7777 * completed the reset process for the vpath
7778 */
7779 vxge_hal_status_e
__hal_vpath_reset_check(__hal_virtualpath_t * vpath)7780 __hal_vpath_reset_check(
7781 __hal_virtualpath_t *vpath)
7782 {
7783 __hal_device_t *hldev;
7784 vxge_hal_status_e status;
7785
7786 vxge_assert(vpath != NULL);
7787
7788 hldev = vpath->hldev;
7789
7790 vxge_hal_trace_log_vpath("==> %s:%s:%d",
7791 __FILE__, __func__, __LINE__);
7792
7793 vxge_hal_trace_log_vpath("vpath = 0x"VXGE_OS_STXFMT,
7794 (ptr_t) vpath);
7795
7796 status = vxge_hal_device_register_poll(hldev->header.pdev,
7797 hldev->header.regh0,
7798 &hldev->common_reg->vpath_rst_in_prog,
7799 0,
7800 VXGE_HAL_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(
7801 1 << (16 - vpath->vp_id)),
7802 WAIT_FACTOR * hldev->header.config.device_poll_millis);
7803
7804 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = %d",
7805 __FILE__, __func__, __LINE__, status);
7806
7807 return (status);
7808 }
7809
7810 /*
7811 * __hal_vpath_hw_reset
7812 * @hldev: Handle to the device object
7813 * @vp_id: Virtual Path Id
7814 *
7815 * This routine resets the vpath on the device
7816 */
7817 vxge_hal_status_e
__hal_vpath_hw_reset(vxge_hal_device_h devh,u32 vp_id)7818 __hal_vpath_hw_reset(vxge_hal_device_h devh, u32 vp_id)
7819 {
7820 u64 val64;
7821 vxge_hal_status_e status = VXGE_HAL_OK;
7822
7823 __hal_device_t *hldev;
7824
7825 vxge_assert(devh != NULL);
7826
7827 hldev = (__hal_device_t *) devh;
7828
7829 vxge_hal_trace_log_vpath("==> %s:%s:%d",
7830 __FILE__, __func__, __LINE__);
7831
7832 vxge_hal_trace_log_vpath("devh = 0x"VXGE_OS_STXFMT", vp_id = %d",
7833 (ptr_t) devh, vp_id);
7834
7835 val64 = VXGE_HAL_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(1 << (16 - vp_id));
7836 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
7837 hldev->header.regh0,
7838 (u32) bVAL32(val64, 0),
7839 &hldev->common_reg->cmn_rsthdlr_cfg0);
7840
7841 (void) __hal_ifmsg_wmsg_post(hldev,
7842 vp_id,
7843 VXGE_HAL_RTS_ACCESS_STEER_MSG_DEST_BROADCAST,
7844 VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_VPATH_RESET_BEGIN,
7845 0);
7846
7847 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
7848 __FILE__, __func__, __LINE__, status);
7849
7850 return (status);
7851 }
7852
7853 /*
7854 * __hal_vpath_sw_reset
7855 * @hldev: Handle to the device object
7856 * @vp_id: Virtual Path Id
7857 *
7858 * This routine resets the vpath structures
7859 */
7860 vxge_hal_status_e
__hal_vpath_sw_reset(vxge_hal_device_h devh,u32 vp_id)7861 __hal_vpath_sw_reset(
7862 vxge_hal_device_h devh,
7863 u32 vp_id)
7864 {
7865 vxge_hal_status_e status = VXGE_HAL_OK;
7866 __hal_device_t *hldev = (__hal_device_t *) devh;
7867 __hal_virtualpath_t *vpath;
7868
7869 vxge_assert(devh != NULL);
7870
7871 vpath = (__hal_virtualpath_t *) &hldev->virtual_paths[vp_id];
7872
7873 vxge_hal_trace_log_vpath("==> %s:%s:%d",
7874 __FILE__, __func__, __LINE__);
7875
7876 vxge_hal_trace_log_vpath("devh = 0x"VXGE_OS_STXFMT", vp_id = %d",
7877 (ptr_t) devh, vp_id);
7878
7879 if (vpath->ringh) {
7880
7881 status = __hal_ring_reset(vpath->ringh);
7882
7883 if (status != VXGE_HAL_OK) {
7884 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
7885 __FILE__, __func__, __LINE__, status);
7886 return (status);
7887 }
7888 }
7889
7890 if (vpath->fifoh) {
7891
7892 status = __hal_fifo_reset(vpath->fifoh);
7893
7894 if (status != VXGE_HAL_OK) {
7895 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
7896 __FILE__, __func__, __LINE__, status);
7897 return (status);
7898 }
7899 }
7900
7901 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
7902 __FILE__, __func__, __LINE__, status);
7903 return (VXGE_HAL_OK);
7904 }
7905
7906 /*
7907 * vxge_hal_vpath_enable
7908 * @vpath_handle: Handle to the vpath object
7909 *
7910 * This routine clears the vpath reset and puts vpath in service
7911 */
7912 vxge_hal_status_e
vxge_hal_vpath_enable(vxge_hal_vpath_h vpath_handle)7913 vxge_hal_vpath_enable(
7914 vxge_hal_vpath_h vpath_handle)
7915 {
7916 u64 val64;
7917 vxge_hal_status_e status = VXGE_HAL_OK;
7918 __hal_device_t *hldev;
7919 __hal_virtualpath_t *vpath;
7920
7921 vxge_assert(vpath_handle != NULL);
7922
7923 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
7924
7925 hldev = vpath->hldev;
7926
7927 vxge_hal_trace_log_vpath("==> %s:%s:%d",
7928 __FILE__, __func__, __LINE__);
7929
7930 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
7931 (ptr_t) vpath_handle);
7932
7933 val64 = VXGE_HAL_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET(
7934 1 << (16 - vpath->vp_id));
7935
7936 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
7937 hldev->header.regh0,
7938 (u32) bVAL32(val64, 0),
7939 &hldev->common_reg->cmn_rsthdlr_cfg1);
7940
7941 (void) __hal_ifmsg_wmsg_post(hldev,
7942 vpath->vp_id,
7943 VXGE_HAL_RTS_ACCESS_STEER_MSG_DEST_BROADCAST,
7944 VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_VPATH_RESET_END,
7945 0);
7946
7947 VXGE_HAL_RING_POST_DOORBELL(vpath_handle, vpath->ringh);
7948
7949 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
7950 __FILE__, __func__, __LINE__, status);
7951
7952 return (status);
7953 }
7954
7955
7956 /*
7957 * __hal_vpath_prc_configure
7958 * @hldev: Handle to the device object
7959 * @vp_id: Virtual Path Id
7960 *
7961 * This routine configures the prc registers of virtual path
7962 * using the config passed
7963 */
7964 vxge_hal_status_e
__hal_vpath_prc_configure(vxge_hal_device_h devh,u32 vp_id)7965 __hal_vpath_prc_configure(
7966 vxge_hal_device_h devh,
7967 u32 vp_id)
7968 {
7969 u64 val64;
7970 vxge_hal_status_e status = VXGE_HAL_OK;
7971 __hal_device_t *hldev = (__hal_device_t *) devh;
7972 __hal_virtualpath_t *vpath;
7973 vxge_hal_vp_config_t *vp_config;
7974
7975 vxge_assert(devh != NULL);
7976
7977 vpath = (__hal_virtualpath_t *) &hldev->virtual_paths[vp_id];
7978
7979 vxge_hal_trace_log_vpath("==> %s:%s:%d",
7980 __FILE__, __func__, __LINE__);
7981
7982 vxge_hal_trace_log_vpath("devh = 0x"VXGE_OS_STXFMT", vp_id = %d",
7983 (ptr_t) devh, vp_id);
7984
7985 vp_config = vpath->vp_config;
7986
7987 if (vp_config->ring.enable == VXGE_HAL_RING_DISABLE) {
7988 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
7989 __FILE__, __func__, __LINE__, status);
7990 return (status);
7991 }
7992
7993 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
7994 hldev->header.regh0,
7995 &vpath->vp_reg->prc_cfg1);
7996
7997 if (vp_config->ring.rx_timer_val !=
7998 VXGE_HAL_RING_USE_FLASH_DEFAULT_RX_TIMER_VAL) {
7999 val64 &= ~VXGE_HAL_PRC_CFG1_RX_TIMER_VAL(0x1fffffff);
8000 val64 |= VXGE_HAL_PRC_CFG1_RX_TIMER_VAL(
8001 vp_config->ring.rx_timer_val);
8002 }
8003
8004 val64 |= VXGE_HAL_PRC_CFG1_RTI_TINT_DISABLE;
8005
8006 if (vp_config->ring.greedy_return !=
8007 VXGE_HAL_RING_GREEDY_RETURN_USE_FLASH_DEFAULT) {
8008 if (vp_config->ring.greedy_return)
8009 val64 |= VXGE_HAL_PRC_CFG1_GREEDY_RETURN;
8010 else
8011 val64 &= ~VXGE_HAL_PRC_CFG1_GREEDY_RETURN;
8012 }
8013
8014 if (vp_config->ring.rx_timer_ci !=
8015 VXGE_HAL_RING_RX_TIMER_CI_USE_FLASH_DEFAULT) {
8016 if (vp_config->ring.rx_timer_ci)
8017 val64 |= VXGE_HAL_PRC_CFG1_RX_TIMER_CI;
8018 else
8019 val64 &= ~VXGE_HAL_PRC_CFG1_RX_TIMER_CI;
8020 }
8021
8022 vxge_os_pio_mem_write64(hldev->header.pdev,
8023 hldev->header.regh0,
8024 val64,
8025 &vpath->vp_reg->prc_cfg1);
8026
8027 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8028 hldev->header.regh0,
8029 &vpath->vp_reg->prc_cfg7);
8030
8031 if (vpath->vp_config->ring.scatter_mode !=
8032 VXGE_HAL_RING_SCATTER_MODE_USE_FLASH_DEFAULT) {
8033
8034 val64 &= ~VXGE_HAL_PRC_CFG7_SCATTER_MODE(0x3);
8035
8036 switch (vpath->vp_config->ring.scatter_mode) {
8037 case VXGE_HAL_RING_SCATTER_MODE_A:
8038 val64 |= VXGE_HAL_PRC_CFG7_SCATTER_MODE(
8039 VXGE_HAL_PRC_CFG7_SCATTER_MODE_A);
8040 break;
8041 case VXGE_HAL_RING_SCATTER_MODE_B:
8042 val64 |= VXGE_HAL_PRC_CFG7_SCATTER_MODE(
8043 VXGE_HAL_PRC_CFG7_SCATTER_MODE_B);
8044 break;
8045 case VXGE_HAL_RING_SCATTER_MODE_C:
8046 val64 |= VXGE_HAL_PRC_CFG7_SCATTER_MODE(
8047 VXGE_HAL_PRC_CFG7_SCATTER_MODE_C);
8048 break;
8049 }
8050 }
8051
8052 vxge_os_pio_mem_write64(hldev->header.pdev,
8053 hldev->header.regh0,
8054 val64,
8055 &vpath->vp_reg->prc_cfg7);
8056
8057 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8058 hldev->header.regh0,
8059 &vpath->vp_reg->prc_cfg6);
8060
8061 if (vpath->vp_config->ring.post_mode !=
8062 VXGE_HAL_RING_POST_MODE_USE_FLASH_DEFAULT) {
8063
8064 if (vpath->vp_config->ring.post_mode ==
8065 VXGE_HAL_RING_POST_MODE_DOORBELL)
8066 val64 |= VXGE_HAL_PRC_CFG6_DOORBELL_MODE_EN;
8067 else
8068 val64 &= ~VXGE_HAL_PRC_CFG6_DOORBELL_MODE_EN;
8069
8070 } else {
8071
8072 vpath->vp_config->ring.post_mode =
8073 ((val64 & VXGE_HAL_PRC_CFG6_DOORBELL_MODE_EN) ?
8074 VXGE_HAL_RING_POST_MODE_DOORBELL :
8075 VXGE_HAL_RING_POST_MODE_LEGACY);
8076
8077 }
8078
8079 vxge_os_pio_mem_write64(hldev->header.pdev,
8080 hldev->header.regh0,
8081 val64,
8082 &vpath->vp_reg->prc_cfg6);
8083
8084 vxge_os_pio_mem_write64(hldev->header.pdev,
8085 hldev->header.regh0,
8086 VXGE_HAL_PRC_CFG5_RXD0_ADD(
8087 __hal_ring_first_block_address_get(vpath->ringh) >> 3),
8088 &vpath->vp_reg->prc_cfg5);
8089
8090 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8091 hldev->header.regh0,
8092 &vpath->vp_reg->prc_cfg4);
8093
8094 val64 |= VXGE_HAL_PRC_CFG4_IN_SVC;
8095
8096 val64 &= ~VXGE_HAL_PRC_CFG4_RING_MODE(0x3);
8097
8098 if (vp_config->ring.buffer_mode == VXGE_HAL_RING_RXD_BUFFER_MODE_1) {
8099 val64 |= VXGE_HAL_PRC_CFG4_RING_MODE(
8100 VXGE_HAL_PRC_CFG4_RING_MODE_ONE_BUFFER);
8101 } else {
8102 if (vp_config->ring.buffer_mode ==
8103 VXGE_HAL_RING_RXD_BUFFER_MODE_3) {
8104 val64 |= VXGE_HAL_PRC_CFG4_RING_MODE(
8105 VXGE_HAL_PRC_CFG4_RING_MODE_THREE_BUFFER);
8106 } else {
8107 val64 |= VXGE_HAL_PRC_CFG4_RING_MODE(
8108 VXGE_HAL_PRC_CFG4_RING_MODE_FIVE_BUFFER);
8109 }
8110 }
8111
8112 if (vp_config->ring.no_snoop_bits !=
8113 VXGE_HAL_RING_NO_SNOOP_USE_FLASH_DEFAULT) {
8114
8115 val64 &= ~(VXGE_HAL_PRC_CFG4_FRM_NO_SNOOP |
8116 VXGE_HAL_PRC_CFG4_RXD_NO_SNOOP);
8117
8118 if (vp_config->ring.no_snoop_bits ==
8119 VXGE_HAL_RING_NO_SNOOP_RXD) {
8120 val64 |= VXGE_HAL_PRC_CFG4_RXD_NO_SNOOP;
8121 } else {
8122 if (vp_config->ring.no_snoop_bits ==
8123 VXGE_HAL_RING_NO_SNOOP_FRM) {
8124 val64 |= VXGE_HAL_PRC_CFG4_FRM_NO_SNOOP;
8125 } else {
8126 if (vp_config->ring.no_snoop_bits ==
8127 VXGE_HAL_RING_NO_SNOOP_ALL) {
8128 val64 |= VXGE_HAL_PRC_CFG4_FRM_NO_SNOOP;
8129 val64 |= VXGE_HAL_PRC_CFG4_RXD_NO_SNOOP;
8130 }
8131 }
8132 }
8133
8134 }
8135
8136 if (hldev->header.config.rth_en == VXGE_HAL_RTH_DISABLE)
8137 val64 |= VXGE_HAL_PRC_CFG4_RTH_DISABLE;
8138 else
8139 val64 &= ~VXGE_HAL_PRC_CFG4_RTH_DISABLE;
8140
8141 val64 |= VXGE_HAL_PRC_CFG4_SIGNAL_BENIGN_OVFLW;
8142
8143 val64 |= VXGE_HAL_PRC_CFG4_BIMODAL_INTERRUPT;
8144
8145 if (vp_config->ring.backoff_interval_us !=
8146 VXGE_HAL_USE_FLASH_DEFAULT_BACKOFF_INTERVAL_US) {
8147
8148 val64 &= ~VXGE_HAL_PRC_CFG4_BACKOFF_INTERVAL(0xffffff);
8149
8150 val64 |= VXGE_HAL_PRC_CFG4_BACKOFF_INTERVAL(
8151 vp_config->ring.backoff_interval_us * 1000 / 4);
8152
8153 }
8154
8155 vxge_os_pio_mem_write64(hldev->header.pdev,
8156 hldev->header.regh0,
8157 val64,
8158 &vpath->vp_reg->prc_cfg4);
8159
8160 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
8161 __FILE__, __func__, __LINE__, status);
8162 return (status);
8163 }
8164
8165 /*
8166 * __hal_vpath_kdfc_configure
8167 * @hldev: Handle to the device object
8168 * @vp_id: Virtual Path Id
8169 *
8170 * This routine configures the kdfc registers of virtual path
8171 * using the config passed
8172 */
8173 vxge_hal_status_e
__hal_vpath_kdfc_configure(vxge_hal_device_h devh,u32 vp_id)8174 __hal_vpath_kdfc_configure(
8175 vxge_hal_device_h devh,
8176 u32 vp_id)
8177 {
8178 u64 val64;
8179 u64 vpath_stride;
8180 u64 fifo_stride;
8181 vxge_hal_status_e status = VXGE_HAL_OK;
8182 __hal_device_t *hldev = (__hal_device_t *) devh;
8183 __hal_virtualpath_t *vpath;
8184
8185 vxge_assert(devh != NULL);
8186
8187 vpath = (__hal_virtualpath_t *) &hldev->virtual_paths[vp_id];
8188
8189 vxge_hal_trace_log_vpath("==> %s:%s:%d",
8190 __FILE__, __func__, __LINE__);
8191
8192 vxge_hal_trace_log_vpath("devh = 0x"VXGE_OS_STXFMT", vp_id = %d",
8193 (ptr_t) devh, vp_id);
8194
8195 status = __hal_kdfc_swapper_set((vxge_hal_device_t *) hldev, vp_id);
8196
8197
8198 if (status != VXGE_HAL_OK) {
8199
8200 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
8201 __FILE__, __func__, __LINE__, status);
8202 return (status);
8203
8204 }
8205
8206 if ((vpath->vp_config->ring.post_mode ==
8207 VXGE_HAL_RING_POST_MODE_DOORBELL) &&
8208 (vxge_hal_device_check_id(devh) == VXGE_HAL_CARD_TITAN_1)) {
8209
8210 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8211 hldev->header.regh0,
8212 &vpath->vp_reg->rxdmem_size);
8213
8214 vpath->rxd_mem_size =
8215 (u32) VXGE_HAL_RXDMEM_SIZE_PRC_RXDMEM_SIZE(val64) * 8;
8216
8217 } else {
8218
8219 vpath->rxd_mem_size = (VXGE_HAL_MAX_RING_LENGTH /
8220 vxge_hal_ring_rxds_per_block_get(
8221 vpath->vp_config->ring.buffer_mode)) *
8222 VXGE_OS_HOST_PAGE_SIZE;
8223
8224 }
8225
8226 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8227 hldev->header.regh0,
8228 &vpath->vp_reg->kdfc_drbl_triplet_total);
8229
8230 vpath->max_kdfc_db =
8231 (u32) VXGE_HAL_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE(val64 + 1) / 2;
8232
8233 vpath->max_ofl_db = 0;
8234
8235 if (vpath->vp_config->fifo.enable == VXGE_HAL_FIFO_ENABLE) {
8236
8237 vpath->max_nofl_db = vpath->max_kdfc_db - 1;
8238 vpath->max_msg_db = 0;
8239
8240 if (vpath->max_nofl_db < vpath->vp_config->fifo.fifo_length) {
8241
8242 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
8243 __FILE__, __func__, __LINE__,
8244 VXGE_HAL_BADCFG_FIFO_LENGTH);
8245 return (VXGE_HAL_BADCFG_FIFO_LENGTH);
8246 }
8247
8248 } else {
8249
8250 vpath->max_nofl_db = 0;
8251 vpath->max_msg_db = vpath->max_kdfc_db;
8252 }
8253
8254 val64 = 0;
8255
8256 if (vpath->max_nofl_db)
8257 val64 |= VXGE_HAL_KDFC_FIFO_TRPL_PARTITION_LENGTH_0(
8258 (vpath->max_nofl_db * 2) - 1);
8259
8260 if (vpath->max_msg_db)
8261 val64 |= VXGE_HAL_KDFC_FIFO_TRPL_PARTITION_LENGTH_1(
8262 (vpath->max_msg_db * 2) - 1);
8263
8264 vxge_os_pio_mem_write64(hldev->header.pdev,
8265 hldev->header.regh0,
8266 val64,
8267 &vpath->vp_reg->kdfc_fifo_trpl_partition);
8268
8269 vxge_os_pio_mem_write64(hldev->header.pdev,
8270 hldev->header.regh0,
8271 VXGE_HAL_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE,
8272 &vpath->vp_reg->kdfc_fifo_trpl_ctrl);
8273
8274 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8275 hldev->header.regh0,
8276 &vpath->vp_reg->kdfc_trpl_fifo_0_ctrl);
8277
8278 if (vpath->max_nofl_db) {
8279
8280 val64 &= ~(VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_MODE(0x3) |
8281 VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_SELECT(0xFF));
8282
8283 val64 |= VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_MODE(
8284 VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY) |
8285 #if !defined(VXGE_OS_HOST_BIG_ENDIAN)
8286 VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN |
8287 #endif
8288 VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_SELECT(0);
8289
8290 if (vpath->vp_config->no_snoop !=
8291 VXGE_HAL_VPATH_NO_SNOOP_USE_FLASH_DEFAULT) {
8292 if (vpath->vp_config->no_snoop)
8293 val64 |=
8294 VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_NO_SNOOP;
8295 else
8296 val64 &=
8297 ~VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_NO_SNOOP;
8298 }
8299 }
8300
8301 vxge_os_pio_mem_write64(hldev->header.pdev,
8302 hldev->header.regh0,
8303 val64,
8304 &vpath->vp_reg->kdfc_trpl_fifo_0_ctrl);
8305
8306 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8307 hldev->header.regh0,
8308 &vpath->vp_reg->kdfc_trpl_fifo_1_ctrl);
8309
8310 if (vpath->max_msg_db) {
8311
8312 val64 &= ~(VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_MODE(0x3) |
8313 VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_SELECT(0xFF));
8314
8315 val64 |= VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_MODE(
8316 VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_MODE_MESSAGES_ONLY) |
8317 #if !defined(VXGE_OS_HOST_BIG_ENDIAN)
8318 VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_SWAP_EN |
8319 #endif
8320 VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_SELECT(0);
8321
8322 if (vpath->vp_config->no_snoop !=
8323 VXGE_HAL_VPATH_NO_SNOOP_USE_FLASH_DEFAULT) {
8324 if (vpath->vp_config->no_snoop)
8325 val64 |=
8326 VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_NO_SNOOP;
8327 else
8328 val64 &=
8329 ~VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_NO_SNOOP;
8330 }
8331 }
8332
8333 vxge_os_pio_mem_write64(hldev->header.pdev,
8334 hldev->header.regh0,
8335 val64,
8336 &vpath->vp_reg->kdfc_trpl_fifo_1_ctrl);
8337
8338 vxge_os_pio_mem_write64(hldev->header.pdev,
8339 hldev->header.regh0,
8340 (u64) 0,
8341 &vpath->vp_reg->kdfc_trpl_fifo_2_ctrl);
8342
8343 vxge_os_pio_mem_write64(hldev->header.pdev,
8344 hldev->header.regh0,
8345 (u64) 0,
8346 &vpath->vp_reg->kdfc_trpl_fifo_0_wb_address);
8347
8348 vxge_os_pio_mem_write64(hldev->header.pdev,
8349 hldev->header.regh0,
8350 (u64) 0,
8351 &vpath->vp_reg->kdfc_trpl_fifo_1_wb_address);
8352
8353 vxge_os_pio_mem_write64(hldev->header.pdev,
8354 hldev->header.regh0,
8355 (u64) 0,
8356 &vpath->vp_reg->kdfc_trpl_fifo_2_wb_address);
8357
8358
8359 vxge_os_wmb();
8360
8361 vpath_stride = vxge_os_pio_mem_read64(hldev->header.pdev,
8362 hldev->header.regh0,
8363 &hldev->toc_reg->toc_kdfc_vpath_stride);
8364
8365 fifo_stride = vxge_os_pio_mem_read64(hldev->header.pdev,
8366 hldev->header.regh0,
8367 &hldev->toc_reg->toc_kdfc_fifo_stride);
8368
8369 vpath->nofl_db = (__hal_non_offload_db_wrapper_t *) ((void *)(hldev->kdfc +
8370 (vp_id * VXGE_HAL_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE(
8371 vpath_stride))));
8372
8373 vpath->msg_db = (__hal_messaging_db_wrapper_t *) ((void *)(hldev->kdfc +
8374 (vp_id * VXGE_HAL_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE(
8375 vpath_stride)) +
8376 VXGE_HAL_TOC_KDFC_FIFO_STRIDE_GET_TOC_KDFC_FIFO_STRIDE(
8377 fifo_stride)));
8378
8379 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
8380 __FILE__, __func__, __LINE__, status);
8381 return (status);
8382 }
8383
8384 /*
8385 * __hal_vpath_mac_configure
8386 * @hldev: Handle to the device object
8387 * @vp_id: Virtual Path Id
8388 *
8389 * This routine configures the mac of virtual path using the config passed
8390 */
8391 vxge_hal_status_e
__hal_vpath_mac_configure(vxge_hal_device_h devh,u32 vp_id)8392 __hal_vpath_mac_configure(
8393 vxge_hal_device_h devh,
8394 u32 vp_id)
8395 {
8396 u64 val64;
8397 vxge_hal_status_e status = VXGE_HAL_OK;
8398 __hal_device_t *hldev = (__hal_device_t *) devh;
8399 __hal_virtualpath_t *vpath;
8400 vxge_hal_vp_config_t *vp_config;
8401
8402 vxge_assert(devh != NULL);
8403
8404 vpath = (__hal_virtualpath_t *) &hldev->virtual_paths[vp_id];
8405
8406 vxge_hal_trace_log_vpath("==> %s:%s:%d",
8407 __FILE__, __func__, __LINE__);
8408
8409 vxge_hal_trace_log_vpath("devh = 0x"VXGE_OS_STXFMT", vp_id = %d",
8410 (ptr_t) devh, vp_id);
8411
8412 vp_config = vpath->vp_config;
8413
8414 vxge_os_pio_mem_write64(hldev->header.pdev,
8415 hldev->header.regh0,
8416 VXGE_HAL_XMAC_VSPORT_CHOICE_VSPORT_NUMBER(vpath->vsport_number),
8417 &vpath->vp_reg->xmac_vsport_choice);
8418
8419 if (vp_config->ring.enable == VXGE_HAL_RING_ENABLE) {
8420
8421 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8422 hldev->header.regh0,
8423 &vpath->vp_reg->xmac_rpa_vcfg);
8424
8425 if (vp_config->rpa_ipv4_tcp_incl_ph !=
8426 VXGE_HAL_VPATH_RPA_IPV4_TCP_INCL_PH_USE_FLASH_DEFAULT) {
8427 if (vp_config->rpa_ipv4_tcp_incl_ph)
8428 val64 |=
8429 VXGE_HAL_XMAC_RPA_VCFG_IPV4_TCP_INCL_PH;
8430 else
8431 val64 &=
8432 ~VXGE_HAL_XMAC_RPA_VCFG_IPV4_TCP_INCL_PH;
8433 }
8434
8435 if (vp_config->rpa_ipv6_tcp_incl_ph !=
8436 VXGE_HAL_VPATH_RPA_IPV6_TCP_INCL_PH_USE_FLASH_DEFAULT) {
8437 if (vp_config->rpa_ipv6_tcp_incl_ph)
8438 val64 |=
8439 VXGE_HAL_XMAC_RPA_VCFG_IPV6_TCP_INCL_PH;
8440 else
8441 val64 &=
8442 ~VXGE_HAL_XMAC_RPA_VCFG_IPV6_TCP_INCL_PH;
8443 }
8444
8445 if (vp_config->rpa_ipv4_udp_incl_ph !=
8446 VXGE_HAL_VPATH_RPA_IPV4_UDP_INCL_PH_USE_FLASH_DEFAULT) {
8447 if (vp_config->rpa_ipv4_udp_incl_ph)
8448 val64 |=
8449 VXGE_HAL_XMAC_RPA_VCFG_IPV4_UDP_INCL_PH;
8450 else
8451 val64 &=
8452 ~VXGE_HAL_XMAC_RPA_VCFG_IPV4_UDP_INCL_PH;
8453 }
8454
8455 if (vp_config->rpa_ipv6_udp_incl_ph !=
8456 VXGE_HAL_VPATH_RPA_IPV6_UDP_INCL_PH_USE_FLASH_DEFAULT) {
8457 if (vp_config->rpa_ipv6_udp_incl_ph)
8458 val64 |=
8459 VXGE_HAL_XMAC_RPA_VCFG_IPV6_UDP_INCL_PH;
8460 else
8461 val64 &=
8462 ~VXGE_HAL_XMAC_RPA_VCFG_IPV6_UDP_INCL_PH;
8463 }
8464
8465 if (vp_config->rpa_l4_incl_cf !=
8466 VXGE_HAL_VPATH_RPA_L4_INCL_CF_USE_FLASH_DEFAULT) {
8467 if (vp_config->rpa_l4_incl_cf)
8468 val64 |= VXGE_HAL_XMAC_RPA_VCFG_L4_INCL_CF;
8469 else
8470 val64 &= ~VXGE_HAL_XMAC_RPA_VCFG_L4_INCL_CF;
8471 }
8472
8473 if (vp_config->rpa_strip_vlan_tag !=
8474 VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) {
8475 if (vp_config->rpa_strip_vlan_tag)
8476 val64 |= VXGE_HAL_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
8477 else
8478 val64 &= ~VXGE_HAL_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
8479 }
8480
8481 vxge_os_pio_mem_write64(hldev->header.pdev,
8482 hldev->header.regh0,
8483 val64,
8484 &vpath->vp_reg->xmac_rpa_vcfg);
8485
8486 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8487 hldev->header.regh0,
8488 &vpath->vp_reg->rxmac_vcfg0);
8489
8490 if (vp_config->mtu !=
8491 VXGE_HAL_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) {
8492 val64 &= ~VXGE_HAL_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
8493 if ((vp_config->mtu + VXGE_HAL_MAC_HEADER_MAX_SIZE) <
8494 vpath->max_mtu)
8495 val64 |= VXGE_HAL_RXMAC_VCFG0_RTS_MAX_FRM_LEN(
8496 vp_config->mtu +
8497 VXGE_HAL_MAC_HEADER_MAX_SIZE);
8498 else
8499 val64 |= VXGE_HAL_RXMAC_VCFG0_RTS_MAX_FRM_LEN(
8500 vpath->max_mtu);
8501 }
8502
8503 if (vp_config->rpa_ucast_all_addr_en !=
8504 VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_USE_FLASH_DEFAULT) {
8505 if (vp_config->rpa_ucast_all_addr_en)
8506 val64 |= VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN;
8507 else
8508 val64 &=
8509 ~VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN;
8510 } else {
8511 if (val64 & VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN) {
8512 vp_config->rpa_ucast_all_addr_en =
8513 VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_ENABLE;
8514 } else {
8515 vp_config->rpa_ucast_all_addr_en =
8516 VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_DISABLE;
8517 }
8518 }
8519
8520 if (vp_config->rpa_mcast_all_addr_en !=
8521 VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_USE_FLASH_DEFAULT) {
8522 if (vp_config->rpa_mcast_all_addr_en)
8523 val64 |= VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN;
8524 else
8525 val64 &=
8526 ~VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN;
8527 } else {
8528 if (val64 & VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN) {
8529 vp_config->rpa_mcast_all_addr_en =
8530 VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_ENABLE;
8531 } else {
8532 vp_config->rpa_mcast_all_addr_en =
8533 VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_DISABLE;
8534 }
8535 }
8536
8537 if (vp_config->rpa_bcast_en !=
8538 VXGE_HAL_VPATH_RPA_BCAST_USE_FLASH_DEFAULT) {
8539 if (vp_config->rpa_bcast_en)
8540 val64 |= VXGE_HAL_RXMAC_VCFG0_BCAST_EN;
8541 else
8542 val64 &= ~VXGE_HAL_RXMAC_VCFG0_BCAST_EN;
8543 } else {
8544 if (val64 & VXGE_HAL_RXMAC_VCFG0_BCAST_EN) {
8545 vp_config->rpa_bcast_en =
8546 VXGE_HAL_VPATH_RPA_BCAST_ENABLE;
8547 } else {
8548 vp_config->rpa_bcast_en =
8549 VXGE_HAL_VPATH_RPA_BCAST_DISABLE;
8550 }
8551 }
8552
8553 if (vp_config->rpa_all_vid_en !=
8554 VXGE_HAL_VPATH_RPA_ALL_VID_USE_FLASH_DEFAULT) {
8555 if (vp_config->rpa_all_vid_en)
8556 val64 |= VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN;
8557 else
8558 val64 &= ~VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN;
8559 } else {
8560 if (val64 & VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN) {
8561 vp_config->rpa_all_vid_en =
8562 VXGE_HAL_VPATH_RPA_ALL_VID_ENABLE;
8563 } else {
8564 vp_config->rpa_all_vid_en =
8565 VXGE_HAL_VPATH_RPA_ALL_VID_DISABLE;
8566 }
8567 }
8568
8569 if (vpath->promisc_en == VXGE_HAL_VP_PROMISC_ENABLE) {
8570 val64 |= VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN |
8571 VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN |
8572 VXGE_HAL_RXMAC_VCFG0_BCAST_EN |
8573 VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN;
8574 }
8575
8576 vxge_os_pio_mem_write64(hldev->header.pdev,
8577 hldev->header.regh0,
8578 val64,
8579 &vpath->vp_reg->rxmac_vcfg0);
8580
8581 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8582 hldev->header.regh0,
8583 &vpath->vp_reg->rxmac_vcfg1);
8584
8585 val64 &= ~(VXGE_HAL_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(0x3) |
8586 VXGE_HAL_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE);
8587
8588 if (hldev->header.config.rth_it_type ==
8589 VXGE_HAL_RTH_IT_TYPE_MULTI_IT) {
8590 val64 |=
8591 VXGE_HAL_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(0x2) |
8592 VXGE_HAL_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE;
8593 }
8594
8595 if (vp_config->vp_queue_l2_flow !=
8596 VXGE_HAL_VPATH_VP_Q_L2_FLOW_USE_FLASH_DEFAULT) {
8597 if (vp_config->vp_queue_l2_flow)
8598 val64 |= VXGE_HAL_RXMAC_VCFG1_CONTRIB_L2_FLOW;
8599 else
8600 val64 &= ~VXGE_HAL_RXMAC_VCFG1_CONTRIB_L2_FLOW;
8601 }
8602
8603 vxge_os_pio_mem_write64(hldev->header.pdev,
8604 hldev->header.regh0,
8605 val64,
8606 &vpath->vp_reg->rxmac_vcfg1);
8607
8608 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8609 hldev->header.regh0,
8610 &vpath->vp_reg->fau_rpa_vcfg);
8611
8612 if (vp_config->rpa_l4_comp_csum !=
8613 VXGE_HAL_VPATH_RPA_L4_COMP_CSUM_USE_FLASH_DEFAULT) {
8614 if (vp_config->rpa_l4_comp_csum)
8615 val64 |= VXGE_HAL_FAU_RPA_VCFG_L4_COMP_CSUM;
8616 else
8617 val64 &= ~VXGE_HAL_FAU_RPA_VCFG_L4_COMP_CSUM;
8618 }
8619
8620 if (vp_config->rpa_l3_incl_cf !=
8621 VXGE_HAL_VPATH_RPA_L3_INCL_CF_USE_FLASH_DEFAULT) {
8622 if (vp_config->rpa_l3_incl_cf)
8623 val64 |= VXGE_HAL_FAU_RPA_VCFG_L3_INCL_CF;
8624 else
8625 val64 &= ~VXGE_HAL_FAU_RPA_VCFG_L3_INCL_CF;
8626 }
8627
8628 if (vp_config->rpa_l3_comp_csum !=
8629 VXGE_HAL_VPATH_RPA_L3_COMP_CSUM_USE_FLASH_DEFAULT) {
8630 if (vp_config->rpa_l3_comp_csum)
8631 val64 |= VXGE_HAL_FAU_RPA_VCFG_L3_COMP_CSUM;
8632 else
8633 val64 &= ~VXGE_HAL_FAU_RPA_VCFG_L3_COMP_CSUM;
8634 }
8635
8636 vxge_os_pio_mem_write64(hldev->header.pdev,
8637 hldev->header.regh0,
8638 val64,
8639 &vpath->vp_reg->fau_rpa_vcfg);
8640 }
8641
8642 if (vp_config->fifo.enable == VXGE_HAL_FIFO_ENABLE) {
8643
8644 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8645 hldev->header.regh0,
8646 &vpath->vp_reg->tpa_cfg);
8647
8648 if (vp_config->tpa_ignore_frame_error !=
8649 VXGE_HAL_VPATH_TPA_IGNORE_FRAME_ERROR_USE_FLASH_DEFAULT) {
8650 if (vp_config->tpa_ignore_frame_error)
8651 val64 |= VXGE_HAL_TPA_CFG_IGNORE_FRAME_ERR;
8652 else
8653 val64 &= ~VXGE_HAL_TPA_CFG_IGNORE_FRAME_ERR;
8654 }
8655
8656 if (vp_config->tpa_ipv6_keep_searching !=
8657 VXGE_HAL_VPATH_TPA_IPV6_KEEP_SEARCHING_USE_FLASH_DEFAULT) {
8658 if (vp_config->tpa_ipv6_keep_searching)
8659 val64 |= VXGE_HAL_TPA_CFG_IPV6_STOP_SEARCHING;
8660 else
8661 val64 &= ~VXGE_HAL_TPA_CFG_IPV6_STOP_SEARCHING;
8662 }
8663
8664 if (vp_config->tpa_l4_pshdr_present !=
8665 VXGE_HAL_VPATH_TPA_L4_PSHDR_PRESENT_USE_FLASH_DEFAULT) {
8666 if (vp_config->tpa_l4_pshdr_present)
8667 val64 |= VXGE_HAL_TPA_CFG_L4_PSHDR_PRESENT;
8668 else
8669 val64 &= ~VXGE_HAL_TPA_CFG_L4_PSHDR_PRESENT;
8670 }
8671
8672 if (vp_config->tpa_support_mobile_ipv6_hdrs !=
8673 VXGE_HAL_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS_DEFAULT) {
8674 if (vp_config->tpa_support_mobile_ipv6_hdrs)
8675 val64 |=
8676 VXGE_HAL_TPA_CFG_SUPPORT_MOBILE_IPV6_HDRS;
8677 else
8678 val64 &=
8679 ~VXGE_HAL_TPA_CFG_SUPPORT_MOBILE_IPV6_HDRS;
8680 }
8681
8682 vxge_os_pio_mem_write64(hldev->header.pdev,
8683 hldev->header.regh0,
8684 val64,
8685 &vpath->vp_reg->tpa_cfg);
8686
8687 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8688 hldev->header.regh0,
8689 &vpath->vp_reg->tx_protocol_assist_cfg);
8690
8691 if (vp_config->tpa_lsov2_en !=
8692 VXGE_HAL_VPATH_TPA_LSOV2_EN_USE_FLASH_DEFAULT) {
8693 if (vp_config->tpa_lsov2_en)
8694 val64 |=
8695 VXGE_HAL_TX_PROTOCOL_ASSIST_CFG_LSOV2_EN;
8696 else
8697 val64 &=
8698 ~VXGE_HAL_TX_PROTOCOL_ASSIST_CFG_LSOV2_EN;
8699 }
8700
8701 if (vp_config->tpa_ipv6_keep_searching !=
8702 VXGE_HAL_VPATH_TPA_IPV6_KEEP_SEARCHING_USE_FLASH_DEFAULT) {
8703 if (vp_config->tpa_ipv6_keep_searching)
8704 val64 |= VXGE_HAL_TX_PROTOCOL_ASSIST_CFG_IPV6_KEEP_SEARCHING;
8705 else
8706 val64 &= ~VXGE_HAL_TX_PROTOCOL_ASSIST_CFG_IPV6_KEEP_SEARCHING;
8707 }
8708
8709 vxge_os_pio_mem_write64(hldev->header.pdev,
8710 hldev->header.regh0,
8711 val64,
8712 &vpath->vp_reg->tx_protocol_assist_cfg);
8713
8714 }
8715
8716 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
8717 __FILE__, __func__, __LINE__, status);
8718 return (status);
8719 }
8720
8721 /*
8722 * __hal_vpath_tim_configure
8723 * @hldev: Handle to the device object
8724 * @vp_id: Virtual Path Id
8725 *
8726 * This routine configures the tim registers of virtual path
8727 * using the config passed
8728 */
8729 vxge_hal_status_e
__hal_vpath_tim_configure(vxge_hal_device_h devh,u32 vp_id)8730 __hal_vpath_tim_configure(
8731 vxge_hal_device_h devh,
8732 u32 vp_id)
8733 {
8734 u64 val64;
8735 vxge_hal_status_e status = VXGE_HAL_OK;
8736 __hal_device_t *hldev = (__hal_device_t *) devh;
8737 __hal_virtualpath_t *vpath;
8738
8739 vxge_assert(devh != NULL);
8740
8741 vxge_hal_trace_log_vpath("==> %s:%s:%d",
8742 __FILE__, __func__, __LINE__);
8743
8744 vxge_hal_trace_log_vpath("devh = 0x"VXGE_OS_STXFMT", vp_id = %d",
8745 (ptr_t) devh, vp_id);
8746
8747 vpath = (__hal_virtualpath_t *) &hldev->virtual_paths[vp_id];
8748
8749 vxge_os_pio_mem_write64(hldev->header.pdev,
8750 hldev->header.regh0,
8751 (u64) 0,
8752 &vpath->vp_reg->tim_dest_addr);
8753
8754 vxge_os_pio_mem_write64(hldev->header.pdev,
8755 hldev->header.regh0,
8756 (u64) 0,
8757 &vpath->vp_reg->tim_vpath_map);
8758
8759 vxge_os_pio_mem_write64(hldev->header.pdev,
8760 hldev->header.regh0,
8761 (u64) 0,
8762 &vpath->vp_reg->tim_bitmap);
8763
8764 vxge_os_pio_mem_write64(hldev->header.pdev,
8765 hldev->header.regh0,
8766 (u64) 0,
8767 &vpath->vp_reg->tim_remap);
8768
8769 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8770 hldev->header.regh0,
8771 &vpath->vp_reg->rtdma_rd_optimization_ctrl);
8772
8773 val64 |= VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN;
8774
8775 if (hldev->header.config.intr_mode == VXGE_HAL_INTR_MODE_EMULATED_INTA)
8776 val64 = 0x1000150012000100ULL; /* override for HPISS */
8777
8778 vxge_os_pio_mem_write64(hldev->header.pdev,
8779 hldev->header.regh0,
8780 val64,
8781 &vpath->vp_reg->rtdma_rd_optimization_ctrl);
8782
8783 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8784 hldev->header.regh0,
8785 &vpath->vp_reg->tim_wrkld_clc);
8786
8787 val64 |= VXGE_HAL_TIM_WRKLD_CLC_WRKLD_EVAL_PRD(0x5BE9) |
8788 VXGE_HAL_TIM_WRKLD_CLC_CNT_FRM_BYTE |
8789 VXGE_HAL_TIM_WRKLD_CLC_WRKLD_EVAL_DIV(0x15) |
8790 VXGE_HAL_TIM_WRKLD_CLC_CNT_RX_TX(3);
8791
8792 vxge_os_pio_mem_write64(hldev->header.pdev,
8793 hldev->header.regh0,
8794 val64,
8795 &vpath->vp_reg->tim_wrkld_clc);
8796
8797 if (vpath->vp_config->ring.enable == VXGE_HAL_RING_ENABLE) {
8798
8799 vxge_os_pio_mem_write64(hldev->header.pdev,
8800 hldev->header.regh0,
8801 VXGE_HAL_TIM_RING_ASSN_INT_NUM(vpath->rx_intr_num),
8802 &vpath->vp_reg->tim_ring_assn);
8803
8804 }
8805
8806 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8807 hldev->header.regh0,
8808 &vpath->vp_reg->tim_pci_cfg);
8809
8810 val64 |= VXGE_HAL_TIM_PCI_CFG_ADD_PAD;
8811
8812 if (vpath->vp_config->no_snoop !=
8813 VXGE_HAL_VPATH_NO_SNOOP_USE_FLASH_DEFAULT) {
8814 if (vpath->vp_config->no_snoop)
8815 val64 |= VXGE_HAL_TIM_PCI_CFG_NO_SNOOP;
8816 else
8817 val64 &= ~VXGE_HAL_TIM_PCI_CFG_NO_SNOOP;
8818 }
8819
8820 vxge_os_pio_mem_write64(hldev->header.pdev,
8821 hldev->header.regh0,
8822 val64,
8823 &vpath->vp_reg->tim_pci_cfg);
8824
8825 if (vpath->vp_config->fifo.enable == VXGE_HAL_FIFO_ENABLE) {
8826
8827 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8828 hldev->header.regh0,
8829 &vpath->vp_reg->tim_cfg1_int_num[VXGE_HAL_VPATH_INTR_TX]);
8830
8831 if (vpath->vp_config->tti.btimer_val !=
8832 VXGE_HAL_USE_FLASH_DEFAULT_TIM_BTIMER_VAL) {
8833 val64 &=
8834 ~VXGE_HAL_TIM_CFG1_INT_NUM_BTIMER_VAL(0x3ffffff);
8835 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_BTIMER_VAL(
8836 vpath->vp_config->tti.btimer_val);
8837 }
8838
8839 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_BITMP_EN;
8840
8841 if (vpath->vp_config->tti.txfrm_cnt_en !=
8842 VXGE_HAL_TXFRM_CNT_EN_USE_FLASH_DEFAULT) {
8843 if (vpath->vp_config->tti.txfrm_cnt_en)
8844 val64 |=
8845 VXGE_HAL_TIM_CFG1_INT_NUM_TXFRM_CNT_EN;
8846 else
8847 val64 &=
8848 ~VXGE_HAL_TIM_CFG1_INT_NUM_TXFRM_CNT_EN;
8849 }
8850
8851 if (vpath->vp_config->tti.txd_cnt_en !=
8852 VXGE_HAL_TXD_CNT_EN_USE_FLASH_DEFAULT) {
8853 if (vpath->vp_config->tti.txd_cnt_en)
8854 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_TXD_CNT_EN;
8855 else
8856 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_TXD_CNT_EN;
8857 }
8858
8859 if (vpath->vp_config->tti.timer_ac_en !=
8860 VXGE_HAL_TIM_TIMER_AC_USE_FLASH_DEFAULT) {
8861 if (vpath->vp_config->tti.timer_ac_en)
8862 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_AC;
8863 else
8864 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_AC;
8865 }
8866
8867 if (vpath->vp_config->tti.timer_ci_en !=
8868 VXGE_HAL_TIM_TIMER_CI_USE_FLASH_DEFAULT) {
8869 if (vpath->vp_config->tti.timer_ci_en)
8870 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_CI;
8871 else
8872 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_CI;
8873 }
8874
8875 if (vpath->vp_config->tti.urange_a !=
8876 VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_A) {
8877 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_URNG_A(0x3f);
8878 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_URNG_A(
8879 vpath->vp_config->tti.urange_a);
8880 }
8881
8882 if (vpath->vp_config->tti.urange_b !=
8883 VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_B) {
8884 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_URNG_B(0x3f);
8885 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_URNG_B(
8886 vpath->vp_config->tti.urange_b);
8887 }
8888
8889 if (vpath->vp_config->tti.urange_c !=
8890 VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_C) {
8891 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_URNG_C(0x3f);
8892 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_URNG_C(
8893 vpath->vp_config->tti.urange_c);
8894 }
8895
8896 vxge_os_pio_mem_write64(hldev->header.pdev,
8897 hldev->header.regh0,
8898 val64,
8899 &vpath->vp_reg->tim_cfg1_int_num[VXGE_HAL_VPATH_INTR_TX]);
8900
8901 vpath->tim_tti_cfg1_saved = val64;
8902
8903 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8904 hldev->header.regh0,
8905 &vpath->vp_reg->tim_cfg2_int_num[VXGE_HAL_VPATH_INTR_TX]);
8906
8907 if (vpath->vp_config->tti.uec_a !=
8908 VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_A) {
8909 val64 &= ~VXGE_HAL_TIM_CFG2_INT_NUM_UEC_A(0xffff);
8910 val64 |= VXGE_HAL_TIM_CFG2_INT_NUM_UEC_A(
8911 vpath->vp_config->tti.uec_a);
8912 }
8913
8914 if (vpath->vp_config->tti.uec_b !=
8915 VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_B) {
8916 val64 &= ~VXGE_HAL_TIM_CFG2_INT_NUM_UEC_B(0xffff);
8917 val64 |= VXGE_HAL_TIM_CFG2_INT_NUM_UEC_B(
8918 vpath->vp_config->tti.uec_b);
8919 }
8920
8921 if (vpath->vp_config->tti.uec_c !=
8922 VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_C) {
8923 val64 &= ~VXGE_HAL_TIM_CFG2_INT_NUM_UEC_C(0xffff);
8924 val64 |= VXGE_HAL_TIM_CFG2_INT_NUM_UEC_C(
8925 vpath->vp_config->tti.uec_c);
8926 }
8927
8928 if (vpath->vp_config->tti.uec_d !=
8929 VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_D) {
8930 val64 &= ~VXGE_HAL_TIM_CFG2_INT_NUM_UEC_D(0xffff);
8931 val64 |= VXGE_HAL_TIM_CFG2_INT_NUM_UEC_D(
8932 vpath->vp_config->tti.uec_d);
8933 }
8934
8935 vxge_os_pio_mem_write64(hldev->header.pdev,
8936 hldev->header.regh0,
8937 val64,
8938 &vpath->vp_reg->tim_cfg2_int_num[VXGE_HAL_VPATH_INTR_TX]);
8939
8940 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8941 hldev->header.regh0,
8942 &vpath->vp_reg->tim_cfg3_int_num[VXGE_HAL_VPATH_INTR_TX]);
8943
8944 if (vpath->vp_config->tti.timer_ri_en !=
8945 VXGE_HAL_TIM_TIMER_RI_USE_FLASH_DEFAULT) {
8946 if (vpath->vp_config->tti.timer_ri_en)
8947 val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_TIMER_RI;
8948 else
8949 val64 &= ~VXGE_HAL_TIM_CFG3_INT_NUM_TIMER_RI;
8950 }
8951
8952 if (vpath->vp_config->tti.rtimer_event_sf !=
8953 VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_EVENT_SF) {
8954 val64 &=
8955 ~VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(0xf);
8956 val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(
8957 vpath->vp_config->tti.rtimer_event_sf);
8958 }
8959
8960 if (vpath->vp_config->tti.rtimer_val !=
8961 VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_VAL) {
8962 val64 &= ~VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_VAL(
8963 0x3ffffff);
8964 val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_VAL(
8965 vpath->vp_config->tti.rtimer_val);
8966 }
8967
8968 if (vpath->vp_config->tti.util_sel !=
8969 VXGE_HAL_TIM_UTIL_SEL_USE_FLASH_DEFAULT) {
8970 val64 &= ~VXGE_HAL_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
8971 val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_UTIL_SEL(
8972 vpath->vp_config->tti.util_sel);
8973 }
8974
8975 if (vpath->vp_config->tti.ltimer_val !=
8976 VXGE_HAL_USE_FLASH_DEFAULT_TIM_LTIMER_VAL) {
8977 val64 &=
8978 ~VXGE_HAL_TIM_CFG3_INT_NUM_LTIMER_VAL(0x3ffffff);
8979 val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_LTIMER_VAL(
8980 vpath->vp_config->tti.ltimer_val);
8981 }
8982
8983 vxge_os_pio_mem_write64(hldev->header.pdev,
8984 hldev->header.regh0,
8985 val64,
8986 &vpath->vp_reg->tim_cfg3_int_num[VXGE_HAL_VPATH_INTR_TX]);
8987
8988 vpath->tim_tti_cfg3_saved = val64;
8989 }
8990
8991 if (vpath->vp_config->ring.enable == VXGE_HAL_RING_ENABLE) {
8992
8993 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8994 hldev->header.regh0,
8995 &vpath->vp_reg->tim_cfg1_int_num[VXGE_HAL_VPATH_INTR_RX]);
8996
8997 if (vpath->vp_config->rti.btimer_val !=
8998 VXGE_HAL_USE_FLASH_DEFAULT_TIM_BTIMER_VAL) {
8999 val64 &=
9000 ~VXGE_HAL_TIM_CFG1_INT_NUM_BTIMER_VAL(0x3ffffff);
9001 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_BTIMER_VAL(
9002 vpath->vp_config->rti.btimer_val);
9003 }
9004
9005 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_BITMP_EN;
9006
9007 if (vpath->vp_config->rti.txfrm_cnt_en !=
9008 VXGE_HAL_TXFRM_CNT_EN_USE_FLASH_DEFAULT) {
9009 if (vpath->vp_config->rti.txfrm_cnt_en)
9010 val64 |=
9011 VXGE_HAL_TIM_CFG1_INT_NUM_TXFRM_CNT_EN;
9012 else
9013 val64 &=
9014 ~VXGE_HAL_TIM_CFG1_INT_NUM_TXFRM_CNT_EN;
9015 }
9016
9017 if (vpath->vp_config->rti.txd_cnt_en !=
9018 VXGE_HAL_TXD_CNT_EN_USE_FLASH_DEFAULT) {
9019 if (vpath->vp_config->rti.txd_cnt_en)
9020 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_TXD_CNT_EN;
9021 else
9022 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_TXD_CNT_EN;
9023 }
9024
9025 if (vpath->vp_config->rti.timer_ac_en !=
9026 VXGE_HAL_TIM_TIMER_AC_USE_FLASH_DEFAULT) {
9027 if (vpath->vp_config->rti.timer_ac_en)
9028 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_AC;
9029 else
9030 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_AC;
9031 }
9032
9033 if (vpath->vp_config->rti.timer_ci_en !=
9034 VXGE_HAL_TIM_TIMER_CI_USE_FLASH_DEFAULT) {
9035 if (vpath->vp_config->rti.timer_ci_en)
9036 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_CI;
9037 else
9038 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_CI;
9039 }
9040
9041 if (vpath->vp_config->rti.urange_a !=
9042 VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_A) {
9043 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_URNG_A(0x3f);
9044 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_URNG_A(
9045 vpath->vp_config->rti.urange_a);
9046 }
9047
9048 if (vpath->vp_config->rti.urange_b !=
9049 VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_B) {
9050 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_URNG_B(0x3f);
9051 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_URNG_B(
9052 vpath->vp_config->rti.urange_b);
9053 }
9054
9055 if (vpath->vp_config->rti.urange_c !=
9056 VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_C) {
9057 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_URNG_C(0x3f);
9058 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_URNG_C(
9059 vpath->vp_config->rti.urange_c);
9060 }
9061
9062 vxge_os_pio_mem_write64(hldev->header.pdev,
9063 hldev->header.regh0,
9064 val64,
9065 &vpath->vp_reg->tim_cfg1_int_num[VXGE_HAL_VPATH_INTR_RX]);
9066
9067 vpath->tim_rti_cfg1_saved = val64;
9068
9069 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
9070 hldev->header.regh0,
9071 &vpath->vp_reg->tim_cfg2_int_num[VXGE_HAL_VPATH_INTR_RX]);
9072
9073 if (vpath->vp_config->rti.uec_a !=
9074 VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_A) {
9075 val64 &= ~VXGE_HAL_TIM_CFG2_INT_NUM_UEC_A(0xffff);
9076 val64 |= VXGE_HAL_TIM_CFG2_INT_NUM_UEC_A(
9077 vpath->vp_config->rti.uec_a);
9078 }
9079
9080 if (vpath->vp_config->rti.uec_b !=
9081 VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_B) {
9082 val64 &= ~VXGE_HAL_TIM_CFG2_INT_NUM_UEC_B(0xffff);
9083 val64 |= VXGE_HAL_TIM_CFG2_INT_NUM_UEC_B(
9084 vpath->vp_config->rti.uec_b);
9085 }
9086
9087 if (vpath->vp_config->rti.uec_c !=
9088 VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_C) {
9089 val64 &= ~VXGE_HAL_TIM_CFG2_INT_NUM_UEC_C(0xffff);
9090 val64 |= VXGE_HAL_TIM_CFG2_INT_NUM_UEC_C(
9091 vpath->vp_config->rti.uec_c);
9092 }
9093
9094 if (vpath->vp_config->rti.uec_d !=
9095 VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_D) {
9096 val64 &= ~VXGE_HAL_TIM_CFG2_INT_NUM_UEC_D(0xffff);
9097 val64 |= VXGE_HAL_TIM_CFG2_INT_NUM_UEC_D(
9098 vpath->vp_config->rti.uec_d);
9099 }
9100
9101 vxge_os_pio_mem_write64(hldev->header.pdev,
9102 hldev->header.regh0,
9103 val64,
9104 &vpath->vp_reg->tim_cfg2_int_num[VXGE_HAL_VPATH_INTR_RX]);
9105
9106 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
9107 hldev->header.regh0,
9108 &vpath->vp_reg->tim_cfg3_int_num[VXGE_HAL_VPATH_INTR_RX]);
9109
9110 if (vpath->vp_config->rti.timer_ri_en !=
9111 VXGE_HAL_TIM_TIMER_RI_USE_FLASH_DEFAULT) {
9112 if (vpath->vp_config->rti.timer_ri_en)
9113 val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_TIMER_RI;
9114 else
9115 val64 &= ~VXGE_HAL_TIM_CFG3_INT_NUM_TIMER_RI;
9116 }
9117
9118 if (vpath->vp_config->rti.rtimer_event_sf !=
9119 VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_EVENT_SF) {
9120 val64 &=
9121 ~VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(0xf);
9122 val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(
9123 vpath->vp_config->rti.rtimer_event_sf);
9124 }
9125
9126 if (vpath->vp_config->rti.rtimer_val !=
9127 VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_VAL) {
9128 val64 &=
9129 ~VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_VAL(0x3ffffff);
9130 val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_VAL(
9131 vpath->vp_config->rti.rtimer_val);
9132 }
9133
9134 if (vpath->vp_config->rti.util_sel !=
9135 VXGE_HAL_TIM_UTIL_SEL_USE_FLASH_DEFAULT) {
9136 val64 &= ~VXGE_HAL_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
9137 val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_UTIL_SEL(
9138 vpath->vp_config->rti.util_sel);
9139 }
9140
9141 if (vpath->vp_config->rti.ltimer_val !=
9142 VXGE_HAL_USE_FLASH_DEFAULT_TIM_LTIMER_VAL) {
9143 val64 &=
9144 ~VXGE_HAL_TIM_CFG3_INT_NUM_LTIMER_VAL(0x3ffffff);
9145 val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_LTIMER_VAL(
9146 vpath->vp_config->rti.ltimer_val);
9147 }
9148
9149 vxge_os_pio_mem_write64(hldev->header.pdev,
9150 hldev->header.regh0,
9151 val64,
9152 &vpath->vp_reg->tim_cfg3_int_num[VXGE_HAL_VPATH_INTR_RX]);
9153
9154 vpath->tim_rti_cfg3_saved = val64;
9155 }
9156
9157 val64 = 0;
9158
9159 if (hldev->header.config.intr_mode ==
9160 VXGE_HAL_INTR_MODE_EMULATED_INTA) {
9161
9162 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_BTIMER_VAL(1) |
9163 VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_CI;
9164
9165 }
9166
9167 vxge_os_pio_mem_write64(hldev->header.pdev,
9168 hldev->header.regh0,
9169 val64,
9170 &vpath->vp_reg->tim_cfg1_int_num[VXGE_HAL_VPATH_INTR_EINTA]);
9171
9172 vxge_os_pio_mem_write64(hldev->header.pdev,
9173 hldev->header.regh0,
9174 (u64) 0,
9175 &vpath->vp_reg->tim_cfg2_int_num[VXGE_HAL_VPATH_INTR_EINTA]);
9176
9177 vxge_os_pio_mem_write64(hldev->header.pdev,
9178 hldev->header.regh0,
9179 (u64) 0,
9180 &vpath->vp_reg->tim_cfg3_int_num[VXGE_HAL_VPATH_INTR_EINTA]);
9181
9182 vxge_os_pio_mem_write64(hldev->header.pdev,
9183 hldev->header.regh0,
9184 (u64) 0,
9185 &vpath->vp_reg->tim_cfg1_int_num[VXGE_HAL_VPATH_INTR_BMAP]);
9186
9187 vxge_os_pio_mem_write64(hldev->header.pdev,
9188 hldev->header.regh0,
9189 (u64) 0,
9190 &vpath->vp_reg->tim_cfg2_int_num[VXGE_HAL_VPATH_INTR_BMAP]);
9191
9192 vxge_os_pio_mem_write64(hldev->header.pdev,
9193 hldev->header.regh0,
9194 (u64) 0,
9195 &vpath->vp_reg->tim_cfg3_int_num[VXGE_HAL_VPATH_INTR_BMAP]);
9196
9197 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
9198 __FILE__, __func__, __LINE__, status);
9199 return (status);
9200 }
9201
9202 /*
9203 * vxge_hal_vpath_is_rxdmem_leak - Check for the rxd memory leak.
9204 * @vpath_handle: Virtual Path handle.
9205 *
9206 * The function checks for the rxd memory leak.
9207 *
9208 */
9209 u32
vxge_hal_vpath_is_rxdmem_leak(vxge_hal_vpath_h vpath_handle)9210 vxge_hal_vpath_is_rxdmem_leak(vxge_hal_vpath_h vpath_handle)
9211 {
9212 u64 val64;
9213 u32 new_qw_count, rxd_spat, bRet = 0;
9214 __hal_device_t *hldev;
9215 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
9216
9217 vxge_assert(vp != NULL);
9218
9219 hldev = vp->vpath->hldev;
9220
9221 vxge_hal_trace_log_vpath("==> %s:%s:%d",
9222 __FILE__, __func__, __LINE__);
9223
9224 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
9225 (ptr_t) vpath_handle);
9226
9227 if (vp->vpath->vp_config->ring.enable == VXGE_HAL_RING_DISABLE) {
9228 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
9229 __FILE__, __func__, __LINE__, bRet);
9230 return (bRet);
9231 }
9232
9233 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
9234 hldev->header.regh0,
9235 &vp->vpath->vp_reg->prc_rxd_doorbell);
9236
9237 new_qw_count = (u32) VXGE_HAL_PRC_RXD_DOORBELL_GET_NEW_QW_CNT(val64);
9238
9239 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
9240 hldev->header.regh0,
9241 &vp->vpath->vp_reg->prc_cfg6);
9242
9243 rxd_spat = (u32) VXGE_HAL_PRC_CFG6_GET_RXD_SPAT(val64);
9244
9245 bRet = (new_qw_count > (rxd_spat * 3 / 2));
9246
9247 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
9248 __FILE__, __func__, __LINE__, bRet);
9249
9250 return (bRet);
9251 }
9252
9253 /*
9254 * vxge_hal_vpath_mtu_check - check MTU value for ranges
9255 * @vpath_handle: Virtal path handle
9256 * @new_mtu: new MTU value to check
9257 *
9258 * Will do sanity check for new MTU value.
9259 *
9260 * Returns: VXGE_HAL_OK - success.
9261 * VXGE_HAL_ERR_INVALID_MTU_SIZE - MTU is invalid.
9262 *
9263 * See also: vxge_hal_vpath_mtu_set()
9264 */
9265 vxge_hal_status_e
vxge_hal_device_mtu_check(vxge_hal_vpath_h vpath_handle,unsigned long new_mtu)9266 vxge_hal_device_mtu_check(vxge_hal_vpath_h vpath_handle,
9267 unsigned long new_mtu)
9268 {
9269 vxge_hal_status_e status = VXGE_HAL_OK;
9270 __hal_device_t *hldev;
9271 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
9272
9273 vxge_assert(vpath_handle != NULL);
9274
9275 hldev = vp->vpath->hldev;
9276
9277 vxge_hal_trace_log_vpath("==> %s:%s:%d",
9278 __FILE__, __func__, __LINE__);
9279
9280 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
9281 (ptr_t) vpath_handle);
9282
9283 if (vp == NULL) {
9284 vxge_hal_trace_log_vpath(
9285 "<== %s:%s:%d Result: %d", __FILE__, __func__,
9286 __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
9287 return (VXGE_HAL_ERR_INVALID_HANDLE);
9288 }
9289
9290 new_mtu += VXGE_HAL_MAC_HEADER_MAX_SIZE;
9291
9292 if ((new_mtu < VXGE_HAL_MIN_MTU) || (new_mtu > vp->vpath->max_mtu)) {
9293 status = VXGE_HAL_ERR_INVALID_MTU_SIZE;
9294 }
9295
9296 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
9297 __FILE__, __func__, __LINE__, status);
9298 return (status);
9299 }
9300
9301 /*
9302 * vxge_hal_vpath_mtu_set - Set MTU.
9303 * @vpath_handle: Virtal path handle
9304 * @new_mtu: New MTU size to configure.
9305 *
9306 * Set new MTU value. Example, to use jumbo frames:
9307 * vxge_hal_vpath_mtu_set(my_device, 9600);
9308 *
9309 */
9310 vxge_hal_status_e
vxge_hal_vpath_mtu_set(vxge_hal_vpath_h vpath_handle,unsigned long new_mtu)9311 vxge_hal_vpath_mtu_set(vxge_hal_vpath_h vpath_handle,
9312 unsigned long new_mtu)
9313 {
9314 u64 val64;
9315 __hal_device_t *hldev;
9316 vxge_hal_status_e status = VXGE_HAL_OK;
9317 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
9318
9319 vxge_assert(vpath_handle != NULL);
9320
9321 hldev = vp->vpath->hldev;
9322
9323 vxge_hal_trace_log_vpath("==> %s:%s:%d",
9324 __FILE__, __func__, __LINE__);
9325
9326 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
9327 (ptr_t) vpath_handle);
9328
9329 if (vp == NULL) {
9330 vxge_hal_trace_log_vpath(
9331 "<== %s:%s:%d Result: %d", __FILE__, __func__,
9332 __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
9333 return (VXGE_HAL_ERR_INVALID_HANDLE);
9334 }
9335
9336 new_mtu += VXGE_HAL_MAC_HEADER_MAX_SIZE;
9337
9338 if ((new_mtu < VXGE_HAL_MIN_MTU) || (new_mtu > vp->vpath->max_mtu)) {
9339 status = VXGE_HAL_ERR_INVALID_MTU_SIZE;
9340 }
9341
9342 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
9343 hldev->header.regh0,
9344 &vp->vpath->vp_reg->rxmac_vcfg0);
9345
9346 val64 &= ~VXGE_HAL_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
9347 val64 |= VXGE_HAL_RXMAC_VCFG0_RTS_MAX_FRM_LEN(new_mtu);
9348
9349 vxge_os_pio_mem_write64(hldev->header.pdev,
9350 hldev->header.regh0,
9351 val64,
9352 &vp->vpath->vp_reg->rxmac_vcfg0);
9353
9354 vp->vpath->vp_config->mtu = new_mtu - VXGE_HAL_MAC_HEADER_MAX_SIZE;
9355
9356 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
9357 __FILE__, __func__, __LINE__, status);
9358
9359 return (status);
9360 }
9361
9362
9363 /*
9364 * __hal_vpath_size_quantum_set
9365 * @hldev: Handle to the device object
9366 * @vp_id: Virtual Path Id
9367 *
9368 * This routine configures the size quantum of virtual path
9369 * using the config passed
9370 */
9371 vxge_hal_status_e
__hal_vpath_size_quantum_set(vxge_hal_device_h devh,u32 vp_id)9372 __hal_vpath_size_quantum_set(
9373 vxge_hal_device_h devh,
9374 u32 vp_id)
9375 {
9376 u64 val64;
9377 __hal_device_t *hldev = (__hal_device_t *) devh;
9378 __hal_virtualpath_t *vpath;
9379
9380 vxge_assert(devh != NULL);
9381
9382 vxge_hal_trace_log_vpath("==> %s:%s:%d",
9383 __FILE__, __func__, __LINE__);
9384
9385 vxge_hal_trace_log_vpath("devh = 0x"VXGE_OS_STXFMT", vp_id = %d",
9386 (ptr_t) devh, vp_id);
9387
9388 vpath = (__hal_virtualpath_t *) &hldev->virtual_paths[vp_id];
9389
9390 switch (__vxge_os_cacheline_size) {
9391 case 8:
9392 val64 = 0;
9393 break;
9394 case 16:
9395 val64 = 1;
9396 break;
9397 case 32:
9398 val64 = 2;
9399 break;
9400 case 64:
9401 val64 = 3;
9402 break;
9403 default:
9404 case 128:
9405 val64 = 4;
9406 break;
9407 case 256:
9408 val64 = 5;
9409 break;
9410 case 512:
9411 val64 = 6;
9412 break;
9413 }
9414
9415 vxge_os_pio_mem_write64(hldev->header.pdev, hldev->header.regh0,
9416 val64,
9417 &vpath->vp_reg->vpath_general_cfg2);
9418
9419 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: 0",
9420 __FILE__, __func__, __LINE__);
9421 return (VXGE_HAL_OK);
9422 }
9423
9424 /*
9425 * __hal_vpath_hw_initialize
9426 * @hldev: Handle to the device object
9427 * @vp_id: Virtual Path Id
9428 *
9429 * This routine initializes the registers of virtual path
9430 * using the config passed
9431 */
9432 vxge_hal_status_e
__hal_vpath_hw_initialize(vxge_hal_device_h devh,u32 vp_id)9433 __hal_vpath_hw_initialize(
9434 vxge_hal_device_h devh,
9435 u32 vp_id)
9436 {
9437 u64 val64;
9438 u32 mrrs;
9439 vxge_hal_status_e status = VXGE_HAL_OK;
9440 __hal_virtualpath_t *vpath;
9441 __hal_device_t *hldev = (__hal_device_t *) devh;
9442 vxge_hal_pci_e_capability_t *pci_e_cap;
9443
9444 vxge_assert(devh != NULL);
9445
9446 vxge_hal_trace_log_vpath("==> %s:%s:%d",
9447 __FILE__, __func__, __LINE__);
9448
9449 vxge_hal_trace_log_vpath("devh = 0x"VXGE_OS_STXFMT", vp_id = %d",
9450 (ptr_t) devh, vp_id);
9451
9452 vpath = (__hal_virtualpath_t *) &hldev->virtual_paths[vp_id];
9453
9454 if (!(hldev->vpath_assignments & mBIT(vp_id))) {
9455
9456 vxge_hal_trace_log_vpath(
9457 "<== %s:%s:%d Result: %d", __FILE__, __func__,
9458 __LINE__, VXGE_HAL_ERR_VPATH_NOT_AVAILABLE);
9459 return (VXGE_HAL_ERR_VPATH_NOT_AVAILABLE);
9460 }
9461
9462 status = __hal_vpath_swapper_set((vxge_hal_device_t *) hldev, vp_id);
9463 if (status != VXGE_HAL_OK) {
9464
9465 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
9466 __FILE__, __func__, __LINE__, status);
9467 return (status);
9468 }
9469
9470 status = __hal_vpath_size_quantum_set(hldev, vp_id);
9471 if (status != VXGE_HAL_OK) {
9472
9473 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
9474 __FILE__, __func__, __LINE__, status);
9475 return (status);
9476 }
9477
9478 status = __hal_vpath_mac_configure(hldev, vp_id);
9479 if (status != VXGE_HAL_OK) {
9480
9481 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
9482 __FILE__, __func__, __LINE__, status);
9483 return (status);
9484 }
9485
9486 status = __hal_vpath_kdfc_configure(hldev, vp_id);
9487 if (status != VXGE_HAL_OK) {
9488
9489 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
9490 __FILE__, __func__, __LINE__, status);
9491 return (status);
9492 }
9493
9494
9495 status = __hal_vpath_tim_configure(hldev, vp_id);
9496 if (status != VXGE_HAL_OK) {
9497
9498 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
9499 __FILE__, __func__, __LINE__, status);
9500 return (status);
9501 }
9502
9503 vxge_os_pio_mem_write64(hldev->header.pdev, hldev->header.regh0,
9504 VXGE_HAL_USDC_VPATH_SGRP_ASSIGN(
9505 vpath->sess_grps_available),
9506 &vpath->vp_reg->usdc_vpath);
9507
9508 vxge_os_wmb();
9509
9510 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
9511 hldev->header.regh0,
9512 &vpath->vp_reg->qcc_pci_cfg);
9513
9514 val64 |= VXGE_HAL_QCC_PCI_CFG_ADD_PAD_CQE_SPACE |
9515 VXGE_HAL_QCC_PCI_CFG_ADD_PAD_WQE |
9516 VXGE_HAL_QCC_PCI_CFG_ADD_PAD_SRQIR |
9517 VXGE_HAL_QCC_PCI_CFG_CTL_STR_CQE_SPACE |
9518 VXGE_HAL_QCC_PCI_CFG_CTL_STR_WQE |
9519 VXGE_HAL_QCC_PCI_CFG_CTL_STR_SRQIR;
9520
9521 if (vpath->vp_config->no_snoop !=
9522 VXGE_HAL_VPATH_NO_SNOOP_USE_FLASH_DEFAULT) {
9523 if (vpath->vp_config->no_snoop) {
9524 val64 |= VXGE_HAL_QCC_PCI_CFG_NO_SNOOP_CQE_SPACE |
9525 VXGE_HAL_QCC_PCI_CFG_NO_SNOOP_WQE |
9526 VXGE_HAL_QCC_PCI_CFG_NO_SNOOP_SRQIR;
9527 } else {
9528 val64 &= ~(VXGE_HAL_QCC_PCI_CFG_NO_SNOOP_CQE_SPACE |
9529 VXGE_HAL_QCC_PCI_CFG_NO_SNOOP_WQE |
9530 VXGE_HAL_QCC_PCI_CFG_NO_SNOOP_SRQIR);
9531 }
9532 }
9533
9534 vxge_os_pio_mem_write64(hldev->header.pdev, hldev->header.regh0,
9535 val64,
9536 &vpath->vp_reg->qcc_pci_cfg);
9537
9538 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
9539 hldev->header.regh0,
9540 &vpath->vp_reg->h2l_vpath_config);
9541
9542 if (vpath->vp_config->no_snoop !=
9543 VXGE_HAL_VPATH_NO_SNOOP_USE_FLASH_DEFAULT) {
9544 if (vpath->vp_config->no_snoop) {
9545 val64 |= VXGE_HAL_H2L_VPATH_CONFIG_OD_NO_SNOOP;
9546 } else {
9547 val64 &= ~VXGE_HAL_H2L_VPATH_CONFIG_OD_NO_SNOOP;
9548 }
9549 }
9550
9551 vxge_os_pio_mem_write64(hldev->header.pdev, hldev->header.regh0,
9552 val64,
9553 &vpath->vp_reg->h2l_vpath_config);
9554
9555 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
9556 hldev->header.regh0,
9557 &vpath->vp_reg->ph2l_vp_cfg0);
9558
9559 if (vpath->vp_config->no_snoop !=
9560 VXGE_HAL_VPATH_NO_SNOOP_USE_FLASH_DEFAULT) {
9561 if (vpath->vp_config->no_snoop) {
9562 val64 |= VXGE_HAL_PH2L_VP_CFG0_NOSNOOP_DATA;
9563 } else {
9564 val64 &= ~VXGE_HAL_PH2L_VP_CFG0_NOSNOOP_DATA;
9565 }
9566 }
9567
9568 vxge_os_pio_mem_write64(hldev->header.pdev, hldev->header.regh0,
9569 val64,
9570 &vpath->vp_reg->ph2l_vp_cfg0);
9571
9572 vxge_os_pio_mem_write64(hldev->header.pdev, hldev->header.regh0,
9573 0,
9574 &vpath->vp_reg->gendma_int);
9575
9576 pci_e_cap = (vxge_hal_pci_e_capability_t *)
9577 (((char *)&hldev->pci_config_space_bios) + hldev->pci_e_caps);
9578
9579 mrrs = pci_e_cap->pci_e_devctl >> 12;
9580
9581 val64 = VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_GEN_INT_AFTER_ABORT |
9582 VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(mrrs) |
9583 VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN |
9584 VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_TXD_FILL_THRESH(1);
9585
9586 vxge_os_pio_mem_write64(hldev->header.pdev, hldev->header.regh0,
9587 val64,
9588 &vpath->vp_reg->rtdma_rd_optimization_ctrl);
9589
9590 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
9591 __FILE__, __func__, __LINE__, status);
9592 return (status);
9593 }
9594
9595 /*
9596 * __hal_vp_initialize - Initialize Virtual Path structure
9597 * @hldev: Handle to the device object
9598 * @vp_id: Virtual Path Id
9599 * @config: Configuration for the virtual path
9600 *
9601 * This routine initializes virtual path using the config passed
9602 */
9603 vxge_hal_status_e
__hal_vp_initialize(vxge_hal_device_h devh,u32 vp_id,vxge_hal_vp_config_t * config)9604 __hal_vp_initialize(vxge_hal_device_h devh,
9605 u32 vp_id,
9606 vxge_hal_vp_config_t *config)
9607 {
9608 __hal_device_t *hldev = (__hal_device_t *) devh;
9609 __hal_virtualpath_t *vpath;
9610 vxge_hal_status_e status = VXGE_HAL_OK;
9611
9612 vxge_assert((hldev != NULL) && (config != NULL));
9613
9614 vxge_hal_trace_log_vpath("==> %s:%s:%d",
9615 __FILE__, __func__, __LINE__);
9616
9617 vxge_hal_trace_log_vpath(
9618 "devh = 0x"VXGE_OS_STXFMT", vp_id = %d, config = 0x"VXGE_OS_STXFMT,
9619 (ptr_t) devh, vp_id, (ptr_t) config);
9620
9621 if (!(hldev->vpath_assignments & mBIT(vp_id))) {
9622
9623 vxge_hal_trace_log_vpath(
9624 "<== %s:%s:%d Result: %d", __FILE__, __func__,
9625 __LINE__, VXGE_HAL_ERR_VPATH_NOT_AVAILABLE);
9626 return (VXGE_HAL_ERR_VPATH_NOT_AVAILABLE);
9627 }
9628
9629 vpath = (__hal_virtualpath_t *) &hldev->virtual_paths[vp_id];
9630 vpath->vp_id = vp_id;
9631
9632 vpath->vp_open = VXGE_HAL_VP_OPEN;
9633
9634 vpath->hldev = (__hal_device_t *) devh;
9635
9636 vpath->vp_config = config;
9637
9638 vpath->vp_reg = hldev->vpath_reg[vp_id];
9639
9640 vpath->vpmgmt_reg = hldev->vpmgmt_reg[vp_id];
9641
9642 status = __hal_vpath_hw_reset(devh, vp_id);
9643
9644 if (status != VXGE_HAL_OK) {
9645 vxge_hal_trace_log_vpath(
9646 "vpath is already in reset %s:%s:%d",
9647 __FILE__, __func__, __LINE__);
9648 }
9649
9650 status = __hal_vpath_reset_check(vpath);
9651
9652 if (status != VXGE_HAL_OK) {
9653 vxge_os_memzero(vpath, sizeof(__hal_virtualpath_t));
9654 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = %d",
9655 __FILE__, __func__, __LINE__, status);
9656
9657 return (status);
9658 }
9659
9660 status = __hal_vpath_mgmt_read(hldev, vpath);
9661
9662 if (status != VXGE_HAL_OK) {
9663 vxge_os_memzero(vpath, sizeof(__hal_virtualpath_t));
9664 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
9665 __FILE__, __func__, __LINE__, status);
9666 return (status);
9667 }
9668
9669 vpath->tx_intr_num =
9670 (vp_id * VXGE_HAL_MAX_INTR_PER_VP) + VXGE_HAL_VPATH_INTR_TX;
9671
9672 vpath->rx_intr_num =
9673 (vp_id * VXGE_HAL_MAX_INTR_PER_VP) + VXGE_HAL_VPATH_INTR_RX;
9674
9675 vpath->einta_intr_num =
9676 (vp_id * VXGE_HAL_MAX_INTR_PER_VP) + VXGE_HAL_VPATH_INTR_EINTA;
9677
9678 vpath->bmap_intr_num =
9679 (vp_id * VXGE_HAL_MAX_INTR_PER_VP) + VXGE_HAL_VPATH_INTR_BMAP;
9680
9681
9682 #if defined(VXGE_HAL_VP_CBS)
9683 vxge_os_spin_lock_init(&vpath->vpath_handles_lock, hldev->pdev);
9684 #elif defined(VXGE_HAL_VP_CBS_IRQ)
9685 vxge_os_spin_lock_init_irq(&vpath->vpath_handles_lock, hldev->irqh);
9686 #endif
9687
9688 vxge_list_init(&vpath->vpath_handles);
9689
9690 vpath->sw_stats = &hldev->stats.sw_dev_info_stats.vpath_info[vp_id];
9691
9692 vxge_os_memzero(&vpath->sw_stats->obj_counts,
9693 sizeof(vxge_hal_vpath_sw_obj_count_t));
9694
9695 VXGE_HAL_DEVICE_TIM_INT_MASK_SET(vpath->hldev, vpath->vp_id);
9696
9697 status = __hal_vpath_hw_initialize(vpath->hldev, vpath->vp_id);
9698
9699 if (status != VXGE_HAL_OK) {
9700 __hal_vp_terminate(devh, vp_id);
9701 }
9702
9703 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
9704 __FILE__, __func__, __LINE__, status);
9705 return (status);
9706 }
9707
9708 /*
9709 * __hal_vp_terminate - Terminate Virtual Path structure
9710 * @hldev: Handle to the device object
9711 * @vp_id: Virtual Path Id
9712 *
9713 * This routine closes all channels it opened and freeup memory
9714 */
9715 void
__hal_vp_terminate(vxge_hal_device_h devh,u32 vp_id)9716 __hal_vp_terminate(vxge_hal_device_h devh, u32 vp_id)
9717 {
9718 __hal_virtualpath_t *vpath;
9719 __hal_device_t *hldev = (__hal_device_t *) devh;
9720
9721 vxge_assert(devh != NULL);
9722
9723 vxge_hal_trace_log_vpath("==> %s:%s:%d",
9724 __FILE__, __func__, __LINE__);
9725
9726 vxge_hal_trace_log_vpath(
9727 "devh = 0x"VXGE_OS_STXFMT", vp_id = %d", (ptr_t) devh, vp_id);
9728
9729 vpath = (__hal_virtualpath_t *) &hldev->virtual_paths[vp_id];
9730
9731 if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
9732
9733 vxge_hal_trace_log_vpath(
9734 "<== %s:%s:%d Result: %d", __FILE__, __func__,
9735 __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
9736 return;
9737
9738 }
9739
9740 VXGE_HAL_DEVICE_TIM_INT_MASK_RESET(vpath->hldev, vpath->vp_id);
9741
9742
9743 #if defined(VXGE_HAL_VP_CBS)
9744 vxge_os_spin_lock_destroy(
9745 &vpath->vpath_handles_lock, hldev->header.pdev);
9746 #elif defined(VXGE_HAL_VP_CBS_IRQ)
9747 vxge_os_spin_lock_destroy_irq(
9748 &vpath->vpath_handles_lock, hldev->header.pdev);
9749 #endif
9750
9751 vxge_os_memzero(vpath, sizeof(__hal_virtualpath_t));
9752
9753 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: 0",
9754 __FILE__, __func__, __LINE__);
9755 }
9756
9757
9758 /*
9759 * vxge_hal_vpath_obj_count_get - Get the Object usage count for a given
9760 * virtual path
9761 * @vpath_handle: Virtal path handle
9762 * @obj_counts: Buffer to return object counts
9763 *
9764 * This function returns the object counts for virtual path.
9765 */
9766 vxge_hal_status_e
vxge_hal_vpath_obj_count_get(vxge_hal_vpath_h vpath_handle,vxge_hal_vpath_sw_obj_count_t * obj_count)9767 vxge_hal_vpath_obj_count_get(
9768 vxge_hal_vpath_h vpath_handle,
9769 vxge_hal_vpath_sw_obj_count_t *obj_count)
9770 {
9771 __hal_device_t *hldev;
9772 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
9773
9774 if ((vpath_handle == NULL) || (obj_count == NULL))
9775 return (VXGE_HAL_FAIL);
9776
9777 hldev = vp->vpath->hldev;
9778
9779 vxge_hal_trace_log_vpath("==> %s:%s:%d",
9780 __FILE__, __func__, __LINE__);
9781
9782 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT", "
9783 "obj_count = 0x"VXGE_OS_STXFMT, (ptr_t) vpath_handle,
9784 (ptr_t) obj_count);
9785
9786 vxge_os_memcpy(obj_count, &vp->vpath->sw_stats->obj_counts,
9787 sizeof(vxge_hal_vpath_sw_obj_count_t));
9788
9789 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: 0",
9790 __FILE__, __func__, __LINE__);
9791
9792 return (VXGE_HAL_OK);
9793 }
9794
9795 /*
9796 * vxge_hal_vpath_open - Open a virtual path on a given adapter
9797 * @devh: handle to device object
9798 * @attr: Virtual path attributes
9799 * @cb_fn: Call back to be called to complete an asynchronous function call
9800 * @client_handle: handle to be returned in the callback
9801 * @vpath_handle: Buffer to return a handle to the vpath
9802 *
9803 * This function is used to open access to virtual path of an
9804 * adapter for offload, LRO and SPDM operations. This function returns
9805 * synchronously.
9806 */
9807 vxge_hal_status_e
vxge_hal_vpath_open(vxge_hal_device_h devh,vxge_hal_vpath_attr_t * attr,vxge_hal_vpath_callback_f cb_fn,vxge_hal_client_h client_handle,vxge_hal_vpath_h * vpath_handle)9808 vxge_hal_vpath_open(vxge_hal_device_h devh,
9809 vxge_hal_vpath_attr_t *attr,
9810 vxge_hal_vpath_callback_f cb_fn,
9811 vxge_hal_client_h client_handle,
9812 vxge_hal_vpath_h *vpath_handle)
9813 {
9814 __hal_device_t *hldev = (__hal_device_t *) devh;
9815 __hal_virtualpath_t *vpath;
9816 __hal_vpath_handle_t *vp;
9817 vxge_hal_status_e status;
9818
9819 vxge_assert((devh != NULL) && (attr != NULL) && (cb_fn != NULL) &&
9820 (vpath_handle != NULL));
9821
9822 vxge_hal_trace_log_vpath("==> %s:%s:%d",
9823 __FILE__, __func__, __LINE__);
9824
9825 vxge_hal_trace_log_vpath("devh = 0x"VXGE_OS_STXFMT", "
9826 "attr = 0x"VXGE_OS_STXFMT", cb_fn = 0x"VXGE_OS_STXFMT", "
9827 "client_handle = 0x"VXGE_OS_STXFMT", "
9828 "vpath_handle = 0x"VXGE_OS_STXFMT,
9829 (ptr_t) devh, (ptr_t) attr, (ptr_t) cb_fn,
9830 (ptr_t) client_handle, (ptr_t) vpath_handle);
9831
9832
9833 vpath = (__hal_virtualpath_t *) &hldev->virtual_paths[attr->vp_id];
9834
9835 if (vpath->vp_open == VXGE_HAL_VP_OPEN) {
9836 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
9837 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_STATE);
9838 return (VXGE_HAL_ERR_INVALID_STATE);
9839 }
9840
9841 status = __hal_vp_initialize(hldev, attr->vp_id,
9842 &hldev->header.config.vp_config[attr->vp_id]);
9843
9844 if (status != VXGE_HAL_OK) {
9845
9846 vxge_hal_err_log_vpath(
9847 "virtual Paths: __hal_vp_initialize failed == > %s : %d",
9848 __func__, __LINE__);
9849
9850 goto vpath_open_exit1;
9851
9852 }
9853
9854 vp = (__hal_vpath_handle_t *) vxge_os_malloc(hldev->header.pdev,
9855 sizeof(__hal_vpath_handle_t));
9856
9857 if (vp == NULL) {
9858
9859 status = VXGE_HAL_ERR_OUT_OF_MEMORY;
9860
9861 goto vpath_open_exit2;
9862
9863 }
9864
9865 vxge_os_memzero(vp, sizeof(__hal_vpath_handle_t));
9866
9867 vp->vpath = vpath;
9868 vp->cb_fn = cb_fn;
9869 vp->client_handle = client_handle;
9870
9871
9872 if (vp->vpath->vp_config->fifo.enable == VXGE_HAL_FIFO_ENABLE) {
9873
9874 status = __hal_fifo_create(vp, &attr->fifo_attr);
9875 if (status != VXGE_HAL_OK) {
9876 goto vpath_open_exit6;
9877 }
9878 }
9879
9880 if (vp->vpath->vp_config->ring.enable == VXGE_HAL_RING_ENABLE) {
9881
9882 status = __hal_ring_create(vp, &attr->ring_attr);
9883 if (status != VXGE_HAL_OK) {
9884 goto vpath_open_exit7;
9885 }
9886
9887 status = __hal_vpath_prc_configure(devh, attr->vp_id);
9888 if (status != VXGE_HAL_OK) {
9889 goto vpath_open_exit8;
9890 }
9891 }
9892
9893
9894
9895 vp->vpath->stats_block = __hal_blockpool_block_allocate(devh,
9896 VXGE_OS_HOST_PAGE_SIZE);
9897
9898 if (vp->vpath->stats_block == NULL) {
9899
9900 status = VXGE_HAL_ERR_OUT_OF_MEMORY;
9901
9902 goto vpath_open_exit8;
9903
9904 }
9905
9906 vp->vpath->hw_stats =
9907 (vxge_hal_vpath_stats_hw_info_t *) vp->vpath->stats_block->memblock;
9908
9909 vxge_os_memzero(vp->vpath->hw_stats,
9910 sizeof(vxge_hal_vpath_stats_hw_info_t));
9911
9912 hldev->stats.hw_dev_info_stats.vpath_info[attr->vp_id] =
9913 vp->vpath->hw_stats;
9914
9915 vp->vpath->hw_stats_sav =
9916 &hldev->stats.hw_dev_info_stats.vpath_info_sav[attr->vp_id];
9917
9918 vxge_os_memzero(vp->vpath->hw_stats_sav,
9919 sizeof(vxge_hal_vpath_stats_hw_info_t));
9920
9921 vxge_os_pio_mem_write64(hldev->header.pdev,
9922 hldev->header.regh0,
9923 vp->vpath->stats_block->dma_addr,
9924 &vpath->vp_reg->stats_cfg);
9925
9926 status = vxge_hal_vpath_hw_stats_enable(vp);
9927
9928 if (status != VXGE_HAL_OK) {
9929
9930 goto vpath_open_exit8;
9931
9932 }
9933
9934 vxge_list_insert(&vp->item, &vpath->vpath_handles);
9935
9936 hldev->vpaths_deployed |= mBIT(vpath->vp_id);
9937 *vpath_handle = vp;
9938
9939 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: 0",
9940 __FILE__, __func__, __LINE__);
9941 return (VXGE_HAL_OK);
9942
9943 vpath_open_exit8:
9944 if (vpath->ringh != NULL)
9945 __hal_ring_delete(vp);
9946 vpath_open_exit7:
9947 if (vpath->fifoh != NULL)
9948 __hal_fifo_delete(vp);
9949 vpath_open_exit6:
9950
9951 vxge_os_free(hldev->header.pdev, vp,
9952 sizeof(__hal_vpath_handle_t));
9953 vpath_open_exit2:
9954 __hal_vp_terminate(devh, attr->vp_id);
9955 vpath_open_exit1:
9956 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
9957 __FILE__, __func__, __LINE__, status);
9958
9959 return (status);
9960 }
9961
9962 /*
9963 * vxge_hal_vpath_id - Get virtual path ID
9964 * @vpath_handle: Handle got from previous vpath open
9965 *
9966 * This function returns virtual path id
9967 */
9968 u32
vxge_hal_vpath_id(vxge_hal_vpath_h vpath_handle)9969 vxge_hal_vpath_id(
9970 vxge_hal_vpath_h vpath_handle)
9971 {
9972 u32 id;
9973 __hal_device_t *hldev;
9974 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
9975
9976 vxge_assert(vpath_handle != NULL);
9977
9978 hldev = vp->vpath->hldev;
9979
9980 vxge_hal_trace_log_vpath("==> %s:%s:%d",
9981 __FILE__, __func__, __LINE__);
9982
9983 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
9984 (ptr_t) vpath_handle);
9985
9986 id = ((__hal_vpath_handle_t *) vpath_handle)->vpath->vp_id;
9987
9988 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: 0",
9989 __FILE__, __func__, __LINE__);
9990
9991 return (id);
9992 }
9993
9994 /*
9995 * vxge_hal_vpath_close - Close the handle got from previous vpath (vpath) open
9996 * @vpath_handle: Handle got from previous vpath open
9997 *
9998 * This function is used to close access to virtual path opened
9999 * earlier.
10000 */
10001 vxge_hal_status_e
vxge_hal_vpath_close(vxge_hal_vpath_h vpath_handle)10002 vxge_hal_vpath_close(
10003 vxge_hal_vpath_h vpath_handle)
10004 {
10005 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
10006 __hal_virtualpath_t *vpath;
10007 __hal_device_t *hldev;
10008 u32 vp_id;
10009 u32 is_empty = TRUE;
10010
10011 vxge_assert(vpath_handle != NULL);
10012
10013 vpath = (__hal_virtualpath_t *) vp->vpath;
10014
10015 hldev = (__hal_device_t *) vpath->hldev;
10016
10017 vp_id = vpath->vp_id;
10018
10019 vxge_hal_trace_log_vpath("==> %s:%s:%d",
10020 __FILE__, __func__, __LINE__);
10021
10022 vxge_hal_trace_log_vpath(
10023 "vpath_handle = 0x"VXGE_OS_STXFMT, (ptr_t) vpath_handle);
10024
10025 if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
10026 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
10027 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
10028 return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
10029 }
10030
10031 #if defined(VXGE_HAL_VP_CBS)
10032 vxge_os_spin_lock(&vpath->vpath_handles_lock);
10033 #elif defined(VXGE_HAL_VP_CBS_IRQ)
10034 vxge_os_spin_lock_irq(&vpath->vpath_handles_lock, flags);
10035 #endif
10036
10037 vxge_list_remove(&vp->item);
10038
10039 if (!vxge_list_is_empty(&vpath->vpath_handles)) {
10040 vxge_list_insert(&vp->item, &vpath->vpath_handles);
10041 is_empty = FALSE;
10042 }
10043
10044 #if defined(VXGE_HAL_VP_CBS)
10045 vxge_os_spin_unlock(&vpath->vpath_handles_lock);
10046 #elif defined(VXGE_HAL_VP_CBS_IRQ)
10047 vxge_os_spin_unlock_irq(&vpath->vpath_handles_lock, flags);
10048 #endif
10049
10050 if (!is_empty) {
10051 vxge_hal_err_log_vpath("clients are still attached == > %s : %d",
10052 __func__, __LINE__);
10053 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: 1",
10054 __FILE__, __func__, __LINE__);
10055 return (VXGE_HAL_FAIL);
10056 }
10057
10058 vpath->hldev->vpaths_deployed &= ~mBIT(vp_id);
10059
10060 if (vpath->ringh != NULL)
10061 __hal_ring_delete(vpath_handle);
10062
10063 if (vpath->fifoh != NULL)
10064 __hal_fifo_delete(vpath_handle);
10065
10066
10067 if (vpath->stats_block != NULL) {
10068 __hal_blockpool_block_free(hldev, vpath->stats_block);
10069 }
10070
10071 vxge_os_free(hldev->header.pdev,
10072 vpath_handle, sizeof(__hal_vpath_handle_t));
10073
10074 __hal_vp_terminate(hldev, vp_id);
10075
10076 vpath->vp_open = VXGE_HAL_VP_NOT_OPEN;
10077
10078 (void) __hal_ifmsg_wmsg_post(hldev,
10079 vp_id,
10080 VXGE_HAL_RTS_ACCESS_STEER_MSG_DEST_BROADCAST,
10081 VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_VPATH_RESET_END,
10082 0);
10083
10084 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: 0",
10085 __FILE__, __func__, __LINE__);
10086 return (VXGE_HAL_OK);
10087 }
10088
10089 /*
10090 * vxge_hal_vpath_reset - Resets vpath
10091 * @vpath_handle: Handle got from previous vpath open
10092 *
10093 * This function is used to request a reset of vpath
10094 */
10095 vxge_hal_status_e
vxge_hal_vpath_reset(vxge_hal_vpath_h vpath_handle)10096 vxge_hal_vpath_reset(
10097 vxge_hal_vpath_h vpath_handle)
10098 {
10099 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
10100 __hal_device_t *hldev;
10101 vxge_hal_status_e status;
10102 u32 count = 0, total_count = 0;
10103
10104 vxge_assert(vpath_handle != NULL);
10105
10106 hldev = vp->vpath->hldev;
10107
10108 vxge_hal_trace_log_vpath("==> %s:%s:%d",
10109 __FILE__, __func__, __LINE__);
10110
10111 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
10112 (ptr_t) vpath_handle);
10113
10114 if (vp->vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
10115 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
10116 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
10117 return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
10118 }
10119
10120 vxge_hw_vpath_set_zero_rx_frm_len(hldev, vp->vpath->vp_id);
10121
10122 vxge_hw_vpath_wait_receive_idle(hldev, vp->vpath->vp_id,
10123 &count, &total_count);
10124
10125 status = __hal_vpath_hw_reset((vxge_hal_device_h) hldev,
10126 vp->vpath->vp_id);
10127
10128 if (status == VXGE_HAL_OK)
10129 vp->vpath->sw_stats->soft_reset_cnt++;
10130
10131 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
10132 __FILE__, __func__, __LINE__, status);
10133 return (status);
10134 }
10135
10136 /*
10137 * vxge_hal_vpath_reset_poll - Poll for reset complete
10138 * @vpath_handle: Handle got from previous vpath open
10139 *
10140 * This function is used to poll for the vpath reset completion
10141 */
10142 vxge_hal_status_e
vxge_hal_vpath_reset_poll(vxge_hal_vpath_h vpath_handle)10143 vxge_hal_vpath_reset_poll(
10144 vxge_hal_vpath_h vpath_handle)
10145 {
10146 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
10147 __hal_device_t *hldev;
10148 vxge_hal_status_e status;
10149
10150 vxge_assert(vpath_handle != NULL);
10151
10152 hldev = vp->vpath->hldev;
10153
10154 vxge_hal_trace_log_vpath("==> %s:%s:%d",
10155 __FILE__, __func__, __LINE__);
10156
10157 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
10158 (ptr_t) vpath_handle);
10159
10160 if (vp->vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
10161 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
10162 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
10163 return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
10164 }
10165
10166 status = __hal_vpath_reset_check(vp->vpath);
10167
10168 if (status != VXGE_HAL_OK) {
10169
10170 vxge_hal_trace_log_vpath("<== %s:%s:%d Result = %d",
10171 __FILE__, __func__, __LINE__, status);
10172
10173 return (status);
10174 }
10175
10176 status = __hal_vpath_sw_reset((vxge_hal_device_h) hldev,
10177 vp->vpath->vp_id);
10178
10179 if (status != VXGE_HAL_OK) {
10180 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
10181 __FILE__, __func__, __LINE__, status);
10182 return (status);
10183 }
10184
10185 vxge_os_memzero(vp->vpath->sw_stats,
10186 sizeof(vxge_hal_vpath_stats_sw_info_t));
10187
10188 status = __hal_vpath_hw_initialize((vxge_hal_device_h) hldev,
10189 vp->vpath->vp_id);
10190
10191 if (status != VXGE_HAL_OK) {
10192 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
10193 __FILE__, __func__, __LINE__, status);
10194 return (status);
10195 }
10196
10197 if (vp->vpath->ringh != NULL) {
10198
10199 status = __hal_vpath_prc_configure(
10200 (vxge_hal_device_h) hldev,
10201 vp->vpath->vp_id);
10202
10203 if (status != VXGE_HAL_OK) {
10204 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
10205 __FILE__, __func__, __LINE__, status);
10206 return (status);
10207 }
10208 }
10209
10210 vxge_os_memzero(vp->vpath->hw_stats,
10211 sizeof(vxge_hal_vpath_stats_hw_info_t));
10212
10213 vxge_os_memzero(vp->vpath->hw_stats_sav,
10214 sizeof(vxge_hal_vpath_stats_hw_info_t));
10215
10216 vxge_os_pio_mem_write64(hldev->header.pdev,
10217 hldev->header.regh0,
10218 vp->vpath->stats_block->dma_addr,
10219 &vp->vpath->vp_reg->stats_cfg);
10220
10221
10222 status = vxge_hal_vpath_hw_stats_enable(vp);
10223
10224 if (status != VXGE_HAL_OK) {
10225
10226 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
10227 __FILE__, __func__, __LINE__, status);
10228 return (status);
10229
10230 }
10231
10232 vxge_hal_trace_log_vpath("<== %s:%s:%d Result: %d",
10233 __FILE__, __func__, __LINE__, status);
10234
10235 return (status);
10236 }
10237
10238 /*
10239 * vxge_hal_vpath_hw_stats_enable - Enable vpath h/wstatistics.
10240 * @vpath_handle: Virtual Path handle.
10241 *
10242 * Enable the DMA vpath statistics. The function is to be called to re-enable
10243 * the adapter to update stats into the host memory
10244 *
10245 * See also: vxge_hal_vpath_hw_stats_disable(), vxge_hal_vpath_hw_stats_get()
10246 */
10247 vxge_hal_status_e
vxge_hal_vpath_hw_stats_enable(vxge_hal_vpath_h vpath_handle)10248 vxge_hal_vpath_hw_stats_enable(vxge_hal_vpath_h vpath_handle)
10249 {
10250 u64 val64;
10251 vxge_hal_status_e status = VXGE_HAL_OK;
10252 __hal_device_t *hldev;
10253 __hal_virtualpath_t *vpath;
10254 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
10255
10256 vxge_assert(vpath_handle != NULL);
10257
10258 hldev = vp->vpath->hldev;
10259
10260 vxge_hal_trace_log_stats("==> %s:%s:%d",
10261 __FILE__, __func__, __LINE__);
10262
10263 vxge_hal_trace_log_stats("vpath = 0x"VXGE_OS_STXFMT,
10264 (ptr_t) vpath_handle);
10265
10266 vpath = vp->vpath;
10267
10268 if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
10269 vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d",
10270 __FILE__, __func__, __LINE__,
10271 VXGE_HAL_ERR_VPATH_NOT_OPEN);
10272 return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
10273 }
10274
10275 vxge_os_memcpy(vpath->hw_stats_sav,
10276 vpath->hw_stats,
10277 sizeof(vxge_hal_vpath_stats_hw_info_t));
10278
10279 if (hldev->header.config.stats_read_method ==
10280 VXGE_HAL_STATS_READ_METHOD_DMA) {
10281 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
10282 hldev->header.regh0,
10283 &hldev->common_reg->stats_cfg0);
10284
10285 val64 |= VXGE_HAL_STATS_CFG0_STATS_ENABLE(
10286 (1 << (16 - vpath->vp_id)));
10287
10288 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
10289 hldev->header.regh0,
10290 (u32) bVAL32(val64, 0),
10291 &hldev->common_reg->stats_cfg0);
10292 } else {
10293 status = __hal_vpath_hw_stats_get(
10294 vpath,
10295 vpath->hw_stats);
10296 }
10297
10298 vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d",
10299 __FILE__, __func__, __LINE__, status);
10300
10301 return (VXGE_HAL_OK);
10302 }
10303
10304 /*
10305 * vxge_hal_vpath_hw_stats_disable - Disable vpath h/w statistics.
10306 * @vpath_handle: Virtual Path handle.
10307 *
10308 * Enable the DMA vpath statistics. The function is to be called to disable
10309 * the adapter to update stats into the host memory. This function is not
10310 * needed to be called, normally.
10311 *
10312 * See also: vxge_hal_vpath_hw_stats_enable(), vxge_hal_vpath_hw_stats_get()
10313 */
10314 vxge_hal_status_e
vxge_hal_vpath_hw_stats_disable(vxge_hal_vpath_h vpath_handle)10315 vxge_hal_vpath_hw_stats_disable(vxge_hal_vpath_h vpath_handle)
10316 {
10317 u64 val64;
10318 __hal_device_t *hldev;
10319 __hal_virtualpath_t *vpath;
10320 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
10321
10322 vxge_assert(vpath_handle != NULL);
10323
10324 hldev = vp->vpath->hldev;
10325
10326 vxge_hal_trace_log_stats("==> %s:%s:%d",
10327 __FILE__, __func__, __LINE__);
10328
10329 vxge_hal_trace_log_stats(
10330 "vpath = 0x"VXGE_OS_STXFMT, (ptr_t) vpath_handle);
10331
10332 vpath = (__hal_virtualpath_t *)
10333 ((__hal_vpath_handle_t *) vpath_handle)->vpath;
10334
10335 if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
10336 vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d",
10337 __FILE__, __func__, __LINE__,
10338 VXGE_HAL_ERR_VPATH_NOT_OPEN);
10339 return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
10340 }
10341
10342 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
10343 hldev->header.regh0,
10344 &hldev->common_reg->stats_cfg0);
10345
10346 val64 &= ~VXGE_HAL_STATS_CFG0_STATS_ENABLE((1 << (16 - vpath->vp_id)));
10347
10348 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
10349 hldev->header.regh0,
10350 (u32) bVAL32(val64, 0),
10351 &hldev->common_reg->stats_cfg0);
10352
10353 vxge_hal_trace_log_stats("<== %s:%s:%d Result: 0",
10354 __FILE__, __func__, __LINE__);
10355
10356 return (VXGE_HAL_OK);
10357 }
10358
10359 /*
10360 * vxge_hal_vpath_hw_stats_get - Get the vpath hw statistics.
10361 * @vpath_handle: Virtual Path handle.
10362 * @hw_stats: Hardware stats
10363 *
10364 * Returns the vpath h/w stats.
10365 *
10366 * See also: vxge_hal_vpath_hw_stats_enable(),
10367 * vxge_hal_vpath_hw_stats_disable()
10368 */
10369 vxge_hal_status_e
vxge_hal_vpath_hw_stats_get(vxge_hal_vpath_h vpath_handle,vxge_hal_vpath_stats_hw_info_t * hw_stats)10370 vxge_hal_vpath_hw_stats_get(vxge_hal_vpath_h vpath_handle,
10371 vxge_hal_vpath_stats_hw_info_t *hw_stats)
10372 {
10373 __hal_virtualpath_t *vpath;
10374 __hal_device_t *hldev;
10375 vxge_hal_status_e status;
10376 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
10377
10378 vxge_assert((vpath_handle != NULL) && (hw_stats != NULL));
10379
10380 hldev = vp->vpath->hldev;
10381
10382 vxge_hal_trace_log_stats("==> %s:%s:%d",
10383 __FILE__, __func__, __LINE__);
10384
10385 vxge_hal_trace_log_stats(
10386 "vpath = 0x"VXGE_OS_STXFMT", hw_stats = 0x"VXGE_OS_STXFMT,
10387 (ptr_t) vpath_handle, (ptr_t) hw_stats);
10388
10389 vpath = (__hal_virtualpath_t *)
10390 ((__hal_vpath_handle_t *) vpath_handle)->vpath;
10391
10392 if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
10393 vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d",
10394 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
10395 return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
10396 }
10397
10398 status = vxge_hal_device_register_poll(hldev->header.pdev,
10399 hldev->header.regh0,
10400 &hldev->common_reg->stats_cfg0,
10401 0,
10402 VXGE_HAL_STATS_CFG0_STATS_ENABLE((1 << (16 - vpath->vp_id))),
10403 hldev->header.config.device_poll_millis);
10404
10405 if (status == VXGE_HAL_OK) {
10406 vxge_os_memcpy(hw_stats,
10407 vpath->hw_stats,
10408 sizeof(vxge_hal_vpath_stats_hw_info_t));
10409 }
10410
10411 vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d",
10412 __FILE__, __func__, __LINE__, status);
10413 return (status);
10414 }
10415
10416 /*
10417 * vxge_hal_vpath_sw_stats_get - Get the vpath sw statistics.
10418 * @vpath_handle: Virtual Path handle.
10419 * @sw_stats: Software stats
10420 *
10421 * Returns the vpath s/w stats.
10422 *
10423 * See also: vxge_hal_vpath_hw_stats_get()
10424 */
10425 vxge_hal_status_e
vxge_hal_vpath_sw_stats_get(vxge_hal_vpath_h vpath_handle,vxge_hal_vpath_stats_sw_info_t * sw_stats)10426 vxge_hal_vpath_sw_stats_get(vxge_hal_vpath_h vpath_handle,
10427 vxge_hal_vpath_stats_sw_info_t *sw_stats)
10428 {
10429 __hal_device_t *hldev;
10430 __hal_virtualpath_t *vpath;
10431 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
10432
10433 vxge_assert((vpath_handle != NULL) && (sw_stats != NULL));
10434
10435 hldev = vp->vpath->hldev;
10436
10437 vxge_hal_trace_log_stats("==> %s:%s:%d",
10438 __FILE__, __func__, __LINE__);
10439
10440 vxge_hal_trace_log_stats(
10441 "vpath = 0x"VXGE_OS_STXFMT", sw_stats = 0x"VXGE_OS_STXFMT,
10442 (ptr_t) vpath_handle, (ptr_t) sw_stats);
10443
10444 vpath = (__hal_virtualpath_t *)
10445 ((__hal_vpath_handle_t *) vpath_handle)->vpath;
10446
10447 if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
10448 vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d",
10449 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
10450
10451 return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
10452 }
10453
10454 if (hldev->header.traffic_intr_cnt) {
10455 int intrcnt = hldev->header.traffic_intr_cnt;
10456
10457 if (!intrcnt)
10458 intrcnt = 1;
10459
10460 vpath->sw_stats->fifo_stats.common_stats.avg_compl_per_intr_cnt =
10461 vpath->sw_stats->fifo_stats.common_stats.total_compl_cnt / intrcnt;
10462
10463 if (vpath->sw_stats->fifo_stats.common_stats.avg_compl_per_intr_cnt ==
10464 0) {
10465 /* to not confuse user */
10466 vpath->sw_stats->fifo_stats.common_stats.avg_compl_per_intr_cnt = 1;
10467 }
10468
10469 vpath->sw_stats->ring_stats.common_stats.avg_compl_per_intr_cnt =
10470 vpath->sw_stats->ring_stats.common_stats.total_compl_cnt / intrcnt;
10471
10472 if (vpath->sw_stats->ring_stats.common_stats.avg_compl_per_intr_cnt ==
10473 0) {
10474 /* to not confuse user */
10475 vpath->sw_stats->ring_stats.common_stats.avg_compl_per_intr_cnt = 1;
10476 }
10477 }
10478
10479 if (vpath->sw_stats->fifo_stats.total_posts) {
10480 vpath->sw_stats->fifo_stats.avg_buffers_per_post =
10481 vpath->sw_stats->fifo_stats.total_buffers /
10482 vpath->sw_stats->fifo_stats.total_posts;
10483
10484 vpath->sw_stats->fifo_stats.avg_post_size =
10485 (u32) (vpath->hw_stats->tx_stats.tx_ttl_eth_octets /
10486 vpath->sw_stats->fifo_stats.total_posts);
10487 }
10488
10489 if (vpath->sw_stats->fifo_stats.total_buffers) {
10490 vpath->sw_stats->fifo_stats.avg_buffer_size =
10491 (u32) (vpath->hw_stats->tx_stats.tx_ttl_eth_octets /
10492 vpath->sw_stats->fifo_stats.total_buffers);
10493 }
10494
10495 vxge_os_memcpy(sw_stats,
10496 vpath->sw_stats,
10497 sizeof(vxge_hal_vpath_stats_sw_info_t));
10498
10499 vxge_hal_trace_log_stats("<== %s:%s:%d Result: 0",
10500 __FILE__, __func__, __LINE__);
10501 return (VXGE_HAL_OK);
10502 }
10503
10504 /*
10505 * __hal_vpath_stats_access - Get the statistics from the given location
10506 * and offset and perform an operation
10507 * @vpath: Virtual path.
10508 * @operation: Operation to be performed
10509 * @location: Location (one of vpath id, aggregate or port)
10510 * @offset: Offset with in the location
10511 * @stat: Pointer to a buffer to return the value
10512 *
10513 * Get the statistics from the given location and offset.
10514 *
10515 */
10516 vxge_hal_status_e
__hal_vpath_stats_access(__hal_virtualpath_t * vpath,u32 operation,u32 offset,u64 * stat)10517 __hal_vpath_stats_access(
10518 __hal_virtualpath_t *vpath,
10519 u32 operation,
10520 u32 offset,
10521 u64 *stat)
10522 {
10523 u64 val64;
10524 __hal_device_t *hldev;
10525 vxge_hal_status_e status = VXGE_HAL_OK;
10526
10527 vxge_assert(vpath != NULL);
10528
10529 hldev = vpath->hldev;
10530
10531 vxge_hal_trace_log_stats("==> %s:%s:%d",
10532 __FILE__, __func__, __LINE__);
10533
10534 vxge_hal_trace_log_stats("vpath = 0x"VXGE_OS_STXFMT,
10535 (ptr_t) vpath);
10536
10537 if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
10538 vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d",
10539 __FILE__, __func__, __LINE__,
10540 VXGE_HAL_ERR_VPATH_NOT_OPEN);
10541
10542 return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
10543 }
10544
10545 val64 = VXGE_HAL_XMAC_STATS_ACCESS_CMD_OP(operation) |
10546 VXGE_HAL_XMAC_STATS_ACCESS_CMD_STROBE |
10547 VXGE_HAL_XMAC_STATS_ACCESS_CMD_OFFSET_SEL(offset);
10548
10549 vxge_hal_pio_mem_write32_lower(hldev->header.pdev,
10550 hldev->header.regh0,
10551 (u32) bVAL32(val64, 32),
10552 &vpath->vp_reg->xmac_stats_access_cmd);
10553 vxge_os_wmb();
10554
10555 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
10556 hldev->header.regh0,
10557 (u32) bVAL32(val64, 0),
10558 &vpath->vp_reg->xmac_stats_access_cmd);
10559 vxge_os_wmb();
10560
10561 status = vxge_hal_device_register_poll(hldev->header.pdev,
10562 hldev->header.regh0,
10563 &vpath->vp_reg->xmac_stats_access_cmd,
10564 0,
10565 VXGE_HAL_XMAC_STATS_ACCESS_CMD_STROBE,
10566 hldev->header.config.device_poll_millis);
10567
10568 if ((status == VXGE_HAL_OK) && (operation == VXGE_HAL_STATS_OP_READ)) {
10569
10570 *stat = vxge_os_pio_mem_read64(hldev->header.pdev,
10571 hldev->header.regh0,
10572 &vpath->vp_reg->xmac_stats_access_data);
10573
10574 } else {
10575 *stat = 0;
10576 }
10577
10578 vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d",
10579 __FILE__, __func__, __LINE__, status);
10580 return (status);
10581 }
10582
10583 /*
10584 * vxge_hal_vpath_stats_access
10585 * Get statistics from given location and offset to perform an operation
10586 * @vpath_handle: Virtual path handle.
10587 * @operation: Operation to be performed
10588 * @offset: Offset with in the location
10589 * @stat: Pointer to a buffer to return the value
10590 *
10591 * Get the statistics from the given location and offset.
10592 *
10593 */
10594 vxge_hal_status_e
vxge_hal_vpath_stats_access(vxge_hal_vpath_h vpath_handle,u32 operation,u32 offset,u64 * stat)10595 vxge_hal_vpath_stats_access(
10596 vxge_hal_vpath_h vpath_handle,
10597 u32 operation,
10598 u32 offset,
10599 u64 *stat)
10600 {
10601 __hal_device_t *hldev;
10602 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
10603 vxge_hal_status_e status;
10604
10605 vxge_assert(vpath_handle != NULL);
10606
10607 hldev = vp->vpath->hldev;
10608
10609 vxge_hal_trace_log_stats("==> %s:%s:%d",
10610 __FILE__, __func__, __LINE__);
10611
10612 vxge_hal_trace_log_stats(
10613 "vpath_handle = 0x"VXGE_OS_STXFMT, (ptr_t) vpath_handle);
10614
10615 status = __hal_vpath_stats_access(vp->vpath,
10616 operation,
10617 offset,
10618 stat);
10619
10620 vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d",
10621 __FILE__, __func__, __LINE__, status);
10622
10623 return (status);
10624 }
10625
10626 /*
10627 * __hal_vpath_xmac_tx_stats_get - Get the TX Statistics of a vpath
10628 * @vpath: vpath
10629 * @vpath_tx_stats: Buffer to return TX Statistics of vpath.
10630 *
10631 * Get the TX Statistics of a vpath
10632 *
10633 */
10634 vxge_hal_status_e
__hal_vpath_xmac_tx_stats_get(__hal_virtualpath_t * vpath,vxge_hal_xmac_vpath_tx_stats_t * vpath_tx_stats)10635 __hal_vpath_xmac_tx_stats_get(__hal_virtualpath_t *vpath,
10636 vxge_hal_xmac_vpath_tx_stats_t *vpath_tx_stats)
10637 {
10638 u64 val64;
10639 __hal_device_t *hldev;
10640 vxge_hal_status_e status;
10641
10642 vxge_assert(vpath != NULL);
10643
10644 hldev = vpath->hldev;
10645
10646 vxge_hal_trace_log_stats("==> %s:%s:%d",
10647 __FILE__, __func__, __LINE__);
10648
10649 vxge_hal_trace_log_stats("vpath = 0x"VXGE_OS_STXFMT,
10650 (ptr_t) vpath);
10651
10652 if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
10653 vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d",
10654 __FILE__, __func__,
10655 __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
10656 return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
10657 }
10658
10659 VXGE_HAL_VPATH_STATS_PIO_READ(
10660 VXGE_HAL_STATS_VPATH_TX_TTL_ETH_FRMS_OFFSET);
10661
10662 vpath_tx_stats->tx_ttl_eth_frms =
10663 VXGE_HAL_STATS_GET_VPATH_TX_TTL_ETH_FRMS(val64);
10664
10665 VXGE_HAL_VPATH_STATS_PIO_READ(
10666 VXGE_HAL_STATS_VPATH_TX_TTL_ETH_OCTETS_OFFSET);
10667
10668 vpath_tx_stats->tx_ttl_eth_octets =
10669 VXGE_HAL_STATS_GET_VPATH_TX_TTL_ETH_OCTETS(val64);
10670
10671 VXGE_HAL_VPATH_STATS_PIO_READ(
10672 VXGE_HAL_STATS_VPATH_TX_DATA_OCTETS_OFFSET);
10673
10674 vpath_tx_stats->tx_data_octets =
10675 VXGE_HAL_STATS_GET_VPATH_TX_DATA_OCTETS(val64);
10676
10677 VXGE_HAL_VPATH_STATS_PIO_READ(
10678 VXGE_HAL_STATS_VPATH_TX_MCAST_FRMS_OFFSET);
10679
10680 vpath_tx_stats->tx_mcast_frms =
10681 VXGE_HAL_STATS_GET_VPATH_TX_MCAST_FRMS(val64);
10682
10683 VXGE_HAL_VPATH_STATS_PIO_READ(
10684 VXGE_HAL_STATS_VPATH_TX_BCAST_FRMS_OFFSET);
10685
10686 vpath_tx_stats->tx_bcast_frms =
10687 VXGE_HAL_STATS_GET_VPATH_TX_BCAST_FRMS(val64);
10688
10689 VXGE_HAL_VPATH_STATS_PIO_READ(
10690 VXGE_HAL_STATS_VPATH_TX_UCAST_FRMS_OFFSET);
10691
10692 vpath_tx_stats->tx_ucast_frms =
10693 VXGE_HAL_STATS_GET_VPATH_TX_UCAST_FRMS(val64);
10694
10695 VXGE_HAL_VPATH_STATS_PIO_READ(
10696 VXGE_HAL_STATS_VPATH_TX_TAGGED_FRMS_OFFSET);
10697
10698 vpath_tx_stats->tx_tagged_frms =
10699 VXGE_HAL_STATS_GET_VPATH_TX_TAGGED_FRMS(val64);
10700
10701 VXGE_HAL_VPATH_STATS_PIO_READ(VXGE_HAL_STATS_VPATH_TX_VLD_IP_OFFSET);
10702
10703 vpath_tx_stats->tx_vld_ip =
10704 VXGE_HAL_STATS_GET_VPATH_TX_VLD_IP(val64);
10705
10706 VXGE_HAL_VPATH_STATS_PIO_READ(
10707 VXGE_HAL_STATS_VPATH_TX_VLD_IP_OCTETS_OFFSET);
10708
10709 vpath_tx_stats->tx_vld_ip_octets =
10710 VXGE_HAL_STATS_GET_VPATH_TX_VLD_IP_OCTETS(val64);
10711
10712 VXGE_HAL_VPATH_STATS_PIO_READ(VXGE_HAL_STATS_VPATH_TX_ICMP_OFFSET);
10713
10714 vpath_tx_stats->tx_icmp =
10715 VXGE_HAL_STATS_GET_VPATH_TX_ICMP(val64);
10716
10717 VXGE_HAL_VPATH_STATS_PIO_READ(VXGE_HAL_STATS_VPATH_TX_TCP_OFFSET);
10718
10719 vpath_tx_stats->tx_tcp =
10720 VXGE_HAL_STATS_GET_VPATH_TX_TCP(val64);
10721
10722 VXGE_HAL_VPATH_STATS_PIO_READ(
10723 VXGE_HAL_STATS_VPATH_TX_RST_TCP_OFFSET);
10724
10725 vpath_tx_stats->tx_rst_tcp =
10726 VXGE_HAL_STATS_GET_VPATH_TX_RST_TCP(val64);
10727
10728 VXGE_HAL_VPATH_STATS_PIO_READ(
10729 VXGE_HAL_STATS_VPATH_TX_UDP_OFFSET);
10730
10731 vpath_tx_stats->tx_udp =
10732 VXGE_HAL_STATS_GET_VPATH_TX_UDP(val64);
10733
10734 VXGE_HAL_VPATH_STATS_PIO_READ(
10735 VXGE_HAL_STATS_VPATH_TX_LOST_IP_OFFSET);
10736
10737 vpath_tx_stats->tx_lost_ip =
10738 (u32) VXGE_HAL_STATS_GET_VPATH_TX_LOST_IP(val64);
10739
10740 VXGE_HAL_VPATH_STATS_PIO_READ(
10741 VXGE_HAL_STATS_VPATH_TX_UNKNOWN_PROTOCOL_OFFSET);
10742
10743 vpath_tx_stats->tx_unknown_protocol =
10744 (u32) VXGE_HAL_STATS_GET_VPATH_TX_UNKNOWN_PROTOCOL(val64);
10745
10746 VXGE_HAL_VPATH_STATS_PIO_READ(
10747 VXGE_HAL_STATS_VPATH_TX_PARSE_ERROR_OFFSET);
10748
10749 vpath_tx_stats->tx_parse_error =
10750 (u32) VXGE_HAL_STATS_GET_VPATH_TX_PARSE_ERROR(val64);
10751
10752 VXGE_HAL_VPATH_STATS_PIO_READ(
10753 VXGE_HAL_STATS_VPATH_TX_TCP_OFFLOAD_OFFSET);
10754
10755 vpath_tx_stats->tx_tcp_offload =
10756 VXGE_HAL_STATS_GET_VPATH_TX_TCP_OFFLOAD(val64);
10757
10758 VXGE_HAL_VPATH_STATS_PIO_READ(
10759 VXGE_HAL_STATS_VPATH_TX_RETX_TCP_OFFLOAD_OFFSET);
10760
10761 vpath_tx_stats->tx_retx_tcp_offload =
10762 VXGE_HAL_STATS_GET_VPATH_TX_RETX_TCP_OFFLOAD(val64);
10763
10764 VXGE_HAL_VPATH_STATS_PIO_READ(
10765 VXGE_HAL_STATS_VPATH_TX_LOST_IP_OFFLOAD_OFFSET);
10766
10767 vpath_tx_stats->tx_lost_ip_offload =
10768 VXGE_HAL_STATS_GET_VPATH_TX_LOST_IP_OFFLOAD(val64);
10769
10770 vxge_hal_trace_log_stats("<== %s:%s:%d Result: 0",
10771 __FILE__, __func__, __LINE__);
10772 return (VXGE_HAL_OK);
10773 }
10774
10775 /*
10776 * __hal_vpath_xmac_rx_stats_get - Get the RX Statistics of a vpath
10777 * @vpath: vpath
10778 * @vpath_rx_stats: Buffer to return RX Statistics of vpath.
10779 *
10780 * Get the RX Statistics of a vpath
10781 *
10782 */
10783 vxge_hal_status_e
__hal_vpath_xmac_rx_stats_get(__hal_virtualpath_t * vpath,vxge_hal_xmac_vpath_rx_stats_t * vpath_rx_stats)10784 __hal_vpath_xmac_rx_stats_get(__hal_virtualpath_t *vpath,
10785 vxge_hal_xmac_vpath_rx_stats_t *vpath_rx_stats)
10786 {
10787 u64 val64;
10788 __hal_device_t *hldev;
10789 vxge_hal_status_e status;
10790
10791 vxge_assert(vpath != NULL);
10792
10793 hldev = vpath->hldev;
10794
10795 vxge_hal_trace_log_stats("==> %s:%s:%d",
10796 __FILE__, __func__, __LINE__);
10797
10798 vxge_hal_trace_log_stats("vpath = 0x"VXGE_OS_STXFMT,
10799 (ptr_t) vpath);
10800
10801 if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
10802 vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d",
10803 __FILE__, __func__, __LINE__,
10804 VXGE_HAL_ERR_VPATH_NOT_OPEN);
10805 return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
10806 }
10807
10808 VXGE_HAL_VPATH_STATS_PIO_READ(
10809 VXGE_HAL_STATS_VPATH_RX_TTL_ETH_FRMS_OFFSET);
10810
10811 vpath_rx_stats->rx_ttl_eth_frms =
10812 VXGE_HAL_STATS_GET_VPATH_RX_TTL_ETH_FRMS(val64);
10813
10814 VXGE_HAL_VPATH_STATS_PIO_READ(VXGE_HAL_STATS_VPATH_RX_VLD_FRMS_OFFSET);
10815
10816 vpath_rx_stats->rx_vld_frms =
10817 VXGE_HAL_STATS_GET_VPATH_RX_VLD_FRMS(val64);
10818
10819 VXGE_HAL_VPATH_STATS_PIO_READ(
10820 VXGE_HAL_STATS_VPATH_RX_OFFLOAD_FRMS_OFFSET);
10821
10822 vpath_rx_stats->rx_offload_frms =
10823 VXGE_HAL_STATS_GET_VPATH_RX_OFFLOAD_FRMS(val64);
10824
10825 VXGE_HAL_VPATH_STATS_PIO_READ(
10826 VXGE_HAL_STATS_VPATH_RX_TTL_ETH_OCTETS_OFFSET);
10827
10828 vpath_rx_stats->rx_ttl_eth_octets =
10829 VXGE_HAL_STATS_GET_VPATH_RX_TTL_ETH_OCTETS(val64);
10830
10831 VXGE_HAL_VPATH_STATS_PIO_READ(
10832 VXGE_HAL_STATS_VPATH_RX_DATA_OCTETS_OFFSET);
10833
10834 vpath_rx_stats->rx_data_octets =
10835 VXGE_HAL_STATS_GET_VPATH_RX_DATA_OCTETS(val64);
10836
10837 VXGE_HAL_VPATH_STATS_PIO_READ(
10838 VXGE_HAL_STATS_VPATH_RX_OFFLOAD_OCTETS_OFFSET);
10839
10840 vpath_rx_stats->rx_offload_octets =
10841 VXGE_HAL_STATS_GET_VPATH_RX_OFFLOAD_OCTETS(val64);
10842
10843 VXGE_HAL_VPATH_STATS_PIO_READ(
10844 VXGE_HAL_STATS_VPATH_RX_VLD_MCAST_FRMS_OFFSET);
10845
10846 vpath_rx_stats->rx_vld_mcast_frms =
10847 VXGE_HAL_STATS_GET_VPATH_RX_VLD_MCAST_FRMS(val64);
10848
10849 VXGE_HAL_VPATH_STATS_PIO_READ(
10850 VXGE_HAL_STATS_VPATH_RX_VLD_BCAST_FRMS_OFFSET);
10851
10852 vpath_rx_stats->rx_vld_bcast_frms =
10853 VXGE_HAL_STATS_GET_VPATH_RX_VLD_BCAST_FRMS(val64);
10854
10855 VXGE_HAL_VPATH_STATS_PIO_READ(
10856 VXGE_HAL_STATS_VPATH_RX_ACC_UCAST_FRMS_OFFSET);
10857
10858 vpath_rx_stats->rx_accepted_ucast_frms =
10859 VXGE_HAL_STATS_GET_VPATH_RX_ACC_UCAST_FRMS(val64);
10860
10861 VXGE_HAL_VPATH_STATS_PIO_READ(
10862 VXGE_HAL_STATS_VPATH_RX_ACC_NUCAST_FRMS_OFFSET);
10863
10864 vpath_rx_stats->rx_accepted_nucast_frms =
10865 VXGE_HAL_STATS_GET_VPATH_RX_ACC_NUCAST_FRMS(val64);
10866
10867 VXGE_HAL_VPATH_STATS_PIO_READ(
10868 VXGE_HAL_STATS_VPATH_RX_TAGGED_FRMS_OFFSET);
10869
10870 vpath_rx_stats->rx_tagged_frms =
10871 VXGE_HAL_STATS_GET_VPATH_RX_TAGGED_FRMS(val64);
10872
10873 VXGE_HAL_VPATH_STATS_PIO_READ(
10874 VXGE_HAL_STATS_VPATH_RX_LONG_FRMS_OFFSET);
10875
10876 vpath_rx_stats->rx_long_frms =
10877 VXGE_HAL_STATS_GET_VPATH_RX_LONG_FRMS(val64);
10878
10879 VXGE_HAL_VPATH_STATS_PIO_READ(
10880 VXGE_HAL_STATS_VPATH_RX_USIZED_FRMS_OFFSET);
10881
10882 vpath_rx_stats->rx_usized_frms =
10883 VXGE_HAL_STATS_GET_VPATH_RX_USIZED_FRMS(val64);
10884
10885 VXGE_HAL_VPATH_STATS_PIO_READ(
10886 VXGE_HAL_STATS_VPATH_RX_OSIZED_FRMS_OFFSET);
10887
10888 vpath_rx_stats->rx_osized_frms =
10889 VXGE_HAL_STATS_GET_VPATH_RX_OSIZED_FRMS(val64);
10890
10891 VXGE_HAL_VPATH_STATS_PIO_READ(
10892 VXGE_HAL_STATS_VPATH_RX_FRAG_FRMS_OFFSET);
10893
10894 vpath_rx_stats->rx_frag_frms =
10895 VXGE_HAL_STATS_GET_VPATH_RX_FRAG_FRMS(val64);
10896
10897 VXGE_HAL_VPATH_STATS_PIO_READ(
10898 VXGE_HAL_STATS_VPATH_RX_JABBER_FRMS_OFFSET);
10899
10900 vpath_rx_stats->rx_jabber_frms =
10901 VXGE_HAL_STATS_GET_VPATH_RX_JABBER_FRMS(val64);
10902
10903 VXGE_HAL_VPATH_STATS_PIO_READ(
10904 VXGE_HAL_STATS_VPATH_RX_TTL_64_FRMS_OFFSET);
10905
10906 vpath_rx_stats->rx_ttl_64_frms =
10907 VXGE_HAL_STATS_GET_VPATH_RX_TTL_64_FRMS(val64);
10908
10909 VXGE_HAL_VPATH_STATS_PIO_READ(
10910 VXGE_HAL_STATS_VPATH_RX_TTL_65_127_FRMS_OFFSET);
10911
10912 vpath_rx_stats->rx_ttl_65_127_frms =
10913 VXGE_HAL_STATS_GET_VPATH_RX_TTL_65_127_FRMS(val64);
10914
10915 VXGE_HAL_VPATH_STATS_PIO_READ(
10916 VXGE_HAL_STATS_VPATH_RX_TTL_128_255_FRMS_OFFSET);
10917
10918 vpath_rx_stats->rx_ttl_128_255_frms =
10919 VXGE_HAL_STATS_GET_VPATH_RX_TTL_128_255_FRMS(val64);
10920
10921 VXGE_HAL_VPATH_STATS_PIO_READ(
10922 VXGE_HAL_STATS_VPATH_RX_TTL_256_511_FRMS_OFFSET);
10923
10924 vpath_rx_stats->rx_ttl_256_511_frms =
10925 VXGE_HAL_STATS_GET_VPATH_RX_TTL_256_511_FRMS(val64);
10926
10927 VXGE_HAL_VPATH_STATS_PIO_READ(
10928 VXGE_HAL_STATS_VPATH_RX_TTL_512_1023_FRMS_OFFSET);
10929
10930 vpath_rx_stats->rx_ttl_512_1023_frms =
10931 VXGE_HAL_STATS_GET_VPATH_RX_TTL_512_1023_FRMS(val64);
10932
10933 VXGE_HAL_VPATH_STATS_PIO_READ(
10934 VXGE_HAL_STATS_VPATH_RX_TTL_1024_1518_FRMS_OFFSET);
10935
10936 vpath_rx_stats->rx_ttl_1024_1518_frms =
10937 VXGE_HAL_STATS_GET_VPATH_RX_TTL_1024_1518_FRMS(val64);
10938
10939 VXGE_HAL_VPATH_STATS_PIO_READ(
10940 VXGE_HAL_STATS_VPATH_RX_TTL_1519_4095_FRMS_OFFSET);
10941
10942 vpath_rx_stats->rx_ttl_1519_4095_frms =
10943 VXGE_HAL_STATS_GET_VPATH_RX_TTL_1519_4095_FRMS(val64);
10944
10945 VXGE_HAL_VPATH_STATS_PIO_READ(
10946 VXGE_HAL_STATS_VPATH_RX_TTL_4096_8191_FRMS_OFFSET);
10947
10948 vpath_rx_stats->rx_ttl_4096_8191_frms =
10949 VXGE_HAL_STATS_GET_VPATH_RX_TTL_4096_8191_FRMS(val64);
10950
10951 VXGE_HAL_VPATH_STATS_PIO_READ(
10952 VXGE_HAL_STATS_VPATH_RX_TTL_8192_MAX_FRMS_OFFSET);
10953
10954 vpath_rx_stats->rx_ttl_8192_max_frms =
10955 VXGE_HAL_STATS_GET_VPATH_RX_TTL_8192_MAX_FRMS(val64);
10956
10957 VXGE_HAL_VPATH_STATS_PIO_READ(
10958 VXGE_HAL_STATS_VPATH_RX_TTL_GT_MAX_FRMS_OFFSET);
10959
10960 vpath_rx_stats->rx_ttl_gt_max_frms =
10961 VXGE_HAL_STATS_GET_VPATH_RX_TTL_GT_MAX_FRMS(val64);
10962
10963 VXGE_HAL_VPATH_STATS_PIO_READ(VXGE_HAL_STATS_VPATH_RX_IP_OFFSET);
10964
10965 vpath_rx_stats->rx_ip =
10966 VXGE_HAL_STATS_GET_VPATH_RX_IP(val64);
10967
10968 VXGE_HAL_VPATH_STATS_PIO_READ(VXGE_HAL_STATS_VPATH_RX_ACC_IP_OFFSET);
10969
10970 vpath_rx_stats->rx_accepted_ip =
10971 VXGE_HAL_STATS_GET_VPATH_RX_ACC_IP(val64);
10972
10973 VXGE_HAL_VPATH_STATS_PIO_READ(VXGE_HAL_STATS_VPATH_RX_IP_OCTETS_OFFSET);
10974
10975 vpath_rx_stats->rx_ip_octets =
10976 VXGE_HAL_STATS_GET_VPATH_RX_IP_OCTETS(val64);
10977
10978 VXGE_HAL_VPATH_STATS_PIO_READ(VXGE_HAL_STATS_VPATH_RX_ERR_IP_OFFSET);
10979
10980 vpath_rx_stats->rx_err_ip =
10981 VXGE_HAL_STATS_GET_VPATH_RX_ERR_IP(val64);
10982
10983 VXGE_HAL_VPATH_STATS_PIO_READ(VXGE_HAL_STATS_VPATH_RX_ICMP_OFFSET);
10984
10985 vpath_rx_stats->rx_icmp =
10986 VXGE_HAL_STATS_GET_VPATH_RX_ICMP(val64);
10987
10988 VXGE_HAL_VPATH_STATS_PIO_READ(VXGE_HAL_STATS_VPATH_RX_TCP_OFFSET);
10989
10990 vpath_rx_stats->rx_tcp =
10991 VXGE_HAL_STATS_GET_VPATH_RX_TCP(val64);
10992
10993 VXGE_HAL_VPATH_STATS_PIO_READ(VXGE_HAL_STATS_VPATH_RX_UDP_OFFSET);
10994
10995 vpath_rx_stats->rx_udp =
10996 VXGE_HAL_STATS_GET_VPATH_RX_UDP(val64);
10997
10998 VXGE_HAL_VPATH_STATS_PIO_READ(VXGE_HAL_STATS_VPATH_RX_ERR_TCP_OFFSET);
10999
11000 vpath_rx_stats->rx_err_tcp =
11001 VXGE_HAL_STATS_GET_VPATH_RX_ERR_TCP(val64);
11002
11003 VXGE_HAL_VPATH_STATS_PIO_READ(
11004 VXGE_HAL_STATS_VPATH_RX_LOST_FRMS_OFFSET);
11005
11006 vpath_rx_stats->rx_lost_frms =
11007 VXGE_HAL_STATS_GET_VPATH_RX_LOST_FRMS(val64);
11008
11009 VXGE_HAL_VPATH_STATS_PIO_READ(VXGE_HAL_STATS_VPATH_RX_LOST_IP_OFFSET);
11010
11011 vpath_rx_stats->rx_lost_ip =
11012 VXGE_HAL_STATS_GET_VPATH_RX_LOST_IP(val64);
11013
11014 VXGE_HAL_VPATH_STATS_PIO_READ(
11015 VXGE_HAL_STATS_VPATH_RX_LOST_IP_OFFLOAD_OFFSET);
11016
11017 vpath_rx_stats->rx_lost_ip_offload =
11018 VXGE_HAL_STATS_GET_VPATH_RX_LOST_IP_OFFLOAD(val64);
11019
11020 VXGE_HAL_VPATH_STATS_PIO_READ(
11021 VXGE_HAL_STATS_VPATH_RX_QUEUE_FULL_DISCARD_OFFSET);
11022
11023 vpath_rx_stats->rx_queue_full_discard =
11024 (u16) VXGE_HAL_STATS_GET_VPATH_RX_QUEUE_FULL_DISCARD(val64);
11025
11026 VXGE_HAL_VPATH_STATS_PIO_READ(
11027 VXGE_HAL_STATS_VPATH_RX_RED_DISCARD_OFFSET);
11028
11029 vpath_rx_stats->rx_red_discard =
11030 (u16) VXGE_HAL_STATS_GET_VPATH_RX_RED_DISCARD(val64);
11031
11032 VXGE_HAL_VPATH_STATS_PIO_READ(
11033 VXGE_HAL_STATS_VPATH_RX_SLEEP_DISCARD_OFFSET);
11034
11035 vpath_rx_stats->rx_sleep_discard =
11036 (u16) VXGE_HAL_STATS_GET_VPATH_RX_SLEEP_DISCARD(val64);
11037
11038 vpath_rx_stats->rx_various_discard =
11039 vpath_rx_stats->rx_queue_full_discard;
11040
11041 VXGE_HAL_VPATH_STATS_PIO_READ(
11042 VXGE_HAL_STATS_VPATH_RX_MPA_OK_FRMS_OFFSET);
11043
11044 vpath_rx_stats->rx_mpa_ok_frms =
11045 VXGE_HAL_STATS_GET_VPATH_RX_MPA_OK_FRMS(val64);
11046
11047 vxge_hal_trace_log_stats("<== %s:%s:%d Result: 0",
11048 __FILE__, __func__, __LINE__);
11049 return (VXGE_HAL_OK);
11050 }
11051
11052 /*
11053 * vxge_hal_vpath_xmac_tx_stats_get - Get the TX Statistics of a vpath
11054 * @vpath_handle: vpath handle.
11055 * @vpath_tx_stats: Buffer to return TX Statistics of vpath.
11056 *
11057 * Get the TX Statistics of a vpath
11058 *
11059 */
11060 vxge_hal_status_e
vxge_hal_vpath_xmac_tx_stats_get(vxge_hal_vpath_h vpath_handle,vxge_hal_xmac_vpath_tx_stats_t * vpath_tx_stats)11061 vxge_hal_vpath_xmac_tx_stats_get(vxge_hal_vpath_h vpath_handle,
11062 vxge_hal_xmac_vpath_tx_stats_t *vpath_tx_stats)
11063 {
11064 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
11065 __hal_device_t *hldev;
11066 vxge_hal_status_e status;
11067
11068 vxge_assert(vpath_handle != NULL);
11069
11070 hldev = vp->vpath->hldev;
11071
11072 vxge_hal_trace_log_stats("==> %s:%s:%d",
11073 __FILE__, __func__, __LINE__);
11074
11075 vxge_hal_trace_log_stats("vpath_handle = 0x"VXGE_OS_STXFMT,
11076 (ptr_t) vpath_handle);
11077
11078 status = __hal_vpath_xmac_tx_stats_get(vp->vpath, vpath_tx_stats);
11079
11080 vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d",
11081 __FILE__, __func__, __LINE__, status);
11082
11083 return (status);
11084 }
11085
11086 /*
11087 * vxge_hal_vpath_xmac_rx_stats_get - Get the RX Statistics of a vpath
11088 * @vpath_handle: vpath handle.
11089 * @vpath_rx_stats: Buffer to return RX Statistics of vpath.
11090 *
11091 * Get the RX Statistics of a vpath
11092 *
11093 */
11094 vxge_hal_status_e
vxge_hal_vpath_xmac_rx_stats_get(vxge_hal_vpath_h vpath_handle,vxge_hal_xmac_vpath_rx_stats_t * vpath_rx_stats)11095 vxge_hal_vpath_xmac_rx_stats_get(vxge_hal_vpath_h vpath_handle,
11096 vxge_hal_xmac_vpath_rx_stats_t *vpath_rx_stats)
11097 {
11098 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
11099 __hal_device_t *hldev;
11100 vxge_hal_status_e status;
11101
11102 vxge_assert(vpath_handle != NULL);
11103
11104 hldev = vp->vpath->hldev;
11105
11106 vxge_hal_trace_log_stats("==> %s:%s:%d",
11107 __FILE__, __func__, __LINE__);
11108
11109 vxge_hal_trace_log_stats("vpath_handle = 0x"VXGE_OS_STXFMT,
11110 (ptr_t) vpath_handle);
11111
11112 status = __hal_vpath_xmac_rx_stats_get(vp->vpath, vpath_rx_stats);
11113
11114 vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d",
11115 __FILE__, __func__, __LINE__, status);
11116
11117 return (status);
11118 }
11119
11120 /*
11121 * __hal_vpath_hw_stats_get - Get the vpath hw statistics.
11122 * @vpath: Virtual Path.
11123 * @hw_stats: Hardware stats
11124 *
11125 * Returns the vpath h/w stats.
11126 *
11127 * See also: vxge_hal_vpath_hw_stats_enable(),
11128 * vxge_hal_vpath_hw_stats_disable()
11129 */
11130 vxge_hal_status_e
__hal_vpath_hw_stats_get(__hal_virtualpath_t * vpath,vxge_hal_vpath_stats_hw_info_t * hw_stats)11131 __hal_vpath_hw_stats_get(__hal_virtualpath_t *vpath,
11132 vxge_hal_vpath_stats_hw_info_t *hw_stats)
11133 {
11134 u64 val64;
11135 __hal_device_t *hldev;
11136 vxge_hal_status_e status;
11137
11138 vxge_assert((vpath != NULL) && (hw_stats != NULL));
11139
11140 hldev = vpath->hldev;
11141
11142 vxge_hal_trace_log_stats("==> %s:%s:%d",
11143 __FILE__, __func__, __LINE__);
11144
11145 vxge_hal_trace_log_stats(
11146 "vpath = 0x"VXGE_OS_STXFMT", hw_stats = 0x"VXGE_OS_STXFMT,
11147 (ptr_t) vpath, (ptr_t) hw_stats);
11148
11149 if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
11150 vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d",
11151 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
11152 return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
11153 }
11154
11155 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11156 hldev->header.regh0,
11157 &vpath->vp_reg->vpath_debug_stats0);
11158
11159 hw_stats->ini_num_mwr_sent =
11160 (u32) VXGE_HAL_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT(val64);
11161
11162 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11163 hldev->header.regh0,
11164 &vpath->vp_reg->vpath_debug_stats1);
11165
11166 hw_stats->ini_num_mrd_sent =
11167 (u32) VXGE_HAL_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT(val64);
11168
11169 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11170 hldev->header.regh0,
11171 &vpath->vp_reg->vpath_debug_stats2);
11172
11173 hw_stats->ini_num_cpl_rcvd =
11174 (u32) VXGE_HAL_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD(val64);
11175
11176 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11177 hldev->header.regh0,
11178 &vpath->vp_reg->vpath_debug_stats3);
11179
11180 hw_stats->ini_num_mwr_byte_sent =
11181 VXGE_HAL_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT(val64);
11182
11183 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11184 hldev->header.regh0,
11185 &vpath->vp_reg->vpath_debug_stats4);
11186
11187 hw_stats->ini_num_cpl_byte_rcvd =
11188 VXGE_HAL_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD(val64);
11189
11190 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11191 hldev->header.regh0,
11192 &vpath->vp_reg->vpath_debug_stats5);
11193
11194 hw_stats->wrcrdtarb_xoff =
11195 (u32) VXGE_HAL_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF(val64);
11196
11197 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11198 hldev->header.regh0,
11199 &vpath->vp_reg->vpath_debug_stats6);
11200
11201 hw_stats->rdcrdtarb_xoff =
11202 (u32) VXGE_HAL_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF(val64);
11203
11204 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11205 hldev->header.regh0,
11206 &vpath->vp_reg->vpath_genstats_count01);
11207
11208 hw_stats->vpath_genstats_count0 =
11209 (u32) VXGE_HAL_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT0(
11210 val64);
11211
11212 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11213 hldev->header.regh0,
11214 &vpath->vp_reg->vpath_genstats_count01);
11215
11216 hw_stats->vpath_genstats_count1 =
11217 (u32) VXGE_HAL_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT1(
11218 val64);
11219
11220 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11221 hldev->header.regh0,
11222 &vpath->vp_reg->vpath_genstats_count23);
11223
11224 hw_stats->vpath_genstats_count2 =
11225 (u32) VXGE_HAL_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT2(
11226 val64);
11227
11228 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11229 hldev->header.regh0,
11230 &vpath->vp_reg->vpath_genstats_count01);
11231
11232 hw_stats->vpath_genstats_count3 =
11233 (u32) VXGE_HAL_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT3(
11234 val64);
11235
11236 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11237 hldev->header.regh0,
11238 &vpath->vp_reg->vpath_genstats_count4);
11239
11240 hw_stats->vpath_genstats_count4 =
11241 (u32) VXGE_HAL_VPATH_GENSTATS_COUNT4_GET_PPIF_VPATH_GENSTATS_COUNT4(
11242 val64);
11243
11244 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11245 hldev->header.regh0,
11246 &vpath->vp_reg->vpath_genstats_count5);
11247
11248 hw_stats->vpath_genstats_count5 = (u32)
11249 VXGE_HAL_VPATH_GENSTATS_COUNT5_GET_PPIF_VPATH_GENSTATS_COUNT5(
11250 val64);
11251
11252 status = __hal_vpath_xmac_tx_stats_get(vpath, &hw_stats->tx_stats);
11253 if (status != VXGE_HAL_OK) {
11254 vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d",
11255 __FILE__, __func__, __LINE__, status);
11256 return (status);
11257 }
11258
11259 status = __hal_vpath_xmac_rx_stats_get(vpath, &hw_stats->rx_stats);
11260 if (status != VXGE_HAL_OK) {
11261 vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d",
11262 __FILE__, __func__, __LINE__, status);
11263 return (status);
11264 }
11265
11266 VXGE_HAL_VPATH_STATS_PIO_READ(
11267 VXGE_HAL_STATS_VPATH_PROG_EVENT_VNUM0_OFFSET);
11268
11269 hw_stats->prog_event_vnum0 =
11270 (u32) VXGE_HAL_STATS_GET_VPATH_PROG_EVENT_VNUM0(val64);
11271
11272 hw_stats->prog_event_vnum1 =
11273 (u32) VXGE_HAL_STATS_GET_VPATH_PROG_EVENT_VNUM1(val64);
11274
11275 VXGE_HAL_VPATH_STATS_PIO_READ(
11276 VXGE_HAL_STATS_VPATH_PROG_EVENT_VNUM2_OFFSET);
11277
11278 hw_stats->prog_event_vnum2 =
11279 (u32) VXGE_HAL_STATS_GET_VPATH_PROG_EVENT_VNUM2(val64);
11280
11281 hw_stats->prog_event_vnum3 =
11282 (u32) VXGE_HAL_STATS_GET_VPATH_PROG_EVENT_VNUM3(val64);
11283
11284 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11285 hldev->header.regh0,
11286 &vpath->vp_reg->rx_multi_cast_stats);
11287
11288 hw_stats->rx_multi_cast_frame_discard =
11289 (u16) VXGE_HAL_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD(val64);
11290
11291 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11292 hldev->header.regh0,
11293 &vpath->vp_reg->rx_frm_transferred);
11294
11295 hw_stats->rx_frm_transferred =
11296 (u32) VXGE_HAL_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED(val64);
11297
11298 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11299 hldev->header.regh0,
11300 &vpath->vp_reg->rxd_returned);
11301
11302 hw_stats->rxd_returned =
11303 (u16) VXGE_HAL_RXD_RETURNED_GET_RXD_RETURNED(val64);
11304
11305
11306 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11307 hldev->header.regh0,
11308 &vpath->vp_reg->dbg_stats_rx_mpa);
11309
11310 hw_stats->rx_mpa_len_fail_frms =
11311 (u16) VXGE_HAL_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS(val64);
11312 hw_stats->rx_mpa_mrk_fail_frms =
11313 (u16) VXGE_HAL_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS(val64);
11314 hw_stats->rx_mpa_crc_fail_frms =
11315 (u16) VXGE_HAL_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS(val64);
11316
11317 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11318 hldev->header.regh0,
11319 &vpath->vp_reg->dbg_stats_rx_fau);
11320
11321 hw_stats->rx_permitted_frms =
11322 (u16) VXGE_HAL_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS(val64);
11323 hw_stats->rx_vp_reset_discarded_frms = (u16)
11324 VXGE_HAL_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(val64);
11325 hw_stats->rx_wol_frms =
11326 (u16) VXGE_HAL_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS(val64);
11327
11328 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11329 hldev->header.regh0,
11330 &vpath->vp_reg->tx_vp_reset_discarded_frms);
11331
11332 hw_stats->tx_vp_reset_discarded_frms = (u16)
11333 VXGE_HAL_TX_VP_RESET_DISCARDED_FRMS_GET_TX_VP_RESET_DISCARDED_FRMS(
11334 val64);
11335
11336 vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d",
11337 __FILE__, __func__, __LINE__, status);
11338
11339 return (status);
11340 }
11341
11342 /*
11343 * vxge_hal_vpath_stats_clear - Clear all the statistics of vpath
11344 * @vpath_handle: Virtual path handle.
11345 *
11346 * Clear the statistics of the given vpath.
11347 *
11348 */
11349 vxge_hal_status_e
vxge_hal_vpath_stats_clear(vxge_hal_vpath_h vpath_handle)11350 vxge_hal_vpath_stats_clear(vxge_hal_vpath_h vpath_handle)
11351 {
11352 u64 stat;
11353 vxge_hal_status_e status;
11354 __hal_device_t *hldev;
11355 __hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
11356
11357 vxge_assert(vp != NULL);
11358
11359 hldev = vp->vpath->hldev;
11360
11361 vxge_hal_trace_log_stats("==> %s:%s:%d",
11362 __FILE__, __func__, __LINE__);
11363
11364 vxge_hal_trace_log_stats("vpath = 0x"VXGE_OS_STXFMT,
11365 (ptr_t) vpath_handle);
11366
11367 vxge_os_memcpy(vp->vpath->hw_stats_sav,
11368 vp->vpath->hw_stats,
11369 sizeof(vxge_hal_vpath_stats_hw_info_t));
11370
11371 vxge_os_memzero(vp->vpath->hw_stats,
11372 sizeof(vxge_hal_vpath_stats_hw_info_t));
11373
11374 vxge_os_memzero(vp->vpath->sw_stats,
11375 sizeof(vxge_hal_vpath_stats_sw_info_t));
11376
11377 status = vxge_hal_vpath_stats_access(
11378 vpath_handle,
11379 VXGE_HAL_STATS_OP_CLEAR_ALL_VPATH_STATS,
11380 0,
11381 &stat);
11382
11383 vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d",
11384 __FILE__, __func__, __LINE__, status);
11385
11386 return (status);
11387 }
11388
11389
11390 /*
11391 * vxge_hal_set_fw_api - Setup FW api
11392 * @devh: Device Handle.
11393 *
11394 */
11395 vxge_hal_status_e
vxge_hal_set_fw_api(vxge_hal_device_h devh,u64 vp_id,u32 action,u32 offset,u64 data0,u64 data1)11396 vxge_hal_set_fw_api(vxge_hal_device_h devh,
11397 u64 vp_id, u32 action, u32 offset,
11398 u64 data0, u64 data1)
11399 {
11400 vxge_hal_status_e status = VXGE_HAL_OK;
11401 u64 val64;
11402 u32 fw_memo = VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO;
11403
11404 vxge_hal_vpath_reg_t *vp_reg;
11405
11406 __hal_device_t *hldev = (__hal_device_t *) devh;
11407 vxge_assert(hldev != NULL);
11408
11409 /* Assumption: Privileged vpath is zero */
11410 vp_reg = hldev->vpath_reg[vp_id];
11411
11412 vxge_os_pio_mem_write64(hldev->header.pdev,
11413 hldev->header.regh0, data0,
11414 &vp_reg->rts_access_steer_data0);
11415
11416 vxge_os_pio_mem_write64(hldev->header.pdev,
11417 hldev->header.regh0, data1,
11418 &vp_reg->rts_access_steer_data1);
11419
11420 vxge_os_wmb();
11421
11422 val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(action) |
11423 VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(fw_memo) |
11424 VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(offset) |
11425 VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE;
11426
11427 vxge_os_pio_mem_write64(hldev->header.pdev,
11428 hldev->header.regh0, val64,
11429 &vp_reg->rts_access_steer_ctrl);
11430
11431 vxge_os_wmb();
11432
11433 status =
11434 vxge_hal_device_register_poll(
11435 hldev->header.pdev, hldev->header.regh0,
11436 &vp_reg->rts_access_steer_ctrl, 0,
11437 VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE,
11438 WAIT_FACTOR * hldev->header.config.device_poll_millis);
11439
11440 if (status != VXGE_HAL_OK)
11441 return (VXGE_HAL_FAIL);
11442
11443 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11444 hldev->header.regh0,
11445 &vp_reg->rts_access_steer_ctrl);
11446
11447 if (val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS)
11448 status = VXGE_HAL_OK;
11449 else
11450 status = VXGE_HAL_FAIL;
11451
11452 return (status);
11453 }
11454
11455 /*
11456 * vxge_hal_get_active_config - Get active configuration
11457 * @devh: Device Handle.
11458 *
11459 */
11460 vxge_hal_status_e
vxge_hal_get_active_config(vxge_hal_device_h devh,vxge_hal_xmac_nwif_actconfig req_config,u64 * cur_config)11461 vxge_hal_get_active_config(vxge_hal_device_h devh,
11462 vxge_hal_xmac_nwif_actconfig req_config,
11463 u64 *cur_config)
11464 {
11465 u32 action;
11466 u64 data0 = 0x0, data1 = 0x0;
11467 u32 cmd = VXGE_HAL_XMAC_NWIF_Cmd_Get_Active_Config;
11468
11469 vxge_hal_vpath_reg_t *vp_reg;
11470 __hal_device_t *hldev = (__hal_device_t *) devh;
11471
11472 vxge_hal_status_e status = VXGE_HAL_OK;
11473 vxge_assert(hldev != NULL);
11474
11475 /* Assumption: Privileged vpath is zero */
11476 vp_reg = hldev->vpath_reg[0];
11477
11478 /* get port mode */
11479 data0 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_SET_NWIF_CMD(cmd) | req_config;
11480 action = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_PORT_CTRL;
11481
11482 status = vxge_hal_set_fw_api(devh, 0, action, 0x0, data0, data1);
11483 if (status == VXGE_HAL_OK) {
11484 *cur_config = vxge_os_pio_mem_read64(hldev->header.pdev,
11485 hldev->header.regh0,
11486 &vp_reg->rts_access_steer_data1);
11487 }
11488
11489 return (status);
11490 }
11491
11492 /*
11493 * vxge_hal_set_port_mode - Set dual port mode
11494 * override the default dual port mode
11495 * @devh: Device Handle.
11496 *
11497 */
11498 vxge_hal_status_e
vxge_hal_set_port_mode(vxge_hal_device_h devh,vxge_hal_xmac_nwif_dp_mode port_mode)11499 vxge_hal_set_port_mode(vxge_hal_device_h devh,
11500 vxge_hal_xmac_nwif_dp_mode port_mode)
11501 {
11502 u32 action;
11503 u64 data0 = 0x0, data1 = 0x0;
11504 u32 cmd = VXGE_HAL_XMAC_NWIF_Cmd_SetMode;
11505
11506 vxge_hal_status_e status = VXGE_HAL_OK;
11507
11508 if ((port_mode < VXGE_HAL_DP_NP_MODE_DEFAULT) ||
11509 (port_mode > VXGE_HAL_DP_NP_MODE_DISABLE_PORT_MGMT)) {
11510
11511 vxge_os_printf("Invalid port mode : %d\n", port_mode);
11512 return (VXGE_HAL_ERR_INVALID_DP_MODE);
11513 }
11514
11515 data0 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_SET_NWIF_CMD(cmd);
11516 data1 = port_mode;
11517 action = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_PORT_CTRL;
11518
11519 status = vxge_hal_set_fw_api(devh, 0, action, 0x0, data0, data1);
11520
11521 return (status);
11522 }
11523
11524 /*
11525 * vxge_hal_set_port_mode - Set dual port mode
11526 * change behavior on failure *
11527 * @devh: Device Handle.
11528 */
11529 vxge_hal_status_e
vxge_hal_set_behavior_on_failure(vxge_hal_device_h devh,vxge_hal_xmac_nwif_behavior_on_failure behave_on_failure)11530 vxge_hal_set_behavior_on_failure(vxge_hal_device_h devh,
11531 vxge_hal_xmac_nwif_behavior_on_failure behave_on_failure)
11532 {
11533 u32 action;
11534 u64 data0 = 0x0, data1 = 0x0;
11535 u32 cmd = VXGE_HAL_XMAC_NWIF_Cmd_CfgSetBehaviourOnFailure;
11536 vxge_hal_status_e status = VXGE_HAL_OK;
11537
11538 if ((behave_on_failure < VXGE_HAL_XMAC_NWIF_OnFailure_NoMove) ||
11539 (behave_on_failure >
11540 VXGE_HAL_XMAC_NWIF_OnFailure_OtherPortBackOnRestore)) {
11541 vxge_os_printf("Invalid setting for failure behavior : %d\n",
11542 behave_on_failure);
11543
11544 return (VXGE_HAL_FAIL);
11545 }
11546
11547 data0 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_SET_NWIF_CMD(cmd);
11548 data1 = behave_on_failure;
11549 action = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_PORT_CTRL;
11550
11551 status = vxge_hal_set_fw_api(devh, 0, action, 0x0, data0, data1);
11552
11553 return (status);
11554 }
11555
11556 vxge_hal_status_e
vxge_hal_set_l2switch_mode(vxge_hal_device_h devh,enum vxge_hal_xmac_nwif_l2_switch_status l2_switch)11557 vxge_hal_set_l2switch_mode(vxge_hal_device_h devh,
11558 enum vxge_hal_xmac_nwif_l2_switch_status l2_switch)
11559 {
11560 u32 action;
11561 u64 data0 = 0x0, data1 = 0x0;
11562 u32 cmd = VXGE_HAL_XMAC_NWIF_Cmd_CfgDualPort_L2SwitchEnable;
11563
11564 vxge_hal_status_e status = VXGE_HAL_OK;
11565
11566 if ((l2_switch < VXGE_HAL_XMAC_NWIF_L2_SWITCH_DISABLE) ||
11567 (l2_switch > VXGE_HAL_XMAC_NWIF_L2_SWITCH_ENABLE)) {
11568 vxge_os_printf("Invalid setting for failure behavior : %d\n",
11569 l2_switch);
11570
11571 return (VXGE_HAL_ERR_INVALID_L2_SWITCH_STATE);
11572 }
11573
11574 data0 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_SET_NWIF_CMD(cmd);
11575 data1 = l2_switch;
11576 action = VXGE_HAL_RTS_ACCESS_FW_MEMO_ACTION_PRIV_NWIF;
11577
11578 status = vxge_hal_set_fw_api(devh, 0, action, 0x0, data0, data1);
11579
11580 return (status);
11581 }
11582
11583 /* Get function mode */
11584 vxge_hal_status_e
vxge_hal_func_mode_get(vxge_hal_device_h devh,u32 * func_mode)11585 vxge_hal_func_mode_get(vxge_hal_device_h devh, u32 *func_mode)
11586 {
11587 int vp_id;
11588 u32 action;
11589 u64 val64;
11590
11591 vxge_hal_status_e status = VXGE_HAL_OK;
11592 vxge_hal_vpath_reg_t *vp_reg;
11593
11594 __hal_device_t *hldev = (__hal_device_t *) devh;
11595
11596 vxge_assert(hldev != NULL);
11597 /* get the first vpath number assigned to this function */
11598 vp_id = hldev->first_vp_id;
11599
11600 vp_reg = hldev->vpath_reg[vp_id];
11601 action = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_GET_FUNC_MODE;
11602
11603 status = vxge_hal_set_fw_api(devh, vp_id, action, 0x0, 0x0, 0x0);
11604 if (status == VXGE_HAL_OK) {
11605 val64 = vxge_os_pio_mem_read64(
11606 hldev->header.pdev, hldev->header.regh0,
11607 &vp_reg->rts_access_steer_data0);
11608
11609 *func_mode =
11610 (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FUNC_MODE(val64);
11611 }
11612
11613 return (status);
11614 }
11615
11616 vxge_hal_status_e
vxge_hal_func_mode_count(vxge_hal_device_h devh,u32 func_mode,u32 * num_funcs)11617 vxge_hal_func_mode_count(vxge_hal_device_h devh, u32 func_mode, u32 *num_funcs)
11618 {
11619 int vp_id;
11620 u32 action;
11621 u64 val64, data0;
11622
11623 vxge_hal_vpath_reg_t *vp_reg;
11624 vxge_hal_status_e status = VXGE_HAL_OK;
11625
11626 __hal_device_t *hldev = (__hal_device_t *) devh;
11627
11628 vp_id = hldev->first_vp_id;
11629 vp_reg = hldev->vpath_reg[0];
11630
11631 data0 = func_mode;
11632 action = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_GET_FUNC_COUNT;
11633
11634 status = vxge_hal_set_fw_api(devh, vp_id, action, 0x0, data0, 0x0);
11635 if (status == VXGE_HAL_OK) {
11636
11637 val64 = vxge_os_pio_mem_read64(
11638 hldev->header.pdev, hldev->header.regh0,
11639 &vp_reg->rts_access_steer_data0);
11640
11641 *num_funcs = (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_NUM_FUNC(val64);
11642 }
11643
11644 return (status);
11645 }
11646
11647 vxge_hal_status_e
vxge_hal_config_vpath_map(vxge_hal_device_h devh,u64 port_map)11648 vxge_hal_config_vpath_map(vxge_hal_device_h devh, u64 port_map)
11649 {
11650 u32 action;
11651 u64 data0 = 0x0, data1 = 0x0;
11652 u32 cmd = VXGE_HAL_XMAC_NWIF_Cmd_CfgDualPort_VPathVector;
11653 vxge_hal_status_e status = VXGE_HAL_OK;
11654
11655 action = VXGE_HAL_RTS_ACCESS_FW_MEMO_ACTION_PRIV_NWIF;
11656 data0 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_SET_NWIF_CMD(cmd);
11657 data1 = port_map;
11658
11659 status = vxge_hal_set_fw_api(devh, 0, action, 0x0, data0, data1);
11660
11661 return (status);
11662 }
11663
11664 vxge_hal_status_e
vxge_hal_get_vpath_mask(vxge_hal_device_h devh,u32 vf_id,u32 * num_vp,u64 * data1)11665 vxge_hal_get_vpath_mask(vxge_hal_device_h devh,
11666 u32 vf_id, u32 * num_vp, u64 * data1)
11667 {
11668 u32 action, vhn = 0;
11669 u64 data0 = 0x0;
11670
11671 vxge_hal_vpath_reg_t *vp_reg;
11672 vxge_hal_status_e status = VXGE_HAL_OK;
11673
11674 __hal_device_t *hldev = (__hal_device_t *) devh;
11675 vp_reg = hldev->vpath_reg[0];
11676
11677 data0 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_VFID(vf_id) |
11678 VXGE_HAL_RTS_ACCESS_STEER_DATA0_VHN(vhn);
11679
11680 action = VXGE_HAL_PRIV_VPATH_ACTION;
11681 status = vxge_hal_set_fw_api(devh, 0, action, 0x0, data0, 0x0);
11682 if (status == VXGE_HAL_OK) {
11683
11684 data0 = vxge_os_pio_mem_read64(hldev->header.pdev,
11685 hldev->header.regh0,
11686 &vp_reg->rts_access_steer_data0);
11687
11688 *num_vp = (u32) ((data0 >> 16) & 0xFF);
11689 *data1 = vxge_os_pio_mem_read64(hldev->header.pdev,
11690 hldev->header.regh0,
11691 &vp_reg->rts_access_steer_data1);
11692 }
11693
11694 return (status);
11695 }
11696
11697 vxge_hal_status_e
vxge_hal_get_vpath_list(vxge_hal_device_h devh,u32 vf_id,u64 * vpath_list,u32 * vpath_count)11698 vxge_hal_get_vpath_list(vxge_hal_device_h devh, u32 vf_id,
11699 u64 *vpath_list, u32 *vpath_count)
11700 {
11701 u32 i, j = 0;
11702 u64 pos, vpath_mask;
11703 vxge_hal_status_e status = VXGE_HAL_OK;
11704
11705 *vpath_count = 0;
11706
11707 status = vxge_hal_get_vpath_mask(devh, vf_id, vpath_count, &vpath_mask);
11708 if (status == VXGE_HAL_OK) {
11709 for (i = VXGE_HAL_VPATH_BMAP_END;
11710 i >= VXGE_HAL_VPATH_BMAP_START; i--) {
11711 if (bVAL1(vpath_mask, i)) {
11712 pos = VXGE_HAL_VPATH_BMAP_END - i;
11713 vpath_list[j] = pos;
11714 j++;
11715 }
11716 }
11717 }
11718
11719 return (status);
11720 }
11721
11722 vxge_hal_status_e
vxge_hal_rx_bw_priority_set(vxge_hal_device_h devh,u64 vp_id)11723 vxge_hal_rx_bw_priority_set(vxge_hal_device_h devh, u64 vp_id)
11724 {
11725 u64 data0 = 0x0, data1 = 0x0;
11726 u32 action, bandwidth, priority, set = 0;
11727
11728 vxge_hal_vpath_reg_t *vp_reg;
11729 vxge_hal_status_e status = VXGE_HAL_OK;
11730
11731 __hal_device_t *hldev = (__hal_device_t *) devh;
11732 vp_reg = hldev->vpath_reg[0];
11733 action = VXGE_HAL_BW_CONTROL;
11734
11735 bandwidth =
11736 ((vxge_hal_device_t *) (devh))->config.vp_config[vp_id].bandwidth;
11737
11738 priority =
11739 ((vxge_hal_device_t *) (devh))->config.vp_config[vp_id].priority;
11740
11741 /*
11742 * Get bandwidth and priority settings
11743 * and perform read-modify-write operation
11744 */
11745 data0 = 1;
11746 data0 |= vp_id << 32;
11747
11748 status = vxge_hal_set_fw_api(devh, 0, action, 0x0, data0, data1);
11749 if (status != VXGE_HAL_OK)
11750 goto _exit;
11751
11752 data1 = vxge_os_pio_mem_read64(hldev->header.pdev,
11753 hldev->header.regh0,
11754 &vp_reg->rts_access_steer_data1);
11755
11756 /* Set */
11757 data0 = 0;
11758 data0 |= vp_id << 32;
11759
11760 /* Rx Bandwidth */
11761 if (bandwidth != VXGE_HAL_VPATH_BW_LIMIT_DEFAULT) {
11762 set = 1;
11763 data1 &= ~VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_RX_MAX_BW(0xff);
11764 bandwidth = (bandwidth * 256) / 10000;
11765 data1 |=
11766 VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_RX_MAX_BW(bandwidth);
11767 data1 |= VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_VPATH_OR_FUNC(1);
11768 }
11769
11770 /* Priority */
11771 if (priority != VXGE_HAL_VPATH_PRIORITY_DEFAULT) {
11772 set = 1;
11773 data1 &= ~VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_RX_PRIORITY(0x7);
11774 data1 |=
11775 VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_RX_PRIORITY(priority);
11776 }
11777
11778 if (set == 1)
11779 status = vxge_hal_set_fw_api(devh, 0, action,
11780 0x0, data0, data1);
11781
11782 _exit:
11783 return (status);
11784 }
11785
11786 vxge_hal_status_e
vxge_hal_tx_bw_priority_set(vxge_hal_device_h devh,u64 vp_id)11787 vxge_hal_tx_bw_priority_set(vxge_hal_device_h devh, u64 vp_id)
11788 {
11789 u64 data0 = 0x0, data1 = 0x0;
11790 u32 action, bandwidth, priority, set = 0;
11791
11792 vxge_hal_vpath_reg_t *vp_reg;
11793 vxge_hal_status_e status = VXGE_HAL_OK;
11794
11795 __hal_device_t *hldev = (__hal_device_t *) devh;
11796 vp_reg = hldev->vpath_reg[0];
11797 action = VXGE_HAL_BW_CONTROL;
11798
11799 bandwidth =
11800 ((vxge_hal_device_t *) (devh))->config.vp_config[vp_id].bandwidth;
11801
11802 priority =
11803 ((vxge_hal_device_t *) (devh))->config.vp_config[vp_id].priority;
11804
11805 /*
11806 * Get bandwidth and priority settings and
11807 * perform a read-modify-write operation
11808 */
11809 data0 = 1;
11810 data0 |= vp_id << 32;
11811
11812 status = vxge_hal_set_fw_api(devh, 0, action, 0x0, data0, data1);
11813 if (status != VXGE_HAL_OK)
11814 goto _exit;
11815
11816 data1 = vxge_os_pio_mem_read64(hldev->header.pdev,
11817 hldev->header.regh0,
11818 &vp_reg->rts_access_steer_data1);
11819
11820 /* Set */
11821 data0 = 0;
11822 data0 |= vp_id << 32;
11823
11824 /* Tx Bandwidth */
11825 if (bandwidth != VXGE_HAL_VPATH_BW_LIMIT_DEFAULT) {
11826 set = 1;
11827 data1 &= ~VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_TX_MAX_BW(0xff);
11828 bandwidth = (bandwidth * 256) / 10000;
11829 data1 |=
11830 VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_TX_MAX_BW(bandwidth);
11831 }
11832
11833 /* Priority */
11834 if (priority != VXGE_HAL_VPATH_PRIORITY_DEFAULT) {
11835 set = 1;
11836 data1 &= ~VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_TX_PRIORITY(0x7);
11837 data1 |=
11838 VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_TX_PRIORITY(priority);
11839 }
11840
11841 if (set == 1)
11842 status = vxge_hal_set_fw_api(devh, 0, action,
11843 0x0, data0, data1);
11844
11845 _exit:
11846 return (status);
11847 }
11848
11849 vxge_hal_status_e
vxge_hal_bw_priority_get(vxge_hal_device_h devh,u64 vp_id,u32 * bandwidth,u32 * priority)11850 vxge_hal_bw_priority_get(vxge_hal_device_h devh, u64 vp_id,
11851 u32 *bandwidth, u32 *priority)
11852 {
11853 u32 action;
11854 u64 data0 = 0x0, data1 = 0x0;
11855
11856 vxge_hal_vpath_reg_t *vp_reg;
11857 vxge_hal_status_e status = VXGE_HAL_OK;
11858
11859 __hal_device_t *hldev = (__hal_device_t *) devh;
11860 vp_reg = hldev->vpath_reg[0];
11861 action = VXGE_HAL_BW_CONTROL;
11862
11863 /* Get rx bandwidth and rx priority settings */
11864 data0 = 1;
11865 data0 |= vp_id << 32;
11866
11867 status = vxge_hal_set_fw_api(devh, 0, action, 0x0, data0, data1);
11868 if (status != VXGE_HAL_OK)
11869 return (status);
11870
11871 data1 = vxge_os_pio_mem_read64(hldev->header.pdev,
11872 hldev->header.regh0,
11873 &vp_reg->rts_access_steer_data1);
11874
11875 *priority = (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RX_PRIORITY(data1);
11876
11877 /*
11878 * Bandwidth setting is stored in increments of approx. 39 Mb/s
11879 * so revert it back to get the b/w value
11880 */
11881 *bandwidth = (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RX_MAX_BW(data1);
11882 *bandwidth = ((*bandwidth) * 10000) / 256;
11883
11884 return (status);
11885 }
11886
11887 vxge_hal_status_e
vxge_hal_vf_rx_bw_get(vxge_hal_device_h devh,u64 func_id,u32 * bandwidth,u32 * priority)11888 vxge_hal_vf_rx_bw_get(vxge_hal_device_h devh, u64 func_id,
11889 u32 *bandwidth, u32 *priority)
11890 {
11891 u32 action;
11892 u64 data0 = 0x0, data1 = 0x0;
11893 __hal_device_t *hldev = (__hal_device_t *) devh;
11894
11895 vxge_hal_vpath_reg_t *vp_reg;
11896 vxge_hal_status_e status = VXGE_HAL_OK;
11897
11898 vp_reg = hldev->vpath_reg[func_id];
11899 action = VXGE_HAL_RTS_ACCESS_FW_MEMO_ACTION_NON_PRIV_BANDWIDTH_CTRL;
11900
11901 /* Get rx bandwidth and rx priority settings */
11902 data0 = 3;
11903 data0 |= func_id << 32;
11904
11905 status = vxge_hal_set_fw_api(devh, func_id, action, 0x0, data0, data1);
11906 if (status != VXGE_HAL_OK)
11907 return (status);
11908
11909 data1 = vxge_os_pio_mem_read64(hldev->header.pdev,
11910 hldev->header.regh0,
11911 &vp_reg->rts_access_steer_data1);
11912
11913 *priority =
11914 (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RX_PRIORITY(data1);
11915
11916 /*
11917 * Bandwidth setting is stored in increments of approx. 39 Mb/s
11918 * so revert it back to get the b/w value
11919 */
11920 *bandwidth = (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RX_MAX_BW(data1);
11921 *bandwidth = ((*bandwidth) * 10000) / 256;
11922
11923 return (status);
11924 }
11925
11926 void
vxge_hal_vpath_dynamic_tti_rtimer_set(vxge_hal_vpath_h vpath_handle,u32 timer_val)11927 vxge_hal_vpath_dynamic_tti_rtimer_set(vxge_hal_vpath_h vpath_handle,
11928 u32 timer_val)
11929 {
11930 u64 val64, timer;
11931
11932 __hal_device_t *hldev;
11933 __hal_virtualpath_t *vpath;
11934
11935 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
11936 hldev = vpath->hldev;
11937
11938 val64 = vpath->tim_tti_cfg3_saved;
11939 timer = (timer_val * 1000) / 272;
11940
11941 val64 &= ~VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_VAL(0x3ffffff);
11942 if (timer)
11943 val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_VAL(timer) |
11944 VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(5);
11945
11946 vxge_os_pio_mem_write64(hldev->header.pdev,
11947 hldev->header.regh0,
11948 val64,
11949 &vpath->vp_reg->tim_cfg3_int_num[VXGE_HAL_VPATH_INTR_TX]);
11950
11951 /*
11952 * tti_cfg3_saved is not updated again because it is
11953 * initialized at one place only - init time.
11954 */
11955 }
11956
11957 void
vxge_hal_vpath_dynamic_rti_rtimer_set(vxge_hal_vpath_h vpath_handle,u32 timer_val)11958 vxge_hal_vpath_dynamic_rti_rtimer_set(vxge_hal_vpath_h vpath_handle,
11959 u32 timer_val)
11960 {
11961 u64 val64, timer;
11962
11963 __hal_device_t *hldev;
11964 __hal_virtualpath_t *vpath;
11965
11966 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
11967 hldev = vpath->hldev;
11968
11969 val64 = vpath->tim_rti_cfg3_saved;
11970 timer = (timer_val * 1000) / 272;
11971
11972 val64 &= ~VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_VAL(0x3ffffff);
11973 if (timer)
11974 val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_VAL(timer) |
11975 VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(4);
11976
11977 vxge_os_pio_mem_write64(hldev->header.pdev,
11978 hldev->header.regh0,
11979 val64,
11980 &vpath->vp_reg->tim_cfg3_int_num[VXGE_HAL_VPATH_INTR_RX]);
11981
11982 /*
11983 * rti_cfg3_saved is not updated again because it is
11984 * initialized at one place only - init time.
11985 */
11986 }
11987
11988 void
vxge_hal_vpath_tti_ci_set(vxge_hal_vpath_h vpath_handle)11989 vxge_hal_vpath_tti_ci_set(vxge_hal_vpath_h vpath_handle)
11990 {
11991 u64 val64;
11992
11993 __hal_device_t *hldev;
11994 __hal_virtualpath_t *vpath;
11995
11996 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
11997 hldev = vpath->hldev;
11998
11999 if (vpath->vp_config->fifo.enable == VXGE_HAL_FIFO_ENABLE) {
12000 if (vpath->vp_config->tti.timer_ci_en != VXGE_HAL_TIM_TIMER_CI_ENABLE) {
12001 vpath->vp_config->tti.timer_ci_en = VXGE_HAL_TIM_TIMER_CI_ENABLE;
12002
12003 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
12004 hldev->header.regh0,
12005 &vpath->vp_reg->tim_cfg1_int_num[VXGE_HAL_VPATH_INTR_TX]);
12006
12007 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_CI;
12008 vpath->tim_rti_cfg1_saved = val64;
12009
12010 vxge_os_pio_mem_write64(hldev->header.pdev,
12011 hldev->header.regh0,
12012 val64,
12013 &vpath->vp_reg->tim_cfg1_int_num[VXGE_HAL_VPATH_INTR_TX]);
12014 }
12015 }
12016 }
12017
12018 void
vxge_hal_vpath_tti_ci_reset(vxge_hal_vpath_h vpath_handle)12019 vxge_hal_vpath_tti_ci_reset(vxge_hal_vpath_h vpath_handle)
12020 {
12021 u64 val64;
12022
12023 __hal_device_t *hldev;
12024 __hal_virtualpath_t *vpath;
12025
12026 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
12027 hldev = vpath->hldev;
12028
12029 if (vpath->vp_config->fifo.enable == VXGE_HAL_FIFO_ENABLE) {
12030 if (vpath->vp_config->tti.timer_ci_en != VXGE_HAL_TIM_TIMER_CI_DISABLE) {
12031 vpath->vp_config->tti.timer_ci_en = VXGE_HAL_TIM_TIMER_CI_DISABLE;
12032
12033 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
12034 hldev->header.regh0,
12035 &vpath->vp_reg->tim_cfg1_int_num[VXGE_HAL_VPATH_INTR_TX]);
12036
12037 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_CI;
12038 vpath->tim_rti_cfg1_saved = val64;
12039
12040 vxge_os_pio_mem_write64(hldev->header.pdev,
12041 hldev->header.regh0,
12042 val64,
12043 &vpath->vp_reg->tim_cfg1_int_num[VXGE_HAL_VPATH_INTR_TX]);
12044 }
12045 }
12046 }
12047
12048 void
vxge_hal_vpath_rti_ci_set(vxge_hal_vpath_h vpath_handle)12049 vxge_hal_vpath_rti_ci_set(vxge_hal_vpath_h vpath_handle)
12050 {
12051 u64 val64;
12052
12053 __hal_device_t *hldev;
12054 __hal_virtualpath_t *vpath;
12055
12056 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
12057 hldev = vpath->hldev;
12058
12059 if (vpath->vp_config->ring.enable == VXGE_HAL_RING_ENABLE) {
12060 if (vpath->vp_config->rti.timer_ci_en != VXGE_HAL_TIM_TIMER_CI_ENABLE) {
12061 vpath->vp_config->rti.timer_ci_en = VXGE_HAL_TIM_TIMER_CI_ENABLE;
12062
12063 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
12064 hldev->header.regh0,
12065 &vpath->vp_reg->tim_cfg1_int_num[VXGE_HAL_VPATH_INTR_RX]);
12066
12067 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_CI;
12068 vpath->tim_rti_cfg1_saved = val64;
12069
12070 vxge_os_pio_mem_write64(hldev->header.pdev,
12071 hldev->header.regh0,
12072 val64,
12073 &vpath->vp_reg->tim_cfg1_int_num[VXGE_HAL_VPATH_INTR_RX]);
12074 }
12075 }
12076 }
12077
12078 void
vxge_hal_vpath_rti_ci_reset(vxge_hal_vpath_h vpath_handle)12079 vxge_hal_vpath_rti_ci_reset(vxge_hal_vpath_h vpath_handle)
12080 {
12081 u64 val64;
12082
12083 __hal_device_t *hldev;
12084 __hal_virtualpath_t *vpath;
12085
12086 vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
12087 hldev = vpath->hldev;
12088
12089 if (vpath->vp_config->ring.enable == VXGE_HAL_RING_ENABLE) {
12090 if (vpath->vp_config->rti.timer_ci_en != VXGE_HAL_TIM_TIMER_CI_DISABLE) {
12091 vpath->vp_config->rti.timer_ci_en = VXGE_HAL_TIM_TIMER_CI_DISABLE;
12092
12093 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
12094 hldev->header.regh0,
12095 &vpath->vp_reg->tim_cfg1_int_num[VXGE_HAL_VPATH_INTR_RX]);
12096
12097 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_CI;
12098 vpath->tim_rti_cfg1_saved = val64;
12099
12100 vxge_os_pio_mem_write64(hldev->header.pdev,
12101 hldev->header.regh0,
12102 val64,
12103 &vpath->vp_reg->tim_cfg1_int_num[VXGE_HAL_VPATH_INTR_RX]);
12104 }
12105 }
12106 }
12107
12108 vxge_hal_status_e
vxge_hal_send_message(vxge_hal_device_h devh,u64 vp_id,u8 msg_type,u8 msg_dst,u32 msg_data,u64 * msg_sent_to_vpaths)12109 vxge_hal_send_message(vxge_hal_device_h devh, u64 vp_id, u8 msg_type,
12110 u8 msg_dst, u32 msg_data, u64 *msg_sent_to_vpaths)
12111 {
12112 u32 action;
12113 u64 data0 = 0x0, data1 = 0x0;
12114 u32 attempts = VXGE_HAL_MSG_SEND_RETRY;
12115 vxge_hal_status_e status = VXGE_HAL_OK;
12116
12117 data0 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEND_MSG_TYPE(msg_type) |
12118 VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEND_MSG_DEST(msg_dst) |
12119 VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEND_MSG_SRC(vp_id) |
12120 VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEND_MSG_DATA(msg_data);
12121
12122 action = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_SEND_MSG;
12123
12124 do {
12125 status = vxge_hal_set_fw_api(devh, vp_id, action, 0x0,
12126 data0, data1);
12127 if (status != VXGE_HAL_OK) {
12128 attempts--;
12129 if (attempts == 0)
12130 return (status);
12131 }
12132 } while (status != VXGE_HAL_OK);
12133
12134 if (msg_sent_to_vpaths != NULL) {
12135 /* The API returns a vector of VPATHs the message
12136 * was sent to in the event the destination is a
12137 * broadcast message or being sent to the privileged VPATH
12138 */
12139 *msg_sent_to_vpaths = data0 & VXGE_HAL_MSG_SEND_TO_VPATH_MASK;
12140 }
12141
12142 return (status);
12143 }
12144