1 /* $NetBSD: cacheops.c,v 1.15 2010/06/06 04:50:07 mrg Exp $ */
2
3 /*-
4 * Copyright (c) 1997 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Leo Weppelman
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include "opt_m68k_arch.h"
33
34 #include <sys/cdefs.h>
35 __KERNEL_RCSID(0, "$NetBSD: cacheops.c,v 1.15 2010/06/06 04:50:07 mrg Exp $");
36
37 #include <sys/types.h>
38 #include <machine/cpu.h>
39 #include <m68k/cacheops.h>
40 #ifdef M68K_CACHEOPS_MACHDEP
41 #include <machine/cacheops_machdep.h>
42 #endif
43
44 void
_TBIA(void)45 _TBIA(void)
46 {
47
48 #ifdef M68K_CACHEOPS_MACHDEP_TBIA
49 if (TBIA_md())
50 return;
51 #endif
52
53 switch (cputype) {
54 default:
55 #ifdef M68020
56 case CPU_68020:
57 TBIA_20();
58 break;
59 #endif
60 #ifdef M68030
61 case CPU_68030:
62 TBIA_30();
63 break;
64 #endif
65 #ifdef M68040
66 case CPU_68040:
67 TBIA_40();
68 break;
69 #endif
70 #ifdef M68060
71 case CPU_68060:
72 TBIA_60();
73 break;
74 #endif
75 }
76 }
77
78 void
_TBIAS(void)79 _TBIAS(void)
80 {
81
82 #ifdef M68K_CACHEOPS_MACHDEP_TBIAS
83 if (TBIAS_md())
84 return;
85 #endif
86
87 switch (cputype) {
88 default:
89 #ifdef M68020
90 case CPU_68020:
91 TBIAS_20();
92 break;
93 #endif
94 #ifdef M68030
95 case CPU_68030:
96 TBIAS_30();
97 break;
98 #endif
99 #ifdef M68040
100 case CPU_68040:
101 TBIAS_40();
102 break;
103 #endif
104 #ifdef M68060
105 case CPU_68060:
106 TBIAS_60();
107 break;
108 #endif
109 }
110 }
111
112 void
_TBIAU(void)113 _TBIAU(void)
114 {
115
116 #ifdef M68K_CACHEOPS_MACHDEP_TBIAU
117 if (TBIAU_md())
118 return;
119 #endif
120
121 switch (cputype) {
122 default:
123 #ifdef M68020
124 case CPU_68020:
125 TBIAU_20();
126 break;
127 #endif
128 #ifdef M68030
129 case CPU_68030:
130 TBIAU_30();
131 break;
132 #endif
133 #ifdef M68040
134 case CPU_68040:
135 TBIAU_40();
136 break;
137 #endif
138 #ifdef M68060
139 case CPU_68060:
140 TBIAU_60();
141 break;
142 #endif
143 }
144 }
145
146 void
_ICIA(void)147 _ICIA(void)
148 {
149
150 switch (cputype) {
151 default:
152 #ifdef M68020
153 case CPU_68020:
154 ICIA_20();
155 break;
156 #endif
157 #ifdef M68030
158 case CPU_68030:
159 ICIA_30();
160 break;
161 #endif
162 #ifdef M68040
163 case CPU_68040:
164 ICIA_40();
165 break;
166 #endif
167 #ifdef M68060
168 case CPU_68060:
169 ICIA_60();
170 break;
171 #endif
172 }
173 }
174
175 void
_ICPA(void)176 _ICPA(void)
177 {
178
179 switch (cputype) {
180 default:
181 #ifdef M68020
182 case CPU_68020:
183 ICPA_20();
184 break;
185 #endif
186 #ifdef M68030
187 case CPU_68030:
188 ICPA_30();
189 break;
190 #endif
191 #ifdef M68040
192 case CPU_68040:
193 ICPA_40();
194 break;
195 #endif
196 #ifdef M68060
197 case CPU_68060:
198 ICPA_60();
199 break;
200 #endif
201 }
202 }
203
204 void
_DCIA(void)205 _DCIA(void)
206 {
207
208 #ifdef M68K_CACHEOPS_MACHDEP_DCIA
209 if (DCIA_md())
210 return;
211 #endif
212
213 switch (cputype) {
214 default:
215 #ifdef M68020
216 case CPU_68020:
217 DCIA_20();
218 break;
219 #endif
220 #ifdef M68030
221 case CPU_68030:
222 DCIA_30();
223 break;
224 #endif
225 #ifdef M68040
226 case CPU_68040:
227 DCIA_40();
228 break;
229 #endif
230 #ifdef M68060
231 case CPU_68060:
232 DCIA_60();
233 break;
234 #endif
235 }
236 }
237
238 void
_DCIS(void)239 _DCIS(void)
240 {
241
242 #ifdef M68K_CACHEOPS_MACHDEP_DCIS
243 if (DCIS_md())
244 return;
245 #endif
246
247 switch (cputype) {
248 default:
249 #ifdef M68020
250 case CPU_68020:
251 DCIS_20();
252 break;
253 #endif
254 #ifdef M68030
255 case CPU_68030:
256 DCIS_30();
257 break;
258 #endif
259 #ifdef M68040
260 case CPU_68040:
261 DCIS_40();
262 break;
263 #endif
264 #ifdef M68060
265 case CPU_68060:
266 DCIS_60();
267 break;
268 #endif
269 }
270 }
271
272 void
_DCIU(void)273 _DCIU(void)
274 {
275
276 #ifdef M68K_CACHEOPS_MACHDEP_DCIU
277 if (DCIU_md())
278 return;
279 #endif
280
281 switch (cputype) {
282 default:
283 #ifdef M68020
284 case CPU_68020:
285 DCIU_20();
286 break;
287 #endif
288 #ifdef M68030
289 case CPU_68030:
290 DCIU_30();
291 break;
292 #endif
293 #ifdef M68040
294 case CPU_68040:
295 DCIU_40();
296 break;
297 #endif
298 #ifdef M68060
299 case CPU_68060:
300 DCIU_60();
301 break;
302 #endif
303 }
304 }
305
306 void
_PCIA(void)307 _PCIA(void)
308 {
309
310 #ifdef M68K_CACHEOPS_MACHDEP_PCIA
311 if (PCIA_md())
312 return;
313 #endif
314
315 switch (cputype) {
316 default:
317 #ifdef M68020
318 case CPU_68020:
319 PCIA_20();
320 break;
321 #endif
322 #ifdef M68030
323 case CPU_68030:
324 PCIA_30();
325 break;
326 #endif
327 #ifdef M68040
328 case CPU_68040:
329 PCIA_40();
330 break;
331 #endif
332 #ifdef M68060
333 case CPU_68060:
334 PCIA_60();
335 break;
336 #endif
337 }
338 }
339
340 void
_TBIS(vaddr_t va)341 _TBIS(vaddr_t va)
342 {
343
344 #ifdef M68K_CACHEOPS_MACHDEP_TBIS
345 if (TBIS_md(va))
346 return;
347 #endif
348
349 switch (cputype) {
350 default:
351 #ifdef M68020
352 case CPU_68020:
353 TBIS_20(va);
354 break;
355 #endif
356 #ifdef M68030
357 case CPU_68030:
358 TBIS_30(va);
359 break;
360 #endif
361 #ifdef M68040
362 case CPU_68040:
363 TBIS_40(va);
364 break;
365 #endif
366 #ifdef M68060
367 case CPU_68060:
368 TBIS_60(va);
369 break;
370 #endif
371 }
372 }
373
374 void
_DCIAS(paddr_t pa)375 _DCIAS(paddr_t pa)
376 {
377
378 switch (cputype) {
379 default:
380 #ifdef M68020
381 case CPU_68020:
382 DCIAS_20(pa);
383 break;
384 #endif
385 #ifdef M68030
386 case CPU_68030:
387 DCIAS_30(pa);
388 break;
389 #endif
390 #ifdef M68040
391 case CPU_68040:
392 DCIAS_40(pa);
393 break;
394 #endif
395 #ifdef M68060
396 case CPU_68060:
397 DCIAS_60(pa);
398 break;
399 #endif
400 }
401 }
402