1 /*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * Copyright (c) 2003 Peter Wemm. 4 * Copyright (c) 2008 The DragonFly Project. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * the Systems Programming Group of the University of Utah Computer 9 * Science Department and William Jolitz of UUNET Technologies Inc. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * Derived from hp300 version by Mike Hibler, this version by William 36 * Jolitz uses a recursive map [a pde points to the page directory] to 37 * map the page tables using the pagetables themselves. This is done to 38 * reduce the impact on kernel virtual memory for lots of sparse address 39 * space, and to reduce the cost of memory to each process. 40 * 41 * from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90 42 * from: @(#)pmap.h 7.4 (Berkeley) 5/12/91 43 */ 44 45 #ifndef _CPU_PMAP_H_ 46 #define _CPU_PMAP_H_ 47 48 #ifndef LOCORE 49 50 #include <machine/stdint.h> 51 52 /* 53 * MMU page tables, keep public for VM_MAX_USER_ADDRESS/PS_STRINGS. 54 */ 55 typedef __uint64_t pml4_entry_t; 56 typedef __uint64_t pdp_entry_t; 57 typedef __uint64_t pd_entry_t; 58 typedef __uint64_t pt_entry_t; 59 60 #endif /* !LOCORE */ 61 62 /* 63 * Page-directory and page-table entries follow this format, with a few 64 * of the fields not present here and there, depending on a lot of things. 65 */ 66 /* ---- Intel Nomenclature ---- */ 67 #define X86_PG_V 0x001 /* P Valid */ 68 #define X86_PG_RW 0x002 /* R/W Read/Write */ 69 #define X86_PG_U 0x004 /* U/S User/Supervisor */ 70 #define X86_PG_NC_PWT 0x008 /* PWT Write through */ 71 #define X86_PG_NC_PCD 0x010 /* PCD Cache disable */ 72 #define X86_PG_A 0x020 /* A Accessed */ 73 #define X86_PG_M 0x040 /* D Dirty */ 74 #define X86_PG_PS 0x080 /* PS Page size (0=4k,1=2M) */ 75 #define X86_PG_PTE_PAT 0x080 /* PAT PAT index */ 76 #define X86_PG_G 0x100 /* G Global */ 77 #define X86_PG_AVAIL1 0x200 /* / Available for system */ 78 #define X86_PG_AVAIL2 0x400 /* < programmers use */ 79 #define X86_PG_AVAIL3 0x800 /* \ */ 80 #define X86_PG_PDE_PAT 0x1000 /* PAT PAT index */ 81 #define X86_PG_NX (1UL << 63) /* No-execute */ 82 83 /* 84 * Intel Extended Page Table (EPT) bit definitions. 85 */ 86 #define EPT_PG_READ (1UL << 0) /* R: Read */ 87 #define EPT_PG_WRITE (1UL << 1) /* W: Write */ 88 #define EPT_PG_EXECUTE (1UL << 2) /* X: Execute */ 89 #define EPT_PG_IGNORE_PAT (1UL << 6) /* IPAT: Ignore PAT */ 90 #define EPT_PG_PS (1UL << 7) /* PS: Page size */ 91 #define EPT_PG_A (1UL << 8) /* A: Accessed */ 92 #define EPT_PG_M (1UL << 9) /* D: Dirty */ 93 #define EPT_PG_EXECUTE_USER (1UL << 10) /* XU: Execure for user-mode */ 94 #define EPT_PG_AVAIL1 (1UL << 11) /* ignored */ 95 #define EPT_PG_AVAIL2 (1UL << 52) /* ignored (bits 59-52) */ 96 #define EPT_PG_AVAIL3 (1UL << 53) 97 /* Memory Type (MT) definitions */ 98 #define EPT_MEM_TYPE_UC (0UL << 3) /* Uncacheable */ 99 #define EPT_MEM_TYPE_WC (1UL << 3) /* Write combining */ 100 #define EPT_MEM_TYPE_WT (4UL << 3) /* Write through */ 101 #define EPT_MEM_TYPE_WP (5UL << 3) /* Write protected */ 102 #define EPT_MEM_TYPE_WB (6UL << 3) /* Write back */ 103 #define EPT_MEM_TYPE_MASK (7UL << 3) 104 105 /* Our various interpretations of the above */ 106 //#define PG_W PG_AVAIL1 /* "Wired" pseudoflag */ 107 //#define PG_MANAGED PG_AVAIL2 108 //#define PG_DEVICE PG_AVAIL3 109 #define PG_FRAME (0x000ffffffffff000UL) 110 #define PG_PS_FRAME (0x000fffffffe00000UL) 111 //#define PG_PROT (PG_RW|PG_U) /* all protection bits . */ 112 //#define PG_N (PG_NC_PWT|PG_NC_PCD) /* Non-cacheable */ 113 114 /* 115 * Promotion to a 2MB (PDE) page mapping requires that the corresponding 4KB 116 * (PTE) page mappings have identical settings for the following fields: 117 */ 118 /* 119 #define PG_PTE_PROMOTE (PG_NX | PG_MANAGED | PG_W | PG_G | PG_PTE_PAT | \ 120 PG_M | PG_A | PG_NC_PCD | PG_NC_PWT | PG_U | PG_RW | PG_V) 121 */ 122 123 /* 124 * Page Protection Exception bits 125 */ 126 #define PGEX_P 0x01 /* Protection violation vs. not present */ 127 #define PGEX_W 0x02 /* during a Write cycle */ 128 #define PGEX_U 0x04 /* access from User mode (UPL) */ 129 #define PGEX_RSV 0x08 /* reserved PTE field is non-zero */ 130 #define PGEX_I 0x10 /* during an instruction fetch */ 131 132 /* 133 * Virtual kernel bits, managed by software. Stored in tf_xflags. 134 * 135 * PGEX_FPFAULT - Force the FP unit to generate a T_DNA fault if an 136 * emulated user process tried to use it. This bit is 137 * only used by vmspace_ctl(). 138 */ 139 #define PGEX_FPFAULT 0x80 140 141 #endif /* !_CPU_PMAP_H_ */ 142