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Searched defs:VirtReg (Results 1 – 19 of 19) sorted by relevance

/NextBSD/contrib/llvm/lib/CodeGen/
HDLiveRegMatrix.cpp99 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign()
117 void LiveRegMatrix::unassign(LiveInterval &VirtReg) { in unassign()
142 bool LiveRegMatrix::checkRegMaskInterference(LiveInterval &VirtReg, in checkRegMaskInterference()
160 bool LiveRegMatrix::checkRegUnitInterference(LiveInterval &VirtReg, in checkRegUnitInterference()
174 LiveIntervalUnion::Query &LiveRegMatrix::query(LiveInterval &VirtReg, in query()
182 LiveRegMatrix::checkInterference(LiveInterval &VirtReg, unsigned PhysReg) { in checkInterference()
HDRegAllocFast.cpp72 unsigned VirtReg; // Virtual register number. member
180 LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) { in findLiveVirtReg()
201 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) { in getStackSpaceFor()
256 void RAFast::killVirtReg(unsigned VirtReg) { in killVirtReg()
266 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) { in spillVirtReg()
410 switch (unsigned VirtReg = PhysRegState[PhysReg]) { in definePhysReg() local
426 switch (unsigned VirtReg = PhysRegState[Alias]) { in definePhysReg() local
453 switch (unsigned VirtReg = PhysRegState[PhysReg]) { in calcSpillCost() local
474 switch (unsigned VirtReg = PhysRegState[Alias]) { in calcSpillCost() local
507 RAFast::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) { in assignVirtToPhysReg()
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HDRegAllocGreedy.cpp201 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage()
478 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) { in LRE_CanEraseVirtReg()
490 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) { in LRE_WillShrinkVirtReg()
595 unsigned RAGreedy::tryAssign(LiveInterval &VirtReg, in tryAssign()
639 unsigned RAGreedy::canReassign(LiveInterval &VirtReg, unsigned PrevReg) { in canReassign()
702 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, in canEvictInterference()
784 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg, in evictInterference()
835 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg, in tryEvict()
1324 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order, in tryRegionSplit()
1354 unsigned RAGreedy::calculateRegionSplitCost(LiveInterval &VirtReg, in calculateRegionSplitCost()
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HDLiveIntervalUnion.cpp29 void LiveIntervalUnion::unify(LiveInterval &VirtReg, const LiveRange &Range) { in unify()
56 void LiveIntervalUnion::extract(LiveInterval &VirtReg, const LiveRange &Range) { in extract()
HDVirtRegMap.cpp84 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) { in hasPreferredPhys()
93 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) { in hasKnownPreference()
245 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx); in addMBBLiveIns() local
389 unsigned VirtReg = MO.getReg(); in rewrite() local
HDRegAllocBasic.cpp166 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, in spillInterferences()
220 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, in selectOrSplit()
HDAllocationOrder.cpp30 AllocationOrder::AllocationOrder(unsigned VirtReg, in AllocationOrder()
HDRegAllocBase.cpp88 while (LiveInterval *VirtReg = dequeue()) { in allocatePhysRegs() local
HDRegisterCoalescer.h66 CoalescerPair(unsigned VirtReg, unsigned PhysReg, in CoalescerPair()
HDLiveDebugVariables.cpp478 void LDVImpl::mapVirtReg(unsigned VirtReg, UserValue *EC) { in mapVirtReg()
484 UserValue *LDVImpl::lookupVirtReg(unsigned VirtReg) { in lookupVirtReg()
934 unsigned VirtReg = Loc.getReg(); in rewriteLocations() local
HDTargetRegisterInfo.cpp265 TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg, in getRegAllocationHints()
HDPHIElimination.cpp203 static bool isImplicitlyDefined(unsigned VirtReg, in isImplicitlyDefined()
HDMachineBasicBlock.cpp357 unsigned VirtReg = I->getOperand(0).getReg(); in addLiveIn() local
364 unsigned VirtReg = MRI.createVirtualRegister(RC); in addLiveIn() local
HDInlineSpiller.cpp856 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, in reMaterializeFor()
/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDLiveIntervalUnion.h88 void unify(LiveInterval &VirtReg) { in unify()
94 void extract(LiveInterval &VirtReg) { in extract()
113 LiveInterval *VirtReg; variable
HDVirtRegMap.h151 unsigned getOriginal(unsigned VirtReg) const { in getOriginal()
HDScheduleDAGInstrs.h35 unsigned VirtReg; member
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonFrameLowering.cpp910 unsigned VirtReg = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in replacePredRegPseudoSpillCode() local
937 unsigned VirtReg = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in replacePredRegPseudoSpillCode() local
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMBaseRegisterInfo.cpp224 ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, in getRegAllocationHints()