xref: /dragonfly/contrib/binutils-2.34/bfd/verilog.c (revision b52ef7118d1621abed722c5bbbd542210290ecef)
1 /* BFD back-end for verilog hex memory dump files.
2    Copyright (C) 2009-2020 Free Software Foundation, Inc.
3    Written by Anthony Green <green@moxielogic.com>
4 
5    This file is part of BFD, the Binary File Descriptor library.
6 
7    This program is free software; you can redistribute it and/or modify
8    it under the terms of the GNU General Public License as published by
9    the Free Software Foundation; either version 3 of the License, or
10    (at your option) any later version.
11 
12    This program is distributed in the hope that it will be useful,
13    but WITHOUT ANY WARRANTY; without even the implied warranty of
14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15    GNU General Public License for more details.
16 
17    You should have received a copy of the GNU General Public License
18    along with this program; if not, write to the Free Software
19    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20    MA 02110-1301, USA.  */
21 
22 
23 /* SUBSECTION
24           Verilog hex memory file handling
25 
26    DESCRIPTION
27 
28           Verilog hex memory files cannot hold anything but addresses
29           and data, so that's all that we implement.
30 
31           The syntax of the text file is described in the IEEE standard
32           for Verilog.  Briefly, the file contains two types of tokens:
33           data and optional addresses.  The tokens are separated by
34           whitespace and comments.  Comments may be single line or
35           multiline, using syntax similar to C++.  Addresses are
36           specified by a leading "at" character (@) and are always
37           hexadecimal strings.  Data and addresses may contain
38           underscore (_) characters.
39 
40           If no address is specified, the data is assumed to start at
41           address 0.  Similarly, if data exists before the first
42           specified address, then that data is assumed to start at
43           address 0.
44 
45 
46    EXAMPLE
47           @1000
48           01 ae 3f 45 12
49 
50    DESCRIPTION
51           @1000 specifies the starting address for the memory data.
52           The following characters describe the 5 bytes at 0x1000.  */
53 
54 
55 #include "sysdep.h"
56 #include "bfd.h"
57 #include "libbfd.h"
58 #include "libiberty.h"
59 #include "safe-ctype.h"
60 
61 /* Modified by obcopy.c
62    Data width in bytes.  */
63 unsigned int VerilogDataWidth = 1;
64 
65 /* Macros for converting between hex and binary.  */
66 
67 static const char digs[] = "0123456789ABCDEF";
68 
69 #define NIBBLE(x)    hex_value (x)
70 #define HEX(buffer) ((NIBBLE ((buffer)[0]) << 4) + NIBBLE ((buffer)[1]))
71 #define TOHEX(d, x) \
72           d[1] = digs[(x) & 0xf]; \
73           d[0] = digs[((x) >> 4) & 0xf];
74 
75 /* When writing a verilog memory dump file, we write them in the order
76    in which they appear in memory. This structure is used to hold them
77    in memory.  */
78 
79 struct verilog_data_list_struct
80 {
81   struct verilog_data_list_struct *next;
82   bfd_byte * data;
83   bfd_vma where;
84   bfd_size_type size;
85 };
86 
87 typedef struct verilog_data_list_struct verilog_data_list_type;
88 
89 /* The verilog tdata information.  */
90 
91 typedef struct verilog_data_struct
92 {
93   verilog_data_list_type *head;
94   verilog_data_list_type *tail;
95 }
96 tdata_type;
97 
98 static bfd_boolean
verilog_set_arch_mach(bfd * abfd,enum bfd_architecture arch,unsigned long mach)99 verilog_set_arch_mach (bfd *abfd, enum bfd_architecture arch, unsigned long mach)
100 {
101   if (arch != bfd_arch_unknown)
102     return bfd_default_set_arch_mach (abfd, arch, mach);
103 
104   abfd->arch_info = & bfd_default_arch_struct;
105   return TRUE;
106 }
107 
108 /* We have to save up all the outpu for a splurge before output.  */
109 
110 static bfd_boolean
verilog_set_section_contents(bfd * abfd,sec_ptr section,const void * location,file_ptr offset,bfd_size_type bytes_to_do)111 verilog_set_section_contents (bfd *abfd,
112                                     sec_ptr section,
113                                     const void * location,
114                                     file_ptr offset,
115                                     bfd_size_type bytes_to_do)
116 {
117   tdata_type *tdata = abfd->tdata.verilog_data;
118   verilog_data_list_type *entry;
119 
120   entry = (verilog_data_list_type *) bfd_alloc (abfd, sizeof (* entry));
121   if (entry == NULL)
122     return FALSE;
123 
124   if (bytes_to_do
125       && (section->flags & SEC_ALLOC)
126       && (section->flags & SEC_LOAD))
127     {
128       bfd_byte *data;
129 
130       data = (bfd_byte *) bfd_alloc (abfd, bytes_to_do);
131       if (data == NULL)
132           return FALSE;
133       memcpy ((void *) data, location, (size_t) bytes_to_do);
134 
135       entry->data = data;
136       entry->where = section->lma + offset;
137       entry->size = bytes_to_do;
138 
139       /* Sort the records by address.  Optimize for the common case of
140            adding a record to the end of the list.  */
141       if (tdata->tail != NULL
142             && entry->where >= tdata->tail->where)
143           {
144             tdata->tail->next = entry;
145             entry->next = NULL;
146             tdata->tail = entry;
147           }
148       else
149           {
150             verilog_data_list_type **look;
151 
152             for (look = &tdata->head;
153                  *look != NULL && (*look)->where < entry->where;
154                  look = &(*look)->next)
155               ;
156             entry->next = *look;
157             *look = entry;
158             if (entry->next == NULL)
159               tdata->tail = entry;
160           }
161     }
162   return TRUE;
163 }
164 
165 static bfd_boolean
verilog_write_address(bfd * abfd,bfd_vma address)166 verilog_write_address (bfd *abfd, bfd_vma address)
167 {
168   char buffer[12];
169   char *dst = buffer;
170   bfd_size_type wrlen;
171 
172   /* Write the address.  */
173   *dst++ = '@';
174   TOHEX (dst, (address >> 24));
175   dst += 2;
176   TOHEX (dst, (address >> 16));
177   dst += 2;
178   TOHEX (dst, (address >> 8));
179   dst += 2;
180   TOHEX (dst, (address));
181   dst += 2;
182   *dst++ = '\r';
183   *dst++ = '\n';
184   wrlen = dst - buffer;
185 
186   return bfd_bwrite ((void *) buffer, wrlen, abfd) == wrlen;
187 }
188 
189 /* Write a record of type, of the supplied number of bytes. The
190    supplied bytes and length don't have a checksum.  That's worked
191    out here.  */
192 
193 static bfd_boolean
verilog_write_record(bfd * abfd,const bfd_byte * data,const bfd_byte * end)194 verilog_write_record (bfd *abfd,
195                           const bfd_byte *data,
196                           const bfd_byte *end)
197 {
198   char buffer[52];
199   const bfd_byte *src = data;
200   char *dst = buffer;
201   bfd_size_type wrlen;
202 
203   /* Paranoia - check that we will not overflow "buffer".  */
204   if (((end - data) * 2) /* Number of hex characters we want to emit.  */
205       + ((end - data) / VerilogDataWidth) /* Number of spaces we want to emit.  */
206       + 2 /* The carriage return & line feed characters.  */
207       > (long) sizeof (buffer))
208     {
209       /* FIXME: Should we generate an error message ?  */
210       return FALSE;
211     }
212 
213   /* Write the data.
214      FIXME: Under some circumstances we can emit a space at the end of
215      the line.  This is not really necessary, but catching these cases
216      would make the code more complicated.  */
217   if (VerilogDataWidth == 1)
218     {
219       for (src = data; src < end;)
220           {
221             TOHEX (dst, *src);
222             dst += 2;
223             src ++;
224             if (src < end)
225               *dst++ = ' ';
226           }
227     }
228   else if (bfd_little_endian (abfd))
229     {
230       /* If the input byte stream contains:
231              05 04 03 02 01 00
232            and VerilogDataWidth is 4 then we want to emit:
233            02030405 0001  */
234       int i;
235 
236       for (src = data; src < (end - VerilogDataWidth); src += VerilogDataWidth)
237           {
238             for (i = VerilogDataWidth - 1; i >= 0; i--)
239               {
240                 TOHEX (dst, src[i]);
241                 dst += 2;
242               }
243             *dst++ = ' ';
244           }
245 
246       /* Emit any remaining bytes.  Be careful not to read beyond "end".  */
247       while (end > src)
248           {
249             -- end;
250             TOHEX (dst, *end);
251             dst += 2;
252           }
253     }
254   else
255     {
256       for (src = data; src < end;)
257           {
258             TOHEX (dst, *src);
259             dst += 2;
260             ++ src;
261             if ((src - data) % VerilogDataWidth == 0)
262               *dst++ = ' ';
263           }
264     }
265 
266   *dst++ = '\r';
267   *dst++ = '\n';
268   wrlen = dst - buffer;
269 
270   return bfd_bwrite ((void *) buffer, wrlen, abfd) == wrlen;
271 }
272 
273 static bfd_boolean
verilog_write_section(bfd * abfd,tdata_type * tdata ATTRIBUTE_UNUSED,verilog_data_list_type * list)274 verilog_write_section (bfd *abfd,
275                            tdata_type *tdata ATTRIBUTE_UNUSED,
276                            verilog_data_list_type *list)
277 {
278   unsigned int octets_written = 0;
279   bfd_byte *location = list->data;
280 
281   verilog_write_address (abfd, list->where);
282   while (octets_written < list->size)
283     {
284       unsigned int octets_this_chunk = list->size - octets_written;
285 
286       if (octets_this_chunk > 16)
287           octets_this_chunk = 16;
288 
289       if (! verilog_write_record (abfd,
290                                           location,
291                                           location + octets_this_chunk))
292           return FALSE;
293 
294       octets_written += octets_this_chunk;
295       location += octets_this_chunk;
296     }
297 
298   return TRUE;
299 }
300 
301 static bfd_boolean
verilog_write_object_contents(bfd * abfd)302 verilog_write_object_contents (bfd *abfd)
303 {
304   tdata_type *tdata = abfd->tdata.verilog_data;
305   verilog_data_list_type *list;
306 
307   /* Now wander though all the sections provided and output them.  */
308   list = tdata->head;
309 
310   while (list != (verilog_data_list_type *) NULL)
311     {
312       if (! verilog_write_section (abfd, tdata, list))
313           return FALSE;
314       list = list->next;
315     }
316   return TRUE;
317 }
318 
319 /* Initialize by filling in the hex conversion array.  */
320 
321 static void
verilog_init(void)322 verilog_init (void)
323 {
324   static bfd_boolean inited = FALSE;
325 
326   if (! inited)
327     {
328       inited = TRUE;
329       hex_init ();
330     }
331 }
332 
333 /* Set up the verilog tdata information.  */
334 
335 static bfd_boolean
verilog_mkobject(bfd * abfd)336 verilog_mkobject (bfd *abfd)
337 {
338   tdata_type *tdata;
339 
340   verilog_init ();
341 
342   tdata = (tdata_type *) bfd_alloc (abfd, sizeof (tdata_type));
343   if (tdata == NULL)
344     return FALSE;
345 
346   abfd->tdata.verilog_data = tdata;
347   tdata->head = NULL;
348   tdata->tail = NULL;
349 
350   return TRUE;
351 }
352 
353 #define verilog_close_and_cleanup                      _bfd_generic_close_and_cleanup
354 #define verilog_bfd_free_cached_info                   _bfd_generic_bfd_free_cached_info
355 #define verilog_new_section_hook                       _bfd_generic_new_section_hook
356 #define verilog_bfd_is_target_special_symbol           _bfd_bool_bfd_asymbol_false
357 #define verilog_bfd_is_local_label_name                bfd_generic_is_local_label_name
358 #define verilog_get_lineno                             _bfd_nosymbols_get_lineno
359 #define verilog_find_nearest_line                      _bfd_nosymbols_find_nearest_line
360 #define verilog_find_inliner_info                      _bfd_nosymbols_find_inliner_info
361 #define verilog_make_empty_symbol                      _bfd_generic_make_empty_symbol
362 #define verilog_bfd_make_debug_symbol                  _bfd_nosymbols_bfd_make_debug_symbol
363 #define verilog_read_minisymbols                       _bfd_generic_read_minisymbols
364 #define verilog_minisymbol_to_symbol                   _bfd_generic_minisymbol_to_symbol
365 #define verilog_get_section_contents_in_window         _bfd_generic_get_section_contents_in_window
366 #define verilog_bfd_get_relocated_section_contents   bfd_generic_get_relocated_section_contents
367 #define verilog_bfd_relax_section                      bfd_generic_relax_section
368 #define verilog_bfd_gc_sections                                  bfd_generic_gc_sections
369 #define verilog_bfd_merge_sections                     bfd_generic_merge_sections
370 #define verilog_bfd_is_group_section                   bfd_generic_is_group_section
371 #define verilog_bfd_group_name                                   bfd_generic_group_name
372 #define verilog_bfd_discard_group                      bfd_generic_discard_group
373 #define verilog_section_already_linked                 _bfd_generic_section_already_linked
374 #define verilog_bfd_link_hash_table_create             _bfd_generic_link_hash_table_create
375 #define verilog_bfd_link_add_symbols                   _bfd_generic_link_add_symbols
376 #define verilog_bfd_link_just_syms                     _bfd_generic_link_just_syms
377 #define verilog_bfd_final_link                                   _bfd_generic_final_link
378 #define verilog_bfd_link_split_section                 _bfd_generic_link_split_section
379 
380 const bfd_target verilog_vec =
381 {
382   "verilog",                            /* Name.  */
383   bfd_target_verilog_flavour,
384   BFD_ENDIAN_UNKNOWN,                   /* Target byte order.  */
385   BFD_ENDIAN_UNKNOWN,                   /* Target headers byte order.  */
386   (HAS_RELOC | EXEC_P |                 /* Object flags.  */
387    HAS_LINENO | HAS_DEBUG |
388    HAS_SYMS | HAS_LOCALS | WP_TEXT | D_PAGED),
389   (SEC_CODE | SEC_DATA | SEC_ROM | SEC_HAS_CONTENTS
390    | SEC_ALLOC | SEC_LOAD | SEC_RELOC), /* Section flags.  */
391   0,                                    /* Leading underscore.  */
392   ' ',                                  /* AR_pad_char.  */
393   16,                                   /* AR_max_namelen.  */
394   0,                                    /* match priority.  */
395   bfd_getb64, bfd_getb_signed_64, bfd_putb64,
396   bfd_getb32, bfd_getb_signed_32, bfd_putb32,
397   bfd_getb16, bfd_getb_signed_16, bfd_putb16,     /* Data.  */
398   bfd_getb64, bfd_getb_signed_64, bfd_putb64,
399   bfd_getb32, bfd_getb_signed_32, bfd_putb32,
400   bfd_getb16, bfd_getb_signed_16, bfd_putb16,     /* Hdrs.  */
401 
402   {
403     _bfd_dummy_target,
404     _bfd_dummy_target,
405     _bfd_dummy_target,
406     _bfd_dummy_target,
407   },
408   {
409     _bfd_bool_bfd_false_error,
410     verilog_mkobject,
411     _bfd_bool_bfd_false_error,
412     _bfd_bool_bfd_false_error,
413   },
414   {                                     /* bfd_write_contents.  */
415     _bfd_bool_bfd_false_error,
416     verilog_write_object_contents,
417     _bfd_bool_bfd_false_error,
418     _bfd_bool_bfd_false_error,
419   },
420 
421   BFD_JUMP_TABLE_GENERIC (_bfd_generic),
422   BFD_JUMP_TABLE_COPY (_bfd_generic),
423   BFD_JUMP_TABLE_CORE (_bfd_nocore),
424   BFD_JUMP_TABLE_ARCHIVE (_bfd_noarchive),
425   BFD_JUMP_TABLE_SYMBOLS (_bfd_nosymbols),
426   BFD_JUMP_TABLE_RELOCS (_bfd_norelocs),
427   BFD_JUMP_TABLE_WRITE (verilog),
428   BFD_JUMP_TABLE_LINK (_bfd_nolink),
429   BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
430 
431   NULL,
432 
433   NULL
434 };
435