1 /*- 2 * Copyright(c) 2002-2011 Exar Corp. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification are permitted provided the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Exar Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*$FreeBSD$*/ 32 33 #ifndef VXGE_HAL_STATUS_H 34 #define VXGE_HAL_STATUS_H 35 36 __EXTERN_BEGIN_DECLS 37 38 #define VXGE_HAL_EVENT_BASE 0 39 #define VXGE_LL_EVENT_BASE 100 40 41 /* 42 * enum vxge_hal_event_e - Enumerates slow-path HAL events. 43 * @VXGE_HAL_EVENT_UNKNOWN: Unknown (and invalid) event. 44 * @VXGE_HAL_EVENT_SERR: Serious hardware error event. 45 * @VXGE_HAL_EVENT_CRITICAL: Critical vpath hardware error event. 46 * @VXGE_HAL_EVENT_ECCERR: vpath ECC error event. 47 * @VXGE_HAL_EVENT_KDFCCTL: FIFO Doorbell fifo error. 48 * @VXGE_HAL_EVENT_SRPCIM_CRITICAL: srpcim hardware error event. 49 * @VXGE_HAL_EVENT_MRPCIM_CRITICAL: mrpcim hardware error event. 50 * @VXGE_HAL_EVENT_MRPCIM_ECCERR: mrpcim ecc error event. 51 * @VXGE_HAL_EVENT_DEVICE_RESET_START: Privileged entity starting device reset 52 * @VXGE_HAL_EVENT_DEVICE_RESET_COMPLETE: Device reset has been completed 53 * @VXGE_HAL_EVENT_VPATH_RESET_START: A function is starting vpath reset 54 * @VXGE_HAL_EVENT_VPATH_RESET_COMPLETE: vpath reset has been completed 55 * @VXGE_HAL_EVENT_SLOT_FREEZE: Slot-freeze event. Driver tries to distinguish 56 * slot-freeze from the rest critical events (e.g. ECC) when it is 57 * impossible to PIO read "through" the bus, i.e. when getting all-foxes. 58 * 59 * vxge_hal_event_e enumerates slow-path HAL eventis. 60 * 61 * See also: vxge_hal_uld_cbs_t {}, vxge_uld_link_up_f {}, 62 * vxge_uld_link_down_f {}. 63 */ 64 typedef enum vxge_hal_event_e { 65 VXGE_HAL_EVENT_UNKNOWN = 0, 66 /* HAL events */ 67 VXGE_HAL_EVENT_SERR = VXGE_HAL_EVENT_BASE + 1, 68 VXGE_HAL_EVENT_CRITICAL = VXGE_HAL_EVENT_BASE + 2, 69 VXGE_HAL_EVENT_ECCERR = VXGE_HAL_EVENT_BASE + 3, 70 VXGE_HAL_EVENT_KDFCCTL = VXGE_HAL_EVENT_BASE + 4, 71 VXGE_HAL_EVENT_SRPCIM_CRITICAL = VXGE_HAL_EVENT_BASE + 5, 72 VXGE_HAL_EVENT_MRPCIM_CRITICAL = VXGE_HAL_EVENT_BASE + 6, 73 VXGE_HAL_EVENT_MRPCIM_ECCERR = VXGE_HAL_EVENT_BASE + 7, 74 VXGE_HAL_EVENT_DEVICE_RESET_START = VXGE_HAL_EVENT_BASE + 8, 75 VXGE_HAL_EVENT_DEVICE_RESET_COMPLETE = VXGE_HAL_EVENT_BASE + 9, 76 VXGE_HAL_EVENT_VPATH_RESET_START = VXGE_HAL_EVENT_BASE + 10, 77 VXGE_HAL_EVENT_VPATH_RESET_COMPLETE = VXGE_HAL_EVENT_BASE + 11, 78 VXGE_HAL_EVENT_SLOT_FREEZE = VXGE_HAL_EVENT_BASE + 12 79 } vxge_hal_event_e; 80 81 #define VXGE_HAL_BASE_INF 100 82 #define VXGE_HAL_BASE_ERR 200 83 #define VXGE_HAL_BASE_BADCFG 300 84 85 /* 86 * enum vxge_hal_status_e - HAL return codes. 87 * @VXGE_HAL_OK: Success. 88 * @VXGE_HAL_FAIL: Failure. 89 * @VXGE_HAL_PENDING: Opearation is pending 90 * @VXGE_HAL_CONTINUE: Continue processing 91 * @VXGE_HAL_RETURN: Stop processing and return 92 * @VXGE_HAL_COMPLETIONS_REMAIN: There are more completions on a channel. 93 * (specific to polling mode completion processing). 94 * @VXGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS: No more completed 95 * descriptors. See vxge_hal_fifo_txdl_next_completed(). 96 * @VXGE_HAL_INF_OUT_OF_DESCRIPTORS: Out of descriptors. Channel 97 * descriptors 98 * are reserved (via vxge_hal_fifo_txdl_reserve(), 99 * vxge_hal_ring_rxd_reserve()) 100 * and not yet freed (via vxge_hal_fifo_txdl_free(), 101 * vxge_hal_ring_rxd_free()). 102 * @VXGE_HAL_INF_QUEUE_IS_NOT_READY: A descriptor was reserved and not posted 103 * @VXGE_HAL_INF_MEM_STROBE_CMD_EXECUTING: Indicates that host needs to 104 * poll until PIO is executed. 105 * @VXGE_HAL_INF_STATS_IS_NOT_READY: Queue is not ready for 106 * operation. 107 * @VXGE_HAL_INF_NO_MORE_FREED_DESCRIPTORS: No descriptors left to 108 * reserve. Internal use only. 109 * @VXGE_HAL_INF_IRQ_POLLING_CONTINUE: Returned by the ULD channel 110 * callback when instructed to exit descriptor processing loop 111 * prematurely. Typical usage: polling mode of processing completed 112 * descriptors. 113 * Upon getting LRO_ISED, ll driver shall 114 * 1) initialise lro struct with mbuf if sg_num == 1. 115 * 2) else it will update m_data_ptr_of_mbuf to tcp pointer and 116 * append the new mbuf to the tail of mbuf chain in lro struct. 117 * @VXGE_HAL_INF_SW_LRO_BEGIN: Returned by ULD LRO module, when new LRO is 118 * being initiated. 119 * @VXGE_HAL_INF_SW_LRO_CONT: Returned by ULD LRO module, when new frame 120 * is appended at the end of existing LRO. 121 * @VXGE_HAL_INF_SW_LRO_UNCAPABLE: Returned by ULD LRO module, when new 122 * frame is not LRO capable. 123 * @VXGE_HAL_INF_SW_LRO_FLUSH_SESSION: Returned by ULD LRO module, 124 * when new frame triggers LRO flush. 125 * @VXGE_HAL_INF_SW_LRO_FLUSH_BOTH: Returned by ULD LRO module, when new 126 * frame triggers LRO flush. Lro frame should be flushed first then 127 * new frame should be flushed next. 128 * @VXGE_HAL_INF_SW_LRO_END_3: Returned by ULD LRO module, when new 129 * frame triggers close of current LRO session and opening of new LRO session 130 * with the frame. 131 * @VXGE_HAL_INF_SW_LRO_SESSIONS_XCDED: Returned by ULD LRO module, when no 132 * more LRO sessions can be added. 133 * @VXGE_HAL_INF_NOT_ENOUGH_HW_CQES: Enough CQEs are available 134 * @VXGE_HAL_INF_LINK_UP_DOWN: Link up down indication received 135 * @VXGE_HAL_ERR_DRIVER_NOT_INITIALIZED: HAL is not initialized. 136 * @VXGE_HAL_ERR_INVALID_HANDLE: The handle passed is invalid. 137 * @VXGE_HAL_ERR_OUT_OF_MEMORY: Out of memory (example, when and 138 * allocating descriptors). 139 * @VXGE_HAL_ERR_VPATH_NOT_AVAILABLE: Vpath is not allocated to this 140 * function 141 * @VXGE_HAL_ERR_VPATH_NOT_OPEN: Vpath is not opened i.e put in service. 142 * @VXGE_HAL_ERR_WRONG_IRQ: Returned by HAL's ISR when the latter is 143 * invoked not because of the X3100-generated interrupt. 144 * @VXGE_HAL_ERR_OUT_OF_MAC_ADDRESSES: Returned when user tries to 145 * configure more than VXGE_HAL_MAX_MAC_ADDRESSES mac addresses. 146 * @VXGE_HAL_ERR_SWAPPER_CTRL: Error during device initialization: failed 147 * to set X3100 byte swapper in accordnace with the host 148 * endian-ness. 149 * @VXGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT: Failed to restore the device to 150 * a "quiescent" state. 151 * @VXGE_HAL_ERR_INVALID_MTU_SIZE:Returned when MTU size specified by 152 * caller is not in the (64, 9600) range. 153 * @VXGE_HAL_ERR_OUT_OF_MAPPING: Failed to map DMA-able memory. 154 * @VXGE_HAL_ERR_BAD_SUBSYSTEM_ID: Bad PCI subsystem ID. (Currently we 155 * check for zero/non-zero only.) 156 * @VXGE_HAL_ERR_INVALID_BAR_ID: Invalid BAR ID. X3100 supports two Base 157 * Address Register Spaces: BAR0 (id=0) and BAR1 (id=1). 158 * @VXGE_HAL_ERR_INVALID_INDEX: Invalid index. Example, attempt to read 159 * register value from the register section that is out of range. 160 * @VXGE_HAL_ERR_INVALID_TYPE: Invalid register section. 161 * @VXGE_HAL_ERR_INVALID_OFFSET: Invalid offset. Example, attempt to read 162 * register value (with offset) outside of the register section range 163 * @VXGE_HAL_ERR_INVALID_DEVICE: Invalid device. The HAL device handle 164 * (passed by ULD) is invalid. 165 * @VXGE_HAL_ERR_OUT_OF_SPACE: Out-of-provided-buffer-space. Returned by 166 * management "get" routines when the retrieved information does 167 * not fit into the provided buffer. 168 * @VXGE_HAL_ERR_INVALID_VALUE_BIT_SIZE: Invalid bit size. 169 * @VXGE_HAL_ERR_VERSION_CONFLICT: Upper-layer driver and HAL (versions) 170 * are not compatible. 171 * @VXGE_HAL_ERR_INVALID_MAC_ADDRESS: Invalid MAC address. 172 * @VXGE_HAL_ERR_BAD_DEVICE_ID: Unknown device PCI ID. 173 * @VXGE_HAL_ERR_OUT_ALIGNED_FRAGS: Too many unaligned fragments 174 * in a scatter-gather list. 175 * @VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED: Device is not initialized. 176 * Typically means wrong sequence of API calls. 177 * @VXGE_HAL_ERR_SPDM_NOT_ENABLED: SPDM support is not enabled. 178 * @VXGE_HAL_ERR_SPDM_TABLE_FULL: SPDM table is full. 179 * @VXGE_HAL_ERR_SPDM_INVALID_ENTRY: Invalid SPDM entry. 180 * @VXGE_HAL_ERR_SPDM_ENTRY_NOT_FOUND: Unable to locate the entry in the 181 * SPDM table. 182 * @VXGE_HAL_ERR_SPDM_TABLE_DATA_INCONSISTENT: Local SPDM table is not in 183 * synch ith the actual one. 184 * @VXGE_HAL_ERR_INVALID_PCI_INFO: Invalid or unrecognized PCI parameters. 185 * @VXGE_HAL_ERR_CRITICAL: Critical error. Returned by HAL APIs 186 * (including vxge_hal_fifo_handle_tcode() and vxge_hal_ring_handle_tcode()) 187 * on: ECC, parity, SERR. 188 * Also returned when PIO read does not go through ("all-foxes") 189 * because of "slot-freeze". 190 * @VXGE_HAL_ERR_RESET_FAILED: Failed to soft-reset the device. 191 * Returned by vxge_hal_device_reset(). One circumstance when it could 192 * happen: slot freeze by the system (see @VXGE_HAL_ERR_CRITICAL). 193 * @VXGE_HAL_ERR_TOO_MANY: This error is returned if there were laready 194 * maximum number of sessions or queues allocated 195 * @VXGE_HAL_ERR_PKT_DROP: Packet got dropped 196 * @VXGE_HAL_ERR_INVALID_BLOCK_SIZE: Invalid block size 197 * @VXGE_HAL_ERR_INVALID_STATE: Invalid state 198 * @VXGE_HAL_ERR_PRIVILAGED_OPEARATION: A previleged operation is attempted 199 * @VXGE_HAL_ERR_RESET_IN_PROGRESS: Reset is currently in progress 200 * @VXGE_HAL_ERR_MAC_TABLE_FULL: DA table is full 201 * @VXGE_HAL_ERR_MAC_TABLE_EMPTY: DA table is empty 202 * @VXGE_HAL_ERR_MAC_TABLE_NO_MORE_ENTRIES: There are no more entries in the 203 * DA table 204 * @VXGE_HAL_ERR_RTDMA_RTDMA_READY: RTDMA is ready 205 * @VXGE_HAL_ERR_WRDMA_WRDMA_READY: WRDMA is ready 206 * @VXGE_HAL_ERR_KDFC_KDFC_READY: Kernel mode doorbell controller ready 207 * @VXGE_HAL_ERR_TPA_TMAC_BUF_EMPTY: Transmit Protocol Assist TMAC buffer empty 208 * @VXGE_HAL_ERR_RDCTL_PIC_QUIESCENT: PIC block is quiescent 209 * @VXGE_HAL_ERR_XGMAC_NETWORK_FAULT: Network Fault 210 * @VXGE_HAL_ERR_ROCRC_OFFLOAD_QUIESCENT: ROCRC offload quiescent 211 * @VXGE_HAL_ERR_G3IF_FB_G3IF_FB_GDDR3_READY: G3DDR Interface FB Ready 212 * @VXGE_HAL_ERR_G3IF_CM_G3IF_CM_GDDR3_READY: G3DDR Interface CM Ready 213 * @VXGE_HAL_ERR_RIC_RIC_RUNNING: Adapter RIC is still programming flash 214 * settings to device 215 * @VXGE_HAL_ERR_CMG_C_PLL_IN_LOCK: CMG C PLL in lock 216 * @VXGE_HAL_ERR_XGMAC_X_PLL_IN_LOCK: XGMAC X PLL in Lock 217 * @VXGE_HAL_ERR_FBIF_M_PLL_IN_LOCK: FBUF M PLL in Lock 218 * @VXGE_HAL_ERR_PCC_PCC_IDLE: PCC is idle 219 * @VXGE_HAL_ERR_ROCRC_RC_PRC_QUIESCENT: ROCRC RC PCC quiescent 220 * @VXGE_HAL_ERR_SLOT_FREEZE: PCI Slot frozen 221 * @VXGE_HAL_ERR_INVALID_TCODE: The t-code returned is invalid 222 * @VXGE_HAL_ERR_INVALID_PORT: The port number specified is invalid 223 * @VXGE_HAL_ERR_INVALID_PRIORITY: Proiority specified is invalid 224 * @VXGE_HAL_ERR_INVALID_MIN_BANDWIDTH: Minimum bandwidth specified is invalid 225 * @VXGE_HAL_ERR_INVALID_MAX_BANDWIDTH: Maximum bandwidth specified is invalid 226 * @VXGE_HAL_ERR_INVALID_BANDWIDTH_LIMIT: Bandwidth limit specified is invalid 227 * @VXGE_HAL_ERR_INVALID_TOTAL_BANDWIDTH: Total bandwidth specified is invalid 228 * @VXGE_HAL_ERR_MANAGER_NOT_FOUND: The Function 0 driver or MRPCIM manager is 229 * down 230 * @VXGE_HAL_ERR_TIME_OUT: Timeout occurred 231 * @VXGE_HAL_ERR_EVENT_UNKNOWN: Unknown alarm 232 * @VXGE_HAL_ERR_EVENT_SERR: Serious error on device 233 * @VXGE_HAL_ERR_EVENT_CRITICAL: Critical error in the vpath 234 * @VXGE_HAL_ERR_EVENT_ECCERR: Ecc Error returned in t-code 235 * @VXGE_HAL_ERR_EVENT_KDFCCTL: Kdfcctl error on the device 236 * @VXGE_HAL_ERR_EVENT_SRPCIM_CRITICAL: Critical error in SRPCIM 237 * @VXGE_HAL_ERR_EVENT_MRPCIM_CRITICAL: Critical error in MRPCIM 238 * @VXGE_HAL_ERR_EVENT_MRPCIM_ECCERR: ECC error in MRPCIM 239 * @VXGE_HAL_ERR_EVENT_RESET_START: Device is going to be reset 240 * @VXGE_HAL_ERR_EVENT_RESET_COMPLETE: Device reset is complete 241 * @VXGE_HAL_ERR_EVENT_SLOT_FREEZE: PCI Slot freeze 242 * @VXGE_HAL_BADCFG_WIRE_PORT_PORT_ID: Invalid port id in config 243 * @VXGE_HAL_BADCFG_WIRE_PORT_MAX_MEDIA: Invalid media type in config 244 * @VXGE_HAL_BADCFG_WIRE_PORT_MAX_INITIAL_MTU: Invalid initial MTU size 245 * in config 246 * @VXGE_HAL_BADCFG_WIRE_PORT_AUTONEG_MODE: Invalid autonegotiation mode 247 * in config 248 * @VXGE_HAL_BADCFG_WIRE_PORT_AUTONEG_RATE: Invalid autonegotiation rate 249 * in config 250 * @VXGE_HAL_BADCFG_WIRE_PORT_FIXED_USE_FSM: Invalid fixed use fsm in config 251 * @VXGE_HAL_BADCFG_WIRE_PORT_ANTP_USE_FSM: Invalid ANTP use FSM in config 252 * @VXGE_HAL_BADCFG_WIRE_PORT_ANBE_USE_FSM: Invalid ANBE use FSM in config 253 * @VXGE_HAL_BADCFG_WIRE_PORT_LINK_STABILITY_PERIOD: Invalid link stability 254 * period in config 255 * @VXGE_HAL_BADCFG_WIRE_PORT_PORT_STABILITY_PERIOD: Invalid port stability 256 * period in config 257 * @VXGE_HAL_BADCFG_WIRE_PORT_TMAC_EN: Invalid Transmit MAC enable setting 258 * in config 259 * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_EN: Invalid Receive MAC enable setting 260 * in config 261 * @VXGE_HAL_BADCFG_WIRE_PORT_TMAC_PAD: Invalid Transmit MAC PAD enable setting 262 * in config 263 * @VXGE_HAL_BADCFG_WIRE_PORT_TMAC_PAD_BYTE: Invalid Transmit MAC PAD Byte 264 * setting in config 265 * @VXGE_HAL_BADCFG_WIRE_PORT_TMAC_UTIL_PERIOD: Invalid Transmit MAC utilization 266 * period in config 267 * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_STRIP_FCS: Invalid Receive MAC strip FCS 268 * setting in config 269 * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PROM_EN: Invalid Receive MAC PROM enable 270 * in config 271 * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_DISCARD_PFRM: Invalid Receive MAC discard 272 * pfrm setting in config 273 * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_UTIL_PERIOD: Invalid Receive MAC utilization 274 * period in config 275 * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PAUSE_GEN_EN: Invalid Receive MAC pause 276 * generation enable setting in config 277 * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PAUSE_RCV_EN: Invalid Receive MAC pause 278 * receive enable setting in config 279 * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_HIGH_PTIME: Invalid Receive MAC high ptime 280 * setting in config 281 * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PAUSE_LIMITER_EN: Invalid Receive MAC pause 282 * limitter enable setting in config 283 * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_MAX_LIMIT: Invalid Receive MAC max limit 284 * setting in config 285 * @VXGE_HAL_BADCFG_SWITCH_PORT_MAX_INITIAL_MTU: Invalid initial MTU size 286 * in config 287 * @VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_EN: Invalid Transmit MAC enable setting 288 * in config 289 * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_EN: Invalid Receive MAC enable setting 290 * in config 291 * @VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_PAD: Invalid Transmit MAC PAD enable 292 * setting in config 293 * @VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_PAD_BYTE: Invalid Transmit MAC PAD Byte 294 * setting in config 295 * @VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_UTIL_PERIOD: Invalid Transmit MAC 296 * utilization period in config 297 * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_STRIP_FCS: Invalid Receive MAC strip FCS 298 * setting in config 299 * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PROM_EN: Invalid Receive MAC PROM enable 300 * in config 301 * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_DISCARD_PFRM: Invalid Receive MAC discard 302 * pfrm setting in config 303 * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_UTIL_PERIOD: Invalid Receive MAC 304 * utilization period in config 305 * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PAUSE_GEN_EN: Invalid Receive MAC 306 * pause generation enable setting in config 307 * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PAUSE_RCV_EN: Invalid Receive MAC 308 * pause receive enable setting in config 309 * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_HIGH_PTIME: Invalid Receive MAC 310 * high ptime setting in config 311 * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PAUSE_LIMITER_EN: Invalid Receive MAC pause 312 * limitter enable setting in config 313 * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_MAX_LIMIT: Invalid Receive MAC 314 * max limit setting in config 315 * @VXGE_HAL_BADCFG_MAC_NETWORK_STABILITY_PERIOD: Invalid network 316 * stability period setting in config 317 * @VXGE_HAL_BADCFG_MAC_MC_PAUSE_THRESHOLD: Invalid MC pause threshold 318 * setting in config 319 * @VXGE_HAL_BADCFG_MAC_PERMA_STOP_EN: Invalid perma stop enable setting 320 * in config 321 * @VXGE_HAL_BADCFG_MAC_TMAC_TX_SWITCH_DIS: Invalid Transmit MAC 322 * tx switch disable in config 323 * @VXGE_HAL_BADCFG_MAC_TMAC_LOSSY_SWITCH_EN: Invalid Transmit MAC 324 * lossy switch enable in config 325 * @VXGE_HAL_BADCFG_MAC_TMAC_LOSSY_WIRE_EN: Invalid Transmit MAC 326 * lossy wire enable in config 327 * @VXGE_HAL_BADCFG_MAC_TMAC_BCAST_TO_WIRE_DIS: Invalid Transmit 328 * MAC broadcast to wire disable in config 329 * @VXGE_HAL_BADCFG_MAC_TMAC_BCAST_TO_SWITCH_DIS: Invalid Transmit 330 * MAC broadcast to switch disable in config 331 * @VXGE_HAL_BADCFG_MAC_TMAC_HOST_APPEND_FCS_EN: Invalid Transmit MAC 332 * host append fcs in config 333 * @VXGE_HAL_BADCFG_MAC_TPA_SUPPORT_SNAP_AB_N: Invalid Transmit Protocol 334 * Assist support SNAP AB N setting in config 335 * @VXGE_HAL_BADCFG_MAC_TPA_ECC_ENABLE_N: Invalid Transmit Protocol 336 * Assist ecc enable N setting in config 337 * @VXGE_HAL_BADCFG_MAC_RPA_IGNORE_FRAME_ERR: Invalid Receive Protocol 338 * Assist ignore frame error in config 339 * @VXGE_HAL_BADCFG_MAC_RPA_SNAP_AB_N: Invalid Receive Protocol Assist 340 * SNAP AB N in config 341 * @VXGE_HAL_BADCFG_MAC_RPA_SEARCH_FOR_HAO: Invalid Receive Protocol 342 * Assist search for HAO in config 343 * @VXGE_HAL_BADCFG_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS: Invalid Receive 344 * Protocol support ipv6 mobile headers in config 345 * @VXGE_HAL_BADCFG_MAC_RPA_IPV6_STOP_SEARCHING: Invalid Receive Protocol 346 * Assist ipv6 stop searching in config 347 * @VXGE_HAL_BADCFG_MAC_RPA_NO_PS_IF_UNKNOWN: Invalid Receive Protocol 348 * Assist no ps if unknown in config 349 * @VXGE_HAL_BADCFG_MAC_RPA_SEARCH_FOR_ETYPE: Invalid Receive Protocol 350 * Assist search for etype in config 351 * @VXGE_HAL_BADCFG_MAC_RPA_REPL_L4_COMP_CSUM: Invalid Receive Protocol 352 * Assist replication setting in config 353 * @VXGE_HAL_BADCFG_MAC_RPA_REPL_L3_INCL_CF: Invalid Receive Protocol Assist 354 * replication setting in config 355 * @VXGE_HAL_BADCFG_MAC_RPA_REPL_L3_COMP_CSUM: Invalid Receive Protocol Assist 356 * replication setting in config 357 * @VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV4_TCP_INCL_PH: Invalid Receive Protocol 358 * Assist replication setting in config 359 * @VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV6_TCP_INCL_PH: Invalid Receive Protocol 360 * Assist replication setting in config 361 * @VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV4_UDP_INCL_PH: Invalid Receive Protocol 362 * Assist replication setting in config 363 * @VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV6_UDP_INCL_PH: Invalid Receive Protocol 364 * Assist replication setting in config 365 * @VXGE_HAL_BADCFG_MAC_RPA_REPL_L4_INCL_CF: Invalid Receive Protocol Assist 366 * replication setting in config 367 * @VXGE_HAL_BADCFG_MAC_RPA_REPL_STRIP_VLAN_TAG: Invalid Receive Protocol 368 * Assist replication setting in config 369 * @VXGE_HAL_BADCFG_LAG_LAG_EN: Invalid option for lag_en in config 370 * @VXGE_HAL_BADCFG_LAG_LAG_MODE: Invalid option for lag_mode in config 371 * @VXGE_HAL_BADCFG_LAG_TX_DISCARD: Invalid option for tx_discard in config 372 * @VXGE_HAL_BADCFG_LAG_TX_AGGR_STATS: Invalid option for incr_tx_aggr_stats 373 * in config 374 * @VXGE_HAL_BADCFG_LAG_DISTRIB_ALG_SEL: Invalid option for distrib_alg_sel 375 * in config 376 * @VXGE_HAL_BADCFG_LAG_DISTRIB_REMAP_IF_FAIL: Invalid option for 377 * distrib_remap_if_fail in config 378 * @VXGE_HAL_BADCFG_LAG_COLL_MAX_DELAY: Invalid Collector Max Delay in config 379 * @VXGE_HAL_BADCFG_LAG_RX_DISCARD: Invalid option for rx_discard in config 380 * @VXGE_HAL_BADCFG_LAG_PREF_INDIV_PORT: Invalid option for pref_indiv_port 381 * in config 382 * @VXGE_HAL_BADCFG_LAG_HOT_STANDBY: Invalid option for hot_standby in config 383 * @VXGE_HAL_BADCFG_LAG_LACP_DECIDES: Invalid option for lacp_decides in config 384 * @VXGE_HAL_BADCFG_LAG_PREF_ACTIVE_PORT: Invalid option for pref_active_port 385 * in config 386 * @VXGE_HAL_BADCFG_LAG_AUTO_FAILBACK: Invalid option for auto_failback 387 * in config 388 * @VXGE_HAL_BADCFG_LAG_FAILBACK_EN: Invalid option for failback_en in config 389 * @VXGE_HAL_BADCFG_LAG_COLD_FAILOVER_TIMEOUT: Invalid cold_failover_timeout 390 * in config 391 * @VXGE_HAL_BADCFG_LAG_LACP_EN: Invalid option for lacp_en in config 392 * @VXGE_HAL_BADCFG_LAG_LACP_BEGIN: Invalid option for lacp_begin in config 393 * @VXGE_HAL_BADCFG_LAG_DISCARD_LACP: Invalid option for discard_lacp in config 394 * @VXGE_HAL_BADCFG_LAG_LIBERAL_LEN_CHK: Invalid option for liberal_len_chk 395 * in config 396 * @VXGE_HAL_BADCFG_LAG_MARKER_GEN_RECV_EN: Invalid option for 397 * marker_gen_recv_en in config 398 * @VXGE_HAL_BADCFG_LAG_MARKER_RESP_EN: Invalid option for marker_resp_en 399 * in config 400 * @VXGE_HAL_BADCFG_LAG_MARKER_RESP_TIMEOUT: Invalid option for 401 * marker_resp_timeout in config 402 * @VXGE_HAL_BADCFG_LAG_SLOW_PROTO_MRKR_MIN_INTERVAL: Invalid option for 403 * slow_proto_mrkr_min_interval in config 404 * @VXGE_HAL_BADCFG_LAG_THROTTLE_MRKR_RESP: Invalid option for 405 * throttle_mrkr_resp in config 406 * @VXGE_HAL_BADCFG_LAG_SYS_PRI: Invalid system priority in config 407 * @VXGE_HAL_BADCFG_LAG_USE_PORT_MAC_ADDR: Invalid option for 408 * use_port_mac_addr in config 409 * @VXGE_HAL_BADCFG_LAG_MAC_ADDR_SEL: Invalid option for mac_addr_sel in config 410 * @VXGE_HAL_BADCFG_LAG_ALT_ADMIN_KEY: Invalid alterneate admin key in config 411 * @VXGE_HAL_BADCFG_LAG_ALT_AGGR: Invalid option for alt_aggr in config 412 * @VXGE_HAL_BADCFG_LAG_FAST_PER_TIME: Invalid fast periodic time in config 413 * @VXGE_HAL_BADCFG_LAG_SLOW_PER_TIME: Invalid slow periodic time in config 414 * @VXGE_HAL_BADCFG_LAG_SHORT_TIMEOUT: Invalid short timeout in config 415 * @VXGE_HAL_BADCFG_LAG_LONG_TIMEOUT: Invalid long timeout in config 416 * @VXGE_HAL_BADCFG_LAG_CHURN_DET_TIME: Invalid churn detection time in config 417 * @VXGE_HAL_BADCFG_LAG_AGGR_WAIT_TIME: Invalid Aggregator wait time in config 418 * @VXGE_HAL_BADCFG_LAG_SHORT_TIMER_SCALE: Invalid short timer scale in config 419 * @VXGE_HAL_BADCFG_LAG_LONG_TIMER_SCALE: Invalid long timer scale in config 420 * @VXGE_HAL_BADCFG_LAG_AGGR_AGGR_ID: Invalid Aggregator Id in config 421 * @VXGE_HAL_BADCFG_LAG_AGGR_USE_PORT_MAC_ADDR: Invalid option for 422 * use_port_mac_addr in config 423 * @VXGE_HAL_BADCFG_LAG_AGGR_MAC_ADDR_SEL: Invalid option for mac_addr_sel 424 * in config 425 * @VXGE_HAL_BADCFG_LAG_AGGR_ADMIN_KEY: Invalid admin key in config 426 * @VXGE_HAL_BADCFG_LAG_PORT_PORT_ID: Invalid port id in config 427 * @VXGE_HAL_BADCFG_LAG_PORT_LAG_EN: Invalid option for lag_en in config 428 * @VXGE_HAL_BADCFG_LAG_PORT_DISCARD_SLOW_PROTO: Invalid option for 429 * discard_slow_proto in config 430 * @VXGE_HAL_BADCFG_LAG_PORT_HOST_CHOSEN_AGGR: Invalid option for 431 * host_chosen_aggr in config 432 * @VXGE_HAL_BADCFG_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO: Invalid option 433 * for discard unknown slow proto in config 434 * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_PORT_NUM: Invalid Actor port number in config 435 * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_PORT_PRIORITY: Invalid Actor port priority 436 * in config 437 * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_KEY_10G: Invalid Actor 10G key in config 438 * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_KEY_1G: Invalid Actor 1G key in config 439 * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_LACP_ACTIVITY: Invalid option for 440 * actor_lacp_activity in config 441 * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_LACP_TIMEOUT: Invalid option for 442 * actor_lacp_timeout in config 443 * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_AGGREGATION: Invalid option for 444 * actor_aggregation in config 445 * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_SYNCHRONIZATION: Invalid option 446 * for actor_synchronization in config 447 * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_COLLECTING: Invalid option for 448 * actor_collecting in config 449 * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_DISTRIBUTING: Invalid option for 450 * actor_distributing in config 451 * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_DEFAULTED: Invalid option for 452 * actor_defaulted in config 453 * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_EXPIRED: Invalid option for 454 * actor_expired in config 455 * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_SYS_PRI: Invalid option for 456 * partner_sys_pri in config 457 * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_KEY: Invalid option for 458 * partner_key in config 459 * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_NUM: Invalid option for 460 * partner_port_num in config 461 * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_PORT_PRIORITY: Invalid option for 462 * partner_port_pri in config 463 * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_LACP_ACTIVITY: Invalid option for 464 * partner_lacp_activity in config 465 * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_LACP_TIMEOUT: Invalid option for 466 * partner_lacp_timeout in config 467 * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_AGGREGATION: Invalid option for 468 * partner_aggregation in config 469 * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_SYNCHRONIZATION: Invalid option for 470 * partner_synchronization in config 471 * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_COLLECTING: Invalid option for 472 * partner_collecting in config 473 * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_DISTRIBUTING: Invalid option for 474 * partner_distributing in config 475 * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_DEFAULTED: Invalid option for 476 * partner_defaulted in config 477 * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_EXPIRED: Invalid option for 478 * partner_expired in config 479 * @VXGE_HAL_BADCFG_VPATH_QOS_PRIORITY: Invalid vpath priority 480 * @VXGE_HAL_BADCFG_VPATH_QOS_MIN_BANDWIDTH: Invalid minimum bandwidth 481 * @VXGE_HAL_BADCFG_VPATH_QOS_MAX_BANDWIDTH: Invalid maximum bandwidth 482 * @VXGE_HAL_BADCFG_LOG_LEVEL: Invalid option for partner_mac_addr in config 483 * @VXGE_HAL_BADCFG_RING_ENABLE: Invalid option for ring enable in config 484 * @VXGE_HAL_BADCFG_RING_LENGTH: Invalid ring length in config in config 485 * @VXGE_HAL_BADCFG_RING_RXD_BUFFER_MODE: Invalid receive buffer mode in config 486 * @VXGE_HAL_BADCFG_RING_SCATTER_MODE: Invalid scatter mode setting in config 487 * @VXGE_HAL_BADCFG_RING_POST_MODE: Invalid post mode setting in config 488 * @VXGE_HAL_BADCFG_RING_MAX_FRM_LEN: Invalid max frame length setting in config 489 * @VXGE_HAL_BADCFG_RING_NO_SNOOP_ALL: Invalid no snoop all setting in config 490 * @VXGE_HAL_BADCFG_RING_TIMER_VAL: Invalid timer value setting in config 491 * @VXGE_HAL_BADCFG_RING_GREEDY_RETURN: Invalid grredy return setting in config 492 * @VXGE_HAL_BADCFG_RING_TIMER_CI: Invalid timer ci setting in config 493 * @VXGE_HAL_BADCFG_RING_BACKOFF_INTERVAL_US: Invalid backoff interval 494 * in microseconds setting in config 495 * @VXGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS: Invalid indicate maximum packets 496 * setting in config 497 * @VXGE_HAL_BADCFG_FIFO_ENABLE: Invalid option for FIFO enable in config 498 * @VXGE_HAL_BADCFG_FIFO_LENGTH: Invalid FIFO length in config 499 * @VXGE_HAL_BADCFG_FIFO_FRAGS: Invalid number of transmit frame fragments 500 * in config 501 * @VXGE_HAL_BADCFG_FIFO_ALIGNMENT_SIZE: Invalid alignment size in config 502 * @VXGE_HAL_BADCFG_FIFO_MAX_FRAGS: Invalid maximum number of transmit frame 503 * fragments in config 504 * @VXGE_HAL_BADCFG_FIFO_QUEUE_INTR: Invalid FIFO queue interrupt setting 505 * in config 506 * @VXGE_HAL_BADCFG_FIFO_NO_SNOOP_ALL: Invalid FIFO no snoop all setting 507 * in config 508 * @VXGE_HAL_BADCFG_DMQ_LENGTH: Invalid DMQ length setting in config 509 * @VXGE_HAL_BADCFG_DMQ_IMMED_EN: Invalid DMQ immediate enable setting in config 510 * @VXGE_HAL_BADCFG_DMQ_EVENT_EN: Invalid DMQ event enable setting in config 511 * @VXGE_HAL_BADCFG_DMQ_INTR_CTRL: Invalid DMQ interrupt control setting 512 * in config 513 * @VXGE_HAL_BADCFG_DMQ_GEN_COMPL: Invalid DMQ general completion setting 514 * in config 515 * @VXGE_HAL_BADCFG_UMQ_LENGTH: Invalid UMQ length setting in config 516 * @VXGE_HAL_BADCFG_UMQ_IMMED_EN: Invalid UMQ immediate enable setting in config 517 * @VXGE_HAL_BADCFG_UMQ_EVENT_EN: Invalid UMQ event enable setting in config 518 * @VXGE_HAL_BADCFG_UMQ_INTR_CTRL: Invalid UMQ interrupt control setting 519 * in config 520 * @VXGE_HAL_BADCFG_UMQ_GEN_COMPL: Invalid UMQ general completion setting 521 * in config 522 * @VXGE_HAL_BADCFG_SW_LRO_SESSIONS: Invalid number of SW LRO sessions 523 * setting in config 524 * @VXGE_HAL_BADCFG_SW_LRO_SG_SIZE: Invalid SW LRO Segment size 525 * @VXGE_HAL_BADCFG_SW_LRO_FRM_LEN: Invalid SW LRO Frame Length 526 * @VXGE_HAL_BADCFG_SW_LRO_MODE: Invalid SW LRO mode setting in config 527 * @VXGE_HAL_BADCFG_LRO_SESSIONS_MAX: Invalid maximum number of LRO sessions 528 * setting in config 529 * @VXGE_HAL_BADCFG_LRO_SESSIONS_THRESHOLD: Invalid sessions number threshold 530 * setting in config 531 * @VXGE_HAL_BADCFG_LRO_SESSIONS_TIMEOUT: Invalid sessions timeout setting 532 * in config 533 * @VXGE_HAL_BADCFG_LRO_NO_WQE_THRESHOLD: Invalid lower limit for number 534 * of WQEs in config 535 * @VXGE_HAL_BADCFG_LRO_DUPACK_DETECTION: Invalid option for 536 * dupack_detection_enabled in config 537 * @VXGE_HAL_BADCFG_LRO_DATA_MERGING: Invalid option for 538 * data_merging_enabled in config 539 * @VXGE_HAL_BADCFG_LRO_ACK_MERGING: Invalid option for 540 * ack_merging_enabled in config 541 * @VXGE_HAL_BADCFG_LRO_LLC_HDR_MODE: Invalid LLC Header Mode 542 * @VXGE_HAL_BADCFG_LRO_SNAP_HDR_MODE: Invalid SNAP Header Mode 543 * @VXGE_HAL_BADCFG_LRO_SESSION_ECN: Invalid option for session_ecn_enabled 544 * @VXGE_HAL_BADCFG_LRO_SESSION_ECN_NONCE: Invalid option for 545 * session_ecn_enabled_nonce 546 * @VXGE_HAL_BADCFG_LRO_RXD_BUFFER_MODE: Invalid buffer mode 547 * @VXGE_HAL_BADCFG_LRO_SCATTER_MODE: Invalid scatter mode 548 * @VXGE_HAL_BADCFG_LRO_IP_DATAGRAM_SIZE: Invalid IP Datagram size 549 * @VXGE_HAL_BADCFG_LRO_FRAME_THRESHOLD: Invalid Frame Threshold 550 * @VXGE_HAL_BADCFG_LRO_PSH_THRESHOLD: Invalid push Threshold 551 * @VXGE_HAL_BADCFG_LRO_MTU_THRESHOLD: Invalid MTU Threshold 552 * @VXGE_HAL_BADCFG_LRO_MSS_THRESHOLD: Invalid MSS Threshold 553 * @VXGE_HAL_BADCFG_LRO_TCP_TSVAL_DELTA: Invalid TXP TSVAL DELTA 554 * @VXGE_HAL_BADCFG_LRO_ACK_NBR_DELTA: Invalid Acknowledgement delta 555 * @VXGE_HAL_BADCFG_LRO_SPARE_WQE_CAPACITY: Invalid Spare WQE Capacity 556 * @VXGE_HAL_BADCFG_TIM_INTR_ENABLE: Invalid TIM interrupt enable setting 557 * in config 558 * @VXGE_HAL_BADCFG_TIM_BTIMER_VAL: Invalid TIM btimer value setting in config 559 * @VXGE_HAL_BADCFG_TIM_TIMER_AC_EN: Invalid TIM timer ac enable setting 560 * in config 561 * @VXGE_HAL_BADCFG_TIM_TIMER_CI_EN: Invalid Tx timer continuous interrupt 562 * enable. See the structure vxge_hal_tim_intr_config_t {} for valid values. 563 * @VXGE_HAL_BADCFG_TIM_TIMER_RI_EN: Invalid TIM timer ri enable setting 564 * in config 565 * @VXGE_HAL_BADCFG_TIM_BTIMER_EVENT_SF: Invalid TIM btimer event sf seting 566 * in config 567 * @VXGE_HAL_BADCFG_TIM_RTIMER_VAL: Invalid TIM rtimer setting in config 568 * @VXGE_HAL_BADCFG_TIM_UTIL_SEL: Invalid TIM utilization setting in config 569 * @VXGE_HAL_BADCFG_TIM_LTIMER_VAL: Invalid TIM ltimer value setting in config 570 * @VXGE_HAL_BADCFG_TXFRM_CNT_EN: Invalid transmit frame count enable in config 571 * @VXGE_HAL_BADCFG_TXD_CNT_EN: Invalid transmit count enable in config 572 * @VXGE_HAL_BADCFG_TIM_URANGE_A: Invalid link utilization range A. See 573 * the structure vxge_hal_tim_intr_config_t {} for valid values. 574 * @VXGE_HAL_BADCFG_TIM_UEC_A: Invalid frame count for link utilization 575 * range A. See the structure vxge_hal_tim_intr_config_t {} for valid values. 576 * @VXGE_HAL_BADCFG_TIM_URANGE_B: Invalid link utilization range B. See 577 * the structure vxge_hal_tim_intr_config_t {} for valid values. 578 * @VXGE_HAL_BADCFG_TIM_UEC_B: Invalid frame count for link utilization 579 * range B. See the strucuture vxge_hal_tim_intr_config_t {} for valid values. 580 * @VXGE_HAL_BADCFG_TIM_URANGE_C: Invalid link utilization range C. See 581 * the structure vxge_hal_tim_intr_config_t {} for valid values. 582 * @VXGE_HAL_BADCFG_TIM_UEC_C: Invalid frame count for link utilization 583 * range C. See the structure vxge_hal_tim_intr_config_t {} for valid values. 584 * @VXGE_HAL_BADCFG_TIM_UEC_D: Invalid frame count for link utilization 585 * range D. See the structure vxge_hal_tim_intr_config_t {} for valid values. 586 * @VXGE_HAL_BADCFG_VPATH_ID: Invalid vpath id in config 587 * @VXGE_HAL_BADCFG_VPATH_WIRE_PORT: Invalid wire port to be used 588 * @VXGE_HAL_BADCFG_VPATH_NO_SNOOP: Invalid vpath no snoop setting in config 589 * @VXGE_HAL_BADCFG_VPATH_MTU: Invalid vpath mtu size setting in config 590 * @VXGE_HAL_BADCFG_VPATH_TPA_LSOV2_EN: Invalid vpath transmit protocol assist 591 * lso v2 en setting in config 592 * @VXGE_HAL_BADCFG_VPATH_TPA_IGNORE_FRAME_ERROR: Invalid vpath transmit 593 * protocol assist ignore frame error setting in config 594 * @VXGE_HAL_BADCFG_VPATH_TPA_IPV6_KEEP_SEARCHING: Invalid vpath transmit 595 * protocol assist ipv6 keep searching setting in config 596 * @VXGE_HAL_BADCFG_VPATH_TPA_L4_PSHDR_PRESENT: Invalid vpath transmit protocol 597 * assist L4 pseudo header present setting in config 598 * @VXGE_HAL_BADCFG_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS: Invalid vpath transmit 599 * protocol assist support mobile ipv6 headers setting in config 600 * @VXGE_HAL_BADCFG_VPATH_RPA_IPV4_TCP_INCL_PH: Invalid vpath receive protocol 601 * assist ipv4 tcp include pseudo header setting in config 602 * @VXGE_HAL_BADCFG_VPATH_RPA_IPV6_TCP_INCL_PH: Invalid vpath receive protocol 603 * assist ipv6 tcp include pseudo header setting in config 604 * @VXGE_HAL_BADCFG_VPATH_RPA_IPV4_UDP_INCL_PH: Invalid vpath receive protocol 605 * assist ipv4 udp include pseudo header setting in config 606 * @VXGE_HAL_BADCFG_VPATH_RPA_IPV6_UDP_INCL_PH: Invalid vpath receive protocol 607 * assist ipv6 udp include pseudo header setting in config 608 * @VXGE_HAL_BADCFG_VPATH_RPA_L4_INCL_CF: Invalid vpath receive protocol assist 609 * layer 4 include cf setting in config 610 * @VXGE_HAL_BADCFG_VPATH_RPA_STRIP_VLAN_TAG: Invalid vpath receive protocol 611 * assist strip vlan tag setting in config 612 * @VXGE_HAL_BADCFG_VPATH_RPA_L4_COMP_CSUM: Invalid vpath receive protocol 613 * assist layer 4 compute check sum setting in config 614 * @VXGE_HAL_BADCFG_VPATH_RPA_L3_INCL_CF: Invalid vpath receive protocol 615 * assist layer 3 include cf setting in config 616 * @VXGE_HAL_BADCFG_VPATH_RPA_L3_COMP_CSUM: Invalid vpath receive protocol 617 * assist layer 3 compute check sum setting in config 618 * @VXGE_HAL_BADCFG_VPATH_RPA_UCAST_ALL_ADDR_EN: Invalid vpath receive protocol 619 * assist unicast all address enable setting in config 620 * @VXGE_HAL_BADCFG_VPATH_RPA_MCAST_ALL_ADDR_EN: Invalid vpath receive protocol 621 * assist multi-icast all address enable setting in config 622 * @VXGE_HAL_BADCFG_VPATH_RPA_CAST_EN: Invalid vpath receive protocol assist 623 * cast enable setting in config 624 * @VXGE_HAL_BADCFG_VPATH_RPA_ALL_VID_EN: Invalid vpath receive protocol 625 * assist all vlan ids enable setting in config 626 * @VXGE_HAL_BADCFG_VPATH_VP_Q_L2_FLOW: Invalid Q l2 flow setting in config 627 * @VXGE_HAL_BADCFG_VPATH_VP_STATS_READ_METHOD: Invalid Stats read method 628 * @VXGE_HAL_BADCFG_VPATH_BANDWIDTH_LIMIT: Invalid bandwidth limit 629 * @VXGE_HAL_BADCFG_BLOCKPOOL_MIN: Invalid minimum number of block pool blocks 630 * setting in config 631 * @VXGE_HAL_BADCFG_BLOCKPOOL_INITIAL: Invalid initial number of block pool 632 * blocks setting in config 633 * @VXGE_HAL_BADCFG_BLOCKPOOL_INCR: Invalid number of block pool blocks 634 * increment setting in config 635 * @VXGE_HAL_BADCFG_BLOCKPOOL_MAX: Invalid maximum number of block pool 636 * blocks setting in config 637 * @VXGE_HAL_BADCFG_ISR_POLLING_CNT: Invalid isr polling count setting in config 638 * @VXGE_HAL_BADCFG_MAX_PAYLOAD_SIZE: Invalid maximum payload size setting 639 * in config 640 * @VXGE_HAL_BADCFG_MMRB_COUNT: Invalid mmrb count setting in config 641 * @VXGE_HAL_BADCFG_STATS_REFRESH_TIME: Invalid stats refresh time setting 642 * in config 643 * @VXGE_HAL_BADCFG_DUMP_ON_SERR: Invalid dump on serr setting in config 644 * @VXGE_HAL_BADCFG_DUMP_ON_CRITICAL: Invalid dump on critical error setting 645 * config 646 * @VXGE_HAL_BADCFG_DUMP_ON_ECCERR: Invalid dump on ecc error setting config 647 * @VXGE_HAL_BADCFG_DUMP_ON_UNKNOWN: Invalid dump on unknown alarm setting 648 * config 649 * @VXGE_HAL_BADCFG_INTR_MODE: Invalid interrupt mode setting in config 650 * @VXGE_HAL_BADCFG_RTH_EN: Invalid rth enable setting in config 651 * @VXGE_HAL_BADCFG_RTH_IT_TYPE: Invalid rth it type setting in config 652 * @VXGE_HAL_BADCFG_UFCA_INTR_THRES: Invalid rxufca interrupt threshold 653 * setting in config 654 * @VXGE_HAL_BADCFG_UFCA_LO_LIM: Invalid rxufca low limit setting in config 655 * @VXGE_HAL_BADCFG_UFCA_HI_LIM: Invalid rxufca high limit setting in config 656 * @VXGE_HAL_BADCFG_UFCA_LBOLT_PERIOD: Invalid rxufca lbolt period in config 657 * @VXGE_HAL_BADCFG_DEVICE_POLL_MILLIS: Invalid device poll timeout 658 * in milliseconds setting in config 659 * @VXGE_HAL_BADCFG_RTS_MAC_EN: Invalid rts mac enable setting in config 660 * @VXGE_HAL_BADCFG_RTS_QOS_EN: Invalid rts qos enable setting in config 661 * @VXGE_HAL_BADCFG_RTS_PORT_EN: Invalid rts port enable setting in config 662 * @VXGE_HAL_BADCFG_MAX_CQE_GROUPS: Invalid maximum number of CQE groups 663 * in config 664 * @VXGE_HAL_BADCFG_MAX_NUM_OD_GROUPS: Invalid maximum number of OD groups 665 * in config 666 * @VXGE_HAL_BADCFG_NO_WQE_THRESHOLD: Invalid no wqe threshold setting 667 * in config 668 * @VXGE_HAL_BADCFG_REFILL_THRESHOLD_HIGH: Invalid refill threshold setting 669 * in config 670 * @VXGE_HAL_BADCFG_REFILL_THRESHOLD_LOW: Invalid refill threshold setting 671 * in config 672 * @VXGE_HAL_BADCFG_ACK_BLOCK_LIMIT: Invalid acknowledgement block setting 673 * in config 674 * @VXGE_HAL_BADCFG_STATS_READ_METHOD: Invalid stats read method 675 * @VXGE_HAL_BADCFG_POLL_OR_DOOR_BELL: Invalid poll or doorbell setting 676 * in config 677 * @VXGE_HAL_BADCFG_MSIX_ID: Invalid MSIX Id 678 * @VXGE_HAL_EOF_TRACE_BUF: Invalid end of trace buffer setting in config 679 * 680 */ 681 typedef enum vxge_hal_status_e { 682 VXGE_HAL_OK = 0, 683 VXGE_HAL_FAIL = 1, 684 VXGE_HAL_PENDING = 2, 685 VXGE_HAL_CONTINUE = 3, 686 VXGE_HAL_RETURN = 4, 687 VXGE_HAL_COMPLETIONS_REMAIN = 5, 688 VXGE_HAL_TRAFFIC_INTERRUPT = 6, 689 690 VXGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS = VXGE_HAL_BASE_INF + 1, 691 VXGE_HAL_INF_OUT_OF_DESCRIPTORS = VXGE_HAL_BASE_INF + 2, 692 VXGE_HAL_INF_QUEUE_IS_NOT_READY = VXGE_HAL_BASE_INF + 4, 693 VXGE_HAL_INF_MEM_STROBE_CMD_EXECUTING = VXGE_HAL_BASE_INF + 5, 694 VXGE_HAL_INF_STATS_IS_NOT_READY = VXGE_HAL_BASE_INF + 6, 695 VXGE_HAL_INF_NO_MORE_FREED_DESCRIPTORS = VXGE_HAL_BASE_INF + 7, 696 VXGE_HAL_INF_IRQ_POLLING_CONTINUE = VXGE_HAL_BASE_INF + 8, 697 VXGE_HAL_INF_SW_LRO_BEGIN = VXGE_HAL_BASE_INF + 9, 698 VXGE_HAL_INF_SW_LRO_CONT = VXGE_HAL_BASE_INF + 10, 699 VXGE_HAL_INF_SW_LRO_UNCAPABLE = VXGE_HAL_BASE_INF + 11, 700 VXGE_HAL_INF_SW_LRO_FLUSH_SESSION = VXGE_HAL_BASE_INF + 12, 701 VXGE_HAL_INF_SW_LRO_FLUSH_BOTH = VXGE_HAL_BASE_INF + 13, 702 VXGE_HAL_INF_SW_LRO_END_3 = VXGE_HAL_BASE_INF + 14, 703 VXGE_HAL_INF_SW_LRO_SESSIONS_XCDED = VXGE_HAL_BASE_INF + 15, 704 VXGE_HAL_INF_NOT_ENOUGH_HW_CQES = VXGE_HAL_BASE_INF + 16, 705 VXGE_HAL_INF_LINK_UP_DOWN = VXGE_HAL_BASE_INF + 17, 706 707 VXGE_HAL_ERR_DRIVER_NOT_INITIALIZED = VXGE_HAL_BASE_ERR + 1, 708 VXGE_HAL_ERR_INVALID_HANDLE = VXGE_HAL_BASE_ERR + 2, 709 VXGE_HAL_ERR_OUT_OF_MEMORY = VXGE_HAL_BASE_ERR + 3, 710 VXGE_HAL_ERR_VPATH_NOT_AVAILABLE = VXGE_HAL_BASE_ERR + 4, 711 VXGE_HAL_ERR_VPATH_NOT_OPEN = VXGE_HAL_BASE_ERR + 5, 712 VXGE_HAL_ERR_WRONG_IRQ = VXGE_HAL_BASE_ERR + 6, 713 VXGE_HAL_ERR_OUT_OF_MAC_ADDRESSES = VXGE_HAL_BASE_ERR + 7, 714 VXGE_HAL_ERR_SWAPPER_CTRL = VXGE_HAL_BASE_ERR + 8, 715 VXGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT = VXGE_HAL_BASE_ERR + 9, 716 VXGE_HAL_ERR_INVALID_MTU_SIZE = VXGE_HAL_BASE_ERR + 10, 717 VXGE_HAL_ERR_OUT_OF_MAPPING = VXGE_HAL_BASE_ERR + 11, 718 VXGE_HAL_ERR_BAD_SUBSYSTEM_ID = VXGE_HAL_BASE_ERR + 12, 719 VXGE_HAL_ERR_INVALID_BAR_ID = VXGE_HAL_BASE_ERR + 13, 720 VXGE_HAL_ERR_INVALID_INDEX = VXGE_HAL_BASE_ERR + 14, 721 VXGE_HAL_ERR_INVALID_TYPE = VXGE_HAL_BASE_ERR + 15, 722 VXGE_HAL_ERR_INVALID_OFFSET = VXGE_HAL_BASE_ERR + 16, 723 VXGE_HAL_ERR_INVALID_DEVICE = VXGE_HAL_BASE_ERR + 17, 724 VXGE_HAL_ERR_OUT_OF_SPACE = VXGE_HAL_BASE_ERR + 18, 725 VXGE_HAL_ERR_INVALID_VALUE_BIT_SIZE = VXGE_HAL_BASE_ERR + 19, 726 VXGE_HAL_ERR_VERSION_CONFLICT = VXGE_HAL_BASE_ERR + 20, 727 VXGE_HAL_ERR_INVALID_MAC_ADDRESS = VXGE_HAL_BASE_ERR + 21, 728 VXGE_HAL_ERR_BAD_DEVICE_ID = VXGE_HAL_BASE_ERR + 22, 729 VXGE_HAL_ERR_OUT_ALIGNED_FRAGS = VXGE_HAL_BASE_ERR + 23, 730 VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED = VXGE_HAL_BASE_ERR + 24, 731 VXGE_HAL_ERR_SPDM_NOT_ENABLED = VXGE_HAL_BASE_ERR + 25, 732 VXGE_HAL_ERR_SPDM_TABLE_FULL = VXGE_HAL_BASE_ERR + 26, 733 VXGE_HAL_ERR_SPDM_INVALID_ENTRY = VXGE_HAL_BASE_ERR + 27, 734 VXGE_HAL_ERR_SPDM_ENTRY_NOT_FOUND = VXGE_HAL_BASE_ERR + 28, 735 VXGE_HAL_ERR_SPDM_TABLE_DATA_INCONSISTENT = VXGE_HAL_BASE_ERR + 29, 736 VXGE_HAL_ERR_INVALID_PCI_INFO = VXGE_HAL_BASE_ERR + 30, 737 VXGE_HAL_ERR_CRITICAL = VXGE_HAL_BASE_ERR + 31, 738 VXGE_HAL_ERR_RESET_FAILED = VXGE_HAL_BASE_ERR + 32, 739 VXGE_HAL_ERR_TOO_MANY = VXGE_HAL_BASE_ERR + 33, 740 VXGE_HAL_ERR_PKT_DROP = VXGE_HAL_BASE_ERR + 34, 741 VXGE_HAL_ERR_INVALID_BLOCK_SIZE = VXGE_HAL_BASE_ERR + 35, 742 VXGE_HAL_ERR_INVALID_STATE = VXGE_HAL_BASE_ERR + 36, 743 VXGE_HAL_ERR_PRIVILAGED_OPEARATION = VXGE_HAL_BASE_ERR + 37, 744 VXGE_HAL_ERR_RESET_IN_PROGRESS = VXGE_HAL_BASE_ERR + 38, 745 VXGE_HAL_ERR_MAC_TABLE_FULL = VXGE_HAL_BASE_ERR + 39, 746 VXGE_HAL_ERR_MAC_TABLE_EMPTY = VXGE_HAL_BASE_ERR + 40, 747 VXGE_HAL_ERR_MAC_TABLE_NO_MORE_ENTRIES = VXGE_HAL_BASE_ERR + 41, 748 VXGE_HAL_ERR_RTDMA_RTDMA_READY = VXGE_HAL_BASE_ERR + 42, 749 VXGE_HAL_ERR_WRDMA_WRDMA_READY = VXGE_HAL_BASE_ERR + 43, 750 VXGE_HAL_ERR_KDFC_KDFC_READY = VXGE_HAL_BASE_ERR + 44, 751 VXGE_HAL_ERR_TPA_TMAC_BUF_EMPTY = VXGE_HAL_BASE_ERR + 45, 752 VXGE_HAL_ERR_RDCTL_PIC_QUIESCENT = VXGE_HAL_BASE_ERR + 46, 753 VXGE_HAL_ERR_XGMAC_NETWORK_FAULT = VXGE_HAL_BASE_ERR + 47, 754 VXGE_HAL_ERR_ROCRC_OFFLOAD_QUIESCENT = VXGE_HAL_BASE_ERR + 48, 755 VXGE_HAL_ERR_G3IF_FB_G3IF_FB_GDDR3_READY = VXGE_HAL_BASE_ERR + 49, 756 VXGE_HAL_ERR_G3IF_CM_G3IF_CM_GDDR3_READY = VXGE_HAL_BASE_ERR + 50, 757 VXGE_HAL_ERR_RIC_RIC_RUNNING = VXGE_HAL_BASE_ERR + 51, 758 VXGE_HAL_ERR_CMG_C_PLL_IN_LOCK = VXGE_HAL_BASE_ERR + 52, 759 VXGE_HAL_ERR_XGMAC_X_PLL_IN_LOCK = VXGE_HAL_BASE_ERR + 53, 760 VXGE_HAL_ERR_FBIF_M_PLL_IN_LOCK = VXGE_HAL_BASE_ERR + 54, 761 VXGE_HAL_ERR_PCC_PCC_IDLE = VXGE_HAL_BASE_ERR + 55, 762 VXGE_HAL_ERR_ROCRC_RC_PRC_QUIESCENT = VXGE_HAL_BASE_ERR + 56, 763 VXGE_HAL_ERR_SLOT_FREEZE = VXGE_HAL_BASE_ERR + 57, 764 VXGE_HAL_ERR_INVALID_TCODE = VXGE_HAL_BASE_ERR + 58, 765 VXGE_HAL_ERR_INVALID_PORT = VXGE_HAL_BASE_ERR + 59, 766 VXGE_HAL_ERR_INVALID_WIRE_PORT = VXGE_HAL_BASE_ERR + 60, 767 VXGE_HAL_ERR_INVALID_PRIORITY = VXGE_HAL_BASE_ERR + 61, 768 VXGE_HAL_ERR_INVALID_MIN_BANDWIDTH = VXGE_HAL_BASE_ERR + 62, 769 VXGE_HAL_ERR_INVALID_MAX_BANDWIDTH = VXGE_HAL_BASE_ERR + 63, 770 VXGE_HAL_ERR_INVALID_BANDWIDTH_LIMIT = VXGE_HAL_BASE_ERR + 64, 771 VXGE_HAL_ERR_INVALID_TOTAL_BANDWIDTH = VXGE_HAL_BASE_ERR + 65, 772 VXGE_HAL_ERR_MANAGER_NOT_FOUND = VXGE_HAL_BASE_ERR + 66, 773 VXGE_HAL_ERR_TIME_OUT = VXGE_HAL_BASE_ERR + 67, 774 VXGE_HAL_ERR_EVENT_UNKNOWN = VXGE_HAL_BASE_ERR + 68, 775 VXGE_HAL_ERR_EVENT_SERR = VXGE_HAL_BASE_ERR + 69, 776 VXGE_HAL_ERR_EVENT_CRITICAL = VXGE_HAL_BASE_ERR + 70, 777 VXGE_HAL_ERR_EVENT_ECCERR = VXGE_HAL_BASE_ERR + 71, 778 VXGE_HAL_ERR_EVENT_KDFCCTL = VXGE_HAL_BASE_ERR + 72, 779 VXGE_HAL_ERR_EVENT_SRPCIM_CRITICAL = VXGE_HAL_BASE_ERR + 73, 780 VXGE_HAL_ERR_EVENT_MRPCIM_CRITICAL = VXGE_HAL_BASE_ERR + 74, 781 VXGE_HAL_ERR_EVENT_MRPCIM_ECCERR = VXGE_HAL_BASE_ERR + 75, 782 VXGE_HAL_ERR_EVENT_RESET_START = VXGE_HAL_BASE_ERR + 76, 783 VXGE_HAL_ERR_EVENT_RESET_COMPLETE = VXGE_HAL_BASE_ERR + 77, 784 VXGE_HAL_ERR_EVENT_SLOT_FREEZE = VXGE_HAL_BASE_ERR + 78, 785 VXGE_HAL_ERR_INVALID_DP_MODE = VXGE_HAL_BASE_ERR + 79, 786 VXGE_HAL_ERR_INVALID_L2_SWITCH_STATE = VXGE_HAL_BASE_ERR + 79, 787 788 VXGE_HAL_BADCFG_WIRE_PORT_PORT_ID = VXGE_HAL_BASE_BADCFG + 1, 789 VXGE_HAL_BADCFG_WIRE_PORT_MAX_MEDIA = VXGE_HAL_BASE_BADCFG + 2, 790 VXGE_HAL_BADCFG_WIRE_PORT_MAX_INITIAL_MTU = VXGE_HAL_BASE_BADCFG + 3, 791 VXGE_HAL_BADCFG_WIRE_PORT_AUTONEG_MODE = VXGE_HAL_BASE_BADCFG + 4, 792 VXGE_HAL_BADCFG_WIRE_PORT_AUTONEG_RATE = VXGE_HAL_BASE_BADCFG + 5, 793 VXGE_HAL_BADCFG_WIRE_PORT_FIXED_USE_FSM = VXGE_HAL_BASE_BADCFG + 6, 794 VXGE_HAL_BADCFG_WIRE_PORT_ANTP_USE_FSM = VXGE_HAL_BASE_BADCFG + 7, 795 VXGE_HAL_BADCFG_WIRE_PORT_ANBE_USE_FSM = VXGE_HAL_BASE_BADCFG + 8, 796 VXGE_HAL_BADCFG_WIRE_PORT_LINK_STABILITY_PERIOD = 797 VXGE_HAL_BASE_BADCFG + 9, 798 VXGE_HAL_BADCFG_WIRE_PORT_PORT_STABILITY_PERIOD = 799 VXGE_HAL_BASE_BADCFG + 10, 800 VXGE_HAL_BADCFG_WIRE_PORT_TMAC_EN = VXGE_HAL_BASE_BADCFG + 11, 801 VXGE_HAL_BADCFG_WIRE_PORT_RMAC_EN = VXGE_HAL_BASE_BADCFG + 12, 802 VXGE_HAL_BADCFG_WIRE_PORT_TMAC_PAD = VXGE_HAL_BASE_BADCFG + 13, 803 VXGE_HAL_BADCFG_WIRE_PORT_TMAC_PAD_BYTE = VXGE_HAL_BASE_BADCFG + 14, 804 VXGE_HAL_BADCFG_WIRE_PORT_TMAC_UTIL_PERIOD = VXGE_HAL_BASE_BADCFG + 15, 805 VXGE_HAL_BADCFG_WIRE_PORT_RMAC_STRIP_FCS = VXGE_HAL_BASE_BADCFG + 16, 806 VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PROM_EN = VXGE_HAL_BASE_BADCFG + 18, 807 VXGE_HAL_BADCFG_WIRE_PORT_RMAC_DISCARD_PFRM = VXGE_HAL_BASE_BADCFG + 19, 808 VXGE_HAL_BADCFG_WIRE_PORT_RMAC_UTIL_PERIOD = VXGE_HAL_BASE_BADCFG + 20, 809 VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PAUSE_GEN_EN = VXGE_HAL_BASE_BADCFG + 21, 810 VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PAUSE_RCV_EN = VXGE_HAL_BASE_BADCFG + 22, 811 VXGE_HAL_BADCFG_WIRE_PORT_RMAC_HIGH_PTIME = VXGE_HAL_BASE_BADCFG + 23, 812 VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PAUSE_LIMITER_EN = 813 VXGE_HAL_BASE_BADCFG + 24, 814 VXGE_HAL_BADCFG_WIRE_PORT_RMAC_MAX_LIMIT = VXGE_HAL_BASE_BADCFG + 25, 815 VXGE_HAL_BADCFG_SWITCH_PORT_MAX_INITIAL_MTU = VXGE_HAL_BASE_BADCFG + 26, 816 VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_EN = VXGE_HAL_BASE_BADCFG + 27, 817 VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_EN = VXGE_HAL_BASE_BADCFG + 28, 818 VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_PAD = VXGE_HAL_BASE_BADCFG + 29, 819 VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_PAD_BYTE = VXGE_HAL_BASE_BADCFG + 30, 820 VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_UTIL_PERIOD = 821 VXGE_HAL_BASE_BADCFG + 31, 822 VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_STRIP_FCS = VXGE_HAL_BASE_BADCFG + 32, 823 VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PROM_EN = VXGE_HAL_BASE_BADCFG + 33, 824 VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_DISCARD_PFRM = 825 VXGE_HAL_BASE_BADCFG + 34, 826 VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_UTIL_PERIOD = 827 VXGE_HAL_BASE_BADCFG + 35, 828 VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PAUSE_GEN_EN = 829 VXGE_HAL_BASE_BADCFG + 36, 830 VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PAUSE_RCV_EN = 831 VXGE_HAL_BASE_BADCFG + 37, 832 VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_HIGH_PTIME = VXGE_HAL_BASE_BADCFG + 38, 833 VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PAUSE_LIMITER_EN = 834 VXGE_HAL_BASE_BADCFG + 39, 835 VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_MAX_LIMIT = VXGE_HAL_BASE_BADCFG + 40, 836 VXGE_HAL_BADCFG_MAC_NETWORK_STABILITY_PERIOD = 837 VXGE_HAL_BASE_BADCFG + 41, 838 VXGE_HAL_BADCFG_MAC_MC_PAUSE_THRESHOLD = VXGE_HAL_BASE_BADCFG + 42, 839 VXGE_HAL_BADCFG_MAC_PERMA_STOP_EN = VXGE_HAL_BASE_BADCFG + 43, 840 VXGE_HAL_BADCFG_MAC_TMAC_TX_SWITCH_DIS = VXGE_HAL_BASE_BADCFG + 44, 841 VXGE_HAL_BADCFG_MAC_TMAC_LOSSY_SWITCH_EN = VXGE_HAL_BASE_BADCFG + 45, 842 VXGE_HAL_BADCFG_MAC_TMAC_LOSSY_WIRE_EN = VXGE_HAL_BASE_BADCFG + 46, 843 VXGE_HAL_BADCFG_MAC_TMAC_BCAST_TO_WIRE_DIS = VXGE_HAL_BASE_BADCFG + 47, 844 VXGE_HAL_BADCFG_MAC_TMAC_BCAST_TO_SWITCH_DIS = 845 VXGE_HAL_BASE_BADCFG + 48, 846 VXGE_HAL_BADCFG_MAC_TMAC_HOST_APPEND_FCS_EN = VXGE_HAL_BASE_BADCFG + 49, 847 VXGE_HAL_BADCFG_MAC_TPA_SUPPORT_SNAP_AB_N = VXGE_HAL_BASE_BADCFG + 50, 848 VXGE_HAL_BADCFG_MAC_TPA_ECC_ENABLE_N = VXGE_HAL_BASE_BADCFG + 51, 849 VXGE_HAL_BADCFG_MAC_RPA_IGNORE_FRAME_ERR = VXGE_HAL_BASE_BADCFG + 52, 850 VXGE_HAL_BADCFG_MAC_RPA_SNAP_AB_N = VXGE_HAL_BASE_BADCFG + 53, 851 VXGE_HAL_BADCFG_MAC_RPA_SEARCH_FOR_HAO = VXGE_HAL_BASE_BADCFG + 54, 852 VXGE_HAL_BADCFG_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS = 853 VXGE_HAL_BASE_BADCFG + 55, 854 VXGE_HAL_BADCFG_MAC_RPA_IPV6_STOP_SEARCHING = VXGE_HAL_BASE_BADCFG + 56, 855 VXGE_HAL_BADCFG_MAC_RPA_NO_PS_IF_UNKNOWN = VXGE_HAL_BASE_BADCFG + 57, 856 VXGE_HAL_BADCFG_MAC_RPA_SEARCH_FOR_ETYPE = VXGE_HAL_BASE_BADCFG + 58, 857 VXGE_HAL_BADCFG_MAC_RPA_REPL_L4_COMP_CSUM = VXGE_HAL_BASE_BADCFG + 59, 858 VXGE_HAL_BADCFG_MAC_RPA_REPL_L3_INCL_CF = VXGE_HAL_BASE_BADCFG + 60, 859 VXGE_HAL_BADCFG_MAC_RPA_REPL_L3_COMP_CSUM = VXGE_HAL_BASE_BADCFG + 61, 860 VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV4_TCP_INCL_PH = 861 VXGE_HAL_BASE_BADCFG + 62, 862 VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV6_TCP_INCL_PH = 863 VXGE_HAL_BASE_BADCFG + 63, 864 VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV4_UDP_INCL_PH = 865 VXGE_HAL_BASE_BADCFG + 64, 866 VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV6_UDP_INCL_PH = 867 VXGE_HAL_BASE_BADCFG + 65, 868 VXGE_HAL_BADCFG_MAC_RPA_REPL_L4_INCL_CF = VXGE_HAL_BASE_BADCFG + 66, 869 VXGE_HAL_BADCFG_MAC_RPA_REPL_STRIP_VLAN_TAG = VXGE_HAL_BASE_BADCFG + 67, 870 871 VXGE_HAL_BADCFG_LAG_LAG_EN = VXGE_HAL_BASE_BADCFG + 101, 872 VXGE_HAL_BADCFG_LAG_LAG_MODE = VXGE_HAL_BASE_BADCFG + 102, 873 VXGE_HAL_BADCFG_LAG_TX_DISCARD = VXGE_HAL_BASE_BADCFG + 103, 874 VXGE_HAL_BADCFG_LAG_TX_AGGR_STATS = VXGE_HAL_BASE_BADCFG + 104, 875 VXGE_HAL_BADCFG_LAG_DISTRIB_ALG_SEL = VXGE_HAL_BASE_BADCFG + 105, 876 VXGE_HAL_BADCFG_LAG_DISTRIB_REMAP_IF_FAIL = VXGE_HAL_BASE_BADCFG + 106, 877 VXGE_HAL_BADCFG_LAG_COLL_MAX_DELAY = VXGE_HAL_BASE_BADCFG + 107, 878 VXGE_HAL_BADCFG_LAG_RX_DISCARD = VXGE_HAL_BASE_BADCFG + 108, 879 VXGE_HAL_BADCFG_LAG_PREF_INDIV_PORT = VXGE_HAL_BASE_BADCFG + 109, 880 VXGE_HAL_BADCFG_LAG_HOT_STANDBY = VXGE_HAL_BASE_BADCFG + 110, 881 VXGE_HAL_BADCFG_LAG_LACP_DECIDES = VXGE_HAL_BASE_BADCFG + 111, 882 VXGE_HAL_BADCFG_LAG_PREF_ACTIVE_PORT = VXGE_HAL_BASE_BADCFG + 112, 883 VXGE_HAL_BADCFG_LAG_AUTO_FAILBACK = VXGE_HAL_BASE_BADCFG + 113, 884 VXGE_HAL_BADCFG_LAG_FAILBACK_EN = VXGE_HAL_BASE_BADCFG + 114, 885 VXGE_HAL_BADCFG_LAG_COLD_FAILOVER_TIMEOUT = VXGE_HAL_BASE_BADCFG + 115, 886 VXGE_HAL_BADCFG_LAG_LACP_EN = VXGE_HAL_BASE_BADCFG + 116, 887 VXGE_HAL_BADCFG_LAG_LACP_BEGIN = VXGE_HAL_BASE_BADCFG + 117, 888 VXGE_HAL_BADCFG_LAG_DISCARD_LACP = VXGE_HAL_BASE_BADCFG + 118, 889 VXGE_HAL_BADCFG_LAG_LIBERAL_LEN_CHK = VXGE_HAL_BASE_BADCFG + 119, 890 VXGE_HAL_BADCFG_LAG_MARKER_GEN_RECV_EN = VXGE_HAL_BASE_BADCFG + 120, 891 VXGE_HAL_BADCFG_LAG_MARKER_RESP_EN = VXGE_HAL_BASE_BADCFG + 121, 892 VXGE_HAL_BADCFG_LAG_MARKER_RESP_TIMEOUT = VXGE_HAL_BASE_BADCFG + 122, 893 VXGE_HAL_BADCFG_LAG_SLOW_PROTO_MRKR_MIN_INTERVAL = 894 VXGE_HAL_BASE_BADCFG + 123, 895 VXGE_HAL_BADCFG_LAG_THROTTLE_MRKR_RESP = VXGE_HAL_BASE_BADCFG + 124, 896 VXGE_HAL_BADCFG_LAG_SYS_PRI = VXGE_HAL_BASE_BADCFG + 125, 897 VXGE_HAL_BADCFG_LAG_USE_PORT_MAC_ADDR = VXGE_HAL_BASE_BADCFG + 126, 898 VXGE_HAL_BADCFG_LAG_MAC_ADDR_SEL = VXGE_HAL_BASE_BADCFG + 127, 899 VXGE_HAL_BADCFG_LAG_ALT_ADMIN_KEY = VXGE_HAL_BASE_BADCFG + 128, 900 VXGE_HAL_BADCFG_LAG_ALT_AGGR = VXGE_HAL_BASE_BADCFG + 129, 901 VXGE_HAL_BADCFG_LAG_FAST_PER_TIME = VXGE_HAL_BASE_BADCFG + 130, 902 VXGE_HAL_BADCFG_LAG_SLOW_PER_TIME = VXGE_HAL_BASE_BADCFG + 131, 903 VXGE_HAL_BADCFG_LAG_SHORT_TIMEOUT = VXGE_HAL_BASE_BADCFG + 132, 904 VXGE_HAL_BADCFG_LAG_LONG_TIMEOUT = VXGE_HAL_BASE_BADCFG + 133, 905 VXGE_HAL_BADCFG_LAG_CHURN_DET_TIME = VXGE_HAL_BASE_BADCFG + 134, 906 VXGE_HAL_BADCFG_LAG_AGGR_WAIT_TIME = VXGE_HAL_BASE_BADCFG + 135, 907 VXGE_HAL_BADCFG_LAG_SHORT_TIMER_SCALE = VXGE_HAL_BASE_BADCFG + 136, 908 VXGE_HAL_BADCFG_LAG_LONG_TIMER_SCALE = VXGE_HAL_BASE_BADCFG + 137, 909 VXGE_HAL_BADCFG_LAG_AGGR_AGGR_ID = VXGE_HAL_BASE_BADCFG + 138, 910 VXGE_HAL_BADCFG_LAG_AGGR_USE_PORT_MAC_ADDR = VXGE_HAL_BASE_BADCFG + 139, 911 VXGE_HAL_BADCFG_LAG_AGGR_MAC_ADDR_SEL = VXGE_HAL_BASE_BADCFG + 140, 912 VXGE_HAL_BADCFG_LAG_AGGR_ADMIN_KEY = VXGE_HAL_BASE_BADCFG + 141, 913 VXGE_HAL_BADCFG_LAG_PORT_PORT_ID = VXGE_HAL_BASE_BADCFG + 142, 914 VXGE_HAL_BADCFG_LAG_PORT_LAG_EN = VXGE_HAL_BASE_BADCFG + 143, 915 VXGE_HAL_BADCFG_LAG_PORT_DISCARD_SLOW_PROTO = 916 VXGE_HAL_BASE_BADCFG + 144, 917 VXGE_HAL_BADCFG_LAG_PORT_HOST_CHOSEN_AGGR = VXGE_HAL_BASE_BADCFG + 145, 918 VXGE_HAL_BADCFG_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO = 919 VXGE_HAL_BASE_BADCFG + 146, 920 VXGE_HAL_BADCFG_LAG_PORT_ACTOR_PORT_NUM = VXGE_HAL_BASE_BADCFG + 147, 921 VXGE_HAL_BADCFG_LAG_PORT_ACTOR_PORT_PRIORITY = 922 VXGE_HAL_BASE_BADCFG + 148, 923 VXGE_HAL_BADCFG_LAG_PORT_ACTOR_KEY_10G = VXGE_HAL_BASE_BADCFG + 149, 924 VXGE_HAL_BADCFG_LAG_PORT_ACTOR_KEY_1G = VXGE_HAL_BASE_BADCFG + 150, 925 VXGE_HAL_BADCFG_LAG_PORT_ACTOR_LACP_ACTIVITY = 926 VXGE_HAL_BASE_BADCFG + 151, 927 VXGE_HAL_BADCFG_LAG_PORT_ACTOR_LACP_TIMEOUT = 928 VXGE_HAL_BASE_BADCFG + 152, 929 VXGE_HAL_BADCFG_LAG_PORT_ACTOR_AGGREGATION = VXGE_HAL_BASE_BADCFG + 153, 930 VXGE_HAL_BADCFG_LAG_PORT_ACTOR_SYNCHRONIZATION = 931 VXGE_HAL_BASE_BADCFG + 154, 932 VXGE_HAL_BADCFG_LAG_PORT_ACTOR_COLLECTING = VXGE_HAL_BASE_BADCFG + 155, 933 VXGE_HAL_BADCFG_LAG_PORT_ACTOR_DISTRIBUTING = 934 VXGE_HAL_BASE_BADCFG + 156, 935 VXGE_HAL_BADCFG_LAG_PORT_ACTOR_DEFAULTED = VXGE_HAL_BASE_BADCFG + 157, 936 VXGE_HAL_BADCFG_LAG_PORT_ACTOR_EXPIRED = VXGE_HAL_BASE_BADCFG + 158, 937 VXGE_HAL_BADCFG_LAG_PORT_PARTNER_SYS_PRI = VXGE_HAL_BASE_BADCFG + 159, 938 VXGE_HAL_BADCFG_LAG_PORT_PARTNER_KEY = VXGE_HAL_BASE_BADCFG + 160, 939 VXGE_HAL_BADCFG_LAG_PORT_PARTNER_NUM = VXGE_HAL_BASE_BADCFG + 161, 940 VXGE_HAL_BADCFG_LAG_PORT_PARTNER_PORT_PRIORITY = 941 VXGE_HAL_BASE_BADCFG + 162, 942 VXGE_HAL_BADCFG_LAG_PORT_PARTNER_LACP_ACTIVITY = 943 VXGE_HAL_BASE_BADCFG + 163, 944 VXGE_HAL_BADCFG_LAG_PORT_PARTNER_LACP_TIMEOUT = 945 VXGE_HAL_BASE_BADCFG + 164, 946 VXGE_HAL_BADCFG_LAG_PORT_PARTNER_AGGREGATION = 947 VXGE_HAL_BASE_BADCFG + 165, 948 VXGE_HAL_BADCFG_LAG_PORT_PARTNER_SYNCHRONIZATION = 949 VXGE_HAL_BASE_BADCFG + 166, 950 VXGE_HAL_BADCFG_LAG_PORT_PARTNER_COLLECTING = 951 VXGE_HAL_BASE_BADCFG + 167, 952 VXGE_HAL_BADCFG_LAG_PORT_PARTNER_DISTRIBUTING = 953 VXGE_HAL_BASE_BADCFG + 168, 954 VXGE_HAL_BADCFG_LAG_PORT_PARTNER_DEFAULTED = 955 VXGE_HAL_BASE_BADCFG + 169, 956 VXGE_HAL_BADCFG_LAG_PORT_PARTNER_EXPIRED = 957 VXGE_HAL_BASE_BADCFG + 170, 958 VXGE_HAL_BADCFG_VPATH_QOS_PRIORITY = VXGE_HAL_BASE_BADCFG + 171, 959 VXGE_HAL_BADCFG_VPATH_QOS_MIN_BANDWIDTH = VXGE_HAL_BASE_BADCFG + 172, 960 VXGE_HAL_BADCFG_VPATH_QOS_MAX_BANDWIDTH = VXGE_HAL_BASE_BADCFG + 173, 961 962 VXGE_HAL_BADCFG_LOG_LEVEL = VXGE_HAL_BASE_BADCFG + 202, 963 VXGE_HAL_BADCFG_RING_ENABLE = VXGE_HAL_BASE_BADCFG + 203, 964 VXGE_HAL_BADCFG_RING_LENGTH = VXGE_HAL_BASE_BADCFG + 204, 965 VXGE_HAL_BADCFG_RING_RXD_BUFFER_MODE = VXGE_HAL_BASE_BADCFG + 205, 966 VXGE_HAL_BADCFG_RING_SCATTER_MODE = VXGE_HAL_BASE_BADCFG + 206, 967 VXGE_HAL_BADCFG_RING_POST_MODE = VXGE_HAL_BASE_BADCFG + 207, 968 VXGE_HAL_BADCFG_RING_MAX_FRM_LEN = VXGE_HAL_BASE_BADCFG + 208, 969 VXGE_HAL_BADCFG_RING_NO_SNOOP_ALL = VXGE_HAL_BASE_BADCFG + 209, 970 VXGE_HAL_BADCFG_RING_TIMER_VAL = VXGE_HAL_BASE_BADCFG + 210, 971 VXGE_HAL_BADCFG_RING_GREEDY_RETURN = VXGE_HAL_BASE_BADCFG + 211, 972 VXGE_HAL_BADCFG_RING_TIMER_CI = VXGE_HAL_BASE_BADCFG + 212, 973 VXGE_HAL_BADCFG_RING_BACKOFF_INTERVAL_US = VXGE_HAL_BASE_BADCFG + 213, 974 VXGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS = VXGE_HAL_BASE_BADCFG + 214, 975 VXGE_HAL_BADCFG_FIFO_ENABLE = VXGE_HAL_BASE_BADCFG + 215, 976 VXGE_HAL_BADCFG_FIFO_LENGTH = VXGE_HAL_BASE_BADCFG + 216, 977 VXGE_HAL_BADCFG_FIFO_FRAGS = VXGE_HAL_BASE_BADCFG + 217, 978 VXGE_HAL_BADCFG_FIFO_ALIGNMENT_SIZE = VXGE_HAL_BASE_BADCFG + 218, 979 VXGE_HAL_BADCFG_FIFO_MAX_FRAGS = VXGE_HAL_BASE_BADCFG + 219, 980 VXGE_HAL_BADCFG_FIFO_QUEUE_INTR = VXGE_HAL_BASE_BADCFG + 220, 981 VXGE_HAL_BADCFG_FIFO_NO_SNOOP_ALL = VXGE_HAL_BASE_BADCFG + 221, 982 VXGE_HAL_BADCFG_DMQ_LENGTH = VXGE_HAL_BASE_BADCFG + 222, 983 VXGE_HAL_BADCFG_DMQ_IMMED_EN = VXGE_HAL_BASE_BADCFG + 223, 984 VXGE_HAL_BADCFG_DMQ_EVENT_EN = VXGE_HAL_BASE_BADCFG + 224, 985 VXGE_HAL_BADCFG_DMQ_INTR_CTRL = VXGE_HAL_BASE_BADCFG + 225, 986 VXGE_HAL_BADCFG_DMQ_GEN_COMPL = VXGE_HAL_BASE_BADCFG + 226, 987 VXGE_HAL_BADCFG_UMQ_LENGTH = VXGE_HAL_BASE_BADCFG + 227, 988 VXGE_HAL_BADCFG_UMQ_IMMED_EN = VXGE_HAL_BASE_BADCFG + 228, 989 VXGE_HAL_BADCFG_UMQ_EVENT_EN = VXGE_HAL_BASE_BADCFG + 229, 990 VXGE_HAL_BADCFG_UMQ_INTR_CTRL = VXGE_HAL_BASE_BADCFG + 230, 991 VXGE_HAL_BADCFG_UMQ_GEN_COMPL = VXGE_HAL_BASE_BADCFG + 231, 992 VXGE_HAL_BADCFG_SW_LRO_SESSIONS = VXGE_HAL_BASE_BADCFG + 232, 993 VXGE_HAL_BADCFG_SW_LRO_SG_SIZE = VXGE_HAL_BASE_BADCFG + 333, 994 VXGE_HAL_BADCFG_SW_LRO_FRM_LEN = VXGE_HAL_BASE_BADCFG + 334, 995 VXGE_HAL_BADCFG_SW_LRO_MODE = VXGE_HAL_BASE_BADCFG + 235, 996 VXGE_HAL_BADCFG_LRO_SESSIONS_MAX = VXGE_HAL_BASE_BADCFG + 236, 997 VXGE_HAL_BADCFG_LRO_SESSIONS_THRESHOLD = VXGE_HAL_BASE_BADCFG + 237, 998 VXGE_HAL_BADCFG_LRO_SESSIONS_TIMEOUT = VXGE_HAL_BASE_BADCFG + 238, 999 VXGE_HAL_BADCFG_LRO_NO_WQE_THRESHOLD = VXGE_HAL_BASE_BADCFG + 239, 1000 VXGE_HAL_BADCFG_LRO_DUPACK_DETECTION = VXGE_HAL_BASE_BADCFG + 242, 1001 VXGE_HAL_BADCFG_LRO_DATA_MERGING = VXGE_HAL_BASE_BADCFG + 243, 1002 VXGE_HAL_BADCFG_LRO_ACK_MERGING = VXGE_HAL_BASE_BADCFG + 244, 1003 VXGE_HAL_BADCFG_LRO_LLC_HDR_MODE = VXGE_HAL_BASE_BADCFG + 245, 1004 VXGE_HAL_BADCFG_LRO_SNAP_HDR_MODE = VXGE_HAL_BASE_BADCFG + 246, 1005 VXGE_HAL_BADCFG_LRO_SESSION_ECN = VXGE_HAL_BASE_BADCFG + 247, 1006 VXGE_HAL_BADCFG_LRO_SESSION_ECN_NONCE = VXGE_HAL_BASE_BADCFG + 248, 1007 VXGE_HAL_BADCFG_LRO_RXD_BUFFER_MODE = VXGE_HAL_BASE_BADCFG + 249, 1008 VXGE_HAL_BADCFG_LRO_SCATTER_MODE = VXGE_HAL_BASE_BADCFG + 250, 1009 VXGE_HAL_BADCFG_LRO_IP_DATAGRAM_SIZE = VXGE_HAL_BASE_BADCFG + 251, 1010 VXGE_HAL_BADCFG_LRO_FRAME_THRESHOLD = VXGE_HAL_BASE_BADCFG + 252, 1011 VXGE_HAL_BADCFG_LRO_PSH_THRESHOLD = VXGE_HAL_BASE_BADCFG + 253, 1012 VXGE_HAL_BADCFG_LRO_MTU_THRESHOLD = VXGE_HAL_BASE_BADCFG + 254, 1013 VXGE_HAL_BADCFG_LRO_MSS_THRESHOLD = VXGE_HAL_BASE_BADCFG + 255, 1014 VXGE_HAL_BADCFG_LRO_TCP_TSVAL_DELTA = VXGE_HAL_BASE_BADCFG + 256, 1015 VXGE_HAL_BADCFG_LRO_ACK_NBR_DELTA = VXGE_HAL_BASE_BADCFG + 257, 1016 VXGE_HAL_BADCFG_LRO_SPARE_WQE_CAPACITY = VXGE_HAL_BASE_BADCFG + 258, 1017 VXGE_HAL_BADCFG_TIM_INTR_ENABLE = VXGE_HAL_BASE_BADCFG + 259, 1018 VXGE_HAL_BADCFG_TIM_BTIMER_VAL = VXGE_HAL_BASE_BADCFG + 261, 1019 VXGE_HAL_BADCFG_TIM_TIMER_AC_EN = VXGE_HAL_BASE_BADCFG + 262, 1020 VXGE_HAL_BADCFG_TIM_TIMER_CI_EN = VXGE_HAL_BASE_BADCFG + 263, 1021 VXGE_HAL_BADCFG_TIM_TIMER_RI_EN = VXGE_HAL_BASE_BADCFG + 264, 1022 VXGE_HAL_BADCFG_TIM_BTIMER_EVENT_SF = VXGE_HAL_BASE_BADCFG + 265, 1023 VXGE_HAL_BADCFG_TIM_RTIMER_VAL = VXGE_HAL_BASE_BADCFG + 266, 1024 VXGE_HAL_BADCFG_TIM_UTIL_SEL = VXGE_HAL_BASE_BADCFG + 267, 1025 VXGE_HAL_BADCFG_TIM_LTIMER_VAL = VXGE_HAL_BASE_BADCFG + 268, 1026 VXGE_HAL_BADCFG_TXFRM_CNT_EN = VXGE_HAL_BASE_BADCFG + 269, 1027 VXGE_HAL_BADCFG_TXD_CNT_EN = VXGE_HAL_BASE_BADCFG + 270, 1028 VXGE_HAL_BADCFG_TIM_URANGE_A = VXGE_HAL_BASE_BADCFG + 271, 1029 VXGE_HAL_BADCFG_TIM_UEC_A = VXGE_HAL_BASE_BADCFG + 272, 1030 VXGE_HAL_BADCFG_TIM_URANGE_B = VXGE_HAL_BASE_BADCFG + 273, 1031 VXGE_HAL_BADCFG_TIM_UEC_B = VXGE_HAL_BASE_BADCFG + 274, 1032 VXGE_HAL_BADCFG_TIM_URANGE_C = VXGE_HAL_BASE_BADCFG + 275, 1033 VXGE_HAL_BADCFG_TIM_UEC_C = VXGE_HAL_BASE_BADCFG + 276, 1034 VXGE_HAL_BADCFG_TIM_UEC_D = VXGE_HAL_BASE_BADCFG + 277, 1035 VXGE_HAL_BADCFG_VPATH_ID = VXGE_HAL_BASE_BADCFG + 278, 1036 VXGE_HAL_BADCFG_VPATH_WIRE_PORT = VXGE_HAL_BASE_BADCFG + 279, 1037 VXGE_HAL_BADCFG_VPATH_NO_SNOOP = VXGE_HAL_BASE_BADCFG + 281, 1038 VXGE_HAL_BADCFG_VPATH_MTU = VXGE_HAL_BASE_BADCFG + 282, 1039 VXGE_HAL_BADCFG_VPATH_TPA_LSOV2_EN = VXGE_HAL_BASE_BADCFG + 283, 1040 VXGE_HAL_BADCFG_VPATH_TPA_IGNORE_FRAME_ERROR = 1041 VXGE_HAL_BASE_BADCFG + 284, 1042 VXGE_HAL_BADCFG_VPATH_TPA_IPV6_KEEP_SEARCHING = 1043 VXGE_HAL_BASE_BADCFG + 285, 1044 VXGE_HAL_BADCFG_VPATH_TPA_L4_PSHDR_PRESENT = VXGE_HAL_BASE_BADCFG + 286, 1045 VXGE_HAL_BADCFG_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS = 1046 VXGE_HAL_BASE_BADCFG + 287, 1047 VXGE_HAL_BADCFG_VPATH_RPA_IPV4_TCP_INCL_PH = VXGE_HAL_BASE_BADCFG + 288, 1048 VXGE_HAL_BADCFG_VPATH_RPA_IPV6_TCP_INCL_PH = VXGE_HAL_BASE_BADCFG + 289, 1049 VXGE_HAL_BADCFG_VPATH_RPA_IPV4_UDP_INCL_PH = VXGE_HAL_BASE_BADCFG + 290, 1050 VXGE_HAL_BADCFG_VPATH_RPA_IPV6_UDP_INCL_PH = VXGE_HAL_BASE_BADCFG + 291, 1051 VXGE_HAL_BADCFG_VPATH_RPA_L4_INCL_CF = VXGE_HAL_BASE_BADCFG + 292, 1052 VXGE_HAL_BADCFG_VPATH_RPA_STRIP_VLAN_TAG = VXGE_HAL_BASE_BADCFG + 293, 1053 VXGE_HAL_BADCFG_VPATH_RPA_L4_COMP_CSUM = VXGE_HAL_BASE_BADCFG + 294, 1054 VXGE_HAL_BADCFG_VPATH_RPA_L3_INCL_CF = VXGE_HAL_BASE_BADCFG + 295, 1055 VXGE_HAL_BADCFG_VPATH_RPA_L3_COMP_CSUM = VXGE_HAL_BASE_BADCFG + 296, 1056 VXGE_HAL_BADCFG_VPATH_RPA_UCAST_ALL_ADDR_EN = 1057 VXGE_HAL_BASE_BADCFG + 297, 1058 VXGE_HAL_BADCFG_VPATH_RPA_MCAST_ALL_ADDR_EN = 1059 VXGE_HAL_BASE_BADCFG + 298, 1060 VXGE_HAL_BADCFG_VPATH_RPA_CAST_EN = VXGE_HAL_BASE_BADCFG + 299, 1061 VXGE_HAL_BADCFG_VPATH_RPA_ALL_VID_EN = VXGE_HAL_BASE_BADCFG + 300, 1062 VXGE_HAL_BADCFG_VPATH_VP_Q_L2_FLOW = VXGE_HAL_BASE_BADCFG + 301, 1063 VXGE_HAL_BADCFG_VPATH_VP_STATS_READ_METHOD = VXGE_HAL_BASE_BADCFG + 302, 1064 VXGE_HAL_BADCFG_VPATH_BANDWIDTH_LIMIT = VXGE_HAL_BASE_BADCFG + 305, 1065 VXGE_HAL_BADCFG_BLOCKPOOL_MIN = VXGE_HAL_BASE_BADCFG + 306, 1066 VXGE_HAL_BADCFG_BLOCKPOOL_INITIAL = VXGE_HAL_BASE_BADCFG + 307, 1067 VXGE_HAL_BADCFG_BLOCKPOOL_INCR = VXGE_HAL_BASE_BADCFG + 308, 1068 VXGE_HAL_BADCFG_BLOCKPOOL_MAX = VXGE_HAL_BASE_BADCFG + 309, 1069 VXGE_HAL_BADCFG_ISR_POLLING_CNT = VXGE_HAL_BASE_BADCFG + 310, 1070 VXGE_HAL_BADCFG_MAX_PAYLOAD_SIZE = VXGE_HAL_BASE_BADCFG + 312, 1071 VXGE_HAL_BADCFG_MMRB_COUNT = VXGE_HAL_BASE_BADCFG + 313, 1072 VXGE_HAL_BADCFG_STATS_REFRESH_TIME = VXGE_HAL_BASE_BADCFG + 314, 1073 VXGE_HAL_BADCFG_DUMP_ON_UNKNOWN = VXGE_HAL_BASE_BADCFG + 315, 1074 VXGE_HAL_BADCFG_DUMP_ON_SERR = VXGE_HAL_BASE_BADCFG + 316, 1075 VXGE_HAL_BADCFG_DUMP_ON_CRITICAL = VXGE_HAL_BASE_BADCFG + 317, 1076 VXGE_HAL_BADCFG_DUMP_ON_ECCERR = VXGE_HAL_BASE_BADCFG + 318, 1077 VXGE_HAL_BADCFG_INTR_MODE = VXGE_HAL_BASE_BADCFG + 319, 1078 VXGE_HAL_BADCFG_RTH_EN = VXGE_HAL_BASE_BADCFG + 320, 1079 VXGE_HAL_BADCFG_RTH_IT_TYPE = VXGE_HAL_BASE_BADCFG + 321, 1080 VXGE_HAL_BADCFG_UFCA_INTR_THRES = VXGE_HAL_BASE_BADCFG + 323, 1081 VXGE_HAL_BADCFG_UFCA_LO_LIM = VXGE_HAL_BASE_BADCFG + 324, 1082 VXGE_HAL_BADCFG_UFCA_HI_LIM = VXGE_HAL_BASE_BADCFG + 325, 1083 VXGE_HAL_BADCFG_UFCA_LBOLT_PERIOD = VXGE_HAL_BASE_BADCFG + 326, 1084 VXGE_HAL_BADCFG_DEVICE_POLL_MILLIS = VXGE_HAL_BASE_BADCFG + 327, 1085 VXGE_HAL_BADCFG_RTS_MAC_EN = VXGE_HAL_BASE_BADCFG + 330, 1086 VXGE_HAL_BADCFG_RTS_QOS_EN = VXGE_HAL_BASE_BADCFG + 331, 1087 VXGE_HAL_BADCFG_RTS_PORT_EN = VXGE_HAL_BASE_BADCFG + 332, 1088 VXGE_HAL_BADCFG_MAX_CQE_GROUPS = VXGE_HAL_BASE_BADCFG + 333, 1089 VXGE_HAL_BADCFG_MAX_NUM_OD_GROUPS = VXGE_HAL_BASE_BADCFG + 334, 1090 VXGE_HAL_BADCFG_NO_WQE_THRESHOLD = VXGE_HAL_BASE_BADCFG + 335, 1091 VXGE_HAL_BADCFG_REFILL_THRESHOLD_HIGH = VXGE_HAL_BASE_BADCFG + 336, 1092 VXGE_HAL_BADCFG_REFILL_THRESHOLD_LOW = VXGE_HAL_BASE_BADCFG + 337, 1093 VXGE_HAL_BADCFG_ACK_BLOCK_LIMIT = VXGE_HAL_BASE_BADCFG + 338, 1094 VXGE_HAL_BADCFG_STATS_READ_METHOD = VXGE_HAL_BASE_BADCFG + 339, 1095 VXGE_HAL_BADCFG_POLL_OR_DOOR_BELL = VXGE_HAL_BASE_BADCFG + 340, 1096 VXGE_HAL_BADCFG_MSIX_ID = VXGE_HAL_BASE_BADCFG + 341, 1097 VXGE_HAL_BADCFG_VPATH_PRIORITY = VXGE_HAL_BASE_BADCFG + 342, 1098 VXGE_HAL_EOF_TRACE_BUF = -1 1099 1100 } vxge_hal_status_e; 1101 1102 /* 1103 * enum vxge_hal_result_e - HAL Up Message result codes. 1104 * @VXGE_HAL_RESULT_OK: Success 1105 */ 1106 typedef enum vxge_hal_result_e { 1107 VXGE_HAL_RESULT_OK = 0 1108 } vxge_hal_result_e; 1109 1110 __EXTERN_END_DECLS 1111 1112 #endif /* VXGE_HAL_STATUS_H */ 1113