1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: stable/12/sys/amd64/include/vmm_dev.h 368641 2020-12-14 20:40:21Z jhb $ 29 */ 30 31 #ifndef _VMM_DEV_H_ 32 #define _VMM_DEV_H_ 33 34 #ifdef _KERNEL 35 void vmmdev_init(void); 36 int vmmdev_cleanup(void); 37 #endif 38 39 struct vm_memmap { 40 vm_paddr_t gpa; 41 int segid; /* memory segment */ 42 vm_ooffset_t segoff; /* offset into memory segment */ 43 size_t len; /* mmap length */ 44 int prot; /* RWX */ 45 int flags; 46 }; 47 #define VM_MEMMAP_F_WIRED 0x01 48 #define VM_MEMMAP_F_IOMMU 0x02 49 50 #define VM_MEMSEG_NAME(m) ((m)->name[0] != '\0' ? (m)->name : NULL) 51 struct vm_memseg { 52 int segid; 53 size_t len; 54 char name[SPECNAMELEN + 1]; 55 }; 56 57 struct vm_register { 58 int cpuid; 59 int regnum; /* enum vm_reg_name */ 60 uint64_t regval; 61 }; 62 63 struct vm_seg_desc { /* data or code segment */ 64 int cpuid; 65 int regnum; /* enum vm_reg_name */ 66 struct seg_desc desc; 67 }; 68 69 struct vm_register_set { 70 int cpuid; 71 unsigned int count; 72 const int *regnums; /* enum vm_reg_name */ 73 uint64_t *regvals; 74 }; 75 76 struct vm_run { 77 int cpuid; 78 struct vm_exit vm_exit; 79 }; 80 81 struct vm_exception { 82 int cpuid; 83 int vector; 84 uint32_t error_code; 85 int error_code_valid; 86 int restart_instruction; 87 }; 88 89 struct vm_lapic_msi { 90 uint64_t msg; 91 uint64_t addr; 92 }; 93 94 struct vm_lapic_irq { 95 int cpuid; 96 int vector; 97 }; 98 99 struct vm_ioapic_irq { 100 int irq; 101 }; 102 103 struct vm_isa_irq { 104 int atpic_irq; 105 int ioapic_irq; 106 }; 107 108 struct vm_isa_irq_trigger { 109 int atpic_irq; 110 enum vm_intr_trigger trigger; 111 }; 112 113 struct vm_capability { 114 int cpuid; 115 enum vm_cap_type captype; 116 int capval; 117 int allcpus; 118 }; 119 120 struct vm_pptdev { 121 int bus; 122 int slot; 123 int func; 124 }; 125 126 struct vm_pptdev_mmio { 127 int bus; 128 int slot; 129 int func; 130 vm_paddr_t gpa; 131 vm_paddr_t hpa; 132 size_t len; 133 }; 134 135 struct vm_pptdev_msi { 136 int vcpu; 137 int bus; 138 int slot; 139 int func; 140 int numvec; /* 0 means disabled */ 141 uint64_t msg; 142 uint64_t addr; 143 }; 144 145 struct vm_pptdev_msix { 146 int vcpu; 147 int bus; 148 int slot; 149 int func; 150 int idx; 151 uint64_t msg; 152 uint32_t vector_control; 153 uint64_t addr; 154 }; 155 156 struct vm_nmi { 157 int cpuid; 158 }; 159 160 #define MAX_VM_STATS 64 161 struct vm_stats { 162 int cpuid; /* in */ 163 int num_entries; /* out */ 164 struct timeval tv; 165 uint64_t statbuf[MAX_VM_STATS]; 166 }; 167 168 struct vm_stat_desc { 169 int index; /* in */ 170 char desc[128]; /* out */ 171 }; 172 173 struct vm_x2apic { 174 int cpuid; 175 enum x2apic_state state; 176 }; 177 178 struct vm_gpa_pte { 179 uint64_t gpa; /* in */ 180 uint64_t pte[4]; /* out */ 181 int ptenum; 182 }; 183 184 struct vm_hpet_cap { 185 uint32_t capabilities; /* lower 32 bits of HPET capabilities */ 186 }; 187 188 struct vm_suspend { 189 enum vm_suspend_how how; 190 }; 191 192 struct vm_gla2gpa { 193 int vcpuid; /* inputs */ 194 int prot; /* PROT_READ or PROT_WRITE */ 195 uint64_t gla; 196 struct vm_guest_paging paging; 197 int fault; /* outputs */ 198 uint64_t gpa; 199 }; 200 201 struct vm_activate_cpu { 202 int vcpuid; 203 }; 204 205 struct vm_cpuset { 206 int which; 207 int cpusetsize; 208 cpuset_t *cpus; 209 }; 210 #define VM_ACTIVE_CPUS 0 211 #define VM_SUSPENDED_CPUS 1 212 #define VM_DEBUG_CPUS 2 213 214 struct vm_intinfo { 215 int vcpuid; 216 uint64_t info1; 217 uint64_t info2; 218 }; 219 220 struct vm_rtc_time { 221 time_t secs; 222 }; 223 224 struct vm_rtc_data { 225 int offset; 226 uint8_t value; 227 }; 228 229 struct vm_cpu_topology { 230 uint16_t sockets; 231 uint16_t cores; 232 uint16_t threads; 233 uint16_t maxcpus; 234 }; 235 236 enum { 237 /* general routines */ 238 IOCNUM_ABIVERS = 0, 239 IOCNUM_RUN = 1, 240 IOCNUM_SET_CAPABILITY = 2, 241 IOCNUM_GET_CAPABILITY = 3, 242 IOCNUM_SUSPEND = 4, 243 IOCNUM_REINIT = 5, 244 245 /* memory apis */ 246 IOCNUM_MAP_MEMORY = 10, /* deprecated */ 247 IOCNUM_GET_MEMORY_SEG = 11, /* deprecated */ 248 IOCNUM_GET_GPA_PMAP = 12, 249 IOCNUM_GLA2GPA = 13, 250 IOCNUM_ALLOC_MEMSEG = 14, 251 IOCNUM_GET_MEMSEG = 15, 252 IOCNUM_MMAP_MEMSEG = 16, 253 IOCNUM_MMAP_GETNEXT = 17, 254 IOCNUM_GLA2GPA_NOFAULT = 18, 255 256 /* register/state accessors */ 257 IOCNUM_SET_REGISTER = 20, 258 IOCNUM_GET_REGISTER = 21, 259 IOCNUM_SET_SEGMENT_DESCRIPTOR = 22, 260 IOCNUM_GET_SEGMENT_DESCRIPTOR = 23, 261 IOCNUM_SET_REGISTER_SET = 24, 262 IOCNUM_GET_REGISTER_SET = 25, 263 264 /* interrupt injection */ 265 IOCNUM_GET_INTINFO = 28, 266 IOCNUM_SET_INTINFO = 29, 267 IOCNUM_INJECT_EXCEPTION = 30, 268 IOCNUM_LAPIC_IRQ = 31, 269 IOCNUM_INJECT_NMI = 32, 270 IOCNUM_IOAPIC_ASSERT_IRQ = 33, 271 IOCNUM_IOAPIC_DEASSERT_IRQ = 34, 272 IOCNUM_IOAPIC_PULSE_IRQ = 35, 273 IOCNUM_LAPIC_MSI = 36, 274 IOCNUM_LAPIC_LOCAL_IRQ = 37, 275 IOCNUM_IOAPIC_PINCOUNT = 38, 276 IOCNUM_RESTART_INSTRUCTION = 39, 277 278 /* PCI pass-thru */ 279 IOCNUM_BIND_PPTDEV = 40, 280 IOCNUM_UNBIND_PPTDEV = 41, 281 IOCNUM_MAP_PPTDEV_MMIO = 42, 282 IOCNUM_PPTDEV_MSI = 43, 283 IOCNUM_PPTDEV_MSIX = 44, 284 IOCNUM_PPTDEV_DISABLE_MSIX = 45, 285 286 /* statistics */ 287 IOCNUM_VM_STATS = 50, 288 IOCNUM_VM_STAT_DESC = 51, 289 290 /* kernel device state */ 291 IOCNUM_SET_X2APIC_STATE = 60, 292 IOCNUM_GET_X2APIC_STATE = 61, 293 IOCNUM_GET_HPET_CAPABILITIES = 62, 294 295 /* CPU Topology */ 296 IOCNUM_SET_TOPOLOGY = 63, 297 IOCNUM_GET_TOPOLOGY = 64, 298 299 /* legacy interrupt injection */ 300 IOCNUM_ISA_ASSERT_IRQ = 80, 301 IOCNUM_ISA_DEASSERT_IRQ = 81, 302 IOCNUM_ISA_PULSE_IRQ = 82, 303 IOCNUM_ISA_SET_IRQ_TRIGGER = 83, 304 305 /* vm_cpuset */ 306 IOCNUM_ACTIVATE_CPU = 90, 307 IOCNUM_GET_CPUSET = 91, 308 IOCNUM_SUSPEND_CPU = 92, 309 IOCNUM_RESUME_CPU = 93, 310 311 /* RTC */ 312 IOCNUM_RTC_READ = 100, 313 IOCNUM_RTC_WRITE = 101, 314 IOCNUM_RTC_SETTIME = 102, 315 IOCNUM_RTC_GETTIME = 103, 316 }; 317 318 #define VM_RUN \ 319 _IOWR('v', IOCNUM_RUN, struct vm_run) 320 #define VM_SUSPEND \ 321 _IOW('v', IOCNUM_SUSPEND, struct vm_suspend) 322 #define VM_REINIT \ 323 _IO('v', IOCNUM_REINIT) 324 #define VM_ALLOC_MEMSEG \ 325 _IOW('v', IOCNUM_ALLOC_MEMSEG, struct vm_memseg) 326 #define VM_GET_MEMSEG \ 327 _IOWR('v', IOCNUM_GET_MEMSEG, struct vm_memseg) 328 #define VM_MMAP_MEMSEG \ 329 _IOW('v', IOCNUM_MMAP_MEMSEG, struct vm_memmap) 330 #define VM_MMAP_GETNEXT \ 331 _IOWR('v', IOCNUM_MMAP_GETNEXT, struct vm_memmap) 332 #define VM_SET_REGISTER \ 333 _IOW('v', IOCNUM_SET_REGISTER, struct vm_register) 334 #define VM_GET_REGISTER \ 335 _IOWR('v', IOCNUM_GET_REGISTER, struct vm_register) 336 #define VM_SET_SEGMENT_DESCRIPTOR \ 337 _IOW('v', IOCNUM_SET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 338 #define VM_GET_SEGMENT_DESCRIPTOR \ 339 _IOWR('v', IOCNUM_GET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 340 #define VM_SET_REGISTER_SET \ 341 _IOW('v', IOCNUM_SET_REGISTER_SET, struct vm_register_set) 342 #define VM_GET_REGISTER_SET \ 343 _IOWR('v', IOCNUM_GET_REGISTER_SET, struct vm_register_set) 344 #define VM_INJECT_EXCEPTION \ 345 _IOW('v', IOCNUM_INJECT_EXCEPTION, struct vm_exception) 346 #define VM_LAPIC_IRQ \ 347 _IOW('v', IOCNUM_LAPIC_IRQ, struct vm_lapic_irq) 348 #define VM_LAPIC_LOCAL_IRQ \ 349 _IOW('v', IOCNUM_LAPIC_LOCAL_IRQ, struct vm_lapic_irq) 350 #define VM_LAPIC_MSI \ 351 _IOW('v', IOCNUM_LAPIC_MSI, struct vm_lapic_msi) 352 #define VM_IOAPIC_ASSERT_IRQ \ 353 _IOW('v', IOCNUM_IOAPIC_ASSERT_IRQ, struct vm_ioapic_irq) 354 #define VM_IOAPIC_DEASSERT_IRQ \ 355 _IOW('v', IOCNUM_IOAPIC_DEASSERT_IRQ, struct vm_ioapic_irq) 356 #define VM_IOAPIC_PULSE_IRQ \ 357 _IOW('v', IOCNUM_IOAPIC_PULSE_IRQ, struct vm_ioapic_irq) 358 #define VM_IOAPIC_PINCOUNT \ 359 _IOR('v', IOCNUM_IOAPIC_PINCOUNT, int) 360 #define VM_ISA_ASSERT_IRQ \ 361 _IOW('v', IOCNUM_ISA_ASSERT_IRQ, struct vm_isa_irq) 362 #define VM_ISA_DEASSERT_IRQ \ 363 _IOW('v', IOCNUM_ISA_DEASSERT_IRQ, struct vm_isa_irq) 364 #define VM_ISA_PULSE_IRQ \ 365 _IOW('v', IOCNUM_ISA_PULSE_IRQ, struct vm_isa_irq) 366 #define VM_ISA_SET_IRQ_TRIGGER \ 367 _IOW('v', IOCNUM_ISA_SET_IRQ_TRIGGER, struct vm_isa_irq_trigger) 368 #define VM_SET_CAPABILITY \ 369 _IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability) 370 #define VM_GET_CAPABILITY \ 371 _IOWR('v', IOCNUM_GET_CAPABILITY, struct vm_capability) 372 #define VM_BIND_PPTDEV \ 373 _IOW('v', IOCNUM_BIND_PPTDEV, struct vm_pptdev) 374 #define VM_UNBIND_PPTDEV \ 375 _IOW('v', IOCNUM_UNBIND_PPTDEV, struct vm_pptdev) 376 #define VM_MAP_PPTDEV_MMIO \ 377 _IOW('v', IOCNUM_MAP_PPTDEV_MMIO, struct vm_pptdev_mmio) 378 #define VM_PPTDEV_MSI \ 379 _IOW('v', IOCNUM_PPTDEV_MSI, struct vm_pptdev_msi) 380 #define VM_PPTDEV_MSIX \ 381 _IOW('v', IOCNUM_PPTDEV_MSIX, struct vm_pptdev_msix) 382 #define VM_PPTDEV_DISABLE_MSIX \ 383 _IOW('v', IOCNUM_PPTDEV_DISABLE_MSIX, struct vm_pptdev) 384 #define VM_INJECT_NMI \ 385 _IOW('v', IOCNUM_INJECT_NMI, struct vm_nmi) 386 #define VM_STATS \ 387 _IOWR('v', IOCNUM_VM_STATS, struct vm_stats) 388 #define VM_STAT_DESC \ 389 _IOWR('v', IOCNUM_VM_STAT_DESC, struct vm_stat_desc) 390 #define VM_SET_X2APIC_STATE \ 391 _IOW('v', IOCNUM_SET_X2APIC_STATE, struct vm_x2apic) 392 #define VM_GET_X2APIC_STATE \ 393 _IOWR('v', IOCNUM_GET_X2APIC_STATE, struct vm_x2apic) 394 #define VM_GET_HPET_CAPABILITIES \ 395 _IOR('v', IOCNUM_GET_HPET_CAPABILITIES, struct vm_hpet_cap) 396 #define VM_SET_TOPOLOGY \ 397 _IOW('v', IOCNUM_SET_TOPOLOGY, struct vm_cpu_topology) 398 #define VM_GET_TOPOLOGY \ 399 _IOR('v', IOCNUM_GET_TOPOLOGY, struct vm_cpu_topology) 400 #define VM_GET_GPA_PMAP \ 401 _IOWR('v', IOCNUM_GET_GPA_PMAP, struct vm_gpa_pte) 402 #define VM_GLA2GPA \ 403 _IOWR('v', IOCNUM_GLA2GPA, struct vm_gla2gpa) 404 #define VM_GLA2GPA_NOFAULT \ 405 _IOWR('v', IOCNUM_GLA2GPA_NOFAULT, struct vm_gla2gpa) 406 #define VM_ACTIVATE_CPU \ 407 _IOW('v', IOCNUM_ACTIVATE_CPU, struct vm_activate_cpu) 408 #define VM_GET_CPUS \ 409 _IOW('v', IOCNUM_GET_CPUSET, struct vm_cpuset) 410 #define VM_SUSPEND_CPU \ 411 _IOW('v', IOCNUM_SUSPEND_CPU, struct vm_activate_cpu) 412 #define VM_RESUME_CPU \ 413 _IOW('v', IOCNUM_RESUME_CPU, struct vm_activate_cpu) 414 #define VM_SET_INTINFO \ 415 _IOW('v', IOCNUM_SET_INTINFO, struct vm_intinfo) 416 #define VM_GET_INTINFO \ 417 _IOWR('v', IOCNUM_GET_INTINFO, struct vm_intinfo) 418 #define VM_RTC_WRITE \ 419 _IOW('v', IOCNUM_RTC_WRITE, struct vm_rtc_data) 420 #define VM_RTC_READ \ 421 _IOWR('v', IOCNUM_RTC_READ, struct vm_rtc_data) 422 #define VM_RTC_SETTIME \ 423 _IOW('v', IOCNUM_RTC_SETTIME, struct vm_rtc_time) 424 #define VM_RTC_GETTIME \ 425 _IOR('v', IOCNUM_RTC_GETTIME, struct vm_rtc_time) 426 #define VM_RESTART_INSTRUCTION \ 427 _IOW('v', IOCNUM_RESTART_INSTRUCTION, int) 428 #endif 429