1 /*- 2 * Copyright (c) 2011 NetApp, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _VMM_DEV_H_ 30 #define _VMM_DEV_H_ 31 32 #ifdef _KERNEL 33 void vmmdev_init(void); 34 int vmmdev_cleanup(void); 35 #endif 36 37 struct vm_memmap { 38 vm_paddr_t gpa; 39 int segid; /* memory segment */ 40 vm_ooffset_t segoff; /* offset into memory segment */ 41 size_t len; /* mmap length */ 42 int prot; /* RWX */ 43 int flags; 44 }; 45 #define VM_MEMMAP_F_WIRED 0x01 46 #define VM_MEMMAP_F_IOMMU 0x02 47 48 #define VM_MEMSEG_NAME(m) ((m)->name[0] != '\0' ? (m)->name : NULL) 49 struct vm_memseg { 50 int segid; 51 size_t len; 52 char name[SPECNAMELEN + 1]; 53 }; 54 55 struct vm_register { 56 int cpuid; 57 int regnum; /* enum vm_reg_name */ 58 uint64_t regval; 59 }; 60 61 struct vm_seg_desc { /* data or code segment */ 62 int cpuid; 63 int regnum; /* enum vm_reg_name */ 64 struct seg_desc desc; 65 }; 66 67 struct vm_run { 68 int cpuid; 69 struct vm_exit vm_exit; 70 }; 71 72 struct vm_exception { 73 int cpuid; 74 int vector; 75 uint32_t error_code; 76 int error_code_valid; 77 int restart_instruction; 78 }; 79 80 struct vm_lapic_msi { 81 uint64_t msg; 82 uint64_t addr; 83 }; 84 85 struct vm_lapic_irq { 86 int cpuid; 87 int vector; 88 }; 89 90 struct vm_ioapic_irq { 91 int irq; 92 }; 93 94 struct vm_isa_irq { 95 int atpic_irq; 96 int ioapic_irq; 97 }; 98 99 struct vm_isa_irq_trigger { 100 int atpic_irq; 101 enum vm_intr_trigger trigger; 102 }; 103 104 struct vm_capability { 105 int cpuid; 106 enum vm_cap_type captype; 107 int capval; 108 int allcpus; 109 }; 110 111 struct vm_pptdev { 112 int bus; 113 int slot; 114 int func; 115 }; 116 117 struct vm_pptdev_mmio { 118 int bus; 119 int slot; 120 int func; 121 vm_paddr_t gpa; 122 vm_paddr_t hpa; 123 size_t len; 124 }; 125 126 struct vm_pptdev_msi { 127 int vcpu; 128 int bus; 129 int slot; 130 int func; 131 int numvec; /* 0 means disabled */ 132 uint64_t msg; 133 uint64_t addr; 134 }; 135 136 struct vm_pptdev_msix { 137 int vcpu; 138 int bus; 139 int slot; 140 int func; 141 int idx; 142 uint64_t msg; 143 uint32_t vector_control; 144 uint64_t addr; 145 }; 146 147 struct vm_nmi { 148 int cpuid; 149 }; 150 151 #define MAX_VM_STATS 64 152 struct vm_stats { 153 int cpuid; /* in */ 154 int num_entries; /* out */ 155 struct timeval tv; 156 uint64_t statbuf[MAX_VM_STATS]; 157 }; 158 159 struct vm_stat_desc { 160 int index; /* in */ 161 char desc[128]; /* out */ 162 }; 163 164 struct vm_x2apic { 165 int cpuid; 166 enum x2apic_state state; 167 }; 168 169 struct vm_gpa_pte { 170 uint64_t gpa; /* in */ 171 uint64_t pte[4]; /* out */ 172 int ptenum; 173 }; 174 175 struct vm_hpet_cap { 176 uint32_t capabilities; /* lower 32 bits of HPET capabilities */ 177 }; 178 179 struct vm_suspend { 180 enum vm_suspend_how how; 181 }; 182 183 struct vm_gla2gpa { 184 int vcpuid; /* inputs */ 185 int prot; /* PROT_READ or PROT_WRITE */ 186 uint64_t gla; 187 struct vm_guest_paging paging; 188 int fault; /* outputs */ 189 uint64_t gpa; 190 }; 191 192 struct vm_activate_cpu { 193 int vcpuid; 194 }; 195 196 struct vm_cpuset { 197 int which; 198 int cpusetsize; 199 cpuset_t *cpus; 200 }; 201 #define VM_ACTIVE_CPUS 0 202 #define VM_SUSPENDED_CPUS 1 203 204 struct vm_intinfo { 205 int vcpuid; 206 uint64_t info1; 207 uint64_t info2; 208 }; 209 210 struct vm_rtc_time { 211 time_t secs; 212 }; 213 214 struct vm_rtc_data { 215 int offset; 216 uint8_t value; 217 }; 218 219 struct vm_cpu_topology { 220 uint16_t sockets; 221 uint16_t cores; 222 uint16_t threads; 223 uint16_t maxcpus; 224 }; 225 226 enum { 227 /* general routines */ 228 IOCNUM_ABIVERS = 0, 229 IOCNUM_RUN = 1, 230 IOCNUM_SET_CAPABILITY = 2, 231 IOCNUM_GET_CAPABILITY = 3, 232 IOCNUM_SUSPEND = 4, 233 IOCNUM_REINIT = 5, 234 235 /* memory apis */ 236 IOCNUM_MAP_MEMORY = 10, /* deprecated */ 237 IOCNUM_GET_MEMORY_SEG = 11, /* deprecated */ 238 IOCNUM_GET_GPA_PMAP = 12, 239 IOCNUM_GLA2GPA = 13, 240 IOCNUM_ALLOC_MEMSEG = 14, 241 IOCNUM_GET_MEMSEG = 15, 242 IOCNUM_MMAP_MEMSEG = 16, 243 IOCNUM_MMAP_GETNEXT = 17, 244 245 /* register/state accessors */ 246 IOCNUM_SET_REGISTER = 20, 247 IOCNUM_GET_REGISTER = 21, 248 IOCNUM_SET_SEGMENT_DESCRIPTOR = 22, 249 IOCNUM_GET_SEGMENT_DESCRIPTOR = 23, 250 251 /* interrupt injection */ 252 IOCNUM_GET_INTINFO = 28, 253 IOCNUM_SET_INTINFO = 29, 254 IOCNUM_INJECT_EXCEPTION = 30, 255 IOCNUM_LAPIC_IRQ = 31, 256 IOCNUM_INJECT_NMI = 32, 257 IOCNUM_IOAPIC_ASSERT_IRQ = 33, 258 IOCNUM_IOAPIC_DEASSERT_IRQ = 34, 259 IOCNUM_IOAPIC_PULSE_IRQ = 35, 260 IOCNUM_LAPIC_MSI = 36, 261 IOCNUM_LAPIC_LOCAL_IRQ = 37, 262 IOCNUM_IOAPIC_PINCOUNT = 38, 263 IOCNUM_RESTART_INSTRUCTION = 39, 264 265 /* PCI pass-thru */ 266 IOCNUM_BIND_PPTDEV = 40, 267 IOCNUM_UNBIND_PPTDEV = 41, 268 IOCNUM_MAP_PPTDEV_MMIO = 42, 269 IOCNUM_PPTDEV_MSI = 43, 270 IOCNUM_PPTDEV_MSIX = 44, 271 272 /* statistics */ 273 IOCNUM_VM_STATS = 50, 274 IOCNUM_VM_STAT_DESC = 51, 275 276 /* kernel device state */ 277 IOCNUM_SET_X2APIC_STATE = 60, 278 IOCNUM_GET_X2APIC_STATE = 61, 279 IOCNUM_GET_HPET_CAPABILITIES = 62, 280 281 /* CPU Topology */ 282 IOCNUM_SET_TOPOLOGY = 63, 283 IOCNUM_GET_TOPOLOGY = 64, 284 285 /* legacy interrupt injection */ 286 IOCNUM_ISA_ASSERT_IRQ = 80, 287 IOCNUM_ISA_DEASSERT_IRQ = 81, 288 IOCNUM_ISA_PULSE_IRQ = 82, 289 IOCNUM_ISA_SET_IRQ_TRIGGER = 83, 290 291 /* vm_cpuset */ 292 IOCNUM_ACTIVATE_CPU = 90, 293 IOCNUM_GET_CPUSET = 91, 294 295 /* RTC */ 296 IOCNUM_RTC_READ = 100, 297 IOCNUM_RTC_WRITE = 101, 298 IOCNUM_RTC_SETTIME = 102, 299 IOCNUM_RTC_GETTIME = 103, 300 }; 301 302 #define VM_RUN \ 303 _IOWR('v', IOCNUM_RUN, struct vm_run) 304 #define VM_SUSPEND \ 305 _IOW('v', IOCNUM_SUSPEND, struct vm_suspend) 306 #define VM_REINIT \ 307 _IO('v', IOCNUM_REINIT) 308 #define VM_ALLOC_MEMSEG \ 309 _IOW('v', IOCNUM_ALLOC_MEMSEG, struct vm_memseg) 310 #define VM_GET_MEMSEG \ 311 _IOWR('v', IOCNUM_GET_MEMSEG, struct vm_memseg) 312 #define VM_MMAP_MEMSEG \ 313 _IOW('v', IOCNUM_MMAP_MEMSEG, struct vm_memmap) 314 #define VM_MMAP_GETNEXT \ 315 _IOWR('v', IOCNUM_MMAP_GETNEXT, struct vm_memmap) 316 #define VM_SET_REGISTER \ 317 _IOW('v', IOCNUM_SET_REGISTER, struct vm_register) 318 #define VM_GET_REGISTER \ 319 _IOWR('v', IOCNUM_GET_REGISTER, struct vm_register) 320 #define VM_SET_SEGMENT_DESCRIPTOR \ 321 _IOW('v', IOCNUM_SET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 322 #define VM_GET_SEGMENT_DESCRIPTOR \ 323 _IOWR('v', IOCNUM_GET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 324 #define VM_INJECT_EXCEPTION \ 325 _IOW('v', IOCNUM_INJECT_EXCEPTION, struct vm_exception) 326 #define VM_LAPIC_IRQ \ 327 _IOW('v', IOCNUM_LAPIC_IRQ, struct vm_lapic_irq) 328 #define VM_LAPIC_LOCAL_IRQ \ 329 _IOW('v', IOCNUM_LAPIC_LOCAL_IRQ, struct vm_lapic_irq) 330 #define VM_LAPIC_MSI \ 331 _IOW('v', IOCNUM_LAPIC_MSI, struct vm_lapic_msi) 332 #define VM_IOAPIC_ASSERT_IRQ \ 333 _IOW('v', IOCNUM_IOAPIC_ASSERT_IRQ, struct vm_ioapic_irq) 334 #define VM_IOAPIC_DEASSERT_IRQ \ 335 _IOW('v', IOCNUM_IOAPIC_DEASSERT_IRQ, struct vm_ioapic_irq) 336 #define VM_IOAPIC_PULSE_IRQ \ 337 _IOW('v', IOCNUM_IOAPIC_PULSE_IRQ, struct vm_ioapic_irq) 338 #define VM_IOAPIC_PINCOUNT \ 339 _IOR('v', IOCNUM_IOAPIC_PINCOUNT, int) 340 #define VM_ISA_ASSERT_IRQ \ 341 _IOW('v', IOCNUM_ISA_ASSERT_IRQ, struct vm_isa_irq) 342 #define VM_ISA_DEASSERT_IRQ \ 343 _IOW('v', IOCNUM_ISA_DEASSERT_IRQ, struct vm_isa_irq) 344 #define VM_ISA_PULSE_IRQ \ 345 _IOW('v', IOCNUM_ISA_PULSE_IRQ, struct vm_isa_irq) 346 #define VM_ISA_SET_IRQ_TRIGGER \ 347 _IOW('v', IOCNUM_ISA_SET_IRQ_TRIGGER, struct vm_isa_irq_trigger) 348 #define VM_SET_CAPABILITY \ 349 _IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability) 350 #define VM_GET_CAPABILITY \ 351 _IOWR('v', IOCNUM_GET_CAPABILITY, struct vm_capability) 352 #define VM_BIND_PPTDEV \ 353 _IOW('v', IOCNUM_BIND_PPTDEV, struct vm_pptdev) 354 #define VM_UNBIND_PPTDEV \ 355 _IOW('v', IOCNUM_UNBIND_PPTDEV, struct vm_pptdev) 356 #define VM_MAP_PPTDEV_MMIO \ 357 _IOW('v', IOCNUM_MAP_PPTDEV_MMIO, struct vm_pptdev_mmio) 358 #define VM_PPTDEV_MSI \ 359 _IOW('v', IOCNUM_PPTDEV_MSI, struct vm_pptdev_msi) 360 #define VM_PPTDEV_MSIX \ 361 _IOW('v', IOCNUM_PPTDEV_MSIX, struct vm_pptdev_msix) 362 #define VM_INJECT_NMI \ 363 _IOW('v', IOCNUM_INJECT_NMI, struct vm_nmi) 364 #define VM_STATS \ 365 _IOWR('v', IOCNUM_VM_STATS, struct vm_stats) 366 #define VM_STAT_DESC \ 367 _IOWR('v', IOCNUM_VM_STAT_DESC, struct vm_stat_desc) 368 #define VM_SET_X2APIC_STATE \ 369 _IOW('v', IOCNUM_SET_X2APIC_STATE, struct vm_x2apic) 370 #define VM_GET_X2APIC_STATE \ 371 _IOWR('v', IOCNUM_GET_X2APIC_STATE, struct vm_x2apic) 372 #define VM_GET_HPET_CAPABILITIES \ 373 _IOR('v', IOCNUM_GET_HPET_CAPABILITIES, struct vm_hpet_cap) 374 #define VM_SET_TOPOLOGY \ 375 _IOW('v', IOCNUM_SET_TOPOLOGY, struct vm_cpu_topology) 376 #define VM_GET_TOPOLOGY \ 377 _IOR('v', IOCNUM_GET_TOPOLOGY, struct vm_cpu_topology) 378 #define VM_GET_GPA_PMAP \ 379 _IOWR('v', IOCNUM_GET_GPA_PMAP, struct vm_gpa_pte) 380 #define VM_GLA2GPA \ 381 _IOWR('v', IOCNUM_GLA2GPA, struct vm_gla2gpa) 382 #define VM_ACTIVATE_CPU \ 383 _IOW('v', IOCNUM_ACTIVATE_CPU, struct vm_activate_cpu) 384 #define VM_GET_CPUS \ 385 _IOW('v', IOCNUM_GET_CPUSET, struct vm_cpuset) 386 #define VM_SET_INTINFO \ 387 _IOW('v', IOCNUM_SET_INTINFO, struct vm_intinfo) 388 #define VM_GET_INTINFO \ 389 _IOWR('v', IOCNUM_GET_INTINFO, struct vm_intinfo) 390 #define VM_RTC_WRITE \ 391 _IOW('v', IOCNUM_RTC_WRITE, struct vm_rtc_data) 392 #define VM_RTC_READ \ 393 _IOWR('v', IOCNUM_RTC_READ, struct vm_rtc_data) 394 #define VM_RTC_SETTIME \ 395 _IOW('v', IOCNUM_RTC_SETTIME, struct vm_rtc_time) 396 #define VM_RTC_GETTIME \ 397 _IOR('v', IOCNUM_RTC_GETTIME, struct vm_rtc_time) 398 #define VM_RESTART_INSTRUCTION \ 399 _IOW('v', IOCNUM_RESTART_INSTRUCTION, int) 400 #endif 401