1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that ARM uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef ARMISELLOWERING_H 16 #define ARMISELLOWERING_H 17 18 #include "ARM.h" 19 #include "ARMSubtarget.h" 20 #include "llvm/CodeGen/CallingConvLower.h" 21 #include "llvm/CodeGen/FastISel.h" 22 #include "llvm/CodeGen/SelectionDAG.h" 23 #include "llvm/Target/TargetLowering.h" 24 #include "llvm/Target/TargetRegisterInfo.h" 25 #include <vector> 26 27 namespace llvm { 28 class ARMConstantPoolValue; 29 30 namespace ARMISD { 31 // ARM Specific DAG Nodes 32 enum NodeType { 33 // Start the numbering where the builtin ops and target ops leave off. 34 FIRST_NUMBER = ISD::BUILTIN_OP_END, 35 36 Wrapper, // Wrapper - A wrapper node for TargetConstantPool, 37 // TargetExternalSymbol, and TargetGlobalAddress. 38 WrapperDYN, // WrapperDYN - A wrapper node for TargetGlobalAddress in 39 // DYN mode. 40 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in 41 // PIC mode. 42 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable 43 44 // Add pseudo op to model memcpy for struct byval. 45 COPY_STRUCT_BYVAL, 46 47 CALL, // Function call. 48 CALL_PRED, // Function call that's predicable. 49 CALL_NOLINK, // Function call with branch not branch-and-link. 50 tCALL, // Thumb function call. 51 BRCOND, // Conditional branch. 52 BR_JT, // Jumptable branch. 53 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump). 54 RET_FLAG, // Return with a flag operand. 55 INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand. 56 57 PIC_ADD, // Add with a PC operand and a PIC label. 58 59 CMP, // ARM compare instructions. 60 CMN, // ARM CMN instructions. 61 CMPZ, // ARM compare that sets only Z flag. 62 CMPFP, // ARM VFP compare instruction, sets FPSCR. 63 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR. 64 FMSTAT, // ARM fmstat instruction. 65 66 CMOV, // ARM conditional move instructions. 67 68 BCC_i64, 69 70 RBIT, // ARM bitreverse instruction 71 72 FTOSI, // FP to sint within a FP register. 73 FTOUI, // FP to uint within a FP register. 74 SITOF, // sint to FP within a FP register. 75 UITOF, // uint to FP within a FP register. 76 77 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out. 78 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out. 79 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. 80 81 ADDC, // Add with carry 82 ADDE, // Add using carry 83 SUBC, // Sub with carry 84 SUBE, // Sub using carry 85 86 VMOVRRD, // double to two gprs. 87 VMOVDRR, // Two gprs to double. 88 89 EH_SJLJ_SETJMP, // SjLj exception handling setjmp. 90 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp. 91 92 TC_RETURN, // Tail call return pseudo. 93 94 THREAD_POINTER, 95 96 DYN_ALLOC, // Dynamic allocation on the stack. 97 98 MEMBARRIER_MCR, // Memory barrier (MCR) 99 100 PRELOAD, // Preload 101 102 VCEQ, // Vector compare equal. 103 VCEQZ, // Vector compare equal to zero. 104 VCGE, // Vector compare greater than or equal. 105 VCGEZ, // Vector compare greater than or equal to zero. 106 VCLEZ, // Vector compare less than or equal to zero. 107 VCGEU, // Vector compare unsigned greater than or equal. 108 VCGT, // Vector compare greater than. 109 VCGTZ, // Vector compare greater than zero. 110 VCLTZ, // Vector compare less than zero. 111 VCGTU, // Vector compare unsigned greater than. 112 VTST, // Vector test bits. 113 114 // Vector shift by immediate: 115 VSHL, // ...left 116 VSHRs, // ...right (signed) 117 VSHRu, // ...right (unsigned) 118 VSHLLs, // ...left long (signed) 119 VSHLLu, // ...left long (unsigned) 120 VSHLLi, // ...left long (with maximum shift count) 121 VSHRN, // ...right narrow 122 123 // Vector rounding shift by immediate: 124 VRSHRs, // ...right (signed) 125 VRSHRu, // ...right (unsigned) 126 VRSHRN, // ...right narrow 127 128 // Vector saturating shift by immediate: 129 VQSHLs, // ...left (signed) 130 VQSHLu, // ...left (unsigned) 131 VQSHLsu, // ...left (signed to unsigned) 132 VQSHRNs, // ...right narrow (signed) 133 VQSHRNu, // ...right narrow (unsigned) 134 VQSHRNsu, // ...right narrow (signed to unsigned) 135 136 // Vector saturating rounding shift by immediate: 137 VQRSHRNs, // ...right narrow (signed) 138 VQRSHRNu, // ...right narrow (unsigned) 139 VQRSHRNsu, // ...right narrow (signed to unsigned) 140 141 // Vector shift and insert: 142 VSLI, // ...left 143 VSRI, // ...right 144 145 // Vector get lane (VMOV scalar to ARM core register) 146 // (These are used for 8- and 16-bit element types only.) 147 VGETLANEu, // zero-extend vector extract element 148 VGETLANEs, // sign-extend vector extract element 149 150 // Vector move immediate and move negated immediate: 151 VMOVIMM, 152 VMVNIMM, 153 154 // Vector move f32 immediate: 155 VMOVFPIMM, 156 157 // Vector duplicate: 158 VDUP, 159 VDUPLANE, 160 161 // Vector shuffles: 162 VEXT, // extract 163 VREV64, // reverse elements within 64-bit doublewords 164 VREV32, // reverse elements within 32-bit words 165 VREV16, // reverse elements within 16-bit halfwords 166 VZIP, // zip (interleave) 167 VUZP, // unzip (deinterleave) 168 VTRN, // transpose 169 VTBL1, // 1-register shuffle with mask 170 VTBL2, // 2-register shuffle with mask 171 172 // Vector multiply long: 173 VMULLs, // ...signed 174 VMULLu, // ...unsigned 175 176 UMLAL, // 64bit Unsigned Accumulate Multiply 177 SMLAL, // 64bit Signed Accumulate Multiply 178 179 // Operands of the standard BUILD_VECTOR node are not legalized, which 180 // is fine if BUILD_VECTORs are always lowered to shuffles or other 181 // operations, but for ARM some BUILD_VECTORs are legal as-is and their 182 // operands need to be legalized. Define an ARM-specific version of 183 // BUILD_VECTOR for this purpose. 184 BUILD_VECTOR, 185 186 // Floating-point max and min: 187 FMAX, 188 FMIN, 189 VMAXNM, 190 VMINNM, 191 192 // Bit-field insert 193 BFI, 194 195 // Vector OR with immediate 196 VORRIMM, 197 // Vector AND with NOT of immediate 198 VBICIMM, 199 200 // Vector bitwise select 201 VBSL, 202 203 // Vector load N-element structure to all lanes: 204 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE, 205 VLD3DUP, 206 VLD4DUP, 207 208 // NEON loads with post-increment base updates: 209 VLD1_UPD, 210 VLD2_UPD, 211 VLD3_UPD, 212 VLD4_UPD, 213 VLD2LN_UPD, 214 VLD3LN_UPD, 215 VLD4LN_UPD, 216 VLD2DUP_UPD, 217 VLD3DUP_UPD, 218 VLD4DUP_UPD, 219 220 // NEON stores with post-increment base updates: 221 VST1_UPD, 222 VST2_UPD, 223 VST3_UPD, 224 VST4_UPD, 225 VST2LN_UPD, 226 VST3LN_UPD, 227 VST4LN_UPD 228 }; 229 } 230 231 /// Define some predicates that are used for node matching. 232 namespace ARM { 233 bool isBitFieldInvertedMask(unsigned v); 234 } 235 236 //===--------------------------------------------------------------------===// 237 // ARMTargetLowering - ARM Implementation of the TargetLowering interface 238 239 class ARMTargetLowering : public TargetLowering { 240 public: 241 explicit ARMTargetLowering(TargetMachine &TM); 242 243 virtual unsigned getJumpTableEncoding() const; 244 245 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 246 247 /// ReplaceNodeResults - Replace the results of node with an illegal result 248 /// type with new values built out of custom code. 249 /// 250 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 251 SelectionDAG &DAG) const; 252 253 virtual const char *getTargetNodeName(unsigned Opcode) const; 254 isSelectSupported(SelectSupportKind Kind)255 virtual bool isSelectSupported(SelectSupportKind Kind) const { 256 // ARM does not support scalar condition selects on vectors. 257 return (Kind != ScalarCondVectorVal); 258 } 259 260 /// getSetCCResultType - Return the value type to use for ISD::SETCC. 261 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const; 262 263 virtual MachineBasicBlock * 264 EmitInstrWithCustomInserter(MachineInstr *MI, 265 MachineBasicBlock *MBB) const; 266 267 virtual void 268 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const; 269 270 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const; 271 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 272 273 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const; 274 275 /// allowsUnalignedMemoryAccesses - Returns true if the target allows 276 /// unaligned memory accesses of the specified type. Returns whether it 277 /// is "fast" by reference in the second argument. 278 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const; 279 280 virtual EVT getOptimalMemOpType(uint64_t Size, 281 unsigned DstAlign, unsigned SrcAlign, 282 bool IsMemset, bool ZeroMemset, 283 bool MemcpyStrSrc, 284 MachineFunction &MF) const; 285 286 using TargetLowering::isZExtFree; 287 virtual bool isZExtFree(SDValue Val, EVT VT2) const; 288 289 virtual bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const; 290 291 292 /// isLegalAddressingMode - Return true if the addressing mode represented 293 /// by AM is legal for this target, for a load/store of the specified type. 294 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const; 295 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 296 297 /// isLegalICmpImmediate - Return true if the specified immediate is legal 298 /// icmp immediate, that is the target has icmp instructions which can 299 /// compare a register against the immediate without having to materialize 300 /// the immediate into a register. 301 virtual bool isLegalICmpImmediate(int64_t Imm) const; 302 303 /// isLegalAddImmediate - Return true if the specified immediate is legal 304 /// add immediate, that is the target has add instructions which can 305 /// add a register and the immediate without having to materialize 306 /// the immediate into a register. 307 virtual bool isLegalAddImmediate(int64_t Imm) const; 308 309 /// getPreIndexedAddressParts - returns true by value, base pointer and 310 /// offset pointer and addressing mode by reference if the node's address 311 /// can be legally represented as pre-indexed load / store address. 312 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 313 SDValue &Offset, 314 ISD::MemIndexedMode &AM, 315 SelectionDAG &DAG) const; 316 317 /// getPostIndexedAddressParts - returns true by value, base pointer and 318 /// offset pointer and addressing mode by reference if this node can be 319 /// combined with a load / store to form a post-indexed load / store. 320 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 321 SDValue &Base, SDValue &Offset, 322 ISD::MemIndexedMode &AM, 323 SelectionDAG &DAG) const; 324 325 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 326 APInt &KnownZero, 327 APInt &KnownOne, 328 const SelectionDAG &DAG, 329 unsigned Depth) const; 330 331 332 virtual bool ExpandInlineAsm(CallInst *CI) const; 333 334 ConstraintType getConstraintType(const std::string &Constraint) const; 335 336 /// Examine constraint string and operand type and determine a weight value. 337 /// The operand object must already have been set up with the operand type. 338 ConstraintWeight getSingleConstraintMatchWeight( 339 AsmOperandInfo &info, const char *constraint) const; 340 341 std::pair<unsigned, const TargetRegisterClass*> 342 getRegForInlineAsmConstraint(const std::string &Constraint, 343 MVT VT) const; 344 345 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 346 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 347 /// true it means one of the asm constraint of the inline asm instruction 348 /// being processed is 'm'. 349 virtual void LowerAsmOperandForConstraint(SDValue Op, 350 std::string &Constraint, 351 std::vector<SDValue> &Ops, 352 SelectionDAG &DAG) const; 353 getSubtarget()354 const ARMSubtarget* getSubtarget() const { 355 return Subtarget; 356 } 357 358 /// getRegClassFor - Return the register class that should be used for the 359 /// specified value type. 360 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const; 361 362 /// getMaximalGlobalOffset - Returns the maximal possible offset which can 363 /// be used for loads / stores from the global. 364 virtual unsigned getMaximalGlobalOffset() const; 365 366 /// Returns true if a cast between SrcAS and DestAS is a noop. isNoopAddrSpaceCast(unsigned SrcAS,unsigned DestAS)367 virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const { 368 // Addrspacecasts are always noops. 369 return true; 370 } 371 372 /// createFastISel - This method returns a target specific FastISel object, 373 /// or null if the target does not support "fast" ISel. 374 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 375 const TargetLibraryInfo *libInfo) const; 376 377 Sched::Preference getSchedulingPreference(SDNode *N) const; 378 379 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const; 380 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 381 382 /// isFPImmLegal - Returns true if the target can instruction select the 383 /// specified FP immediate natively. If false, the legalizer will 384 /// materialize the FP immediate as a load from a constant pool. 385 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 386 387 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, 388 const CallInst &I, 389 unsigned Intrinsic) const; 390 protected: 391 std::pair<const TargetRegisterClass*, uint8_t> 392 findRepresentativeClass(MVT VT) const; 393 394 private: 395 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 396 /// make the right decision when generating code for different targets. 397 const ARMSubtarget *Subtarget; 398 399 const TargetRegisterInfo *RegInfo; 400 401 const InstrItineraryData *Itins; 402 403 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created. 404 /// 405 unsigned ARMPCLabelIndex; 406 407 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT); 408 void addDRTypeForNEON(MVT VT); 409 void addQRTypeForNEON(MVT VT); 410 411 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector; 412 void PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG, 413 SDValue Chain, SDValue &Arg, 414 RegsToPassVector &RegsToPass, 415 CCValAssign &VA, CCValAssign &NextVA, 416 SDValue &StackPtr, 417 SmallVectorImpl<SDValue> &MemOpChains, 418 ISD::ArgFlagsTy Flags) const; 419 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 420 SDValue &Root, SelectionDAG &DAG, 421 SDLoc dl) const; 422 423 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, 424 bool isVarArg) const; 425 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 426 SDLoc dl, SelectionDAG &DAG, 427 const CCValAssign &VA, 428 ISD::ArgFlagsTy Flags) const; 429 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 430 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 431 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 432 const ARMSubtarget *Subtarget) const; 433 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 434 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 435 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const; 436 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 437 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 438 SelectionDAG &DAG) const; 439 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA, 440 SelectionDAG &DAG, 441 TLSModel::Model model) const; 442 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const; 443 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 444 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 445 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 446 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 447 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 448 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 449 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 450 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const; 451 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 452 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 453 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG, 454 const ARMSubtarget *ST) const; 455 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, 456 const ARMSubtarget *ST) const; 457 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const; 458 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const; 459 460 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster 461 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be 462 /// expanded to FMAs when this method returns true, otherwise fmuladd is 463 /// expanded to fmul + fadd. 464 /// 465 /// ARM supports both fused and unfused multiply-add operations; we already 466 /// lower a pair of fmul and fadd to the latter so it's not clear that there 467 /// would be a gain or that the gain would be worthwhile enough to risk 468 /// correctness bugs. isFMAFasterThanFMulAndFAdd(EVT VT)469 virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const { return false; } 470 471 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const; 472 473 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 474 CallingConv::ID CallConv, bool isVarArg, 475 const SmallVectorImpl<ISD::InputArg> &Ins, 476 SDLoc dl, SelectionDAG &DAG, 477 SmallVectorImpl<SDValue> &InVals, 478 bool isThisReturn, SDValue ThisVal) const; 479 480 virtual SDValue 481 LowerFormalArguments(SDValue Chain, 482 CallingConv::ID CallConv, bool isVarArg, 483 const SmallVectorImpl<ISD::InputArg> &Ins, 484 SDLoc dl, SelectionDAG &DAG, 485 SmallVectorImpl<SDValue> &InVals) const; 486 487 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, 488 SDLoc dl, SDValue &Chain, 489 const Value *OrigArg, 490 unsigned InRegsParamRecordIdx, 491 unsigned OffsetFromOrigArg, 492 unsigned ArgOffset, 493 unsigned ArgSize, 494 bool ForceMutable) const; 495 496 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, 497 SDLoc dl, SDValue &Chain, 498 unsigned ArgOffset, 499 bool ForceMutable = false) const; 500 501 void computeRegArea(CCState &CCInfo, MachineFunction &MF, 502 unsigned InRegsParamRecordIdx, 503 unsigned ArgSize, 504 unsigned &ArgRegsSize, 505 unsigned &ArgRegsSaveSize) const; 506 507 virtual SDValue 508 LowerCall(TargetLowering::CallLoweringInfo &CLI, 509 SmallVectorImpl<SDValue> &InVals) const; 510 511 /// HandleByVal - Target-specific cleanup for ByVal support. 512 virtual void HandleByVal(CCState *, unsigned &, unsigned) const; 513 514 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 515 /// for tail call optimization. Targets which want to do tail call 516 /// optimization should implement this function. 517 bool IsEligibleForTailCallOptimization(SDValue Callee, 518 CallingConv::ID CalleeCC, 519 bool isVarArg, 520 bool isCalleeStructRet, 521 bool isCallerStructRet, 522 const SmallVectorImpl<ISD::OutputArg> &Outs, 523 const SmallVectorImpl<SDValue> &OutVals, 524 const SmallVectorImpl<ISD::InputArg> &Ins, 525 SelectionDAG& DAG) const; 526 527 virtual bool CanLowerReturn(CallingConv::ID CallConv, 528 MachineFunction &MF, bool isVarArg, 529 const SmallVectorImpl<ISD::OutputArg> &Outs, 530 LLVMContext &Context) const; 531 532 virtual SDValue 533 LowerReturn(SDValue Chain, 534 CallingConv::ID CallConv, bool isVarArg, 535 const SmallVectorImpl<ISD::OutputArg> &Outs, 536 const SmallVectorImpl<SDValue> &OutVals, 537 SDLoc dl, SelectionDAG &DAG) const; 538 539 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const; 540 541 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const; 542 543 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 544 SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl) const; 545 SDValue getVFPCmp(SDValue LHS, SDValue RHS, 546 SelectionDAG &DAG, SDLoc dl) const; 547 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const; 548 549 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const; 550 551 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI, 552 MachineBasicBlock *BB, 553 unsigned Size) const; 554 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, 555 MachineBasicBlock *BB, 556 unsigned Size, 557 unsigned BinOpcode) const; 558 MachineBasicBlock *EmitAtomicBinary64(MachineInstr *MI, 559 MachineBasicBlock *BB, 560 unsigned Op1, 561 unsigned Op2, 562 bool NeedsCarry = false, 563 bool IsCmpxchg = false, 564 bool IsMinMax = false, 565 ARMCC::CondCodes CC = ARMCC::AL) const; 566 MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI, 567 MachineBasicBlock *BB, 568 unsigned Size, 569 bool signExtend, 570 ARMCC::CondCodes Cond) const; 571 MachineBasicBlock *EmitAtomicLoad64(MachineInstr *MI, 572 MachineBasicBlock *BB) const; 573 574 void SetupEntryBlockForSjLj(MachineInstr *MI, 575 MachineBasicBlock *MBB, 576 MachineBasicBlock *DispatchBB, int FI) const; 577 578 MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI, 579 MachineBasicBlock *MBB) const; 580 581 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const; 582 583 MachineBasicBlock *EmitStructByval(MachineInstr *MI, 584 MachineBasicBlock *MBB) const; 585 }; 586 587 enum NEONModImmType { 588 VMOVModImm, 589 VMVNModImm, 590 OtherModImm 591 }; 592 593 594 namespace ARM { 595 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 596 const TargetLibraryInfo *libInfo); 597 } 598 } 599 600 #endif // ARMISELLOWERING_H 601