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Searched defs:V0 (Results 1 – 25 of 38) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/CSKY/
HDCSKYISelDAGToDAG.cpp198 SDValue V0 = N->getOperand(i + 1); in selectInlineAsm() local
383 SDNode *CSKYDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) { in createGPRPairNode()
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
HDMipsMachineFunction.cpp84 Register V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg() local
HDMips16ISelDAGToDAG.cpp75 Register V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(MF); in initGlobalBaseReg() local
/freebsd-13-stable/lib/msun/src/
HDe_j1f.c94 static const float V0[5] = { variable
HDe_j1.c132 static const double V0[5] = { variable
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
HDVectorCombine.cpp542 Value *V0 = Ext0->getVectorOperand(), *V1 = Ext1->getVectorOperand(); in foldExtExtCmp() local
560 Value *V0 = Ext0->getVectorOperand(), *V1 = Ext1->getVectorOperand(); in foldExtExtBinop() local
586 Value *V0, *V1; in foldExtractExtract() local
698 Value *V0, *V1; in foldBitcastShuffle() local
932 Value *V0 = nullptr, *V1 = nullptr; in scalarizeBinopOrCmp() local
1492 Value *V0, *V1; in foldShuffleOfCastops() local
1597 Value *V0, *V1; in foldShuffleOfShuffles() local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
HDSparcISelDAGToDAG.cpp232 SDValue V0 = N->getOperand(i+1); in tryInlineAsm() local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMISelDAGToDAG.cpp1853 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) { in createGPRPairNode()
1864 SDNode *ARMDAGToDAGISel::createSRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createSRegPairNode()
1875 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createDRegPairNode()
1886 SDNode *ARMDAGToDAGISel::createQRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createQRegPairNode()
1897 SDNode *ARMDAGToDAGISel::createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, in createQuadSRegsNode()
1912 SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, in createQuadDRegsNode()
1927 SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, in createQuadQRegsNode()
2318 SDValue V0 = N->getOperand(Vec0Idx + 0); in SelectVST() local
2374 SDValue V0 = N->getOperand(Vec0Idx + 0); in SelectVST() local
2493 SDValue V0 = N->getOperand(Vec0Idx + 0); in SelectVLDSTLane() local
[all …]
/freebsd-13-stable/sys/mips/include/
HDregnum.h57 #define V0 2 macro
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
HDInstCombineAddSub.cpp391 Value *V0 = I->getOperand(0); in drillValueDownOneStep() local
469 Value *V0 = I->getOperand(0); in simplify() local
2284 Value *V0, *V1; in visitSub() local
2967 Value *A0, *A1, *V0, *V1; in visitFSub() local
HDInstCombineVectorOps.cpp84 Value *V0, *V1; in cheapToScalarize() local
2609 Value *V0 = Shuf.getOperand(0), *V1 = Shuf.getOperand(1); in foldShuffleWithInsert() local
HDInstCombineCalls.cpp2823 Value *V0 = Builder.CreateIntCast(CV0, NewVT, /*isSigned=*/!Zext); in visitCallInst() local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
HDLegalizeIntegerTypes.cpp5702 SDValue V0 = GetPromotedInteger(N->getOperand(0)); in PromoteIntRes_VECTOR_SPLICE() local
5712 SDValue V0 = GetPromotedInteger(N->getOperand(0)); in PromoteIntRes_VECTOR_INTERLEAVE_DEINTERLEAVE() local
5829 SDValue V0 = GetPromotedInteger(N->getOperand(0)); in PromoteIntRes_VECTOR_REVERSE() local
5842 SDValue V0 = GetPromotedInteger(N->getOperand(0)); in PromoteIntRes_VECTOR_SHUFFLE() local
6027 SDValue V0 = GetPromotedInteger(N->getOperand(0)); in PromoteIntRes_INSERT_VECTOR_ELT() local
6073 SDValue V0 = GetPromotedInteger(N->getOperand(0)); in PromoteIntOp_EXTRACT_VECTOR_ELT() local
6089 SDValue V0 = N->getOperand(0); in PromoteIntOp_INSERT_SUBVECTOR() local
6102 SDValue V0 = GetPromotedInteger(N->getOperand(0)); in PromoteIntOp_EXTRACT_SUBVECTOR() local
/freebsd-13-stable/crypto/openssl/crypto/aria/
HDaria.c54 #define MAKE_U32(V0, V1, V2, V3) ( \ argument
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
HDReassociate.cpp132 Value *V0 = I->getOperand(0); in XorOpnd() local
988 Value *V0 = Sub->getOperand(0); in ShouldBreakUpSubtract() local
HDConstraintElimination.cpp1708 Value *V0 = B.isConditionFact() ? B.Cond.Op0 : B.Inst->getOperand(0); in eliminateConstraints() local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonISelLoweringHVX.cpp1370 SDValue V0, V1; in insertHvxSubvectorReg() local
1621 SDValue V0 = buildHvxVectorReg(A.take_front(Size/2), dl, SingleTy, DAG); in LowerHvxBuildVector() local
1732 SDValue V0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy, in LowerHvxConcatVectors() local
3530 SDValue V0 = Op.getOperand(0); in combineConcatVectorsBeforeLegal() local
HDHexagonISelDAGToDAG.cpp2315 SDValue V0 = L0.Value; in balanceSubTree() local
2373 SDValue V0 = NewRoot.getOperand(0); in balanceSubTree() local
HDHexagonLoopIdiomRecognition.cpp1761 uint32_t V0 = C0->getZExtValue(); in setupPostSimplifier() local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Analysis/
HDVectorUtils.cpp1004 Value *V0 = ResList[i], *V1 = ResList[i + 1]; in concatenateVectors() local
/freebsd-13-stable/sys/geom/raid/
HDmd_ddf.h267 uint8_t V0[32]; member
/freebsd-13-stable/contrib/llvm-project/clang/lib/Headers/
HDhexagon_types.h2549 HVX_Vector V0(void) { return HEXAGON_HVX_GET_V0(data); }; in V0() function
2558 HVX_Vect V0(HVX_Vector v) { return HVX_Vect(HEXAGON_HVX_PUT_V0(data, v)); }; in V0() function
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDAMDGPUISelLowering.cpp3598 SDValue V0 = DAG.getSelectCC(DL, VLow3, DAG.getConstant(3, DL, MVT::i32), in LowerFP_TO_FP16() local
5273 APFloat V0 = FTZ(N0CFP->getValueAPF()); in PerformDAGCombine() local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/M68k/
HDM68kISelLowering.cpp2062 SDValue V0 = DAG.getNode(ISD::TRUNCATE, DL, VT, WideVal.getOperand(0)); in EmitTest() local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
HDRISCVISelDAGToDAG.cpp1755 SDValue V0 = CurDAG->getRegister(RISCV::V0, VT); in Select() local

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