| /NextBSD/contrib/llvm/lib/Target/PowerPC/ |
| HD | PPCFastISel.cpp | 946 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass); in PPCMoveToFPReg() local
1025 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass); in SelectIToFP() local
1125 unsigned TmpReg = createResultReg(&PPC::F8RCRegClass); in SelectFPToI() local
1336 unsigned TmpReg = createResultReg(RC); in processCallArgs() local
1348 unsigned TmpReg = createResultReg(RC); in processCallArgs() local
1665 unsigned TmpReg = createResultReg(RC); in SelectRet() local
1674 unsigned TmpReg = createResultReg(RC); in SelectRet() local
1907 unsigned TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass); in PPCMaterializeFP() local
2013 unsigned TmpReg = createResultReg(RC); in PPCMaterialize32BitInt() local
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| HD | PPCFrameLowering.cpp | 1598 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; in eliminateCallFramePseudoInstr() local
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| HD | PPCISelLowering.cpp | 8110 unsigned TmpReg = (!BinOpcode) ? incr : in EmitAtomicBinary() local
8195 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary() local
8916 unsigned TmpReg = RegInfo.createVirtualRegister(RC); in EmitInstrWithCustomInserter() local
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| /NextBSD/contrib/llvm/lib/Target/ARM/ |
| HD | MLxExpansionPass.cpp | 290 unsigned TmpReg = MRI->createVirtualRegister( in ExpandFPMLxInstruction() local
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| HD | ThumbRegisterInfo.cpp | 572 unsigned TmpReg = MI.getOperand(0).getReg(); in eliminateFrameIndex() local
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| /NextBSD/contrib/llvm/lib/Target/AMDGPU/ |
| HD | SIRegisterInfo.cpp | 315 unsigned TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, SPAdj); in eliminateFrameIndex() local
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| HD | SIInstrInfo.cpp | 578 RegScavenger *RS, unsigned TmpReg, in calculateLDSSpillAddress()
2594 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalar64BitBFE() local
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| /NextBSD/contrib/llvm/lib/Target/Mips/AsmParser/ |
| HD | MipsAsmParser.cpp | 1859 unsigned TmpReg = DstReg; in loadImmediate() local
1878 unsigned TmpReg = DstReg; in loadImmediate() local
2061 unsigned TmpReg = DstReg; in loadAndAddSymbolAddress() local
3604 unsigned TmpReg = PrevReg + 1; in parseRegisterList() local
4407 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> TmpReg; in parseDirectiveCPSetup() local
5010 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> TmpReg; in ParseDirective() local
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| /NextBSD/contrib/llvm/lib/Target/Mips/ |
| HD | MipsSEInstrInfo.cpp | 494 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg; in expandCvtFPInt() local
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| HD | MipsFastISel.cpp | 315 unsigned TmpReg = createResultReg(RC); in materialize32BitInt() local
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| /NextBSD/contrib/llvm/lib/Target/X86/ |
| HD | X86FastISel.cpp | 1487 unsigned TmpReg = getRegForValue(BI->getCondition()); in X86SelectBranch() local
1820 unsigned TmpReg = createResultReg(&X86::GR8RegClass); in X86FastEmitCMoveSelect() local
1832 unsigned TmpReg = getRegForValue(Cond); in X86FastEmitCMoveSelect() local
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| HD | X86ISelLowering.cpp | 19642 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); in EmitVAARG64WithCustomInserter() local
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| /NextBSD/contrib/llvm/lib/Target/AArch64/ |
| HD | AArch64FastISel.cpp | 380 unsigned TmpReg = createResultReg(RC); in materializeFP() local
4004 unsigned TmpReg = MRI.createVirtualRegister(RC); in emitLSL_ri() local
4125 unsigned TmpReg = MRI.createVirtualRegister(RC); in emitLSR_ri() local
4234 unsigned TmpReg = MRI.createVirtualRegister(RC); in emitASR_ri() local
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| /NextBSD/contrib/llvm/lib/Target/X86/AsmParser/ |
| HD | X86AsmParser.cpp | 264 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anon60f6c09b0111::X86AsmParser::IntelExprStateMachine
1194 unsigned TmpReg; in ParseIntelExpression() local
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| /NextBSD/contrib/llvm/lib/CodeGen/ |
| HD | TwoAddressInstructionPass.cpp | 340 unsigned TmpReg = FromReg; in isRevCopyChain() local
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| /NextBSD/contrib/llvm/lib/Target/Sparc/ |
| HD | SparcISelLowering.cpp | 3050 unsigned TmpReg = UpdReg; in expandAtomicRMW() local
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