1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2004-07 Applied Micro Circuits Corporation.
5 * Copyright (c) 2004-05 Vinod Kashyap.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /*
31 * AMCC'S 3ware driver for 9000 series storage controllers.
32 *
33 * Author: Vinod Kashyap
34 * Modifications by: Adam Radford
35 * Modifications by: Manjunath Ranganathaiah
36 */
37
38 #ifndef TW_OSL_H
39
40 #define TW_OSL_H
41
42 /*
43 * OS Layer internal macros, structures and functions.
44 */
45
46 #define TW_OSLI_DEVICE_NAME "3ware 9000 series Storage Controller"
47
48 #define TW_OSLI_MALLOC_CLASS M_TWA
49 #define TW_OSLI_MAX_NUM_REQUESTS TW_CL_MAX_SIMULTANEOUS_REQUESTS
50 /* Reserve two command packets. One for ioctls and one for AENs */
51 #define TW_OSLI_MAX_NUM_IOS (TW_OSLI_MAX_NUM_REQUESTS - 2)
52 #define TW_OSLI_MAX_NUM_AENS 0x100
53
54 #ifdef PAE
55 #define TW_OSLI_DMA_BOUNDARY (1u << 31)
56 #else
57 #define TW_OSLI_DMA_BOUNDARY ((bus_size_t)((uint64_t)1 << 32))
58 #endif
59
60 /* Possible values of req->state. */
61 #define TW_OSLI_REQ_STATE_INIT 0x0 /* being initialized */
62 #define TW_OSLI_REQ_STATE_BUSY 0x1 /* submitted to CL */
63 #define TW_OSLI_REQ_STATE_PENDING 0x2 /* in pending queue */
64 #define TW_OSLI_REQ_STATE_COMPLETE 0x3 /* completed by CL */
65
66 /* Possible values of req->flags. */
67 #define TW_OSLI_REQ_FLAGS_DATA_IN (1<<0) /* read request */
68 #define TW_OSLI_REQ_FLAGS_DATA_OUT (1<<1) /* write request */
69 #define TW_OSLI_REQ_FLAGS_DATA_COPY_NEEDED (1<<2)/* data in ccb is misaligned,
70 have to copy to/from private buffer */
71 #define TW_OSLI_REQ_FLAGS_MAPPED (1<<3) /* request has been mapped */
72 #define TW_OSLI_REQ_FLAGS_IN_PROGRESS (1<<4) /* bus_dmamap_load returned
73 EINPROGRESS */
74 #define TW_OSLI_REQ_FLAGS_PASSTHRU (1<<5) /* pass through request */
75 #define TW_OSLI_REQ_FLAGS_SLEEPING (1<<6) /* owner sleeping on this cmd */
76 #define TW_OSLI_REQ_FLAGS_FAILED (1<<7) /* bus_dmamap_load() failed */
77 #define TW_OSLI_REQ_FLAGS_CCB (1<<8) /* req is ccb. */
78
79 #ifdef TW_OSL_DEBUG
80 struct tw_osli_q_stats {
81 TW_UINT32 cur_len; /* current # of items in q */
82 TW_UINT32 max_len; /* max value reached by q_length */
83 };
84 #endif /* TW_OSL_DEBUG */
85
86 /* Queues of OSL internal request context packets. */
87 #define TW_OSLI_FREE_Q 0 /* free q */
88 #define TW_OSLI_BUSY_Q 1 /* q of reqs submitted to CL */
89 #define TW_OSLI_Q_COUNT 2 /* total number of queues */
90
91 /* Driver's request packet. */
92 struct tw_osli_req_context {
93 struct tw_cl_req_handle req_handle;/* tag to track req b/w OSL & CL */
94 struct mtx ioctl_wake_timeout_lock_handle;/* non-spin lock used to detect ioctl timeout */
95 struct mtx *ioctl_wake_timeout_lock;/* ptr to above lock */
96 struct twa_softc *ctlr; /* ptr to OSL's controller context */
97 TW_VOID *data; /* ptr to data being passed to CL */
98 TW_UINT32 length; /* length of buf being passed to CL */
99 TW_UINT64 deadline;/* request timeout (in absolute time) */
100
101 /*
102 * ptr to, and length of data passed to us from above, in case a buffer
103 * copy was done due to non-compliance to alignment requirements
104 */
105 TW_VOID *real_data;
106 TW_UINT32 real_length;
107
108 TW_UINT32 state; /* request state */
109 TW_UINT32 flags; /* request flags */
110
111 /* error encountered before request submission to CL */
112 TW_UINT32 error_code;
113
114 /* ptr to orig req for use during callback */
115 TW_VOID *orig_req;
116
117 struct tw_cl_link link; /* to link this request in a list */
118 bus_dmamap_t dma_map;/* DMA map for data */
119 struct tw_cl_req_packet req_pkt;/* req pkt understood by CL */
120 };
121
122 /* Per-controller structure. */
123 struct twa_softc {
124 struct tw_cl_ctlr_handle ctlr_handle;
125 struct tw_osli_req_context *req_ctx_buf;
126
127 /* Controller state. */
128 TW_UINT8 open;
129 TW_UINT32 flags;
130
131 TW_INT32 device_id;
132 TW_UINT32 alignment;
133 TW_UINT32 sg_size_factor;
134
135 TW_VOID *non_dma_mem;
136 TW_VOID *dma_mem;
137 TW_UINT64 dma_mem_phys;
138
139 /* Request queues and arrays. */
140 struct tw_cl_link req_q_head[TW_OSLI_Q_COUNT];
141
142 struct task deferred_intr_callback;/* taskqueue function */
143 struct mtx io_lock_handle;/* general purpose lock */
144 struct mtx *io_lock;/* ptr to general purpose lock */
145 struct mtx q_lock_handle; /* queue manipulation lock */
146 struct mtx *q_lock;/* ptr to queue manipulation lock */
147 struct mtx sim_lock_handle;/* sim lock shared with cam */
148 struct mtx *sim_lock;/* ptr to sim lock */
149
150 struct callout watchdog_callout[2]; /* For command timeout */
151 TW_UINT32 watchdog_index;
152
153 #ifdef TW_OSL_DEBUG
154 struct tw_osli_q_stats q_stats[TW_OSLI_Q_COUNT];/* queue statistics */
155 #endif /* TW_OSL_DEBUG */
156
157 device_t bus_dev; /* bus device */
158 struct cdev *ctrl_dev; /* control device */
159 struct resource *reg_res; /* register interface window */
160 TW_INT32 reg_res_id; /* register resource id */
161 bus_space_handle_t bus_handle; /* bus space handle */
162 bus_space_tag_t bus_tag; /* bus space tag */
163 bus_dma_tag_t parent_tag; /* parent DMA tag */
164 bus_dma_tag_t cmd_tag; /* DMA tag for CL's DMA'able mem */
165 bus_dma_tag_t dma_tag; /* data buffer DMA tag */
166 bus_dma_tag_t ioctl_tag; /* ioctl data buffer DMA tag */
167 bus_dmamap_t cmd_map; /* DMA map for CL's DMA'able mem */
168 bus_dmamap_t ioctl_map; /* DMA map for ioctl data buffers */
169 struct resource *irq_res; /* interrupt resource */
170 TW_INT32 irq_res_id; /* register resource id */
171 TW_VOID *intr_handle; /* interrupt handle */
172
173 struct sysctl_ctx_list sysctl_ctxt; /* sysctl context */
174 struct sysctl_oid *sysctl_tree; /* sysctl oid */
175
176 struct cam_sim *sim; /* sim for this controller */
177 struct cam_path *path; /* peripheral, path, tgt, lun
178 associated with this controller */
179 };
180
181 /*
182 * Queue primitives.
183 */
184
185 #ifdef TW_OSL_DEBUG
186
187 #define TW_OSLI_Q_INIT(sc, q_type) do { \
188 (sc)->q_stats[q_type].cur_len = 0; \
189 (sc)->q_stats[q_type].max_len = 0; \
190 } while(0)
191
192 #define TW_OSLI_Q_INSERT(sc, q_type) do { \
193 struct tw_osli_q_stats *q_stats = &((sc)->q_stats[q_type]); \
194 \
195 if (++(q_stats->cur_len) > q_stats->max_len) \
196 q_stats->max_len = q_stats->cur_len; \
197 } while(0)
198
199 #define TW_OSLI_Q_REMOVE(sc, q_type) \
200 (sc)->q_stats[q_type].cur_len--
201
202 #else /* TW_OSL_DEBUG */
203
204 #define TW_OSLI_Q_INIT(sc, q_index)
205 #define TW_OSLI_Q_INSERT(sc, q_index)
206 #define TW_OSLI_Q_REMOVE(sc, q_index)
207
208 #endif /* TW_OSL_DEBUG */
209
210 /* Initialize a queue of requests. */
211 static __inline TW_VOID
tw_osli_req_q_init(struct twa_softc * sc,TW_UINT8 q_type)212 tw_osli_req_q_init(struct twa_softc *sc, TW_UINT8 q_type)
213 {
214 TW_CL_Q_INIT(&(sc->req_q_head[q_type]));
215 TW_OSLI_Q_INIT(sc, q_type);
216 }
217
218 /* Insert the given request at the head of the given queue (q_type). */
219 static __inline TW_VOID
tw_osli_req_q_insert_head(struct tw_osli_req_context * req,TW_UINT8 q_type)220 tw_osli_req_q_insert_head(struct tw_osli_req_context *req, TW_UINT8 q_type)
221 {
222 mtx_lock_spin(req->ctlr->q_lock);
223 TW_CL_Q_INSERT_HEAD(&(req->ctlr->req_q_head[q_type]), &(req->link));
224 TW_OSLI_Q_INSERT(req->ctlr, q_type);
225 mtx_unlock_spin(req->ctlr->q_lock);
226 }
227
228 /* Insert the given request at the tail of the given queue (q_type). */
229 static __inline TW_VOID
tw_osli_req_q_insert_tail(struct tw_osli_req_context * req,TW_UINT8 q_type)230 tw_osli_req_q_insert_tail(struct tw_osli_req_context *req, TW_UINT8 q_type)
231 {
232 mtx_lock_spin(req->ctlr->q_lock);
233 TW_CL_Q_INSERT_TAIL(&(req->ctlr->req_q_head[q_type]), &(req->link));
234 TW_OSLI_Q_INSERT(req->ctlr, q_type);
235 mtx_unlock_spin(req->ctlr->q_lock);
236 }
237
238 /* Remove and return the request at the head of the given queue (q_type). */
239 static __inline struct tw_osli_req_context *
tw_osli_req_q_remove_head(struct twa_softc * sc,TW_UINT8 q_type)240 tw_osli_req_q_remove_head(struct twa_softc *sc, TW_UINT8 q_type)
241 {
242 struct tw_osli_req_context *req = NULL;
243 struct tw_cl_link *link;
244
245 mtx_lock_spin(sc->q_lock);
246 if ((link = TW_CL_Q_FIRST_ITEM(&(sc->req_q_head[q_type]))) !=
247 TW_CL_NULL) {
248 req = TW_CL_STRUCT_HEAD(link,
249 struct tw_osli_req_context, link);
250 TW_CL_Q_REMOVE_ITEM(&(sc->req_q_head[q_type]), &(req->link));
251 TW_OSLI_Q_REMOVE(sc, q_type);
252 }
253 mtx_unlock_spin(sc->q_lock);
254 return(req);
255 }
256
257 /* Remove the given request from the given queue (q_type). */
258 static __inline TW_VOID
tw_osli_req_q_remove_item(struct tw_osli_req_context * req,TW_UINT8 q_type)259 tw_osli_req_q_remove_item(struct tw_osli_req_context *req, TW_UINT8 q_type)
260 {
261 mtx_lock_spin(req->ctlr->q_lock);
262 TW_CL_Q_REMOVE_ITEM(&(req->ctlr->req_q_head[q_type]), &(req->link));
263 TW_OSLI_Q_REMOVE(req->ctlr, q_type);
264 mtx_unlock_spin(req->ctlr->q_lock);
265 }
266
267 #ifdef TW_OSL_DEBUG
268
269 extern TW_INT32 TW_DEBUG_LEVEL_FOR_OSL;
270
271 #define tw_osli_dbg_dprintf(dbg_level, sc, fmt, args...) \
272 if (dbg_level <= TW_DEBUG_LEVEL_FOR_OSL) \
273 device_printf(sc->bus_dev, "%s: " fmt "\n", \
274 __func__, ##args)
275
276 #define tw_osli_dbg_printf(dbg_level, fmt, args...) \
277 if (dbg_level <= TW_DEBUG_LEVEL_FOR_OSL) \
278 printf("%s: " fmt "\n", __func__, ##args)
279
280 #else /* TW_OSL_DEBUG */
281
282 #define tw_osli_dbg_dprintf(dbg_level, sc, fmt, args...)
283 #define tw_osli_dbg_printf(dbg_level, fmt, args...)
284
285 #endif /* TW_OSL_DEBUG */
286
287 /* For regular printing. */
288 #define twa_printf(sc, fmt, args...) \
289 device_printf(((struct twa_softc *)(sc))->bus_dev, fmt, ##args)
290
291 /* For printing in the "consistent error reporting" format. */
292 #define tw_osli_printf(sc, err_specific_desc, args...) \
293 device_printf((sc)->bus_dev, \
294 "%s: (0x%02X: 0x%04X): %s: " err_specific_desc "\n", ##args)
295
296 #endif /* TW_OSL_H */
297