1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2004-07 Applied Micro Circuits Corporation. 5 * Copyright (c) 2004-05 Vinod Kashyap 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: stable/12/sys/dev/twa/tw_cl_share.h 326255 2017-11-27 14:52:40Z pfg $ 30 */ 31 32 /* 33 * AMCC'S 3ware driver for 9000 series storage controllers. 34 * 35 * Author: Vinod Kashyap 36 * Modifications by: Adam Radford 37 * Modifications by: Manjunath Ranganathaiah 38 */ 39 40 41 42 #ifndef TW_CL_SHARE_H 43 44 #define TW_CL_SHARE_H 45 46 47 /* 48 * Macros, structures and functions shared between OSL and CL, 49 * and defined by CL. 50 */ 51 52 #define TW_CL_NULL ((TW_VOID *)0) 53 #define TW_CL_TRUE 1 54 #define TW_CL_FALSE 0 55 56 #define TW_CL_VENDOR_ID 0x13C1 /* 3ware vendor id */ 57 #define TW_CL_DEVICE_ID_9K 0x1002 /* 9000 PCI series device id */ 58 #define TW_CL_DEVICE_ID_9K_X 0x1003 /* 9000 PCI-X series device id */ 59 #define TW_CL_DEVICE_ID_9K_E 0x1004 /* 9000 PCIe series device id */ 60 #define TW_CL_DEVICE_ID_9K_SA 0x1005 /* 9000 PCIe SAS series device id */ 61 62 #define TW_CL_BAR_TYPE_IO 1 /* I/O base address */ 63 #define TW_CL_BAR_TYPE_MEM 2 /* memory base address */ 64 #define TW_CL_BAR_TYPE_SBUF 3 /* SBUF base address */ 65 66 #ifdef TW_OSL_ENCLOSURE_SUPPORT 67 #define TW_CL_MAX_NUM_UNITS 65 /* max # of units we support 68 -- enclosure target id is 64 */ 69 #else /* TW_OSL_ENCLOSURE_SUPPORT */ 70 #define TW_CL_MAX_NUM_UNITS 32 /* max # of units we support */ 71 #endif /* TW_OSL_ENCLOSURE_SUPPORT */ 72 73 #define TW_CL_MAX_NUM_LUNS 255 /* max # of LUN's we support */ 74 #define TW_CL_MAX_IO_SIZE 0x20000 /* 128K */ 75 76 /* 77 * Though we can support 256 simultaneous requests, we advertise as capable 78 * of supporting only 255, since we want to keep one CL internal request 79 * context packet always available for internal requests. 80 */ 81 #define TW_CL_MAX_SIMULTANEOUS_REQUESTS 256 /* max simult reqs supported */ 82 83 #define TW_CL_MAX_32BIT_SG_ELEMENTS 109 /* max 32-bit sg elements */ 84 #define TW_CL_MAX_64BIT_SG_ELEMENTS 72 /* max 64-bit sg elements */ 85 86 87 /* Possible values of ctlr->flags */ 88 #define TW_CL_64BIT_ADDRESSES (1<<0) /* 64 bit cmdpkt & SG addresses */ 89 #define TW_CL_64BIT_SG_LENGTH (1<<1) /* 64 bit SG length */ 90 #define TW_CL_START_CTLR_ONLY (1<<2) /* Start ctlr only */ 91 #define TW_CL_STOP_CTLR_ONLY (1<<3) /* Stop ctlr only */ 92 #define TW_CL_DEFERRED_INTR_USED (1<<5) /* OS Layer uses deferred intr */ 93 94 /* Possible error values from the Common Layer. */ 95 #define TW_CL_ERR_REQ_SUCCESS 0 96 #define TW_CL_ERR_REQ_GENERAL_FAILURE (1<<0) 97 #define TW_CL_ERR_REQ_INVALID_TARGET (1<<1) 98 #define TW_CL_ERR_REQ_INVALID_LUN (1<<2) 99 #define TW_CL_ERR_REQ_SCSI_ERROR (1<<3) 100 #define TW_CL_ERR_REQ_AUTO_SENSE_VALID (1<<4) 101 #define TW_CL_ERR_REQ_BUS_RESET (1<<5) 102 #define TW_CL_ERR_REQ_UNABLE_TO_SUBMIT_COMMAND (1<<6) 103 104 105 /* Possible values of req_pkt->flags */ 106 #define TW_CL_REQ_RETRY_ON_BUSY (1<<0) 107 #define TW_CL_REQ_CALLBACK_FOR_SGLIST (1<<1) 108 109 110 #define TW_CL_MESSAGE_SOURCE_CONTROLLER_ERROR 3 111 #define TW_CL_MESSAGE_SOURCE_CONTROLLER_EVENT 4 112 #define TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR 21 113 #define TW_CL_MESSAGE_SOURCE_COMMON_LAYER_EVENT 22 114 #define TW_CL_MESSAGE_SOURCE_FREEBSD_DRIVER 5 115 #define TW_CL_MESSAGE_SOURCE_FREEBSD_OS 8 116 #define TW_CL_MESSAGE_SOURCE_WINDOWS_DRIVER 7 117 #define TW_CL_MESSAGE_SOURCE_WINDOWS_OS 10 118 119 #define TW_CL_SEVERITY_ERROR 0x1 120 #define TW_CL_SEVERITY_WARNING 0x2 121 #define TW_CL_SEVERITY_INFO 0x3 122 #define TW_CL_SEVERITY_DEBUG 0x4 123 124 #define TW_CL_SEVERITY_ERROR_STRING "ERROR" 125 #define TW_CL_SEVERITY_WARNING_STRING "WARNING" 126 #define TW_CL_SEVERITY_INFO_STRING "INFO" 127 #define TW_CL_SEVERITY_DEBUG_STRING "DEBUG" 128 129 130 131 /* 132 * Structure, a pointer to which is used as the controller handle in 133 * communications between the OS Layer and the Common Layer. 134 */ 135 struct tw_cl_ctlr_handle { 136 TW_VOID *osl_ctlr_ctxt; /* OSL's ctlr context */ 137 TW_VOID *cl_ctlr_ctxt; /* CL's ctlr context */ 138 }; 139 140 141 /* 142 * Structure, a pointer to which is used as the request handle in 143 * communications between the OS Layer and the Common Layer. 144 */ 145 struct tw_cl_req_handle { 146 TW_VOID *osl_req_ctxt; /* OSL's request context */ 147 TW_VOID *cl_req_ctxt; /* CL's request context */ 148 TW_UINT8 is_io; /* Only freeze/release simq for IOs */ 149 }; 150 151 152 /* Structure used to describe SCSI requests to CL. */ 153 struct tw_cl_scsi_req_packet { 154 TW_UINT32 unit; /* unit # to send cmd to */ 155 TW_UINT32 lun; /* LUN to send cmd to */ 156 TW_UINT8 *cdb; /* ptr to SCSI cdb */ 157 TW_UINT32 cdb_len; /* # of valid cdb bytes */ 158 TW_UINT32 sense_len; /* # of bytes of valid sense info */ 159 TW_UINT8 *sense_data; /* ptr to sense data, if any */ 160 TW_UINT32 scsi_status; /* SCSI status returned by fw */ 161 TW_UINT32 sgl_entries; /* # of SG descriptors */ 162 TW_UINT8 *sg_list; /* ptr to SG list */ 163 }; 164 165 166 /* Structure used to describe pass through command packets to CL. */ 167 struct tw_cl_passthru_req_packet { 168 TW_UINT8 *cmd_pkt; /* ptr to passthru cmd pkt */ 169 TW_UINT32 cmd_pkt_length; /* size of cmd pkt */ 170 TW_UINT32 sgl_entries; /* # of SG descriptors */ 171 TW_UINT8 *sg_list; /* ptr to SG list */ 172 }; 173 174 175 /* Request packet submitted to the Common Layer, by the OS Layer. */ 176 struct tw_cl_req_packet { 177 TW_UINT32 cmd; /* Common Layer cmd */ 178 TW_UINT32 flags; /* flags describing request */ 179 TW_UINT32 status; /* Common Layer returned status */ 180 TW_VOID (*tw_osl_callback)(struct tw_cl_req_handle *req_handle); 181 /* OSL routine to be called by CL on req completion */ 182 TW_VOID (*tw_osl_sgl_callback)( 183 struct tw_cl_req_handle *req_handle, TW_VOID *sg_list, 184 TW_UINT32 *num_sgl_entries); 185 /* OSL callback to get SG list. */ 186 187 union { 188 struct tw_cl_scsi_req_packet scsi_req; /* SCSI req */ 189 struct tw_cl_passthru_req_packet pt_req;/*Passthru req*/ 190 } gen_req_pkt; 191 }; 192 193 194 #pragma pack(1) 195 /* 196 * Packet that describes an AEN/error generated by the controller, 197 * Common Layer, or even the OS Layer. 198 */ 199 struct tw_cl_event_packet { 200 TW_UINT32 sequence_id; 201 TW_UINT32 time_stamp_sec; 202 TW_UINT16 aen_code; 203 TW_UINT8 severity; 204 TW_UINT8 retrieved; 205 TW_UINT8 repeat_count; 206 TW_UINT8 parameter_len; 207 TW_UINT8 parameter_data[98]; 208 TW_UINT32 event_src; 209 TW_UINT8 severity_str[20]; 210 }; 211 #pragma pack() 212 213 214 /* Structure to link 2 adjacent elements in a list. */ 215 struct tw_cl_link { 216 struct tw_cl_link *next; 217 struct tw_cl_link *prev; 218 }; 219 220 221 #pragma pack(1) 222 /* Scatter/Gather list entry with 32 bit addresses. */ 223 struct tw_cl_sg_desc32 { 224 TW_UINT32 address; 225 TW_UINT32 length; 226 }; 227 228 229 /* Scatter/Gather list entry with 64 bit addresses. */ 230 struct tw_cl_sg_desc64 { 231 TW_UINT64 address; 232 TW_UINT32 length; 233 }; 234 235 #pragma pack() 236 237 238 /* Byte swap functions. Valid only if running on big endian platforms. */ 239 #ifdef TW_OSL_BIG_ENDIAN 240 241 #define TW_CL_SWAP16_WITH_CAST(x) \ 242 ((x << 8) | (x >> 8)) 243 244 245 #define TW_CL_SWAP32_WITH_CAST(x) \ 246 ((x << 24) | ((x << 8) & (0xFF0000)) | \ 247 ((x >> 8) & (0xFF00)) | (x >> 24)) 248 249 250 #define TW_CL_SWAP64_WITH_CAST(x) \ 251 ((((TW_UINT64)(TW_CL_SWAP32(((TW_UINT32 *)(&(x)))[1]))) << 32) |\ 252 ((TW_UINT32)(TW_CL_SWAP32(((TW_UINT32 *)(&(x)))[0])))) 253 254 255 #else /* TW_OSL_BIG_ENDIAN */ 256 257 #define TW_CL_SWAP16_WITH_CAST(x) x 258 #define TW_CL_SWAP32_WITH_CAST(x) x 259 #define TW_CL_SWAP64_WITH_CAST(x) x 260 261 #endif /* TW_OSL_BIG_ENDIAN */ 262 263 #define TW_CL_SWAP16(x) TW_CL_SWAP16_WITH_CAST((TW_UINT16)(x)) 264 #define TW_CL_SWAP32(x) TW_CL_SWAP32_WITH_CAST((TW_UINT32)(x)) 265 #define TW_CL_SWAP64(x) TW_CL_SWAP64_WITH_CAST((TW_UINT64)(x)) 266 267 268 /* Queue manipulation functions. */ 269 270 /* Initialize a queue. */ 271 #define TW_CL_Q_INIT(head) do { \ 272 (head)->prev = (head)->next = head; \ 273 } while (0) 274 275 276 /* Insert an item at the head of the queue. */ 277 #define TW_CL_Q_INSERT_HEAD(head, item) do { \ 278 (item)->next = (head)->next; \ 279 (item)->prev = head; \ 280 (head)->next->prev = item; \ 281 (head)->next = item; \ 282 } while (0) 283 284 285 /* Insert an item at the tail of the queue. */ 286 #define TW_CL_Q_INSERT_TAIL(head, item) do { \ 287 (item)->next = head; \ 288 (item)->prev = (head)->prev; \ 289 (head)->prev->next = item; \ 290 (head)->prev = item; \ 291 } while (0) 292 293 294 /* Remove an item from the head of the queue. */ 295 #define TW_CL_Q_REMOVE_ITEM(head, item) do { \ 296 (item)->prev->next = (item)->next; \ 297 (item)->next->prev = (item)->prev; \ 298 } while (0) 299 300 301 /* Retrieve the item at the head of the queue. */ 302 #define TW_CL_Q_FIRST_ITEM(head) \ 303 (((head)->next != head) ? ((head)->next) : TW_CL_NULL) 304 305 306 /* Retrieve the item at the tail of the queue. */ 307 #define TW_CL_Q_LAST_ITEM(head) \ 308 (((head)->prev != head) ? ((head)->prev) : TW_CL_NULL) 309 310 311 /* Retrieve the item next to a given item in the queue. */ 312 #define TW_CL_Q_NEXT_ITEM(head, item) \ 313 (((item)->next != head) ? ((item)->next) : TW_CL_NULL) 314 315 316 /* Retrieve the item previous to a given item in the queue. */ 317 #define TW_CL_Q_PREV_ITEM(head, item) \ 318 (((item)->prev != head) ? ((item)->prev) : TW_CL_NULL) 319 320 321 /* Determine the offset of a field from the head of the structure it is in. */ 322 #define TW_CL_STRUCT_OFFSET(struct_type, field) \ 323 (TW_INT8 *)(&((struct_type *)0)->field) 324 325 326 /* 327 * Determine the address of the head of a structure, given the address of a 328 * field within it. 329 */ 330 #define TW_CL_STRUCT_HEAD(addr, struct_type, field) \ 331 (struct_type *)((TW_INT8 *)addr - \ 332 TW_CL_STRUCT_OFFSET(struct_type, field)) 333 334 335 336 #ifndef TW_BUILDING_API 337 338 #include "tw_osl_inline.h" 339 340 341 342 /* 343 * The following are extern declarations of OS Layer defined functions called 344 * by the Common Layer. If any function has been defined as a macro in 345 * tw_osl_share.h, we will not make the extern declaration here. 346 */ 347 348 #ifndef tw_osl_breakpoint 349 /* Allows setting breakpoints in the CL code for debugging purposes. */ 350 extern TW_VOID tw_osl_breakpoint(TW_VOID); 351 #endif 352 353 354 #ifndef tw_osl_timeout 355 /* Start OS timeout() routine after controller reset sequence */ 356 extern TW_VOID tw_osl_timeout(struct tw_cl_req_handle *req_handle); 357 #endif 358 359 #ifndef tw_osl_untimeout 360 /* Stop OS timeout() routine during controller reset sequence */ 361 extern TW_VOID tw_osl_untimeout(struct tw_cl_req_handle *req_handle); 362 #endif 363 364 365 #ifndef tw_osl_cur_func 366 /* Text name of current function. */ 367 extern TW_INT8 *tw_osl_cur_func(TW_VOID); 368 #endif 369 370 371 #ifdef TW_OSL_DEBUG 372 #ifndef tw_osl_dbg_printf 373 /* Print to syslog/event log/debug console, as applicable. */ 374 extern TW_INT32 tw_osl_dbg_printf(struct tw_cl_ctlr_handle *ctlr_handle, 375 const TW_INT8 *fmt, ...); 376 #endif 377 #endif /* TW_OSL_DEBUG */ 378 379 380 #ifndef tw_osl_delay 381 /* Cause a delay of usecs micro-seconds. */ 382 extern TW_VOID tw_osl_delay(TW_INT32 usecs); 383 #endif 384 385 386 #ifndef tw_osl_destroy_lock 387 /* Create/initialize a lock for CL's use. */ 388 extern TW_VOID tw_osl_destroy_lock(struct tw_cl_ctlr_handle *ctlr_handle, 389 TW_LOCK_HANDLE *lock); 390 #endif 391 392 393 #ifndef tw_osl_free_lock 394 /* Free a previously held lock. */ 395 extern TW_VOID tw_osl_free_lock(struct tw_cl_ctlr_handle *ctlr_handle, 396 TW_LOCK_HANDLE *lock); 397 #endif 398 399 400 #ifndef tw_osl_get_local_time 401 /* Get local time. */ 402 extern TW_TIME tw_osl_get_local_time(TW_VOID); 403 #endif 404 405 406 #ifndef tw_osl_get_lock 407 /* Acquire a lock. */ 408 extern TW_VOID tw_osl_get_lock(struct tw_cl_ctlr_handle *ctlr_handle, 409 TW_LOCK_HANDLE *lock); 410 #endif 411 412 413 #ifndef tw_osl_init_lock 414 /* Create/initialize a lock for CL's use. */ 415 extern TW_VOID tw_osl_init_lock(struct tw_cl_ctlr_handle *ctlr_handle, 416 TW_INT8 *lock_name, TW_LOCK_HANDLE *lock); 417 #endif 418 419 420 #ifndef tw_osl_memcpy 421 /* Copy 'size' bytes from 'src' to 'dest'. */ 422 extern TW_VOID tw_osl_memcpy(TW_VOID *src, TW_VOID *dest, TW_INT32 size); 423 #endif 424 425 426 #ifndef tw_osl_memzero 427 /* Zero 'size' bytes starting at 'addr'. */ 428 extern TW_VOID tw_osl_memzero(TW_VOID *addr, TW_INT32 size); 429 #endif 430 431 432 #ifndef tw_osl_notify_event 433 /* Notify OSL of a controller/CL (or even OSL) event. */ 434 extern TW_VOID tw_osl_notify_event(struct tw_cl_ctlr_handle *ctlr_handle, 435 struct tw_cl_event_packet *event); 436 #endif 437 438 439 #ifdef TW_OSL_PCI_CONFIG_ACCESSIBLE 440 #ifndef tw_osl_read_pci_config 441 /* Read 'size' bytes from 'offset' in the PCI config space. */ 442 extern TW_UINT32 tw_osl_read_pci_config( 443 struct tw_cl_ctlr_handle *ctlr_handle, TW_INT32 offset, TW_INT32 size); 444 #endif 445 #endif /* TW_OSL_PCI_CONFIG_ACCESSIBLE */ 446 447 448 #ifndef tw_osl_read_reg 449 /* Read 'size' bytes at 'offset' from base address of this controller. */ 450 extern TW_UINT32 tw_osl_read_reg(struct tw_cl_ctlr_handle *ctlr_handle, 451 TW_INT32 offset, TW_INT32 size); 452 #endif 453 454 455 #ifndef tw_osl_scan_bus 456 /* Request OSL for a bus scan. */ 457 extern TW_VOID tw_osl_scan_bus(struct tw_cl_ctlr_handle *ctlr_handle); 458 #endif 459 460 461 #ifdef TW_OSL_CAN_SLEEP 462 #ifndef tw_osl_sleep 463 /* Sleep for 'timeout' ms or until woken up (by tw_osl_wakeup). */ 464 extern TW_INT32 tw_osl_sleep(struct tw_cl_ctlr_handle *ctlr_handle, 465 TW_SLEEP_HANDLE *sleep_handle, TW_INT32 timeout); 466 #endif 467 #endif /* TW_OSL_CAN_SLEEP */ 468 469 470 #ifndef tw_osl_sprintf 471 /* Standard sprintf. */ 472 extern TW_INT32 tw_osl_sprintf(TW_INT8 *dest, const TW_INT8 *fmt, ...); 473 #endif 474 475 476 #ifndef tw_osl_strcpy 477 /* Copy string 'src' to 'dest'. */ 478 extern TW_INT8 *tw_osl_strcpy(TW_INT8 *dest, TW_INT8 *src); 479 #endif 480 481 482 #ifndef tw_osl_strlen 483 /* Return length of string pointed at by 'str'. */ 484 extern TW_INT32 tw_osl_strlen(TW_VOID *str); 485 #endif 486 487 #ifndef tw_osl_vsprintf 488 /* Standard vsprintf. */ 489 extern TW_INT32 tw_osl_vsprintf(TW_INT8 *dest, const TW_INT8 *fmt, va_list ap); 490 #endif 491 492 493 #ifdef TW_OSL_CAN_SLEEP 494 #ifndef tw_osl_wakeup 495 /* Wake up a thread sleeping by a call to tw_osl_sleep. */ 496 extern TW_VOID tw_osl_wakeup(struct tw_cl_ctlr_handle *ctlr_handle, 497 TW_SLEEP_HANDLE *sleep_handle); 498 #endif 499 #endif /* TW_OSL_CAN_SLEEP */ 500 501 502 #ifdef TW_OSL_PCI_CONFIG_ACCESSIBLE 503 #ifndef tw_osl_write_pci_config 504 /* Write 'value' of 'size' bytes at 'offset' in the PCI config space. */ 505 extern TW_VOID tw_osl_write_pci_config(struct tw_cl_ctlr_handle *ctlr_handle, 506 TW_INT32 offset, TW_INT32 value, TW_INT32 size); 507 #endif 508 #endif /* TW_OSL_PCI_CONFIG_ACCESSIBLE */ 509 510 511 #ifndef tw_osl_write_reg 512 /* 513 * Write 'value' of 'size' (max 4) bytes at 'offset' from base address of 514 * this controller. 515 */ 516 extern TW_VOID tw_osl_write_reg(struct tw_cl_ctlr_handle *ctlr_handle, 517 TW_INT32 offset, TW_INT32 value, TW_INT32 size); 518 #endif 519 520 521 522 /* Functions in the Common Layer */ 523 524 /* Creates and queues AEN's. Also notifies OS Layer. */ 525 extern TW_VOID tw_cl_create_event(struct tw_cl_ctlr_handle *ctlr_handle, 526 TW_UINT8 queue_event, TW_UINT8 event_src, TW_UINT16 event_code, 527 TW_UINT8 severity, TW_UINT8 *severity_str, TW_UINT8 *event_desc, 528 TW_UINT8 *event_specific_desc, ...); 529 530 /* Indicates whether a ctlr is supported by CL. */ 531 extern TW_INT32 tw_cl_ctlr_supported(TW_INT32 vendor_id, TW_INT32 device_id); 532 533 534 /* Submit a firmware cmd packet. */ 535 extern TW_INT32 tw_cl_fw_passthru(struct tw_cl_ctlr_handle *ctlr_handle, 536 struct tw_cl_req_packet *req_pkt, struct tw_cl_req_handle *req_handle); 537 538 539 /* Find out how much memory CL needs. */ 540 extern TW_INT32 tw_cl_get_mem_requirements( 541 struct tw_cl_ctlr_handle *ctlr_handle, TW_UINT32 flags, 542 TW_INT32 device_id, TW_INT32 max_simult_reqs, TW_INT32 max_aens, 543 TW_UINT32 *alignment, TW_UINT32 *sg_size_factor, 544 TW_UINT32 *non_dma_mem_size, TW_UINT32 *dma_mem_size 545 ); 546 547 548 /* Return PCI BAR info. */ 549 extern TW_INT32 tw_cl_get_pci_bar_info(TW_INT32 device_id, TW_INT32 bar_type, 550 TW_INT32 *bar_num, TW_INT32 *bar0_offset, TW_INT32 *bar_size); 551 552 553 /* Initialize Common Layer for a given controller. */ 554 extern TW_INT32 tw_cl_init_ctlr(struct tw_cl_ctlr_handle *ctlr_handle, 555 TW_UINT32 flags, TW_INT32 device_id, TW_INT32 max_simult_reqs, 556 TW_INT32 max_aens, TW_VOID *non_dma_mem, TW_VOID *dma_mem, 557 TW_UINT64 dma_mem_phys 558 ); 559 560 561 extern TW_VOID tw_cl_set_reset_needed(struct tw_cl_ctlr_handle *ctlr_handle); 562 extern TW_INT32 tw_cl_is_reset_needed(struct tw_cl_ctlr_handle *ctlr_handle); 563 extern TW_INT32 tw_cl_is_active(struct tw_cl_ctlr_handle *ctlr_handle); 564 565 /* CL's interrupt handler. */ 566 extern TW_INT32 tw_cl_interrupt(struct tw_cl_ctlr_handle *ctlr_handle); 567 568 569 /* CL's ioctl handler. */ 570 extern TW_INT32 tw_cl_ioctl(struct tw_cl_ctlr_handle *ctlr_handle, 571 u_long cmd, TW_VOID *buf); 572 573 574 #ifdef TW_OSL_DEBUG 575 /* Print CL's state/statistics for a controller. */ 576 extern TW_VOID tw_cl_print_ctlr_stats(struct tw_cl_ctlr_handle *ctlr_handle); 577 578 /* Prints CL internal details of a given request. */ 579 extern TW_VOID tw_cl_print_req_info(struct tw_cl_req_handle *req_handle); 580 #endif /* TW_OSL_DEBUG */ 581 582 583 /* Soft reset controller. */ 584 extern TW_INT32 tw_cl_reset_ctlr(struct tw_cl_ctlr_handle *ctlr_handle); 585 586 587 #ifdef TW_OSL_DEBUG 588 /* Reset CL's statistics for a controller. */ 589 extern TW_VOID tw_cl_reset_stats(struct tw_cl_ctlr_handle *ctlr_handle); 590 #endif /* TW_OSL_DEBUG */ 591 592 593 /* Stop a controller. */ 594 extern TW_INT32 tw_cl_shutdown_ctlr(struct tw_cl_ctlr_handle *ctlr_handle, 595 TW_UINT32 flags); 596 597 598 /* Submit a SCSI I/O request. */ 599 extern TW_INT32 tw_cl_start_io(struct tw_cl_ctlr_handle *ctlr_handle, 600 struct tw_cl_req_packet *req_pkt, struct tw_cl_req_handle *req_handle); 601 602 603 #endif /* TW_BUILDING_API */ 604 605 #endif /* TW_CL_SHARE_H */ 606