1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2004-07 Applied Micro Circuits Corporation. 5 * Copyright (c) 2004-05 Vinod Kashyap 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * AMCC'S 3ware driver for 9000 series storage controllers. 32 * 33 * Author: Vinod Kashyap 34 * Modifications by: Adam Radford 35 * Modifications by: Manjunath Ranganathaiah 36 */ 37 38 #ifndef TW_CL_SHARE_H 39 40 #define TW_CL_SHARE_H 41 42 /* 43 * Macros, structures and functions shared between OSL and CL, 44 * and defined by CL. 45 */ 46 47 #define TW_CL_NULL ((TW_VOID *)0) 48 #define TW_CL_TRUE 1 49 #define TW_CL_FALSE 0 50 51 #define TW_CL_VENDOR_ID 0x13C1 /* 3ware vendor id */ 52 #define TW_CL_DEVICE_ID_9K 0x1002 /* 9000 PCI series device id */ 53 #define TW_CL_DEVICE_ID_9K_X 0x1003 /* 9000 PCI-X series device id */ 54 #define TW_CL_DEVICE_ID_9K_E 0x1004 /* 9000 PCIe series device id */ 55 #define TW_CL_DEVICE_ID_9K_SA 0x1005 /* 9000 PCIe SAS series device id */ 56 57 #define TW_CL_BAR_TYPE_IO 1 /* I/O base address */ 58 #define TW_CL_BAR_TYPE_MEM 2 /* memory base address */ 59 #define TW_CL_BAR_TYPE_SBUF 3 /* SBUF base address */ 60 61 #ifdef TW_OSL_ENCLOSURE_SUPPORT 62 #define TW_CL_MAX_NUM_UNITS 65 /* max # of units we support 63 -- enclosure target id is 64 */ 64 #else /* TW_OSL_ENCLOSURE_SUPPORT */ 65 #define TW_CL_MAX_NUM_UNITS 32 /* max # of units we support */ 66 #endif /* TW_OSL_ENCLOSURE_SUPPORT */ 67 68 #define TW_CL_MAX_NUM_LUNS 255 /* max # of LUN's we support */ 69 #define TW_CL_MAX_IO_SIZE 0x20000 /* 128K */ 70 71 /* 72 * Though we can support 256 simultaneous requests, we advertise as capable 73 * of supporting only 255, since we want to keep one CL internal request 74 * context packet always available for internal requests. 75 */ 76 #define TW_CL_MAX_SIMULTANEOUS_REQUESTS 256 /* max simult reqs supported */ 77 78 #define TW_CL_MAX_32BIT_SG_ELEMENTS 109 /* max 32-bit sg elements */ 79 #define TW_CL_MAX_64BIT_SG_ELEMENTS 72 /* max 64-bit sg elements */ 80 81 /* Possible values of ctlr->flags */ 82 #define TW_CL_64BIT_ADDRESSES (1<<0) /* 64 bit cmdpkt & SG addresses */ 83 #define TW_CL_64BIT_SG_LENGTH (1<<1) /* 64 bit SG length */ 84 #define TW_CL_START_CTLR_ONLY (1<<2) /* Start ctlr only */ 85 #define TW_CL_STOP_CTLR_ONLY (1<<3) /* Stop ctlr only */ 86 #define TW_CL_DEFERRED_INTR_USED (1<<5) /* OS Layer uses deferred intr */ 87 88 /* Possible error values from the Common Layer. */ 89 #define TW_CL_ERR_REQ_SUCCESS 0 90 #define TW_CL_ERR_REQ_GENERAL_FAILURE (1<<0) 91 #define TW_CL_ERR_REQ_INVALID_TARGET (1<<1) 92 #define TW_CL_ERR_REQ_INVALID_LUN (1<<2) 93 #define TW_CL_ERR_REQ_SCSI_ERROR (1<<3) 94 #define TW_CL_ERR_REQ_AUTO_SENSE_VALID (1<<4) 95 #define TW_CL_ERR_REQ_BUS_RESET (1<<5) 96 #define TW_CL_ERR_REQ_UNABLE_TO_SUBMIT_COMMAND (1<<6) 97 98 /* Possible values of req_pkt->flags */ 99 #define TW_CL_REQ_RETRY_ON_BUSY (1<<0) 100 #define TW_CL_REQ_CALLBACK_FOR_SGLIST (1<<1) 101 102 #define TW_CL_MESSAGE_SOURCE_CONTROLLER_ERROR 3 103 #define TW_CL_MESSAGE_SOURCE_CONTROLLER_EVENT 4 104 #define TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR 21 105 #define TW_CL_MESSAGE_SOURCE_COMMON_LAYER_EVENT 22 106 #define TW_CL_MESSAGE_SOURCE_FREEBSD_DRIVER 5 107 #define TW_CL_MESSAGE_SOURCE_FREEBSD_OS 8 108 #define TW_CL_MESSAGE_SOURCE_WINDOWS_DRIVER 7 109 #define TW_CL_MESSAGE_SOURCE_WINDOWS_OS 10 110 111 #define TW_CL_SEVERITY_ERROR 0x1 112 #define TW_CL_SEVERITY_WARNING 0x2 113 #define TW_CL_SEVERITY_INFO 0x3 114 #define TW_CL_SEVERITY_DEBUG 0x4 115 116 #define TW_CL_SEVERITY_ERROR_STRING "ERROR" 117 #define TW_CL_SEVERITY_WARNING_STRING "WARNING" 118 #define TW_CL_SEVERITY_INFO_STRING "INFO" 119 #define TW_CL_SEVERITY_DEBUG_STRING "DEBUG" 120 121 /* 122 * Structure, a pointer to which is used as the controller handle in 123 * communications between the OS Layer and the Common Layer. 124 */ 125 struct tw_cl_ctlr_handle { 126 TW_VOID *osl_ctlr_ctxt; /* OSL's ctlr context */ 127 TW_VOID *cl_ctlr_ctxt; /* CL's ctlr context */ 128 }; 129 130 /* 131 * Structure, a pointer to which is used as the request handle in 132 * communications between the OS Layer and the Common Layer. 133 */ 134 struct tw_cl_req_handle { 135 TW_VOID *osl_req_ctxt; /* OSL's request context */ 136 TW_VOID *cl_req_ctxt; /* CL's request context */ 137 TW_UINT8 is_io; /* Only freeze/release simq for IOs */ 138 }; 139 140 /* Structure used to describe SCSI requests to CL. */ 141 struct tw_cl_scsi_req_packet { 142 TW_UINT32 unit; /* unit # to send cmd to */ 143 TW_UINT32 lun; /* LUN to send cmd to */ 144 TW_UINT8 *cdb; /* ptr to SCSI cdb */ 145 TW_UINT32 cdb_len; /* # of valid cdb bytes */ 146 TW_UINT32 sense_len; /* # of bytes of valid sense info */ 147 TW_UINT8 *sense_data; /* ptr to sense data, if any */ 148 TW_UINT32 scsi_status; /* SCSI status returned by fw */ 149 TW_UINT32 sgl_entries; /* # of SG descriptors */ 150 TW_UINT8 *sg_list; /* ptr to SG list */ 151 }; 152 153 /* Structure used to describe pass through command packets to CL. */ 154 struct tw_cl_passthru_req_packet { 155 TW_UINT8 *cmd_pkt; /* ptr to passthru cmd pkt */ 156 TW_UINT32 cmd_pkt_length; /* size of cmd pkt */ 157 TW_UINT32 sgl_entries; /* # of SG descriptors */ 158 TW_UINT8 *sg_list; /* ptr to SG list */ 159 }; 160 161 /* Request packet submitted to the Common Layer, by the OS Layer. */ 162 struct tw_cl_req_packet { 163 TW_UINT32 cmd; /* Common Layer cmd */ 164 TW_UINT32 flags; /* flags describing request */ 165 TW_UINT32 status; /* Common Layer returned status */ 166 TW_VOID (*tw_osl_callback)(struct tw_cl_req_handle *req_handle); 167 /* OSL routine to be called by CL on req completion */ 168 TW_VOID (*tw_osl_sgl_callback)( 169 struct tw_cl_req_handle *req_handle, TW_VOID *sg_list, 170 TW_UINT32 *num_sgl_entries); 171 /* OSL callback to get SG list. */ 172 173 union { 174 struct tw_cl_scsi_req_packet scsi_req; /* SCSI req */ 175 struct tw_cl_passthru_req_packet pt_req;/*Passthru req*/ 176 } gen_req_pkt; 177 }; 178 179 #pragma pack(1) 180 /* 181 * Packet that describes an AEN/error generated by the controller, 182 * Common Layer, or even the OS Layer. 183 */ 184 struct tw_cl_event_packet { 185 TW_UINT32 sequence_id; 186 TW_UINT32 time_stamp_sec; 187 TW_UINT16 aen_code; 188 TW_UINT8 severity; 189 TW_UINT8 retrieved; 190 TW_UINT8 repeat_count; 191 TW_UINT8 parameter_len; 192 TW_UINT8 parameter_data[98]; 193 TW_UINT32 event_src; 194 TW_UINT8 severity_str[20]; 195 }; 196 #pragma pack() 197 198 /* Structure to link 2 adjacent elements in a list. */ 199 struct tw_cl_link { 200 struct tw_cl_link *next; 201 struct tw_cl_link *prev; 202 }; 203 204 #pragma pack(1) 205 /* Scatter/Gather list entry with 32 bit addresses. */ 206 struct tw_cl_sg_desc32 { 207 TW_UINT32 address; 208 TW_UINT32 length; 209 }; 210 211 /* Scatter/Gather list entry with 64 bit addresses. */ 212 struct tw_cl_sg_desc64 { 213 TW_UINT64 address; 214 TW_UINT32 length; 215 }; 216 217 #pragma pack() 218 219 /* Byte swap functions. Valid only if running on big endian platforms. */ 220 #ifdef TW_OSL_BIG_ENDIAN 221 222 #define TW_CL_SWAP16_WITH_CAST(x) \ 223 ((x << 8) | (x >> 8)) 224 225 #define TW_CL_SWAP32_WITH_CAST(x) \ 226 ((x << 24) | ((x << 8) & (0xFF0000)) | \ 227 ((x >> 8) & (0xFF00)) | (x >> 24)) 228 229 #define TW_CL_SWAP64_WITH_CAST(x) \ 230 ((((TW_UINT64)(TW_CL_SWAP32(((TW_UINT32 *)(&(x)))[1]))) << 32) |\ 231 ((TW_UINT32)(TW_CL_SWAP32(((TW_UINT32 *)(&(x)))[0])))) 232 233 #else /* TW_OSL_BIG_ENDIAN */ 234 235 #define TW_CL_SWAP16_WITH_CAST(x) x 236 #define TW_CL_SWAP32_WITH_CAST(x) x 237 #define TW_CL_SWAP64_WITH_CAST(x) x 238 239 #endif /* TW_OSL_BIG_ENDIAN */ 240 241 #define TW_CL_SWAP16(x) TW_CL_SWAP16_WITH_CAST((TW_UINT16)(x)) 242 #define TW_CL_SWAP32(x) TW_CL_SWAP32_WITH_CAST((TW_UINT32)(x)) 243 #define TW_CL_SWAP64(x) TW_CL_SWAP64_WITH_CAST((TW_UINT64)(x)) 244 245 /* Queue manipulation functions. */ 246 247 /* Initialize a queue. */ 248 #define TW_CL_Q_INIT(head) do { \ 249 (head)->prev = (head)->next = head; \ 250 } while (0) 251 252 /* Insert an item at the head of the queue. */ 253 #define TW_CL_Q_INSERT_HEAD(head, item) do { \ 254 (item)->next = (head)->next; \ 255 (item)->prev = head; \ 256 (head)->next->prev = item; \ 257 (head)->next = item; \ 258 } while (0) 259 260 /* Insert an item at the tail of the queue. */ 261 #define TW_CL_Q_INSERT_TAIL(head, item) do { \ 262 (item)->next = head; \ 263 (item)->prev = (head)->prev; \ 264 (head)->prev->next = item; \ 265 (head)->prev = item; \ 266 } while (0) 267 268 /* Remove an item from the head of the queue. */ 269 #define TW_CL_Q_REMOVE_ITEM(head, item) do { \ 270 (item)->prev->next = (item)->next; \ 271 (item)->next->prev = (item)->prev; \ 272 } while (0) 273 274 /* Retrieve the item at the head of the queue. */ 275 #define TW_CL_Q_FIRST_ITEM(head) \ 276 (((head)->next != head) ? ((head)->next) : TW_CL_NULL) 277 278 /* Retrieve the item at the tail of the queue. */ 279 #define TW_CL_Q_LAST_ITEM(head) \ 280 (((head)->prev != head) ? ((head)->prev) : TW_CL_NULL) 281 282 /* Retrieve the item next to a given item in the queue. */ 283 #define TW_CL_Q_NEXT_ITEM(head, item) \ 284 (((item)->next != head) ? ((item)->next) : TW_CL_NULL) 285 286 /* Retrieve the item previous to a given item in the queue. */ 287 #define TW_CL_Q_PREV_ITEM(head, item) \ 288 (((item)->prev != head) ? ((item)->prev) : TW_CL_NULL) 289 290 /* Determine the offset of a field from the head of the structure it is in. */ 291 #define TW_CL_STRUCT_OFFSET(struct_type, field) \ 292 (TW_INT8 *)(&((struct_type *)0)->field) 293 294 /* 295 * Determine the address of the head of a structure, given the address of a 296 * field within it. 297 */ 298 #define TW_CL_STRUCT_HEAD(addr, struct_type, field) \ 299 (struct_type *)((TW_INT8 *)addr - \ 300 TW_CL_STRUCT_OFFSET(struct_type, field)) 301 302 #ifndef TW_BUILDING_API 303 304 #include "tw_osl_inline.h" 305 306 /* 307 * The following are extern declarations of OS Layer defined functions called 308 * by the Common Layer. If any function has been defined as a macro in 309 * tw_osl_share.h, we will not make the extern declaration here. 310 */ 311 312 #ifndef tw_osl_breakpoint 313 /* Allows setting breakpoints in the CL code for debugging purposes. */ 314 extern TW_VOID tw_osl_breakpoint(TW_VOID); 315 #endif 316 317 #ifndef tw_osl_timeout 318 /* Start OS timeout() routine after controller reset sequence */ 319 extern TW_VOID tw_osl_timeout(struct tw_cl_req_handle *req_handle); 320 #endif 321 322 #ifndef tw_osl_untimeout 323 /* Stop OS timeout() routine during controller reset sequence */ 324 extern TW_VOID tw_osl_untimeout(struct tw_cl_req_handle *req_handle); 325 #endif 326 327 #ifndef tw_osl_cur_func 328 /* Text name of current function. */ 329 extern TW_INT8 *tw_osl_cur_func(TW_VOID); 330 #endif 331 332 #ifdef TW_OSL_DEBUG 333 #ifndef tw_osl_dbg_printf 334 /* Print to syslog/event log/debug console, as applicable. */ 335 extern TW_INT32 tw_osl_dbg_printf(struct tw_cl_ctlr_handle *ctlr_handle, 336 const TW_INT8 *fmt, ...); 337 #endif 338 #endif /* TW_OSL_DEBUG */ 339 340 #ifndef tw_osl_delay 341 /* Cause a delay of usecs micro-seconds. */ 342 extern TW_VOID tw_osl_delay(TW_INT32 usecs); 343 #endif 344 345 #ifndef tw_osl_destroy_lock 346 /* Create/initialize a lock for CL's use. */ 347 extern TW_VOID tw_osl_destroy_lock(struct tw_cl_ctlr_handle *ctlr_handle, 348 TW_LOCK_HANDLE *lock); 349 #endif 350 351 #ifndef tw_osl_free_lock 352 /* Free a previously held lock. */ 353 extern TW_VOID tw_osl_free_lock(struct tw_cl_ctlr_handle *ctlr_handle, 354 TW_LOCK_HANDLE *lock); 355 #endif 356 357 #ifndef tw_osl_get_local_time 358 /* Get local time. */ 359 extern TW_TIME tw_osl_get_local_time(TW_VOID); 360 #endif 361 362 #ifndef tw_osl_get_lock 363 /* Acquire a lock. */ 364 extern TW_VOID tw_osl_get_lock(struct tw_cl_ctlr_handle *ctlr_handle, 365 TW_LOCK_HANDLE *lock); 366 #endif 367 368 #ifndef tw_osl_init_lock 369 /* Create/initialize a lock for CL's use. */ 370 extern TW_VOID tw_osl_init_lock(struct tw_cl_ctlr_handle *ctlr_handle, 371 TW_INT8 *lock_name, TW_LOCK_HANDLE *lock); 372 #endif 373 374 #ifndef tw_osl_memcpy 375 /* Copy 'size' bytes from 'src' to 'dest'. */ 376 extern TW_VOID tw_osl_memcpy(TW_VOID *src, TW_VOID *dest, TW_INT32 size); 377 #endif 378 379 #ifndef tw_osl_memzero 380 /* Zero 'size' bytes starting at 'addr'. */ 381 extern TW_VOID tw_osl_memzero(TW_VOID *addr, TW_INT32 size); 382 #endif 383 384 #ifndef tw_osl_notify_event 385 /* Notify OSL of a controller/CL (or even OSL) event. */ 386 extern TW_VOID tw_osl_notify_event(struct tw_cl_ctlr_handle *ctlr_handle, 387 struct tw_cl_event_packet *event); 388 #endif 389 390 #ifdef TW_OSL_PCI_CONFIG_ACCESSIBLE 391 #ifndef tw_osl_read_pci_config 392 /* Read 'size' bytes from 'offset' in the PCI config space. */ 393 extern TW_UINT32 tw_osl_read_pci_config( 394 struct tw_cl_ctlr_handle *ctlr_handle, TW_INT32 offset, TW_INT32 size); 395 #endif 396 #endif /* TW_OSL_PCI_CONFIG_ACCESSIBLE */ 397 398 #ifndef tw_osl_read_reg 399 /* Read 'size' bytes at 'offset' from base address of this controller. */ 400 extern TW_UINT32 tw_osl_read_reg(struct tw_cl_ctlr_handle *ctlr_handle, 401 TW_INT32 offset, TW_INT32 size); 402 #endif 403 404 #ifndef tw_osl_scan_bus 405 /* Request OSL for a bus scan. */ 406 extern TW_VOID tw_osl_scan_bus(struct tw_cl_ctlr_handle *ctlr_handle); 407 #endif 408 409 #ifdef TW_OSL_CAN_SLEEP 410 #ifndef tw_osl_sleep 411 /* Sleep for 'timeout' ms or until woken up (by tw_osl_wakeup). */ 412 extern TW_INT32 tw_osl_sleep(struct tw_cl_ctlr_handle *ctlr_handle, 413 TW_SLEEP_HANDLE *sleep_handle, TW_INT32 timeout); 414 #endif 415 #endif /* TW_OSL_CAN_SLEEP */ 416 417 #ifndef tw_osl_sprintf 418 /* Standard sprintf. */ 419 extern TW_INT32 tw_osl_sprintf(TW_INT8 *dest, const TW_INT8 *fmt, ...); 420 #endif 421 422 #ifndef tw_osl_strcpy 423 /* Copy string 'src' to 'dest'. */ 424 extern TW_INT8 *tw_osl_strcpy(TW_INT8 *dest, TW_INT8 *src); 425 #endif 426 427 #ifndef tw_osl_strlen 428 /* Return length of string pointed at by 'str'. */ 429 extern TW_INT32 tw_osl_strlen(TW_VOID *str); 430 #endif 431 432 #ifndef tw_osl_vsprintf 433 /* Standard vsprintf. */ 434 extern TW_INT32 tw_osl_vsprintf(TW_INT8 *dest, const TW_INT8 *fmt, va_list ap); 435 #endif 436 437 #ifdef TW_OSL_CAN_SLEEP 438 #ifndef tw_osl_wakeup 439 /* Wake up a thread sleeping by a call to tw_osl_sleep. */ 440 extern TW_VOID tw_osl_wakeup(struct tw_cl_ctlr_handle *ctlr_handle, 441 TW_SLEEP_HANDLE *sleep_handle); 442 #endif 443 #endif /* TW_OSL_CAN_SLEEP */ 444 445 #ifdef TW_OSL_PCI_CONFIG_ACCESSIBLE 446 #ifndef tw_osl_write_pci_config 447 /* Write 'value' of 'size' bytes at 'offset' in the PCI config space. */ 448 extern TW_VOID tw_osl_write_pci_config(struct tw_cl_ctlr_handle *ctlr_handle, 449 TW_INT32 offset, TW_INT32 value, TW_INT32 size); 450 #endif 451 #endif /* TW_OSL_PCI_CONFIG_ACCESSIBLE */ 452 453 #ifndef tw_osl_write_reg 454 /* 455 * Write 'value' of 'size' (max 4) bytes at 'offset' from base address of 456 * this controller. 457 */ 458 extern TW_VOID tw_osl_write_reg(struct tw_cl_ctlr_handle *ctlr_handle, 459 TW_INT32 offset, TW_INT32 value, TW_INT32 size); 460 #endif 461 462 /* Functions in the Common Layer */ 463 464 /* Creates and queues AEN's. Also notifies OS Layer. */ 465 extern TW_VOID tw_cl_create_event(struct tw_cl_ctlr_handle *ctlr_handle, 466 TW_UINT8 queue_event, TW_UINT8 event_src, TW_UINT16 event_code, 467 TW_UINT8 severity, TW_UINT8 *severity_str, TW_UINT8 *event_desc, 468 TW_UINT8 *event_specific_desc, ...); 469 470 /* Indicates whether a ctlr is supported by CL. */ 471 extern TW_INT32 tw_cl_ctlr_supported(TW_INT32 vendor_id, TW_INT32 device_id); 472 473 /* Submit a firmware cmd packet. */ 474 extern TW_INT32 tw_cl_fw_passthru(struct tw_cl_ctlr_handle *ctlr_handle, 475 struct tw_cl_req_packet *req_pkt, struct tw_cl_req_handle *req_handle); 476 477 /* Find out how much memory CL needs. */ 478 extern TW_INT32 tw_cl_get_mem_requirements( 479 struct tw_cl_ctlr_handle *ctlr_handle, TW_UINT32 flags, 480 TW_INT32 device_id, TW_INT32 max_simult_reqs, TW_INT32 max_aens, 481 TW_UINT32 *alignment, TW_UINT32 *sg_size_factor, 482 TW_UINT32 *non_dma_mem_size, TW_UINT32 *dma_mem_size 483 ); 484 485 /* Return PCI BAR info. */ 486 extern TW_INT32 tw_cl_get_pci_bar_info(TW_INT32 device_id, TW_INT32 bar_type, 487 TW_INT32 *bar_num, TW_INT32 *bar0_offset, TW_INT32 *bar_size); 488 489 /* Initialize Common Layer for a given controller. */ 490 extern TW_INT32 tw_cl_init_ctlr(struct tw_cl_ctlr_handle *ctlr_handle, 491 TW_UINT32 flags, TW_INT32 device_id, TW_INT32 max_simult_reqs, 492 TW_INT32 max_aens, TW_VOID *non_dma_mem, TW_VOID *dma_mem, 493 TW_UINT64 dma_mem_phys 494 ); 495 496 extern TW_VOID tw_cl_set_reset_needed(struct tw_cl_ctlr_handle *ctlr_handle); 497 extern TW_INT32 tw_cl_is_reset_needed(struct tw_cl_ctlr_handle *ctlr_handle); 498 extern TW_INT32 tw_cl_is_active(struct tw_cl_ctlr_handle *ctlr_handle); 499 500 /* CL's interrupt handler. */ 501 extern TW_INT32 tw_cl_interrupt(struct tw_cl_ctlr_handle *ctlr_handle); 502 503 /* CL's ioctl handler. */ 504 extern TW_INT32 tw_cl_ioctl(struct tw_cl_ctlr_handle *ctlr_handle, 505 u_long cmd, TW_VOID *buf); 506 507 #ifdef TW_OSL_DEBUG 508 /* Print CL's state/statistics for a controller. */ 509 extern TW_VOID tw_cl_print_ctlr_stats(struct tw_cl_ctlr_handle *ctlr_handle); 510 511 /* Prints CL internal details of a given request. */ 512 extern TW_VOID tw_cl_print_req_info(struct tw_cl_req_handle *req_handle); 513 #endif /* TW_OSL_DEBUG */ 514 515 /* Soft reset controller. */ 516 extern TW_INT32 tw_cl_reset_ctlr(struct tw_cl_ctlr_handle *ctlr_handle); 517 518 #ifdef TW_OSL_DEBUG 519 /* Reset CL's statistics for a controller. */ 520 extern TW_VOID tw_cl_reset_stats(struct tw_cl_ctlr_handle *ctlr_handle); 521 #endif /* TW_OSL_DEBUG */ 522 523 /* Stop a controller. */ 524 extern TW_INT32 tw_cl_shutdown_ctlr(struct tw_cl_ctlr_handle *ctlr_handle, 525 TW_UINT32 flags); 526 527 /* Submit a SCSI I/O request. */ 528 extern TW_INT32 tw_cl_start_io(struct tw_cl_ctlr_handle *ctlr_handle, 529 struct tw_cl_req_packet *req_pkt, struct tw_cl_req_handle *req_handle); 530 531 #endif /* TW_BUILDING_API */ 532 533 #endif /* TW_CL_SHARE_H */ 534