1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2004-07 Applied Micro Circuits Corporation. 5 * Copyright (c) 2004-05 Vinod Kashyap 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * AMCC'S 3ware driver for 9000 series storage controllers. 32 * 33 * Author: Vinod Kashyap 34 * Modifications by: Adam Radford 35 */ 36 37 #ifndef TW_CL_FWIF_H 38 39 #define TW_CL_FWIF_H 40 41 /* 42 * Macros and data structures for interfacing with the firmware. 43 */ 44 45 /* Register offsets from base address. */ 46 #define TWA_CONTROL_REGISTER_OFFSET 0x0 47 #define TWA_STATUS_REGISTER_OFFSET 0x4 48 #define TWA_COMMAND_QUEUE_OFFSET 0x8 49 #define TWA_RESPONSE_QUEUE_OFFSET 0xC 50 #define TWA_COMMAND_QUEUE_OFFSET_LOW 0x20 51 #define TWA_COMMAND_QUEUE_OFFSET_HIGH 0x24 52 #define TWA_LARGE_RESPONSE_QUEUE_OFFSET 0x30 53 54 /* Control register bit definitions. */ 55 #define TWA_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020 56 #define TWA_CONTROL_DISABLE_INTERRUPTS 0x00000040 57 #define TWA_CONTROL_ENABLE_INTERRUPTS 0x00000080 58 #define TWA_CONTROL_ISSUE_SOFT_RESET 0x00000100 59 #define TWA_CONTROL_UNMASK_RESPONSE_INTERRUPT 0x00004000 60 #define TWA_CONTROL_UNMASK_COMMAND_INTERRUPT 0x00008000 61 #define TWA_CONTROL_MASK_RESPONSE_INTERRUPT 0x00010000 62 #define TWA_CONTROL_MASK_COMMAND_INTERRUPT 0x00020000 63 #define TWA_CONTROL_CLEAR_ATTENTION_INTERRUPT 0x00040000 64 #define TWA_CONTROL_CLEAR_HOST_INTERRUPT 0x00080000 65 #define TWA_CONTROL_CLEAR_PCI_ABORT 0x00100000 66 #define TWA_CONTROL_CLEAR_QUEUE_ERROR 0x00400000 67 #define TWA_CONTROL_CLEAR_PARITY_ERROR 0x00800000 68 69 /* Status register bit definitions. */ 70 #define TWA_STATUS_ROM_BIOS_IN_SBUF 0x00000002 71 #define TWA_STATUS_COMMAND_QUEUE_EMPTY 0x00001000 72 #define TWA_STATUS_MICROCONTROLLER_READY 0x00002000 73 #define TWA_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000 74 #define TWA_STATUS_COMMAND_QUEUE_FULL 0x00008000 75 #define TWA_STATUS_RESPONSE_INTERRUPT 0x00010000 76 #define TWA_STATUS_COMMAND_INTERRUPT 0x00020000 77 #define TWA_STATUS_ATTENTION_INTERRUPT 0x00040000 78 #define TWA_STATUS_HOST_INTERRUPT 0x00080000 79 #define TWA_STATUS_PCI_ABORT_INTERRUPT 0x00100000 80 #define TWA_STATUS_MICROCONTROLLER_ERROR 0x00200000 81 #define TWA_STATUS_QUEUE_ERROR_INTERRUPT 0x00400000 82 #define TWA_STATUS_PCI_PARITY_ERROR_INTERRUPT 0x00800000 83 #define TWA_STATUS_MINOR_VERSION_MASK 0x0F000000 84 #define TWA_STATUS_MAJOR_VERSION_MASK 0xF0000000 85 86 #define TWA_STATUS_UNEXPECTED_BITS 0x00D00000 87 88 /* PCI related defines. */ 89 #define TWA_IO_CONFIG_REG 0x10 90 91 #define TWA_PCI_CONFIG_CLEAR_PARITY_ERROR 0xc100 92 #define TWA_PCI_CONFIG_CLEAR_PCI_ABORT 0x2000 93 94 #define TWA_RESET_PHASE1_NOTIFICATION_RESPONSE 0xFFFF 95 #define TWA_RESET_PHASE1_WAIT_TIME_MS 500 96 97 /* Command packet opcodes. */ 98 #define TWA_FW_CMD_NOP 0x00 99 #define TWA_FW_CMD_INIT_CONNECTION 0x01 100 #define TWA_FW_CMD_READ 0x02 101 #define TWA_FW_CMD_WRITE 0x03 102 #define TWA_FW_CMD_READVERIFY 0x04 103 #define TWA_FW_CMD_VERIFY 0x05 104 #define TWA_FW_CMD_ZEROUNIT 0x08 105 #define TWA_FW_CMD_REPLACEUNIT 0x09 106 #define TWA_FW_CMD_HOTSWAP 0x0A 107 #define TWA_FW_CMD_SELFTESTS 0x0B 108 #define TWA_FW_CMD_SYNC_PARAM 0x0C 109 #define TWA_FW_CMD_REORDER_UNITS 0x0D 110 111 #define TWA_FW_CMD_EXECUTE_SCSI 0x10 112 #define TWA_FW_CMD_ATA_PASSTHROUGH 0x11 113 #define TWA_FW_CMD_GET_PARAM 0x12 114 #define TWA_FW_CMD_SET_PARAM 0x13 115 #define TWA_FW_CMD_CREATEUNIT 0x14 116 #define TWA_FW_CMD_DELETEUNIT 0x15 117 #define TWA_FW_CMD_DOWNLOAD_FIRMWARE 0x16 118 #define TWA_FW_CMD_REBUILDUNIT 0x17 119 #define TWA_FW_CMD_POWER_MANAGEMENT 0x18 120 121 #define TWA_FW_CMD_REMOTE_PRINT 0x1B 122 #define TWA_FW_CMD_HARD_RESET_FIRMWARE 0x1C 123 #define TWA_FW_CMD_DEBUG 0x1D 124 125 #define TWA_FW_CMD_DIAGNOSTICS 0x1F 126 127 /* Misc defines. */ 128 #define TWA_SHUTDOWN_MESSAGE_CREDITS 0x001 129 #define TWA_64BIT_SG_ADDRESSES 0x00000001 130 #define TWA_EXTENDED_INIT_CONNECT 0x00000002 131 #define TWA_BASE_MODE 1 132 #define TWA_BASE_FW_SRL 24 133 #define TWA_BASE_FW_BRANCH 0 134 #define TWA_BASE_FW_BUILD 1 135 #define TWA_CURRENT_FW_SRL 41 136 #define TWA_CURRENT_FW_BRANCH_9K 4 137 #define TWA_CURRENT_FW_BUILD_9K 8 138 #define TWA_CURRENT_FW_BRANCH_9K_X 8 139 #define TWA_CURRENT_FW_BUILD_9K_X 4 140 #define TWA_MULTI_LUN_FW_SRL 28 141 #define TWA_ARCH_ID_9K 0x5 /* 9000 PCI controllers */ 142 #define TWA_ARCH_ID_9K_X 0x6 /* 9000 PCI-X controllers */ 143 #define TWA_CTLR_FW_SAME_OR_NEWER 0x00000001 144 #define TWA_CTLR_FW_COMPATIBLE 0x00000002 145 #define TWA_SENSE_DATA_LENGTH 18 146 147 #define TWA_ARCH_ID(device_id) \ 148 (((device_id) == TW_CL_DEVICE_ID_9K) ? TWA_ARCH_ID_9K : \ 149 TWA_ARCH_ID_9K_X) 150 #define TWA_CURRENT_FW_BRANCH(arch_id) \ 151 (((arch_id) == TWA_ARCH_ID_9K) ? TWA_CURRENT_FW_BRANCH_9K : \ 152 TWA_CURRENT_FW_BRANCH_9K_X) 153 #define TWA_CURRENT_FW_BUILD(arch_id) \ 154 (((arch_id) == TWA_ARCH_ID_9K) ? TWA_CURRENT_FW_BUILD_9K : \ 155 TWA_CURRENT_FW_BUILD_9K_X) 156 157 /* 158 * All SG addresses and DMA'able memory allocated by the OSL should be 159 * TWA_ALIGNMENT bytes aligned, and have a size that is a multiple of 160 * TWA_SG_ELEMENT_SIZE_FACTOR. 161 */ 162 #define TWA_ALIGNMENT(device_id) 0x4 163 #define TWA_SG_ELEMENT_SIZE_FACTOR(device_id) \ 164 (((device_id) == TW_CL_DEVICE_ID_9K) ? 512 : 4) 165 166 /* 167 * Some errors of interest (in cmd_hdr->status_block.error) when a command 168 * is completed by the firmware with a bad status. 169 */ 170 #define TWA_ERROR_LOGICAL_UNIT_NOT_SUPPORTED 0x010a 171 #define TWA_ERROR_UNIT_OFFLINE 0x0128 172 #define TWA_ERROR_MORE_DATA 0x0231 173 174 /* AEN codes of interest. */ 175 #define TWA_AEN_QUEUE_EMPTY 0x00 176 #define TWA_AEN_SOFT_RESET 0x01 177 #define TWA_AEN_SYNC_TIME_WITH_HOST 0x31 178 179 /* Table #'s and id's of parameters of interest in firmware's param table. */ 180 #define TWA_PARAM_VERSION_TABLE 0x0402 181 #define TWA_PARAM_VERSION_FW 3 /* firmware version [16] */ 182 #define TWA_PARAM_VERSION_BIOS 4 /* BIOSs version [16] */ 183 #define TWA_PARAM_CTLR_MODEL 8 /* Controller model [16] */ 184 185 #define TWA_PARAM_CONTROLLER_TABLE 0x0403 186 #define TWA_PARAM_CONTROLLER_PORT_COUNT 3 /* number of ports [1] */ 187 188 #define TWA_PARAM_TIME_TABLE 0x40A 189 #define TWA_PARAM_TIME_SCHED_TIME 0x3 190 191 #define TWA_9K_PARAM_DESCRIPTOR 0x8000 192 193 #pragma pack(1) 194 /* 7000 structures. */ 195 struct tw_cl_command_init_connect { 196 TW_UINT8 res1__opcode; /* 3:5 */ 197 TW_UINT8 size; 198 TW_UINT8 request_id; 199 TW_UINT8 res2; 200 TW_UINT8 status; 201 TW_UINT8 flags; 202 TW_UINT16 message_credits; 203 TW_UINT32 features; 204 TW_UINT16 fw_srl; 205 TW_UINT16 fw_arch_id; 206 TW_UINT16 fw_branch; 207 TW_UINT16 fw_build; 208 TW_UINT32 result; 209 }; 210 211 /* Structure for downloading firmware onto the controller. */ 212 struct tw_cl_command_download_firmware { 213 TW_UINT8 sgl_off__opcode;/* 3:5 */ 214 TW_UINT8 size; 215 TW_UINT8 request_id; 216 TW_UINT8 unit; 217 TW_UINT8 status; 218 TW_UINT8 flags; 219 TW_UINT16 param; 220 TW_UINT8 sgl[1]; 221 }; 222 223 /* Structure for hard resetting the controller. */ 224 struct tw_cl_command_reset_firmware { 225 TW_UINT8 res1__opcode; /* 3:5 */ 226 TW_UINT8 size; 227 TW_UINT8 request_id; 228 TW_UINT8 unit; 229 TW_UINT8 status; 230 TW_UINT8 flags; 231 TW_UINT8 res2; 232 TW_UINT8 param; 233 }; 234 235 /* Structure for sending get/set param commands. */ 236 struct tw_cl_command_param { 237 TW_UINT8 sgl_off__opcode;/* 3:5 */ 238 TW_UINT8 size; 239 TW_UINT8 request_id; 240 TW_UINT8 host_id__unit; /* 4:4 */ 241 TW_UINT8 status; 242 TW_UINT8 flags; 243 TW_UINT16 param_count; 244 TW_UINT8 sgl[1]; 245 }; 246 247 /* Generic command packet. */ 248 struct tw_cl_command_generic { 249 TW_UINT8 sgl_off__opcode;/* 3:5 */ 250 TW_UINT8 size; 251 TW_UINT8 request_id; 252 TW_UINT8 host_id__unit; /* 4:4 */ 253 TW_UINT8 status; 254 TW_UINT8 flags; 255 TW_UINT16 count; /* block cnt, parameter cnt, message credits */ 256 }; 257 258 /* Command packet header. */ 259 struct tw_cl_command_header { 260 TW_UINT8 sense_data[TWA_SENSE_DATA_LENGTH]; 261 struct { 262 TW_INT8 reserved[4]; 263 TW_UINT16 error; 264 TW_UINT8 padding; 265 TW_UINT8 res__severity; /* 5:3 */ 266 } status_block; 267 TW_UINT8 err_specific_desc[98]; 268 struct { 269 TW_UINT8 size_header; 270 TW_UINT16 reserved; 271 TW_UINT8 size_sense; 272 } header_desc; 273 }; 274 275 /* 7000 Command packet. */ 276 union tw_cl_command_7k { 277 struct tw_cl_command_init_connect init_connect; 278 struct tw_cl_command_download_firmware download_fw; 279 struct tw_cl_command_reset_firmware reset_fw; 280 struct tw_cl_command_param param; 281 struct tw_cl_command_generic generic; 282 TW_UINT8 padding[1024 - sizeof(struct tw_cl_command_header)]; 283 }; 284 285 /* 9000 Command Packet. */ 286 struct tw_cl_command_9k { 287 TW_UINT8 res__opcode; /* 3:5 */ 288 TW_UINT8 unit; 289 TW_UINT16 lun_l4__req_id; /* 4:12 */ 290 TW_UINT8 status; 291 TW_UINT8 sgl_offset; /* offset (in bytes) to sg_list, from the 292 end of sgl_entries */ 293 TW_UINT16 lun_h4__sgl_entries; 294 TW_UINT8 cdb[16]; 295 TW_UINT8 sg_list[872];/* total struct size = 296 1024-sizeof(cmd_hdr) */ 297 }; 298 299 /* Full command packet. */ 300 struct tw_cl_command_packet { 301 struct tw_cl_command_header cmd_hdr; 302 union { 303 union tw_cl_command_7k cmd_pkt_7k; 304 struct tw_cl_command_9k cmd_pkt_9k; 305 } command; 306 }; 307 308 /* Structure describing payload for get/set param commands. */ 309 struct tw_cl_param_9k { 310 TW_UINT16 table_id; 311 TW_UINT8 parameter_id; 312 TW_UINT8 reserved; 313 TW_UINT16 parameter_size_bytes; 314 TW_UINT16 parameter_actual_size_bytes; 315 TW_UINT8 data[1]; 316 }; 317 #pragma pack() 318 319 /* Functions to read from, and write to registers */ 320 #define TW_CLI_WRITE_CONTROL_REGISTER(ctlr_handle, value) \ 321 tw_osl_write_reg(ctlr_handle, TWA_CONTROL_REGISTER_OFFSET, value, 4) 322 323 #define TW_CLI_READ_STATUS_REGISTER(ctlr_handle) \ 324 tw_osl_read_reg(ctlr_handle, TWA_STATUS_REGISTER_OFFSET, 4) 325 326 #define TW_CLI_WRITE_COMMAND_QUEUE(ctlr_handle, value) do { \ 327 if (ctlr->flags & TW_CL_64BIT_ADDRESSES) { \ 328 /* First write the low 4 bytes, then the high 4. */ \ 329 tw_osl_write_reg(ctlr_handle, TWA_COMMAND_QUEUE_OFFSET_LOW, \ 330 (TW_UINT32)(value), 4); \ 331 tw_osl_write_reg(ctlr_handle, TWA_COMMAND_QUEUE_OFFSET_HIGH,\ 332 (TW_UINT32)(((TW_UINT64)value)>>32), 4); \ 333 } else \ 334 tw_osl_write_reg(ctlr_handle, TWA_COMMAND_QUEUE_OFFSET, \ 335 (TW_UINT32)(value), 4); \ 336 } while (0) 337 338 #define TW_CLI_READ_RESPONSE_QUEUE(ctlr_handle) \ 339 tw_osl_read_reg(ctlr_handle, TWA_RESPONSE_QUEUE_OFFSET, 4) 340 341 #define TW_CLI_READ_LARGE_RESPONSE_QUEUE(ctlr_handle) \ 342 tw_osl_read_reg(ctlr_handle, TWA_LARGE_RESPONSE_QUEUE_OFFSET, 4) 343 344 #define TW_CLI_SOFT_RESET(ctlr) \ 345 TW_CLI_WRITE_CONTROL_REGISTER(ctlr, \ 346 TWA_CONTROL_ISSUE_SOFT_RESET | \ 347 TWA_CONTROL_CLEAR_HOST_INTERRUPT | \ 348 TWA_CONTROL_CLEAR_ATTENTION_INTERRUPT | \ 349 TWA_CONTROL_MASK_COMMAND_INTERRUPT | \ 350 TWA_CONTROL_MASK_RESPONSE_INTERRUPT | \ 351 TWA_CONTROL_DISABLE_INTERRUPTS) 352 353 /* Detect inconsistencies in the status register. */ 354 #define TW_CLI_STATUS_ERRORS(x) \ 355 ((x & TWA_STATUS_UNEXPECTED_BITS) && \ 356 (x & TWA_STATUS_MICROCONTROLLER_READY)) 357 358 /* 359 * Functions for making transparent, the bit fields in firmware 360 * interface structures. 361 */ 362 #define BUILD_SGL_OFF__OPCODE(sgl_off, opcode) \ 363 ((sgl_off << 5) & 0xE0) | (opcode & 0x1F) /* 3:5 */ 364 365 #define BUILD_RES__OPCODE(res, opcode) \ 366 ((res << 5) & 0xE0) | (opcode & 0x1F) /* 3:5 */ 367 368 #define BUILD_HOST_ID__UNIT(host_id, unit) \ 369 ((host_id << 4) & 0xF0) | (unit & 0xF) /* 4:4 */ 370 371 #define BUILD_RES__SEVERITY(res, severity) \ 372 ((res << 3) & 0xF8) | (severity & 0x7) /* 5:3 */ 373 374 #define BUILD_LUN_L4__REQ_ID(lun, req_id) \ 375 (((lun << 12) & 0xF000) | (req_id & 0xFFF)) /* 4:12 */ 376 377 #define BUILD_LUN_H4__SGL_ENTRIES(lun, sgl_entries) \ 378 (((lun << 8) & 0xF000) | (sgl_entries & 0xFFF)) /* 4:12 */ 379 380 #define GET_OPCODE(sgl_off__opcode) \ 381 (sgl_off__opcode & 0x1F) /* 3:5 */ 382 383 #define GET_SGL_OFF(sgl_off__opcode) \ 384 ((sgl_off__opcode >> 5) & 0x7) /* 3:5 */ 385 386 #define GET_UNIT(host_id__unit) \ 387 (host_id__unit & 0xF) /* 4:4 */ 388 389 #define GET_HOST_ID(host_id__unit) \ 390 ((host_id__unit >> 4) & 0xF) /* 4:4 */ 391 392 #define GET_SEVERITY(res__severity) \ 393 (res__severity & 0x7) /* 5:3 */ 394 395 #define GET_RESP_ID(undef2__resp_id__undef1) \ 396 ((undef2__resp_id__undef1 >> 4) & 0xFF) /* 20:8:4 */ 397 398 #define GET_RESP_ID_9K_X(undef2__resp_id) \ 399 ((undef2__resp_id) & 0xFFF) /* 20:12 */ 400 401 #define GET_LARGE_RESP_ID(misc__large_resp_id) \ 402 ((misc__large_resp_id) & 0xFFFF) /* 16:16 */ 403 404 #define GET_REQ_ID(lun_l4__req_id) \ 405 (lun_l4__req_id & 0xFFF) /* 4:12 */ 406 407 #define GET_LUN_L4(lun_l4__req_id) \ 408 ((lun_l4__req_id >> 12) & 0xF) /* 4:12 */ 409 410 #define GET_SGL_ENTRIES(lun_h4__sgl_entries) \ 411 (lun_h4__sgl_entries & 0xFFF) /* 4:12 */ 412 413 #define GET_LUN_H4(lun_h4__sgl_entries) \ 414 ((lun_h4__sgl_entries >> 12) & 0xF) /* 4:12 */ 415 416 #endif /* TW_CL_FWIF_H */ 417