1 /* $OpenBSD: vaddrs.h,v 1.6 2003/04/23 19:34:07 miod Exp $ */ 2 /* $NetBSD: vaddrs.h,v 1.8 1997/03/10 23:54:41 pk Exp $ */ 3 4 /* 5 * Copyright (c) 1996 6 * The President and Fellows of Harvard College. All rights reserved. 7 * Copyright (c) 1992, 1993 8 * The Regents of the University of California. All rights reserved. 9 * 10 * This software was developed by the Computer Systems Engineering group 11 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 12 * contributed to Berkeley. 13 * 14 * All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Lawrence Berkeley Laboratory. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions 21 * are met: 22 * 1. Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * 2. Redistributions in binary form must reproduce the above copyright 25 * notice, this list of conditions and the following disclaimer in the 26 * documentation and/or other materials provided with the distribution. 27 * 3. All advertising materials mentioning features or use of this software 28 * must display the following acknowledgement: 29 * This product includes software developed by the University of 30 * California, Berkeley and its contributors. 31 * This product includes software developed by Harvard University. 32 * 4. Neither the name of the University nor the names of its contributors 33 * may be used to endorse or promote products derived from this software 34 * without specific prior written permission. 35 * 36 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 37 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 38 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 39 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 40 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 41 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 42 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 43 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 44 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 45 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 46 * SUCH DAMAGE. 47 * 48 * @(#)vaddrs.h 8.1 (Berkeley) 6/11/93 49 */ 50 51 /* 52 * Special (fixed) virtual addresses on the SPARC. 53 * 54 * IO virtual space begins at 0xfe000000 (a segment boundary) and 55 * continues up to the DVMA edge at 0xff000000. (The upper all-1s 56 * byte is special since some of the hardware supplies this to pad 57 * a 24-bit address space out to 32 bits. This is a legacy of the 58 * IBM PC AT bus, actually, just so you know who to blame.) 59 * 60 * We reserve several pages at the base of our IO virtual space 61 * for `oft-used' devices which must be present anyway in order to 62 * configure. In particular, we want the counter-timer register and 63 * the Zilog ZSCC serial port chips to be mapped at fixed VAs to make 64 * microtime() and the zs hardware interrupt handlers faster. 65 * 66 * [sun4/sun4c:] 67 * Ideally, we should map the interrupt enable register here as well, 68 * but that would require allocating pmegs in locore.s, so instead we 69 * use one of the two `wasted' pages at KERNBASE+_MAXNBPG (see locore.s). 70 */ 71 72 #ifndef IODEV_0 73 #define IODEV_0 0xfe000000 /* must match VM_MAX_KERNEL_ADDRESS */ 74 75 #define _MAXNBPG 8192 /* fixed VAs, independent of actual NBPG */ 76 #define _MAXNCPU 4 /* fixed VA allocation allows 4 CPUs */ 77 78 /* [4m:] interrupt and counter registers take (1 + NCPU) pages. */ 79 80 #define TIMERREG_VA (IODEV_0) 81 #define COUNTERREG_VA ( TIMERREG_VA + _MAXNBPG*_MAXNCPU) /* [4m] */ 82 #define ZS0_VA (COUNTERREG_VA + _MAXNBPG) 83 #define ZS1_VA ( ZS0_VA + _MAXNBPG) 84 #define AUXREG_VA ( ZS1_VA + _MAXNBPG) 85 #define TMPMAP_VA ( AUXREG_VA + _MAXNBPG) 86 #define MSGBUF_VA ( TMPMAP_VA + _MAXNBPG) 87 #define INTRREG_VA ( MSGBUF_VA + _MAXNBPG) /* [4/4c] */ 88 #define PI_INTR_VA ( MSGBUF_VA + _MAXNBPG) /* [4m] */ 89 #define SI_INTR_VA ( PI_INTR_VA + _MAXNBPG*_MAXNCPU) /* [4m] */ 90 #define IODEV_BASE ( SI_INTR_VA + _MAXNBPG) 91 #define IODEV_END 0xff000000 /* 16 MB of iospace */ 92 93 #define DVMA_BASE 0xfff00000 94 #define DVMA_END 0xfffc0000 95 96 /* 97 * The next constant defines the amount of reserved DVMA space on the 98 * Sun4m. The amount of space *must* be a multiple of 16MB, and thus 99 * (((u_int)0) - DVMA4M_BASE) must be divisible by 16*1024*1024! 100 * Note that pagetables must be allocated at a cost of 1k per MB of DVMA 101 * space, plus severe alignment restrictions. So don't make DVMA4M_BASE too 102 * low (max space = 2G). 103 * 104 * Since DVMA space overlaps with normal kernel address space (notably 105 * the device mappings and the PROM), we don't want to put any DVMA 106 * mappings where any of this useful stuff is (i.e. if we dvma_malloc 107 * a buffer, we want to still have a SRMMU mapping to it, and we can't 108 * have that if its on top of kernel code). Thus the last two 109 * constants define the actual DVMA addresses used. These can be anything 110 * as long as they are within the bounds setup by the first 2 constants. 111 * This is especially important on MP systems with cache coherency: to 112 * avoid consistency problems, DVMA addresses must map to the same place 113 * in both processor and IOMMU space. 114 */ 115 #define DVMA4M_BASE 0xfc000000 /* can change subject to above rule */ 116 #define DVMA4M_END 0xfffff000 /* XXX is this enough? */ 117 #define DVMA_D24_BASE 0xff000000 118 #define DVMA_D24_END 0xfffff000 119 120 #define M_SPACE_D24 0x0001 121 122 /* 123 * Virtual address of the per cpu `cpu_softc' structure. 124 */ 125 #define CPUINFO_VA (KERNBASE+8192) 126 127 #endif /* IODEV_0 */ 128