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Searched defs:SubRC (Results 1 – 12 of 12) sorted by relevance

/openbsd/src/gnu/llvm/llvm/lib/CodeGen/
DRegisterBank.cpp46 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify() local
DTargetRegisterInfo.cpp201 const TargetRegisterClass *SubRC = getRegClass(It.getID()); in getAllocatableClass() local
/openbsd/src/gnu/llvm/llvm/utils/TableGen/
DCodeGenRegisters.cpp990 CodeGenRegisterClass &SubRC = *I2; in computeSubClasses() local
2276 CodeGenRegisterClass *SubRC = in inferSubClassWithSubReg() local
2321 CodeGenRegisterClass &SubRC = *I; in inferMatchingSuperRegClass() local
DCompressInstEmitter.cpp172 const CodeGenRegisterClass &SubRC = Target.getRegisterClass(DagOpType); in validateTypes() local
DCodeGenRegisters.h400 CodeGenRegisterClass *SubRC) { in setSubClassWithSubReg()
/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DSIFoldOperands.cpp873 if (const TargetRegisterClass *SubRC = in foldOperand() local
DSIRegisterInfo.cpp2817 const TargetRegisterClass *SubRC, in getCompatibleSubRegClass()
DAMDGPUInstructionSelector.cpp238 const TargetRegisterClass &SubRC, in getSubOperand64()
DSIInstrInfo.cpp4225 const TargetRegisterClass *SubRC = in verifyInstruction() local
DSIISelLowering.cpp4197 const TargetRegisterClass *SubRC = in EmitInstrWithCustomInserter() local
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
DUtils.cpp125 if (const auto *SubRC = TRI.getCommonSubClass( in constrainOperandRegClass() local
/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp5996 const TargetRegisterClass *SubRC; in genAlternativeCodeSequence() local