| /trueos/contrib/llvm/lib/Target/ARM/ |
| HD | Thumb2RegisterInfo.cpp | 37 unsigned DestReg, unsigned SubIdx, in emitLoadConstPool()
|
| HD | ARMBaseRegisterInfo.cpp | 394 unsigned DestReg, unsigned SubIdx, int Val, in emitLoadConstPool()
|
| HD | Thumb1RegisterInfo.cpp | 67 unsigned DestReg, unsigned SubIdx, in emitLoadConstPool()
|
| HD | ARMBaseInstrInfo.cpp | 773 unsigned SubIdx, unsigned State, in AddDReg()
1279 unsigned DestReg, unsigned SubIdx, in reMaterialize()
|
| /trueos/contrib/llvm/include/llvm/Target/ |
| HD | TargetRegisterInfo.h | 336 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName()
361 unsigned getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask()
457 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg()
881 unsigned SubIdx; variable
|
| HD | TargetInstrInfo.h | 115 unsigned &SubIdx) const { in isCoalescableExtInstr()
|
| /trueos/contrib/llvm/lib/MC/ |
| HD | MCRegisterInfo.cpp | 18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg()
|
| /trueos/contrib/llvm/lib/CodeGen/ |
| HD | ExpandPostRAPseudos.cpp | 88 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
|
| HD | MachineCopyPropagation.cpp | 120 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def); in isNopCopy() local
|
| HD | TargetInstrInfo.cpp | 281 unsigned SubIdx, unsigned &Size, in getStackSlotRange()
313 unsigned SubIdx, in reMaterialize()
|
| HD | MachineRegisterInfo.cpp | 85 if (unsigned SubIdx = I.getOperand().getSubReg()) { in recomputeRegClass() local
|
| HD | RegisterCoalescer.cpp | 942 unsigned SubIdx) { in updateRegDefsUses()
1283 unsigned SubIdx; member in __anon3fd7f4430211::JoinVals
1769 bool JoinVals::usesLanes(MachineInstr *MI, unsigned Reg, unsigned SubIdx, in usesLanes()
|
| HD | PeepholeOptimizer.cpp | 160 unsigned SrcReg, DstReg, SubIdx; in INITIALIZE_PASS_DEPENDENCY() local
|
| HD | TwoAddressInstructionPass.cpp | 1571 unsigned SubIdx = mi->getOperand(3).getImm(); in runOnMachineFunction() local
1627 unsigned SubIdx = MI->getOperand(i+1).getImm(); in eliminateRegSequence() local
|
| HD | MachineInstr.cpp | 69 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, in substVirtReg()
1204 unsigned SubIdx, in substituteRegister()
|
| HD | MachineVerifier.cpp | 896 unsigned SubIdx = MO->getSubReg(); in visitMachineOperand() local
|
| /trueos/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| HD | InstrEmitter.cpp | 439 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, in ConstrainForSubReg()
490 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); in EmitSubregNode() local
531 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); in EmitSubregNode() local
623 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue(); in EmitRegSequence() local
|
| /trueos/contrib/llvm/utils/TableGen/ |
| HD | CodeGenRegisters.h | 317 getSubClassWithSubReg(CodeGenSubRegIndex *SubIdx) const { in getSubClassWithSubReg()
321 void setSubClassWithSubReg(CodeGenSubRegIndex *SubIdx, in setSubClassWithSubReg()
331 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, in addSuperRegClass()
|
| HD | CodeGenRegisters.cpp | 480 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second); in computeSecondarySubRegs() local
900 CodeGenRegisterClass::getSuperRegClasses(CodeGenSubRegIndex *SubIdx, in getSuperRegClasses()
1496 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size(); in pruneUnitSets() local
1808 CodeGenSubRegIndex *SubIdx = SubRegIndices[sri]; in inferSubClassWithSubReg() local
1841 CodeGenSubRegIndex *SubIdx = SubRegIndices[sri]; in inferMatchingSuperRegClass() local
|
| HD | AsmMatcherEmitter.cpp | 1660 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second; in buildAliasResultOperands() local
|
| /trueos/contrib/llvm/lib/Target/PowerPC/ |
| HD | PPCInstrInfo.cpp | 497 unsigned SubIdx; in insertSelect() local
1168 unsigned SubIdx = UseMI->getOperand(3).getSubReg(); in optimizeCompareInstr() local
|
| /trueos/contrib/llvm/lib/Target/R600/ |
| HD | SIInstrInfo.cpp | 163 while (unsigned SubIdx = *SubIndices++) { in copyPhysReg() local
|
| HD | SIISelLowering.cpp | 1012 int SubIdx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); in getRegClassForNode() local
|
| /trueos/contrib/llvm/lib/Target/Mips/ |
| HD | MipsSEInstrInfo.cpp | 505 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo; in expandExtractElementF64() local
|
| /trueos/contrib/llvm/lib/Target/X86/ |
| HD | X86InstrInfo.cpp | 1797 unsigned DestReg, unsigned SubIdx, in reMaterialize()
|