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Searched defs:SubIdx (Results 1 – 25 of 42) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
HDDetectDeadLanes.cpp158 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferUsedLanes() local
162 unsigned SubIdx = MI.getOperand(3).getImm(); in transferUsedLanes() local
182 unsigned SubIdx = MI.getOperand(2).getImm(); in transferUsedLanes() local
232 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferDefinedLanes() local
238 unsigned SubIdx = MI.getOperand(3).getImm(); in transferDefinedLanes() local
250 unsigned SubIdx = MI.getOperand(2).getImm(); in transferDefinedLanes() local
HDExpandPostRAPseudos.cpp69 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
HDLiveRangeEdit.cpp186 bool Late, unsigned SubIdx, in rematerializeAt()
HDRegisterCoalescer.cpp1817 unsigned SubIdx) { in updateRegDefsUses()
2415 const unsigned SubIdx; member in __anone30f0a030311::JoinVals
2589 JoinVals(LiveRange &LR, Register Reg, unsigned SubIdx, LaneBitmask LaneMask, in JoinVals()
3110 bool JoinVals::usesLanes(const MachineInstr &MI, Register Reg, unsigned SubIdx, in usesLanes()
HDTwoAddressInstructionPass.cpp1920 unsigned SubIdx = mi->getOperand(3).getImm(); in run() local
2006 unsigned SubIdx = MI.getOperand(i+1).getImm(); in eliminateRegSequence() local
HDTargetRegisterInfo.cpp109 unsigned SubIdx, const MachineRegisterInfo *MRI) { in printReg()
HDTargetInstrInfo.cpp389 unsigned SubIdx, unsigned &Size, in getStackSlotRange()
420 Register DestReg, unsigned SubIdx, in reMaterialize()
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDThumbRegisterInfo.cpp64 unsigned SubIdx, int Val, in emitThumb1LoadConstPool()
84 unsigned SubIdx, int Val, in emitThumb2LoadConstPool()
105 const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, in emitLoadConstPool()
HDARMBaseRegisterInfo.cpp498 const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, in emitLoadConstPool()
/freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/
HDGlobalISelEmitter.cpp1311 CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(ChildRec); in importExplicitUseRenderer() local
1445 auto SubIdx = inferSubRegIndexForNode(Dst.getChild(1)); in createAndImportSubInstructionRenderer() local
1490 auto SubIdx = inferSubRegIndexForNode(SubRegChild); in createAndImportSubInstructionRenderer() local
1587 CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef()); in importExplicitUseRenderers() local
1654 CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef()); in importExplicitUseRenderers() local
1879 CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef()); in inferSuperRegisterClass() local
2135 auto SubIdx = inferSubRegIndexForNode(Dst.getChild(1)); in runOnPattern() local
2205 auto SubIdx = inferSubRegIndexForNode(SubRegChild); in runOnPattern() local
HDRegisterBankEmitter.cpp203 for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) { in visitRegisterBankClasses() local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86TileConfig.cpp183 unsigned SubIdx = IsRow ? X86::sub_8bit : X86::sub_16bit; in INITIALIZE_PASS_DEPENDENCY() local
/freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/Common/
HDCodeGenRegisters.h407 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const { in getSubClassWithSubReg()
425 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx, in setSubClassWithSubReg()
436 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, in addSuperRegClass()
HDCodeGenRegisters.cpp139 CodeGenSubRegIndex *SubIdx = *I; in computeConcatTransitiveClosure() local
547 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SubReg.second); in computeSecondarySubRegs() local
1142 void CodeGenRegisterClass::getSuperRegClasses(const CodeGenSubRegIndex *SubIdx, in getSuperRegClasses()
1965 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size(); SubIdx != EndIdx; in pruneUnitSets() local
2313 for (const auto &SubIdx : SubRegIndices) { in inferSubClassWithSubReg() local
2347 for (auto &SubIdx : SubRegIndices) { in inferMatchingSuperRegClass() local
HDCodeGenTarget.cpp181 const CodeGenSubRegIndex *SubIdx, bool MustBeAllocatable) const { in getSuperRegForSubReg() argument
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
HDInstrEmitter.cpp476 Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx, in ConstrainForSubReg()
525 unsigned SubIdx = Node->getConstantOperandVal(1); in EmitSubregNode() local
581 unsigned SubIdx = N2->getAsZExtVal(); in EmitSubregNode() local
680 unsigned SubIdx = Op->getAsZExtVal(); in EmitRegSequence() local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/MC/
HDMCRegisterInfo.cpp108 MCRegisterInfo::getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg()
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/GISel/
HDX86InstructionSelector.cpp218 unsigned SubIdx = X86::NoSubRegister; in getSubRegIndex() local
826 unsigned SubIdx; in selectTruncOrPtrToInt() local
1286 unsigned SubIdx = X86::NoSubRegister; in emitExtractSubreg() local
1324 unsigned SubIdx = X86::NoSubRegister; in emitInsertSubreg() local
HDX86LegalizerInfo.cpp516 unsigned SubIdx = Query.Opcode == G_EXTRACT ? 0 : 1; in X86LegalizerInfo() local
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
HDTargetRegisterInfo.h388 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName()
408 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask()
640 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg()
HDTargetInstrInfo.h265 Register &DstReg, unsigned &SubIdx) const { in isCoalescableExtInstr()
522 unsigned SubIdx; member
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
HDMipsSEInstrInfo.cpp761 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo; in expandExtractElementF64() local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SPIRV/
HDSPIRVPrepareFunctions.cpp224 for (std::size_t SubIdx = 1; SubIdx < MatchStr.size(); ++SubIdx) in parseAnnotation() local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonISelLoweringHVX.cpp744 SDValue SubIdx = DAG.getNode(ISD::AND, dl, MVT::i32, {Idx, Mask}); in getIndexInWord32() local
1168 SDValue SubIdx = getIndexInWord32(IdxV, ElemTy, DAG); in extractHvxElementReg() local
1229 SDValue SubIdx = getIndexInWord32(IdxV, ElemTy, DAG); in insertHvxElementReg() local
1385 unsigned SubIdx = (Idx == 0) ? Hexagon::vsub_lo : Hexagon::vsub_hi; in insertHvxSubvectorReg() local
1594 HexagonTargetLowering::extractSubvector(SDValue Vec, MVT SubTy, unsigned SubIdx, in extractSubvector()
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/M68k/
HDM68kInstrInfo.cpp769 unsigned SubIdx, unsigned &Size, in getStackSlotRange()

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