| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| HD | MachineIRBuilder.h | 130 SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {} in SrcOp() function
131 SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {} in SrcOp() function
132 SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {} in SrcOp() function
133 SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {} in SrcOp() function
139 SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {} in SrcOp() function
140 SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {} in SrcOp() function
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| HD | LegalizationArtifactCombiner.h | 300 unsigned SrcOp = SrcDef->getOpcode(); in tryCombineMerges() local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| HD | HexagonRDFOpt.cpp | 139 const MachineOperand &SrcOp = MI->getOperand(1); in INITIALIZE_PASS_DEPENDENCY() local
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| HD | HexagonExpandCondsets.cpp | 623 MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp, in genCondTfrFor()
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| HD | HexagonFrameLowering.cpp | 2305 MachineOperand &SrcOp = SI.getOperand(2); in optimizeSpillSlots() local
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| HD | HexagonInstrInfo.cpp | 1098 const MachineOperand &SrcOp = MI.getOperand(2); in expandPostRAPseudo() local
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| HD | HexagonBitSimplify.cpp | 2535 const MachineOperand &SrcOp = MI->getOperand(1); in simplifyExtractLow() local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| HD | SILowerControlFlow.cpp | 465 for (const auto &SrcOp : Def->explicit_operands()) in findMaskOperands() local
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| HD | SIInstrInfo.cpp | 1432 const MachineOperand &SrcOp = MI.getOperand(1); in expandPostRAPseudo() local
1596 const MachineOperand &SrcOp = MI.getOperand(I); in expandMovDPP64() local
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| HD | SIISelLowering.cpp | 8841 SDValue SrcOp = Op.getOperand(i); in isCanonicalized() local
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| /freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
| HD | CodeGenInstruction.cpp | 284 std::pair<unsigned,unsigned> SrcOp = (FirstIsDest ? RHSOp : LHSOp); in ParseConstraint() local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| HD | MachineVerifier.cpp | 1279 const MachineOperand &SrcOp = MI->getOperand(1); in verifyPreISelGenericInstruction() local
1301 const MachineOperand &SrcOp = MI->getOperand(2); in verifyPreISelGenericInstruction() local
1529 const MachineOperand &SrcOp = MI->getOperand(1); in visitMachineInstrBefore() local
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| HD | MachineScheduler.cpp | 1689 const MachineOperand &SrcOp = Copy->getOperand(1); in constrainLocalCopy() local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Linker/ |
| HD | IRMover.cpp | 1227 MDNode *SrcOp = SrcModFlags->getOperand(I); in linkModuleFlagsMetadata() local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| HD | LegalizeDAG.cpp | 1745 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT, in EmitStackConvert()
1750 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT, in EmitStackConvert()
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| HD | SelectionDAG.cpp | 2540 SDValue SrcOp = Op.getOperand(i); in computeKnownBits() local
3537 SDValue SrcOp = Op.getOperand(i); in ComputeNumSignBits() local
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| HD | TargetLowering.cpp | 2299 SDValue SrcOp = Op.getOperand(i); in SimplifyDemandedVectorElts() local
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| HD | DAGCombiner.cpp | 18519 SDValue SrcOp = V.getOperand(0); in visitEXTRACT_SUBVECTOR() local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| HD | InstCombineCasts.cpp | 1118 if (auto *SrcOp = dyn_cast<Instruction>(Src)) in visitZExt() local
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| HD | InstructionCombining.cpp | 2196 Value *SrcOp = BCI->getOperand(0); in visitGetElementPtrInst() local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| HD | SystemZISelLowering.cpp | 6579 SDValue SrcOp = Op.getOperand(1); in computeKnownBitsForTargetNode() local
6598 SDValue SrcOp = Op.getOperand(0); in computeKnownBitsForTargetNode() local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/ |
| HD | InstructionSimplify.cpp | 3287 Value *SrcOp = LI->getOperand(0); in SimplifyICmpInst() local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| HD | X86ISelLowering.cpp | 7925 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, unsigned NumBits, in getVShift()
7937 static SDValue LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, const SDLoc &dl, in LowerAsSplatVectorLoad()
23286 SDValue SrcOp, uint64_t ShiftAmt, in getTargetVShiftByConstNode()
23369 SDValue SrcOp, SDValue ShAmt, in getTargetVShiftNode()
33999 SDValue SrcOp = Ops[i]; in combineX86ShufflesConstants() local
35139 SDValue SrcOp = N->getOperand(0); in foldShuffleOfHorizOp() local
37079 SDValue SrcOp = SrcBC.getOperand(0); in combineExtractWithShuffle() local
37157 SDValue SrcOp = Ops[SrcIdx / Mask.size()]; in combineExtractWithShuffle() local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| HD | PPCISelLowering.cpp | 11931 MachineOperand SrcOp = MI.getOperand(1); in EmitInstrWithCustomInserter() local
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