Searched defs:SrcLo (Results 1 – 7 of 7) sorted by relevance
| /freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
| HD | AVRInstrInfo.cpp | 56 Register DestLo, DestHi, SrcLo, SrcHi; in copyPhysReg() local
|
| HD | AVRISelLowering.cpp | 279 SDValue SrcLo = in LowerShifts() local
|
| /freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| HD | MipsSEInstrInfo.cpp | 709 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2); in expandPseudoMTLoHi() local
|
| /freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| HD | HexagonInstrInfo.cpp | 924 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in copyPhysReg() local
1141 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in expandPostRAPseudo() local
1411 Register SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo); in expandPostRAPseudo() local
1423 Register SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo); in expandPostRAPseudo() local
|
| HD | HexagonFrameLowering.cpp | 1899 Register SrcLo = HRI.getSubReg(SrcR, Hexagon::vsub_lo); in expandStoreVec2() local
|
| /freebsd-14-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| HD | LegalizeVectorTypes.cpp | 3006 SDValue SrcLo, SrcHi; in SplitVecRes_FP_TO_XINT_SAT() local
|
| /freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| HD | AArch64ISelLowering.cpp | 4809 SDValue SrcLo = DAG.getNode(ISD::AND, DL, MVT::i64, SrcVal, in LowerINT_TO_FP() local
|