Searched defs:SrcHi (Results 1 – 8 of 8) sorted by relevance
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
| HD | AVRInstrInfo.cpp | 56 Register DestLo, DestHi, SrcLo, SrcHi; in copyPhysReg() local
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| HD | AVRISelLowering.cpp | 282 SDValue SrcHi = in LowerShifts() local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| HD | MipsSEInstrInfo.cpp | 709 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2); in expandPseudoMTLoHi() local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| HD | HexagonInstrInfo.cpp | 925 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in copyPhysReg() local
1142 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in expandPostRAPseudo() local
1412 Register SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi); in expandPostRAPseudo() local
1424 Register SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi); in expandPostRAPseudo() local
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| HD | HexagonFrameLowering.cpp | 1900 Register SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi); in expandStoreVec2() local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| HD | LegalizeVectorTypes.cpp | 3006 SDValue SrcLo, SrcHi; in SplitVecRes_FP_TO_XINT_SAT() local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| HD | SIISelLowering.cpp | 8708 SDValue SrcHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, SrcVec, in LowerINTRINSIC_WO_CHAIN() local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| HD | AArch64ISelLowering.cpp | 4807 SDValue SrcHi = DAG.getNode(ISD::AND, DL, MVT::i64, SrcVal, in LowerINT_TO_FP() local
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