1 /* $NetBSD: rgmiireg.h,v 1.1 2010/03/18 13:47:04 kiyohara Exp $ */ 2 /* 3 * Copyright (c) 2010 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef _IBM4XX_RGMIIREG_H_ 29 #define _IBM4XX_RGMIIREG_H_ 30 31 /* RGMII (reduced GMII) Bridge (405EX/440GX(EMAC 2, 3)) */ 32 33 #define RGMII0_SIZE 0x8 34 35 #define RGMII0_FER 0x0 /* Function Enable Register */ 36 #define FER_MDIOEN_MASK 0x000c0000 /* MDIO enable */ 37 #define FER_MDIOEN(emac) (1 << ((1 - ((emac) % 2)) + 18)) 38 #define FER_CHCFG_MASK 0x7 /* EMAC n Mask */ 39 #define FER_CHCFG_RTBI 0x4 /* RTBI enabled */ 40 #define FER_CHCFG_RGMII 0x5 /* RGMII enabled */ 41 #define FER_CHCFG_TBI 0x6 /* TBI enabled */ 42 #define FER_CHCFG_GMII 0x7 /* GMII enabled */ 43 #define FER_CHCFG(rgmii, val) ((val) << ((rgmii) << 2)) 44 #define RGMII0_SSR 0x4 /* Speed Select Register */ 45 #define SSR_SP_MASK 0x7 46 #define SSR_SP_10MBPS 0x0 47 #define SSR_SP_100MBPS 0x2 48 #define SSR_SP_1000MBPS 0x4 49 #define SSR_SP(emac, sp) ((sp) << (((emac) % 2) << 3)) 50 51 #endif /* _IBM4XX_RGMIIREG_H_ */ 52