1 /* $NetBSD: spr.h,v 1.56 2022/05/07 09:02:19 rin Exp $ */
2
3 /*
4 * Copyright (c) 2001, The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #ifndef _POWERPC_SPR_H_
29 #define _POWERPC_SPR_H_
30
31 #if !defined(_LOCORE) && defined(_KERNEL)
32
33 #ifdef _KERNEL_OPT
34 #include "opt_ppcarch.h"
35 #endif
36
37 #include <powerpc/oea/cpufeat.h>
38
39 #if defined(PPC_OEA64_BRIDGE) || defined (_ARCH_PPC64)
40 static __inline uint64_t
mfspr64(int reg)41 mfspr64(int reg)
42 {
43 uint64_t ret;
44 register_t hi, l;
45
46 __asm volatile( "mfspr %0,%2;"
47 "srdi %1,%0,32;"
48 : "=r"(l), "=r"(hi) : "K"(reg));
49 ret = ((uint64_t)hi << 32) | l;
50 return ret;
51 }
52
53 /* This as an inline breaks as 'reg' ends up not being an immediate */
54 #define mtspr64(reg, v) \
55 ( { \
56 volatile register_t hi, l; \
57 \
58 uint64_t val = v; \
59 hi = (val >> 32); \
60 l = val & 0xffffffff; \
61 __asm volatile( "sldi %2,%2,32;" \
62 "or %2,%2,%1;" \
63 "sync;" \
64 "mtspr %0,%2;" \
65 "mfspr %2,%0;" \
66 "mfspr %2,%0;" \
67 "mfspr %2,%0;" \
68 "mfspr %2,%0;" \
69 "mfspr %2,%0;" \
70 "mfspr %2,%0;" \
71 : : "K"(reg), "r"(l), "r"(hi)); \
72 } )
73 #endif /* PPC_OEA64_BRIDGE || _ARCH_PPC64 */
74
75 static __inline __always_inline uint64_t
mfspr32(const int reg)76 mfspr32(const int reg)
77 {
78 register_t val;
79
80 __asm volatile("mfspr %0,%1" : "=r"(val) : "K"(reg));
81 return val;
82 }
83
84 static __inline __always_inline void
mtspr32(const int reg,uint32_t val)85 mtspr32(const int reg, uint32_t val)
86 {
87
88 __asm volatile("mtspr %0,%1" : : "K"(reg), "r"(val));
89 }
90
91 #if (defined(PPC_OEA) + defined(PPC_OEA64) + defined(PPC_OEA64_BRIDGE)) > 1
92 static __inline uint64_t
mfspr(int reg)93 mfspr(int reg)
94 {
95 if ((oeacpufeat & (OEACPU_64_BRIDGE|OEACPU_64)) != 0)
96 return mfspr64(reg);
97 return mfspr32(reg);
98 }
99
100 /* This as an inline breaks as 'reg' ends up not being an immediate */
101 #define mtspr(reg, val) \
102 ( { \
103 if ((oeacpufeat & (OEACPU_64_BRIDGE|OEACPU_64)) != 0) \
104 mtspr64(reg, (uint64_t)val); \
105 else \
106 mtspr32(reg, val); \
107 } )
108 #else /* PPC_OEA + PPC_OEA64 + PPC_OEA64_BRIDGE != 1 */
109
110 #if defined(PPC_OEA64) || defined(PPC_OEA64_BRIDGE)
111 #define mfspr(r) mfspr64(r)
112 #define mtspr(r,v) mtspr64(r,v)
113 #else
114 #define mfspr(r) mfspr32(r)
115 #define mtspr(r,v) mtspr32(r,v)
116 #endif
117
118 #endif /* PPC_OEA + PPC_OEA64 + PPC_OEA64_BRIDGE > 1 */
119
120 #endif /* !_LOCORE && _KERNEL */
121
122 /*
123 * Special Purpose Register declarations.
124 *
125 * The first column in the comments indicates which PowerPC architectures the
126 * SPR is valid on - E for BookE series, 4 for 4xx series,
127 * 6 for 6xx/7xx series and 8 for 8xx and 8xxx (but not 85xx) series.
128 */
129
130 #define SPR_XER 0x001 /* E468 Fixed Point Exception Register */
131 #define SPR_LR 0x008 /* E468 Link Register */
132 #define SPR_CTR 0x009 /* E468 Count Register */
133 #define SPR_DEC 0x016 /* E468 DECrementer register */
134 #define SPR_SRR0 0x01a /* E468 Save/Restore Register 0 */
135 #define SPR_SRR1 0x01b /* E468 Save/Restore Register 1 */
136 #define SPR_SPRG0 0x110 /* E468 SPR General 0 */
137 #define SPR_SPRG1 0x111 /* E468 SPR General 1 */
138 #define SPR_SPRG2 0x112 /* E468 SPR General 2 */
139 #define SPR_SPRG3 0x113 /* E468 SPR General 3 */
140 #define SPR_SPRG4 0x114 /* E4.. SPR General 4 */
141 #define SPR_SPRG5 0x115 /* E4.. SPR General 5 */
142 #define SPR_SPRG6 0x116 /* E4.. SPR General 6 */
143 #define SPR_SPRG7 0x117 /* E4.. SPR General 7 */
144 #define SPR_TBL 0x11c /* E468 Time Base Lower */
145 #define SPR_TBU 0x11d /* E468 Time Base Upper */
146 #define SPR_PVR 0x11f /* E468 Processor Version Register */
147
148 /* Time Base Register declarations */
149 #define TBR_TBL 0x10c /* E468 Time Base Lower */
150 #define TBR_TBU 0x10d /* E468 Time Base Upper */
151
152 #endif /* !_POWERPC_SPR_H_ */
153