1 /* $NetBSD: auspireg.h,v 1.1 2006/10/02 08:00:07 gdamore Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Urbana-Champaign Independent Media Center. 5 * Copyright (c) 2006 Garrett D'Amore. 6 * All rights reserved. 7 * 8 * Portions of this code were written by Garrett D'Amore for the 9 * Champaign-Urbana Community Wireless Network Project. 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer in the documentation and/or other materials provided 19 * with the distribution. 20 * 3. All advertising materials mentioning features or use of this 21 * software must display the following acknowledgements: 22 * This product includes software developed by the Urbana-Champaign 23 * Independent Media Center. 24 * This product includes software developed by Garrett D'Amore. 25 * 4. Urbana-Champaign Independent Media Center's name and Garrett 26 * D'Amore's name may not be used to endorse or promote products 27 * derived from this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT 30 * MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR 31 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 32 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT 34 * MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT, 35 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 36 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 37 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 38 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 40 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 41 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 */ 43 44 #ifndef _MIPS_ALCHEMY_AUSPIREG_H_ 45 #define _MIPS_ALCHEMY_AUSPIREG_H_ 46 47 #define SPICFG_RT_8 (0x3 << 30) 48 #define SPICFG_RT_4 (0x2 << 30) 49 #define SPICFG_RT_2 (0x1 << 30) 50 #define SPICFG_RT_1 (0x0 << 30) 51 #define SPICFG_TT_8 (0x3 << 28) 52 #define SPICFG_TT_4 (0x2 << 28) 53 #define SPICFG_TT_2 (0x1 << 28) 54 #define SPICFG_TT_1 (0x0 << 28) 55 #define SPICFG_DD (1 << 27) /* disable DMA */ 56 #define SPICFG_DE (1 << 26) /* device enable */ 57 #define SPICFG_BRG_MASK (0x3f << 15) /* baud rate generator */ 58 #define SPICFG_BRG_SHIFT 15 59 #define SPICFG_DIV_MASK (0x3 << 13) /* psc clock divider */ 60 #define SPICFG_DIV_SHIFT 13 61 #define SPICFG_BI (1 << 12) /* bit clock invert */ 62 #define SPICFG_PSE (1 << 11) /* port swap enable */ 63 #define SPICFG_CGE (1 << 10) /* clock gate enable */ 64 #define SPICFG_CDE (1 << 9) /* clock phase delay enable */ 65 #define SPICFG_LEN_MASK (0x1f << 4) /* data length */ 66 #define SPICFG_LEN_SHIFT 4 67 #define SPICFG_LB (1 << 3) /* loopback mode */ 68 #define SPICFG_MLF (1 << 2) /* msb/lsb data first */ 69 #define SPICFG_MO (1 << 0) /* master only mode */ 70 71 /* and also SPIEVNT */ 72 #define SPIMSK_MM (1 << 16) /* multiple master error */ 73 #define SPIMSK_RR (1 << 13) /* rx fifo request */ 74 #define SPIMSK_RO (1 << 12) /* rx fifo overflow */ 75 #define SPIMSK_RU (1 << 11) /* rx fifo underflow */ 76 #define SPIMSK_TR (1 << 10) /* tx fifo request */ 77 #define SPIMSK_TO (1 << 9) /* tx fifo overflow */ 78 #define SPIMSK_TU (1 << 8) /* tx fifo underflow */ 79 #define SPIMSK_SD (1 << 5) /* slave done */ 80 #define SPIMSK_MD (1 << 4) /* master done */ 81 #define SPIMSK_ALL (SPIMSK_MM | SPIMSK_RR | SPIMSK_RO | \ 82 SPIMSK_RU | SPIMSK_TR | SPIMSK_TO | \ 83 SPIMSK_TU | SPIMSK_SD | SPIMSK_MD) 84 #define SPIMSK_NORM (SPIMSK_RU | SPIMSK_TO | SPIMSK_TR | SPIMSK_SD) 85 86 #define SPIPCR_RC (1 << 6) /* rx data clear */ 87 #define SPIPCR_SP (1 << 5) /* slave stop */ 88 #define SPIPCR_SS (1 << 4) /* slave start */ 89 #define SPIPCR_TC (1 << 2) /* tx data clear */ 90 #define SPIPCR_MS (1 << 0) /* master start*/ 91 92 #define SPISTAT_RF (1 << 13) /* rx fifo full */ 93 #define SPISTAT_RE (1 << 12) /* rx fifo empty */ 94 #define SPISTAT_RR (1 << 11) /* rx request */ 95 #define SPISTAT_TF (1 << 10) /* tx fifo full */ 96 #define SPISTAT_TE (1 << 9) /* tx fifo empty */ 97 #define SPISTAT_TR (1 << 8) /* tx request */ 98 #define SPISTAT_SB (1 << 5) /* slave busy */ 99 #define SPISTAT_MB (1 << 4) /* master busy */ 100 #define SPISTAT_DI (1 << 2) /* device interrupt */ 101 #define SPISTAT_DR (1 << 1) /* device ready */ 102 #define SPISTAT_SR (1 << 0) /* psc ready */ 103 104 #define SPITXRX_LC (1 << 29) /* last character */ 105 #define SPITXRX_ST (1 << 28) /* select togle */ 106 #define SPITXRX_DATA_MASK (0xffffff) 107 #define SPITXRX_DATA_SHIFT 0 108 109 #endif /* _MIPS_ALCHEMY_AUSPIREG_H_ */ 110