1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #ifndef SI_H 25 #define SI_H 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #define TAHITI_RB_BITMAP_WIDTH_PER_SH 2 31 32 #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 33 #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 34 35 #define CG_MULT_THERMAL_STATUS 0x714 36 #define ASIC_MAX_TEMP(x) ((x) << 0) 37 #define ASIC_MAX_TEMP_MASK 0x000001ff 38 #define ASIC_MAX_TEMP_SHIFT 0 39 #define CTF_TEMP(x) ((x) << 9) 40 #define CTF_TEMP_MASK 0x0003fe00 41 #define CTF_TEMP_SHIFT 9 42 43 #define SI_MAX_SH_GPRS 256 44 #define SI_MAX_TEMP_GPRS 16 45 #define SI_MAX_SH_THREADS 256 46 #define SI_MAX_SH_STACK_ENTRIES 4096 47 #define SI_MAX_FRC_EOV_CNT 16384 48 #define SI_MAX_BACKENDS 8 49 #define SI_MAX_BACKENDS_MASK 0xFF 50 #define SI_MAX_BACKENDS_PER_SE_MASK 0x0F 51 #define SI_MAX_SIMDS 12 52 #define SI_MAX_SIMDS_MASK 0x0FFF 53 #define SI_MAX_SIMDS_PER_SE_MASK 0x00FF 54 #define SI_MAX_PIPES 8 55 #define SI_MAX_PIPES_MASK 0xFF 56 #define SI_MAX_PIPES_PER_SIMD_MASK 0x3F 57 #define SI_MAX_LDS_NUM 0xFFFF 58 #define SI_MAX_TCC 16 59 #define SI_MAX_TCC_MASK 0xFFFF 60 61 #define VGA_HDP_CONTROL 0x328 62 #define VGA_MEMORY_DISABLE (1 << 4) 63 64 #define DMIF_ADDR_CONFIG 0xBD4 65 66 #define DMIF_ADDR_CALC 0xC00 67 68 #define SRBM_STATUS 0xE50 69 70 #define SRBM_SOFT_RESET 0x0E60 71 #define SOFT_RESET_BIF (1 << 1) 72 #define SOFT_RESET_DC (1 << 5) 73 #define SOFT_RESET_DMA1 (1 << 6) 74 #define SOFT_RESET_GRBM (1 << 8) 75 #define SOFT_RESET_HDP (1 << 9) 76 #define SOFT_RESET_IH (1 << 10) 77 #define SOFT_RESET_MC (1 << 11) 78 #define SOFT_RESET_ROM (1 << 14) 79 #define SOFT_RESET_SEM (1 << 15) 80 #define SOFT_RESET_VMC (1 << 17) 81 #define SOFT_RESET_DMA (1 << 20) 82 #define SOFT_RESET_TST (1 << 21) 83 #define SOFT_RESET_REGBB (1 << 22) 84 #define SOFT_RESET_ORB (1 << 23) 85 86 #define CC_SYS_RB_BACKEND_DISABLE 0xe80 87 #define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84 88 89 #define VM_L2_CNTL 0x1400 90 #define ENABLE_L2_CACHE (1 << 0) 91 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 92 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) 93 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) 94 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 95 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 96 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) 97 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) 98 #define VM_L2_CNTL2 0x1404 99 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 100 #define INVALIDATE_L2_CACHE (1 << 1) 101 #define INVALIDATE_CACHE_MODE(x) ((x) << 26) 102 #define INVALIDATE_PTE_AND_PDE_CACHES 0 103 #define INVALIDATE_ONLY_PTE_CACHES 1 104 #define INVALIDATE_ONLY_PDE_CACHES 2 105 #define VM_L2_CNTL3 0x1408 106 #define BANK_SELECT(x) ((x) << 0) 107 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) 108 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 109 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 110 #define VM_L2_STATUS 0x140C 111 #define L2_BUSY (1 << 0) 112 #define VM_CONTEXT0_CNTL 0x1410 113 #define ENABLE_CONTEXT (1 << 0) 114 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 115 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 116 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 117 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 118 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 119 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 120 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 121 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 122 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 123 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 124 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 125 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 126 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 127 #define VM_CONTEXT1_CNTL 0x1414 128 #define VM_CONTEXT0_CNTL2 0x1430 129 #define VM_CONTEXT1_CNTL2 0x1434 130 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438 131 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c 132 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440 133 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444 134 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448 135 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c 136 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450 137 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454 138 139 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC 140 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC 141 142 #define VM_INVALIDATE_REQUEST 0x1478 143 #define VM_INVALIDATE_RESPONSE 0x147c 144 145 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 146 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 147 148 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 149 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540 150 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544 151 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548 152 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c 153 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550 154 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554 155 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558 156 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 157 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560 158 159 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 160 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580 161 162 #define MC_SHARED_CHMAP 0x2004 163 #define NOOFCHAN_SHIFT 12 164 #define NOOFCHAN_MASK 0x0000f000 165 #define MC_SHARED_CHREMAP 0x2008 166 167 #define MC_VM_FB_LOCATION 0x2024 168 #define MC_VM_AGP_TOP 0x2028 169 #define MC_VM_AGP_BOT 0x202C 170 #define MC_VM_AGP_BASE 0x2030 171 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 172 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 173 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 174 175 #define MC_VM_MX_L1_TLB_CNTL 0x2064 176 #define ENABLE_L1_TLB (1 << 0) 177 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 178 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 179 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 180 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 181 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 182 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 183 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 184 185 #define MC_SHARED_BLACKOUT_CNTL 0x20ac 186 187 #define MC_ARB_RAMCFG 0x2760 188 #define NOOFBANK_SHIFT 0 189 #define NOOFBANK_MASK 0x00000003 190 #define NOOFRANK_SHIFT 2 191 #define NOOFRANK_MASK 0x00000004 192 #define NOOFROWS_SHIFT 3 193 #define NOOFROWS_MASK 0x00000038 194 #define NOOFCOLS_SHIFT 6 195 #define NOOFCOLS_MASK 0x000000C0 196 #define CHANSIZE_SHIFT 8 197 #define CHANSIZE_MASK 0x00000100 198 #define CHANSIZE_OVERRIDE (1 << 11) 199 #define NOOFGROUPS_SHIFT 12 200 #define NOOFGROUPS_MASK 0x00001000 201 202 #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x2808 203 #define TRAIN_DONE_D0 (1 << 30) 204 #define TRAIN_DONE_D1 (1U << 31) 205 206 #define MC_SEQ_SUP_CNTL 0x28c8 207 #define RUN_MASK (1 << 0) 208 #define MC_SEQ_SUP_PGM 0x28cc 209 210 #define MC_IO_PAD_CNTL_D0 0x29d0 211 #define MEM_FALL_OUT_CMD (1 << 8) 212 213 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 214 #define MC_SEQ_IO_DEBUG_DATA 0x2a48 215 216 #define HDP_HOST_PATH_CNTL 0x2C00 217 #define HDP_NONSURFACE_BASE 0x2C04 218 #define HDP_NONSURFACE_INFO 0x2C08 219 #define HDP_NONSURFACE_SIZE 0x2C0C 220 221 #define HDP_ADDR_CONFIG 0x2F48 222 #define HDP_MISC_CNTL 0x2F4C 223 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 224 225 #define IH_RB_CNTL 0x3e00 226 # define IH_RB_ENABLE (1 << 0) 227 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 228 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 229 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 230 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 231 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 232 # define IH_WPTR_OVERFLOW_CLEAR (1U << 31) 233 #define IH_RB_BASE 0x3e04 234 #define IH_RB_RPTR 0x3e08 235 #define IH_RB_WPTR 0x3e0c 236 # define RB_OVERFLOW (1 << 0) 237 # define WPTR_OFFSET_MASK 0x3fffc 238 #define IH_RB_WPTR_ADDR_HI 0x3e10 239 #define IH_RB_WPTR_ADDR_LO 0x3e14 240 #define IH_CNTL 0x3e18 241 # define ENABLE_INTR (1 << 0) 242 # define IH_MC_SWAP(x) ((x) << 1) 243 # define IH_MC_SWAP_NONE 0 244 # define IH_MC_SWAP_16BIT 1 245 # define IH_MC_SWAP_32BIT 2 246 # define IH_MC_SWAP_64BIT 3 247 # define RPTR_REARM (1 << 4) 248 # define MC_WRREQ_CREDIT(x) ((x) << 15) 249 # define MC_WR_CLEAN_CNT(x) ((x) << 20) 250 # define MC_VMID(x) ((x) << 25) 251 252 #define CONFIG_MEMSIZE 0x5428 253 254 #define INTERRUPT_CNTL 0x5468 255 # define IH_DUMMY_RD_OVERRIDE (1 << 0) 256 # define IH_DUMMY_RD_EN (1 << 1) 257 # define IH_REQ_NONSNOOP_EN (1 << 3) 258 # define GEN_IH_INT_EN (1 << 8) 259 #define INTERRUPT_CNTL2 0x546c 260 261 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 262 263 #define BIF_FB_EN 0x5490 264 #define FB_READ_EN (1 << 0) 265 #define FB_WRITE_EN (1 << 1) 266 267 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 268 269 #define DC_LB_MEMORY_SPLIT 0x6b0c 270 #define DC_LB_MEMORY_CONFIG(x) ((x) << 20) 271 272 #define PRIORITY_A_CNT 0x6b18 273 #define PRIORITY_MARK_MASK 0x7fff 274 #define PRIORITY_OFF (1 << 16) 275 #define PRIORITY_ALWAYS_ON (1 << 20) 276 #define PRIORITY_B_CNT 0x6b1c 277 278 #define DPG_PIPE_ARBITRATION_CONTROL3 0x6cc8 279 # define LATENCY_WATERMARK_MASK(x) ((x) << 16) 280 #define DPG_PIPE_LATENCY_CONTROL 0x6ccc 281 # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 282 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 283 284 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ 285 #define VLINE_STATUS 0x6bb8 286 # define VLINE_OCCURRED (1 << 0) 287 # define VLINE_ACK (1 << 4) 288 # define VLINE_STAT (1 << 12) 289 # define VLINE_INTERRUPT (1 << 16) 290 # define VLINE_INTERRUPT_TYPE (1 << 17) 291 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ 292 #define VBLANK_STATUS 0x6bbc 293 # define VBLANK_OCCURRED (1 << 0) 294 # define VBLANK_ACK (1 << 4) 295 # define VBLANK_STAT (1 << 12) 296 # define VBLANK_INTERRUPT (1 << 16) 297 # define VBLANK_INTERRUPT_TYPE (1 << 17) 298 299 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ 300 #define INT_MASK 0x6b40 301 # define VBLANK_INT_MASK (1 << 0) 302 # define VLINE_INT_MASK (1 << 4) 303 304 #define DISP_INTERRUPT_STATUS 0x60f4 305 # define LB_D1_VLINE_INTERRUPT (1 << 2) 306 # define LB_D1_VBLANK_INTERRUPT (1 << 3) 307 # define DC_HPD1_INTERRUPT (1 << 17) 308 # define DC_HPD1_RX_INTERRUPT (1 << 18) 309 # define DACA_AUTODETECT_INTERRUPT (1 << 22) 310 # define DACB_AUTODETECT_INTERRUPT (1 << 23) 311 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 312 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 313 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 314 # define LB_D2_VLINE_INTERRUPT (1 << 2) 315 # define LB_D2_VBLANK_INTERRUPT (1 << 3) 316 # define DC_HPD2_INTERRUPT (1 << 17) 317 # define DC_HPD2_RX_INTERRUPT (1 << 18) 318 # define DISP_TIMER_INTERRUPT (1 << 24) 319 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 320 # define LB_D3_VLINE_INTERRUPT (1 << 2) 321 # define LB_D3_VBLANK_INTERRUPT (1 << 3) 322 # define DC_HPD3_INTERRUPT (1 << 17) 323 # define DC_HPD3_RX_INTERRUPT (1 << 18) 324 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 325 # define LB_D4_VLINE_INTERRUPT (1 << 2) 326 # define LB_D4_VBLANK_INTERRUPT (1 << 3) 327 # define DC_HPD4_INTERRUPT (1 << 17) 328 # define DC_HPD4_RX_INTERRUPT (1 << 18) 329 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 330 # define LB_D5_VLINE_INTERRUPT (1 << 2) 331 # define LB_D5_VBLANK_INTERRUPT (1 << 3) 332 # define DC_HPD5_INTERRUPT (1 << 17) 333 # define DC_HPD5_RX_INTERRUPT (1 << 18) 334 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 335 # define LB_D6_VLINE_INTERRUPT (1 << 2) 336 # define LB_D6_VBLANK_INTERRUPT (1 << 3) 337 # define DC_HPD6_INTERRUPT (1 << 17) 338 # define DC_HPD6_RX_INTERRUPT (1 << 18) 339 340 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ 341 #define GRPH_INT_STATUS 0x6858 342 # define GRPH_PFLIP_INT_OCCURRED (1 << 0) 343 # define GRPH_PFLIP_INT_CLEAR (1 << 8) 344 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ 345 #define GRPH_INT_CONTROL 0x685c 346 # define GRPH_PFLIP_INT_MASK (1 << 0) 347 # define GRPH_PFLIP_INT_TYPE (1 << 8) 348 349 #define DACA_AUTODETECT_INT_CONTROL 0x66c8 350 351 #define DC_HPD1_INT_STATUS 0x601c 352 #define DC_HPD2_INT_STATUS 0x6028 353 #define DC_HPD3_INT_STATUS 0x6034 354 #define DC_HPD4_INT_STATUS 0x6040 355 #define DC_HPD5_INT_STATUS 0x604c 356 #define DC_HPD6_INT_STATUS 0x6058 357 # define DC_HPDx_INT_STATUS (1 << 0) 358 # define DC_HPDx_SENSE (1 << 1) 359 # define DC_HPDx_RX_INT_STATUS (1 << 8) 360 361 #define DC_HPD1_INT_CONTROL 0x6020 362 #define DC_HPD2_INT_CONTROL 0x602c 363 #define DC_HPD3_INT_CONTROL 0x6038 364 #define DC_HPD4_INT_CONTROL 0x6044 365 #define DC_HPD5_INT_CONTROL 0x6050 366 #define DC_HPD6_INT_CONTROL 0x605c 367 # define DC_HPDx_INT_ACK (1 << 0) 368 # define DC_HPDx_INT_POLARITY (1 << 8) 369 # define DC_HPDx_INT_EN (1 << 16) 370 # define DC_HPDx_RX_INT_ACK (1 << 20) 371 # define DC_HPDx_RX_INT_EN (1 << 24) 372 373 #define DC_HPD1_CONTROL 0x6024 374 #define DC_HPD2_CONTROL 0x6030 375 #define DC_HPD3_CONTROL 0x603c 376 #define DC_HPD4_CONTROL 0x6048 377 #define DC_HPD5_CONTROL 0x6054 378 #define DC_HPD6_CONTROL 0x6060 379 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 380 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 381 # define DC_HPDx_EN (1 << 28) 382 383 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ 384 #define CRTC_STATUS_FRAME_COUNT 0x6e98 385 386 #define GRBM_CNTL 0x8000 387 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 388 389 #define GRBM_STATUS2 0x8008 390 #define RLC_RQ_PENDING (1 << 0) 391 #define RLC_BUSY (1 << 8) 392 #define TC_BUSY (1 << 9) 393 394 #define GRBM_STATUS 0x8010 395 #define CMDFIFO_AVAIL_MASK 0x0000000F 396 #define RING2_RQ_PENDING (1 << 4) 397 #define SRBM_RQ_PENDING (1 << 5) 398 #define RING1_RQ_PENDING (1 << 6) 399 #define CF_RQ_PENDING (1 << 7) 400 #define PF_RQ_PENDING (1 << 8) 401 #define GDS_DMA_RQ_PENDING (1 << 9) 402 #define GRBM_EE_BUSY (1 << 10) 403 #define DB_CLEAN (1 << 12) 404 #define CB_CLEAN (1 << 13) 405 #define TA_BUSY (1 << 14) 406 #define GDS_BUSY (1 << 15) 407 #define VGT_BUSY (1 << 17) 408 #define IA_BUSY_NO_DMA (1 << 18) 409 #define IA_BUSY (1 << 19) 410 #define SX_BUSY (1 << 20) 411 #define SPI_BUSY (1 << 22) 412 #define BCI_BUSY (1 << 23) 413 #define SC_BUSY (1 << 24) 414 #define PA_BUSY (1 << 25) 415 #define DB_BUSY (1 << 26) 416 #define CP_COHERENCY_BUSY (1 << 28) 417 #define CP_BUSY (1 << 29) 418 #define CB_BUSY (1 << 30) 419 #define GUI_ACTIVE (1U << 31) 420 #define GRBM_STATUS_SE0 0x8014 421 #define GRBM_STATUS_SE1 0x8018 422 #define SE_DB_CLEAN (1 << 1) 423 #define SE_CB_CLEAN (1 << 2) 424 #define SE_BCI_BUSY (1 << 22) 425 #define SE_VGT_BUSY (1 << 23) 426 #define SE_PA_BUSY (1 << 24) 427 #define SE_TA_BUSY (1 << 25) 428 #define SE_SX_BUSY (1 << 26) 429 #define SE_SPI_BUSY (1 << 27) 430 #define SE_SC_BUSY (1 << 29) 431 #define SE_DB_BUSY (1 << 30) 432 #define SE_CB_BUSY (1U << 31) 433 434 #define GRBM_SOFT_RESET 0x8020 435 #define SOFT_RESET_CP (1 << 0) 436 #define SOFT_RESET_CB (1 << 1) 437 #define SOFT_RESET_RLC (1 << 2) 438 #define SOFT_RESET_DB (1 << 3) 439 #define SOFT_RESET_GDS (1 << 4) 440 #define SOFT_RESET_PA (1 << 5) 441 #define SOFT_RESET_SC (1 << 6) 442 #define SOFT_RESET_BCI (1 << 7) 443 #define SOFT_RESET_SPI (1 << 8) 444 #define SOFT_RESET_SX (1 << 10) 445 #define SOFT_RESET_TC (1 << 11) 446 #define SOFT_RESET_TA (1 << 12) 447 #define SOFT_RESET_VGT (1 << 14) 448 #define SOFT_RESET_IA (1 << 15) 449 450 #define GRBM_GFX_INDEX 0x802C 451 #define INSTANCE_INDEX(x) ((x) << 0) 452 #define SH_INDEX(x) ((x) << 8) 453 #define SE_INDEX(x) ((x) << 16) 454 #define SH_BROADCAST_WRITES (1 << 29) 455 #define INSTANCE_BROADCAST_WRITES (1 << 30) 456 #define SE_BROADCAST_WRITES (1U << 31) 457 458 #define GRBM_INT_CNTL 0x8060 459 # define RDERR_INT_ENABLE (1 << 0) 460 # define GUI_IDLE_INT_ENABLE (1 << 19) 461 462 #define CP_STRMOUT_CNTL 0x84FC 463 #define SCRATCH_REG0 0x8500 464 #define SCRATCH_REG1 0x8504 465 #define SCRATCH_REG2 0x8508 466 #define SCRATCH_REG3 0x850C 467 #define SCRATCH_REG4 0x8510 468 #define SCRATCH_REG5 0x8514 469 #define SCRATCH_REG6 0x8518 470 #define SCRATCH_REG7 0x851C 471 472 #define SCRATCH_UMSK 0x8540 473 #define SCRATCH_ADDR 0x8544 474 475 #define CP_SEM_WAIT_TIMER 0x85BC 476 477 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 478 479 #define CP_ME_CNTL 0x86D8 480 #define CP_CE_HALT (1 << 24) 481 #define CP_PFP_HALT (1 << 26) 482 #define CP_ME_HALT (1 << 28) 483 484 #define CP_COHER_CNTL2 0x85E8 485 486 #define CP_RB2_RPTR 0x86f8 487 #define CP_RB1_RPTR 0x86fc 488 #define CP_RB0_RPTR 0x8700 489 #define CP_RB_WPTR_DELAY 0x8704 490 491 #define CP_QUEUE_THRESHOLDS 0x8760 492 #define ROQ_IB1_START(x) ((x) << 0) 493 #define ROQ_IB2_START(x) ((x) << 8) 494 #define CP_MEQ_THRESHOLDS 0x8764 495 #define MEQ1_START(x) ((x) << 0) 496 #define MEQ2_START(x) ((x) << 8) 497 498 #define CP_PERFMON_CNTL 0x87FC 499 500 #define VGT_VTX_VECT_EJECT_REG 0x88B0 501 502 #define VGT_CACHE_INVALIDATION 0x88C4 503 #define CACHE_INVALIDATION(x) ((x) << 0) 504 #define VC_ONLY 0 505 #define TC_ONLY 1 506 #define VC_AND_TC 2 507 #define AUTO_INVLD_EN(x) ((x) << 6) 508 #define NO_AUTO 0 509 #define ES_AUTO 1 510 #define GS_AUTO 2 511 #define ES_AND_GS_AUTO 3 512 #define VGT_ESGS_RING_SIZE 0x88C8 513 #define VGT_GSVS_RING_SIZE 0x88CC 514 515 #define VGT_GS_VERTEX_REUSE 0x88D4 516 517 #define VGT_PRIMITIVE_TYPE 0x8958 518 #define VGT_INDEX_TYPE 0x895C 519 520 #define VGT_NUM_INDICES 0x8970 521 #define VGT_NUM_INSTANCES 0x8974 522 523 #define VGT_TF_RING_SIZE 0x8988 524 525 #define VGT_HS_OFFCHIP_PARAM 0x89B0 526 527 #define VGT_TF_MEMORY_BASE 0x89B8 528 529 #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc 530 #define INACTIVE_CUS_MASK 0xFFFF0000 531 #define INACTIVE_CUS_SHIFT 16 532 #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 533 534 #define PA_CL_ENHANCE 0x8A14 535 #define CLIP_VTX_REORDER_ENA (1 << 0) 536 #define NUM_CLIP_SEQ(x) ((x) << 1) 537 538 #define PA_SU_LINE_STIPPLE_VALUE 0x8A60 539 540 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 541 542 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 543 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 544 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 545 546 #define PA_SC_FIFO_SIZE 0x8BCC 547 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) 548 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) 549 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) 550 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) 551 552 #define PA_SC_ENHANCE 0x8BF0 553 554 #define SQ_CONFIG 0x8C00 555 556 #define SQC_CACHES 0x8C08 557 558 #define SX_DEBUG_1 0x9060 559 560 #define SPI_STATIC_THREAD_MGMT_1 0x90E0 561 #define SPI_STATIC_THREAD_MGMT_2 0x90E4 562 #define SPI_STATIC_THREAD_MGMT_3 0x90E8 563 #define SPI_PS_MAX_WAVE_ID 0x90EC 564 565 #define SPI_CONFIG_CNTL 0x9100 566 567 #define SPI_CONFIG_CNTL_1 0x913C 568 #define VTX_DONE_DELAY(x) ((x) << 0) 569 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 570 571 #define CGTS_TCC_DISABLE 0x9148 572 #define CGTS_USER_TCC_DISABLE 0x914C 573 #define TCC_DISABLE_MASK 0xFFFF0000 574 #define TCC_DISABLE_SHIFT 16 575 576 #define TA_CNTL_AUX 0x9508 577 578 #define CC_RB_BACKEND_DISABLE 0x98F4 579 #define BACKEND_DISABLE(x) ((x) << 16) 580 #define GB_ADDR_CONFIG 0x98F8 581 #define NUM_PIPES(x) ((x) << 0) 582 #define NUM_PIPES_MASK 0x00000007 583 #define NUM_PIPES_SHIFT 0 584 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 585 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 586 #define PIPE_INTERLEAVE_SIZE_SHIFT 4 587 #define NUM_SHADER_ENGINES(x) ((x) << 12) 588 #define NUM_SHADER_ENGINES_MASK 0x00003000 589 #define NUM_SHADER_ENGINES_SHIFT 12 590 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 591 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 592 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 593 #define NUM_GPUS(x) ((x) << 20) 594 #define NUM_GPUS_MASK 0x00700000 595 #define NUM_GPUS_SHIFT 20 596 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 597 #define MULTI_GPU_TILE_SIZE_MASK 0x03000000 598 #define MULTI_GPU_TILE_SIZE_SHIFT 24 599 #define ROW_SIZE(x) ((x) << 28) 600 #define ROW_SIZE_MASK 0x30000000 601 #define ROW_SIZE_SHIFT 28 602 603 #define GB_TILE_MODE0 0x9910 604 # define MICRO_TILE_MODE(x) ((x) << 0) 605 # define ADDR_SURF_DISPLAY_MICRO_TILING 0 606 # define ADDR_SURF_THIN_MICRO_TILING 1 607 # define ADDR_SURF_DEPTH_MICRO_TILING 2 608 # define ARRAY_MODE(x) ((x) << 2) 609 # define ARRAY_LINEAR_GENERAL 0 610 # define ARRAY_LINEAR_ALIGNED 1 611 # define ARRAY_1D_TILED_THIN1 2 612 # define ARRAY_2D_TILED_THIN1 4 613 # define PIPE_CONFIG(x) ((x) << 6) 614 # define ADDR_SURF_P2 0 615 # define ADDR_SURF_P4_8x16 4 616 # define ADDR_SURF_P4_16x16 5 617 # define ADDR_SURF_P4_16x32 6 618 # define ADDR_SURF_P4_32x32 7 619 # define ADDR_SURF_P8_16x16_8x16 8 620 # define ADDR_SURF_P8_16x32_8x16 9 621 # define ADDR_SURF_P8_32x32_8x16 10 622 # define ADDR_SURF_P8_16x32_16x16 11 623 # define ADDR_SURF_P8_32x32_16x16 12 624 # define ADDR_SURF_P8_32x32_16x32 13 625 # define ADDR_SURF_P8_32x64_32x32 14 626 # define TILE_SPLIT(x) ((x) << 11) 627 # define ADDR_SURF_TILE_SPLIT_64B 0 628 # define ADDR_SURF_TILE_SPLIT_128B 1 629 # define ADDR_SURF_TILE_SPLIT_256B 2 630 # define ADDR_SURF_TILE_SPLIT_512B 3 631 # define ADDR_SURF_TILE_SPLIT_1KB 4 632 # define ADDR_SURF_TILE_SPLIT_2KB 5 633 # define ADDR_SURF_TILE_SPLIT_4KB 6 634 # define BANK_WIDTH(x) ((x) << 14) 635 # define ADDR_SURF_BANK_WIDTH_1 0 636 # define ADDR_SURF_BANK_WIDTH_2 1 637 # define ADDR_SURF_BANK_WIDTH_4 2 638 # define ADDR_SURF_BANK_WIDTH_8 3 639 # define BANK_HEIGHT(x) ((x) << 16) 640 # define ADDR_SURF_BANK_HEIGHT_1 0 641 # define ADDR_SURF_BANK_HEIGHT_2 1 642 # define ADDR_SURF_BANK_HEIGHT_4 2 643 # define ADDR_SURF_BANK_HEIGHT_8 3 644 # define MACRO_TILE_ASPECT(x) ((x) << 18) 645 # define ADDR_SURF_MACRO_ASPECT_1 0 646 # define ADDR_SURF_MACRO_ASPECT_2 1 647 # define ADDR_SURF_MACRO_ASPECT_4 2 648 # define ADDR_SURF_MACRO_ASPECT_8 3 649 # define NUM_BANKS(x) ((x) << 20) 650 # define ADDR_SURF_2_BANK 0 651 # define ADDR_SURF_4_BANK 1 652 # define ADDR_SURF_8_BANK 2 653 # define ADDR_SURF_16_BANK 3 654 655 #define CB_PERFCOUNTER0_SELECT0 0x9a20 656 #define CB_PERFCOUNTER0_SELECT1 0x9a24 657 #define CB_PERFCOUNTER1_SELECT0 0x9a28 658 #define CB_PERFCOUNTER1_SELECT1 0x9a2c 659 #define CB_PERFCOUNTER2_SELECT0 0x9a30 660 #define CB_PERFCOUNTER2_SELECT1 0x9a34 661 #define CB_PERFCOUNTER3_SELECT0 0x9a38 662 #define CB_PERFCOUNTER3_SELECT1 0x9a3c 663 664 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 665 #define BACKEND_DISABLE_MASK 0x00FF0000 666 #define BACKEND_DISABLE_SHIFT 16 667 668 #define TCP_CHAN_STEER_LO 0xac0c 669 #define TCP_CHAN_STEER_HI 0xac10 670 671 #define CP_RB0_BASE 0xC100 672 #define CP_RB0_CNTL 0xC104 673 #define RB_BUFSZ(x) ((x) << 0) 674 #define RB_BLKSZ(x) ((x) << 8) 675 #define BUF_SWAP_32BIT (2 << 16) 676 #define RB_NO_UPDATE (1 << 27) 677 #define RB_RPTR_WR_ENA (1U << 31) 678 679 #define CP_RB0_RPTR_ADDR 0xC10C 680 #define CP_RB0_RPTR_ADDR_HI 0xC110 681 #define CP_RB0_WPTR 0xC114 682 683 #define CP_PFP_UCODE_ADDR 0xC150 684 #define CP_PFP_UCODE_DATA 0xC154 685 #define CP_ME_RAM_RADDR 0xC158 686 #define CP_ME_RAM_WADDR 0xC15C 687 #define CP_ME_RAM_DATA 0xC160 688 689 #define CP_CE_UCODE_ADDR 0xC168 690 #define CP_CE_UCODE_DATA 0xC16C 691 692 #define CP_RB1_BASE 0xC180 693 #define CP_RB1_CNTL 0xC184 694 #define CP_RB1_RPTR_ADDR 0xC188 695 #define CP_RB1_RPTR_ADDR_HI 0xC18C 696 #define CP_RB1_WPTR 0xC190 697 #define CP_RB2_BASE 0xC194 698 #define CP_RB2_CNTL 0xC198 699 #define CP_RB2_RPTR_ADDR 0xC19C 700 #define CP_RB2_RPTR_ADDR_HI 0xC1A0 701 #define CP_RB2_WPTR 0xC1A4 702 #define CP_INT_CNTL_RING0 0xC1A8 703 #define CP_INT_CNTL_RING1 0xC1AC 704 #define CP_INT_CNTL_RING2 0xC1B0 705 # define CNTX_BUSY_INT_ENABLE (1 << 19) 706 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 707 # define WAIT_MEM_SEM_INT_ENABLE (1 << 21) 708 # define TIME_STAMP_INT_ENABLE (1 << 26) 709 # define CP_RINGID2_INT_ENABLE (1 << 29) 710 # define CP_RINGID1_INT_ENABLE (1 << 30) 711 # define CP_RINGID0_INT_ENABLE (1U << 31) 712 #define CP_INT_STATUS_RING0 0xC1B4 713 #define CP_INT_STATUS_RING1 0xC1B8 714 #define CP_INT_STATUS_RING2 0xC1BC 715 # define WAIT_MEM_SEM_INT_STAT (1 << 21) 716 # define TIME_STAMP_INT_STAT (1 << 26) 717 # define CP_RINGID2_INT_STAT (1 << 29) 718 # define CP_RINGID1_INT_STAT (1 << 30) 719 # define CP_RINGID0_INT_STAT (1U << 31) 720 721 #define CP_DEBUG 0xC1FC 722 723 #define RLC_CNTL 0xC300 724 # define RLC_ENABLE (1 << 0) 725 #define RLC_RL_BASE 0xC304 726 #define RLC_RL_SIZE 0xC308 727 #define RLC_LB_CNTL 0xC30C 728 #define RLC_SAVE_AND_RESTORE_BASE 0xC310 729 #define RLC_LB_CNTR_MAX 0xC314 730 #define RLC_LB_CNTR_INIT 0xC318 731 732 #define RLC_CLEAR_STATE_RESTORE_BASE 0xC320 733 734 #define RLC_UCODE_ADDR 0xC32C 735 #define RLC_UCODE_DATA 0xC330 736 737 #define RLC_GPU_CLOCK_COUNT_LSB 0xC338 738 #define RLC_GPU_CLOCK_COUNT_MSB 0xC33C 739 #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC340 740 #define RLC_MC_CNTL 0xC344 741 #define RLC_UCODE_CNTL 0xC348 742 743 #define PA_SC_RASTER_CONFIG 0x28350 744 # define RASTER_CONFIG_RB_MAP_0 0 745 # define RASTER_CONFIG_RB_MAP_1 1 746 # define RASTER_CONFIG_RB_MAP_2 2 747 # define RASTER_CONFIG_RB_MAP_3 3 748 749 #define VGT_EVENT_INITIATOR 0x28a90 750 # define SAMPLE_STREAMOUTSTATS1 (1 << 0) 751 # define SAMPLE_STREAMOUTSTATS2 (2 << 0) 752 # define SAMPLE_STREAMOUTSTATS3 (3 << 0) 753 # define CACHE_FLUSH_TS (4 << 0) 754 # define CACHE_FLUSH (6 << 0) 755 # define CS_PARTIAL_FLUSH (7 << 0) 756 # define VGT_STREAMOUT_RESET (10 << 0) 757 # define END_OF_PIPE_INCR_DE (11 << 0) 758 # define END_OF_PIPE_IB_END (12 << 0) 759 # define RST_PIX_CNT (13 << 0) 760 # define VS_PARTIAL_FLUSH (15 << 0) 761 # define PS_PARTIAL_FLUSH (16 << 0) 762 # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0) 763 # define ZPASS_DONE (21 << 0) 764 # define CACHE_FLUSH_AND_INV_EVENT (22 << 0) 765 # define PERFCOUNTER_START (23 << 0) 766 # define PERFCOUNTER_STOP (24 << 0) 767 # define PIPELINESTAT_START (25 << 0) 768 # define PIPELINESTAT_STOP (26 << 0) 769 # define PERFCOUNTER_SAMPLE (27 << 0) 770 # define SAMPLE_PIPELINESTAT (30 << 0) 771 # define SAMPLE_STREAMOUTSTATS (32 << 0) 772 # define RESET_VTX_CNT (33 << 0) 773 # define VGT_FLUSH (36 << 0) 774 # define BOTTOM_OF_PIPE_TS (40 << 0) 775 # define DB_CACHE_FLUSH_AND_INV (42 << 0) 776 # define FLUSH_AND_INV_DB_DATA_TS (43 << 0) 777 # define FLUSH_AND_INV_DB_META (44 << 0) 778 # define FLUSH_AND_INV_CB_DATA_TS (45 << 0) 779 # define FLUSH_AND_INV_CB_META (46 << 0) 780 # define CS_DONE (47 << 0) 781 # define PS_DONE (48 << 0) 782 # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0) 783 # define THREAD_TRACE_START (51 << 0) 784 # define THREAD_TRACE_STOP (52 << 0) 785 # define THREAD_TRACE_FLUSH (54 << 0) 786 # define THREAD_TRACE_FINISH (55 << 0) 787 788 /* 789 * PM4 790 */ 791 #define PACKET_TYPE0 0 792 #define PACKET_TYPE1 1 793 #define PACKET_TYPE2 2 794 #define PACKET_TYPE3 3 795 796 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 797 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 798 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 799 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 800 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 801 (((reg) >> 2) & 0xFFFF) | \ 802 ((n) & 0x3FFF) << 16) 803 #define CP_PACKET2 0x80000000 804 #define PACKET2_PAD_SHIFT 0 805 #define PACKET2_PAD_MASK (0x3fffffff << 0) 806 807 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 808 809 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 810 (((op) & 0xFF) << 8) | \ 811 ((n) & 0x3FFF) << 16) 812 813 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 814 815 /* Packet 3 types */ 816 #define PACKET3_NOP 0x10 817 #define PACKET3_SET_BASE 0x11 818 #define PACKET3_BASE_INDEX(x) ((x) << 0) 819 #define GDS_PARTITION_BASE 2 820 #define CE_PARTITION_BASE 3 821 #define PACKET3_CLEAR_STATE 0x12 822 #define PACKET3_INDEX_BUFFER_SIZE 0x13 823 #define PACKET3_DISPATCH_DIRECT 0x15 824 #define PACKET3_DISPATCH_INDIRECT 0x16 825 #define PACKET3_ALLOC_GDS 0x1B 826 #define PACKET3_WRITE_GDS_RAM 0x1C 827 #define PACKET3_ATOMIC_GDS 0x1D 828 #define PACKET3_ATOMIC 0x1E 829 #define PACKET3_OCCLUSION_QUERY 0x1F 830 #define PACKET3_SET_PREDICATION 0x20 831 #define PACKET3_REG_RMW 0x21 832 #define PACKET3_COND_EXEC 0x22 833 #define PACKET3_PRED_EXEC 0x23 834 #define PACKET3_DRAW_INDIRECT 0x24 835 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 836 #define PACKET3_INDEX_BASE 0x26 837 #define PACKET3_DRAW_INDEX_2 0x27 838 #define PACKET3_CONTEXT_CONTROL 0x28 839 #define PACKET3_INDEX_TYPE 0x2A 840 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 841 #define PACKET3_DRAW_INDEX_AUTO 0x2D 842 #define PACKET3_DRAW_INDEX_IMMD 0x2E 843 #define PACKET3_NUM_INSTANCES 0x2F 844 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 845 #define PACKET3_INDIRECT_BUFFER_CONST 0x31 846 #define PACKET3_INDIRECT_BUFFER 0x32 847 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 848 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 849 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 850 #define PACKET3_WRITE_DATA 0x37 851 #define WRITE_DATA_DST_SEL(x) ((x) << 8) 852 /* 0 - register 853 * 1 - memory (sync - via GRBM) 854 * 2 - tc/l2 855 * 3 - gds 856 * 4 - reserved 857 * 5 - memory (async - direct) 858 */ 859 #define WR_ONE_ADDR (1 << 16) 860 #define WR_CONFIRM (1 << 20) 861 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 862 /* 0 - me 863 * 1 - pfp 864 * 2 - ce 865 */ 866 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 867 #define PACKET3_MEM_SEMAPHORE 0x39 868 #define PACKET3_MPEG_INDEX 0x3A 869 #define PACKET3_COPY_DW 0x3B 870 #define PACKET3_WAIT_REG_MEM 0x3C 871 #define PACKET3_MEM_WRITE 0x3D 872 #define PACKET3_COPY_DATA 0x40 873 #define PACKET3_CP_DMA 0x41 874 /* 1. header 875 * 2. SRC_ADDR_LO or DATA [31:0] 876 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | 877 * SRC_ADDR_HI [7:0] 878 * 4. DST_ADDR_LO [31:0] 879 * 5. DST_ADDR_HI [7:0] 880 * 6. COMMAND [30:21] | BYTE_COUNT [20:0] 881 */ 882 # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) 883 /* 0 - SRC_ADDR 884 * 1 - GDS 885 */ 886 # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) 887 /* 0 - ME 888 * 1 - PFP 889 */ 890 # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) 891 /* 0 - SRC_ADDR 892 * 1 - GDS 893 * 2 - DATA 894 */ 895 # define PACKET3_CP_DMA_CP_SYNC (1U << 31) 896 /* COMMAND */ 897 # define PACKET3_CP_DMA_DIS_WC (1 << 21) 898 # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) 899 /* 0 - none 900 * 1 - 8 in 16 901 * 2 - 8 in 32 902 * 3 - 8 in 64 903 */ 904 # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) 905 /* 0 - none 906 * 1 - 8 in 16 907 * 2 - 8 in 32 908 * 3 - 8 in 64 909 */ 910 # define PACKET3_CP_DMA_CMD_SAS (1 << 26) 911 /* 0 - memory 912 * 1 - register 913 */ 914 # define PACKET3_CP_DMA_CMD_DAS (1 << 27) 915 /* 0 - memory 916 * 1 - register 917 */ 918 # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) 919 # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) 920 # define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30) 921 #define PACKET3_PFP_SYNC_ME 0x42 922 #define PACKET3_SURFACE_SYNC 0x43 923 # define PACKET3_DEST_BASE_0_ENA (1 << 0) 924 # define PACKET3_DEST_BASE_1_ENA (1 << 1) 925 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 926 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 927 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 928 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 929 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 930 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 931 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 932 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 933 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 934 # define PACKET3_DEST_BASE_2_ENA (1 << 19) 935 # define PACKET3_DEST_BASE_3_ENA (1 << 21) 936 # define PACKET3_TCL1_ACTION_ENA (1 << 22) 937 # define PACKET3_TC_ACTION_ENA (1 << 23) 938 # define PACKET3_CB_ACTION_ENA (1 << 25) 939 # define PACKET3_DB_ACTION_ENA (1 << 26) 940 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 941 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 942 #define PACKET3_ME_INITIALIZE 0x44 943 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 944 #define PACKET3_COND_WRITE 0x45 945 #define PACKET3_EVENT_WRITE 0x46 946 #define EVENT_TYPE(x) ((x) << 0) 947 #define EVENT_INDEX(x) ((x) << 8) 948 /* 0 - any non-TS event 949 * 1 - ZPASS_DONE 950 * 2 - SAMPLE_PIPELINESTAT 951 * 3 - SAMPLE_STREAMOUTSTAT* 952 * 4 - *S_PARTIAL_FLUSH 953 * 5 - EOP events 954 * 6 - EOS events 955 * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT 956 */ 957 #define INV_L2 (1 << 20) 958 /* INV TC L2 cache when EVENT_INDEX = 7 */ 959 #define PACKET3_EVENT_WRITE_EOP 0x47 960 #define DATA_SEL(x) ((x) << 29) 961 /* 0 - discard 962 * 1 - send low 32bit data 963 * 2 - send 64bit data 964 * 3 - send 64bit counter value 965 */ 966 #define INT_SEL(x) ((x) << 24) 967 /* 0 - none 968 * 1 - interrupt only (DATA_SEL = 0) 969 * 2 - interrupt when data write is confirmed 970 */ 971 #define PACKET3_EVENT_WRITE_EOS 0x48 972 #define PACKET3_PREAMBLE_CNTL 0x4A 973 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 974 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 975 #define PACKET3_ONE_REG_WRITE 0x57 976 #define PACKET3_LOAD_CONFIG_REG 0x5F 977 #define PACKET3_LOAD_CONTEXT_REG 0x60 978 #define PACKET3_LOAD_SH_REG 0x61 979 #define PACKET3_SET_CONFIG_REG 0x68 980 #define PACKET3_SET_CONFIG_REG_START 0x00008000 981 #define PACKET3_SET_CONFIG_REG_END 0x0000b000 982 #define PACKET3_SET_CONTEXT_REG 0x69 983 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 984 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 985 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 986 #define PACKET3_SET_RESOURCE_INDIRECT 0x74 987 #define PACKET3_SET_SH_REG 0x76 988 #define PACKET3_SET_SH_REG_START 0x0000b000 989 #define PACKET3_SET_SH_REG_END 0x0000c000 990 #define PACKET3_SET_SH_REG_OFFSET 0x77 991 #define PACKET3_ME_WRITE 0x7A 992 #define PACKET3_SCRATCH_RAM_WRITE 0x7D 993 #define PACKET3_SCRATCH_RAM_READ 0x7E 994 #define PACKET3_CE_WRITE 0x7F 995 #define PACKET3_LOAD_CONST_RAM 0x80 996 #define PACKET3_WRITE_CONST_RAM 0x81 997 #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82 998 #define PACKET3_DUMP_CONST_RAM 0x83 999 #define PACKET3_INCREMENT_CE_COUNTER 0x84 1000 #define PACKET3_INCREMENT_DE_COUNTER 0x85 1001 #define PACKET3_WAIT_ON_CE_COUNTER 0x86 1002 #define PACKET3_WAIT_ON_DE_COUNTER 0x87 1003 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 1004 #define PACKET3_SET_CE_DE_COUNTERS 0x89 1005 #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A 1006 #define PACKET3_SWITCH_BUFFER 0x8B 1007 1008 /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */ 1009 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ 1010 #define DMA1_REGISTER_OFFSET 0x800 /* not a register */ 1011 1012 #define DMA_RB_CNTL 0xd000 1013 # define DMA_RB_ENABLE (1 << 0) 1014 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 1015 # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 1016 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 1017 # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 1018 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 1019 #define DMA_RB_BASE 0xd004 1020 #define DMA_RB_RPTR 0xd008 1021 #define DMA_RB_WPTR 0xd00c 1022 1023 #define DMA_RB_RPTR_ADDR_HI 0xd01c 1024 #define DMA_RB_RPTR_ADDR_LO 0xd020 1025 1026 #define DMA_IB_CNTL 0xd024 1027 # define DMA_IB_ENABLE (1 << 0) 1028 # define DMA_IB_SWAP_ENABLE (1 << 4) 1029 #define DMA_IB_RPTR 0xd028 1030 #define DMA_CNTL 0xd02c 1031 # define TRAP_ENABLE (1 << 0) 1032 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 1033 # define SEM_WAIT_INT_ENABLE (1 << 2) 1034 # define DATA_SWAP_ENABLE (1 << 3) 1035 # define FENCE_SWAP_ENABLE (1 << 4) 1036 # define CTXEMPTY_INT_ENABLE (1 << 28) 1037 #define DMA_STATUS_REG 0xd034 1038 # define DMA_IDLE (1 << 0) 1039 #define DMA_TILING_CONFIG 0xd0b8 1040 1041 #define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \ 1042 (((b) & 0x1) << 26) | \ 1043 (((t) & 0x1) << 23) | \ 1044 (((s) & 0x1) << 22) | \ 1045 (((n) & 0xFFFFF) << 0)) 1046 1047 #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \ 1048 (((vmid) & 0xF) << 20) | \ 1049 (((n) & 0xFFFFF) << 0)) 1050 1051 #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \ 1052 (1 << 26) | \ 1053 (1 << 21) | \ 1054 (((n) & 0xFFFFF) << 0)) 1055 1056 /* async DMA Packet types */ 1057 #define DMA_PACKET_WRITE 0x2 1058 #define DMA_PACKET_COPY 0x3 1059 #define DMA_PACKET_INDIRECT_BUFFER 0x4 1060 #define DMA_PACKET_SEMAPHORE 0x5 1061 #define DMA_PACKET_FENCE 0x6 1062 #define DMA_PACKET_TRAP 0x7 1063 #define DMA_PACKET_SRBM_WRITE 0x9 1064 #define DMA_PACKET_CONSTANT_FILL 0xd 1065 #define DMA_PACKET_NOP 0xf 1066 1067 #endif 1068