1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include "amdgpu.h"
27 #include "amdgpu_smu.h"
28 #include "smu_v11_0.h"
29 #include "smu11_driver_if_vangogh.h"
30 #include "vangogh_ppt.h"
31 #include "smu_v11_5_ppsmc.h"
32 #include "smu_v11_5_pmfw.h"
33 #include "smu_cmn.h"
34 #include "soc15_common.h"
35 #include "asic_reg/gc/gc_10_3_0_offset.h"
36 #include "asic_reg/gc/gc_10_3_0_sh_mask.h"
37 #include <asm/processor.h>
38
39 /*
40 * DO NOT use these for err/warn/info/debug messages.
41 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
42 * They are more MGPU friendly.
43 */
44 #undef pr_err
45 #undef pr_warn
46 #undef pr_info
47 #undef pr_debug
48
49 // Registers related to GFXOFF
50 // addressBlock: smuio_smuio_SmuSmuioDec
51 // base address: 0x5a000
52 #define mmSMUIO_GFX_MISC_CNTL 0x00c5
53 #define mmSMUIO_GFX_MISC_CNTL_BASE_IDX 0
54
55 //SMUIO_GFX_MISC_CNTL
56 #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff__SHIFT 0x0
57 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1
58 #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff_MASK 0x00000001L
59 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L
60
61 #define FEATURE_MASK(feature) (1ULL << feature)
62 #define SMC_DPM_FEATURE ( \
63 FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
64 FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \
65 FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \
66 FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \
67 FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \
68 FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \
69 FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \
70 FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \
71 FEATURE_MASK(FEATURE_GFX_DPM_BIT))
72
73 static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = {
74 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
75 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 0),
76 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 0),
77 MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 0),
78 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
79 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
80 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 0),
81 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 0),
82 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
83 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
84 MSG_MAP(RlcPowerNotify, PPSMC_MSG_RlcPowerNotify, 0),
85 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 0),
86 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 0),
87 MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 0),
88 MSG_MAP(SetHardMinIspiclkByFreq, PPSMC_MSG_SetHardMinIspiclkByFreq, 0),
89 MSG_MAP(SetHardMinIspxclkByFreq, PPSMC_MSG_SetHardMinIspxclkByFreq, 0),
90 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0),
91 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0),
92 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0),
93 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
94 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 0),
95 MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 0),
96 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 0),
97 MSG_MAP(SetSoftMinFclk, PPSMC_MSG_SetSoftMinFclk, 0),
98 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 0),
99 MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 0),
100 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 0),
101 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 0),
102 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 0),
103 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 0),
104 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 0),
105 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 0),
106 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 0),
107 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 0),
108 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
109 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
110 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 0),
111 MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 0),
112 MSG_MAP(PowerUpCvip, PPSMC_MSG_PowerUpCvip, 0),
113 MSG_MAP(PowerDownCvip, PPSMC_MSG_PowerDownCvip, 0),
114 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
115 MSG_MAP(GetThermalLimit, PPSMC_MSG_GetThermalLimit, 0),
116 MSG_MAP(GetCurrentTemperature, PPSMC_MSG_GetCurrentTemperature, 0),
117 MSG_MAP(GetCurrentPower, PPSMC_MSG_GetCurrentPower, 0),
118 MSG_MAP(GetCurrentVoltage, PPSMC_MSG_GetCurrentVoltage, 0),
119 MSG_MAP(GetCurrentCurrent, PPSMC_MSG_GetCurrentCurrent, 0),
120 MSG_MAP(GetAverageCpuActivity, PPSMC_MSG_GetAverageCpuActivity, 0),
121 MSG_MAP(GetAverageGfxActivity, PPSMC_MSG_GetAverageGfxActivity, 0),
122 MSG_MAP(GetAveragePower, PPSMC_MSG_GetAveragePower, 0),
123 MSG_MAP(GetAverageTemperature, PPSMC_MSG_GetAverageTemperature, 0),
124 MSG_MAP(SetAveragePowerTimeConstant, PPSMC_MSG_SetAveragePowerTimeConstant, 0),
125 MSG_MAP(SetAverageActivityTimeConstant, PPSMC_MSG_SetAverageActivityTimeConstant, 0),
126 MSG_MAP(SetAverageTemperatureTimeConstant, PPSMC_MSG_SetAverageTemperatureTimeConstant, 0),
127 MSG_MAP(SetMitigationEndHysteresis, PPSMC_MSG_SetMitigationEndHysteresis, 0),
128 MSG_MAP(GetCurrentFreq, PPSMC_MSG_GetCurrentFreq, 0),
129 MSG_MAP(SetReducedPptLimit, PPSMC_MSG_SetReducedPptLimit, 0),
130 MSG_MAP(SetReducedThermalLimit, PPSMC_MSG_SetReducedThermalLimit, 0),
131 MSG_MAP(DramLogSetDramAddr, PPSMC_MSG_DramLogSetDramAddr, 0),
132 MSG_MAP(StartDramLogging, PPSMC_MSG_StartDramLogging, 0),
133 MSG_MAP(StopDramLogging, PPSMC_MSG_StopDramLogging, 0),
134 MSG_MAP(SetSoftMinCclk, PPSMC_MSG_SetSoftMinCclk, 0),
135 MSG_MAP(SetSoftMaxCclk, PPSMC_MSG_SetSoftMaxCclk, 0),
136 MSG_MAP(RequestActiveWgp, PPSMC_MSG_RequestActiveWgp, 0),
137 MSG_MAP(SetFastPPTLimit, PPSMC_MSG_SetFastPPTLimit, 0),
138 MSG_MAP(SetSlowPPTLimit, PPSMC_MSG_SetSlowPPTLimit, 0),
139 MSG_MAP(GetFastPPTLimit, PPSMC_MSG_GetFastPPTLimit, 0),
140 MSG_MAP(GetSlowPPTLimit, PPSMC_MSG_GetSlowPPTLimit, 0),
141 MSG_MAP(GetGfxOffStatus, PPSMC_MSG_GetGfxOffStatus, 0),
142 MSG_MAP(GetGfxOffEntryCount, PPSMC_MSG_GetGfxOffEntryCount, 0),
143 MSG_MAP(LogGfxOffResidency, PPSMC_MSG_LogGfxOffResidency, 0),
144 };
145
146 static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = {
147 FEA_MAP(PPT),
148 FEA_MAP(TDC),
149 FEA_MAP(THERMAL),
150 FEA_MAP(DS_GFXCLK),
151 FEA_MAP(DS_SOCCLK),
152 FEA_MAP(DS_LCLK),
153 FEA_MAP(DS_FCLK),
154 FEA_MAP(DS_MP1CLK),
155 FEA_MAP(DS_MP0CLK),
156 FEA_MAP(ATHUB_PG),
157 FEA_MAP(CCLK_DPM),
158 FEA_MAP(FAN_CONTROLLER),
159 FEA_MAP(ULV),
160 FEA_MAP(VCN_DPM),
161 FEA_MAP(LCLK_DPM),
162 FEA_MAP(SHUBCLK_DPM),
163 FEA_MAP(DCFCLK_DPM),
164 FEA_MAP(DS_DCFCLK),
165 FEA_MAP(S0I2),
166 FEA_MAP(SMU_LOW_POWER),
167 FEA_MAP(GFX_DEM),
168 FEA_MAP(PSI),
169 FEA_MAP(PROCHOT),
170 FEA_MAP(CPUOFF),
171 FEA_MAP(STAPM),
172 FEA_MAP(S0I3),
173 FEA_MAP(DF_CSTATES),
174 FEA_MAP(PERF_LIMIT),
175 FEA_MAP(CORE_DLDO),
176 FEA_MAP(RSMU_LOW_POWER),
177 FEA_MAP(SMN_LOW_POWER),
178 FEA_MAP(THM_LOW_POWER),
179 FEA_MAP(SMUIO_LOW_POWER),
180 FEA_MAP(MP1_LOW_POWER),
181 FEA_MAP(DS_VCN),
182 FEA_MAP(CPPC),
183 FEA_MAP(OS_CSTATES),
184 FEA_MAP(ISP_DPM),
185 FEA_MAP(A55_DPM),
186 FEA_MAP(CVIP_DSP_DPM),
187 FEA_MAP(MSMU_LOW_POWER),
188 FEA_MAP_REVERSE(SOCCLK),
189 FEA_MAP_REVERSE(FCLK),
190 FEA_MAP_HALF_REVERSE(GFX),
191 };
192
193 static struct cmn2asic_mapping vangogh_table_map[SMU_TABLE_COUNT] = {
194 TAB_MAP_VALID(WATERMARKS),
195 TAB_MAP_VALID(SMU_METRICS),
196 TAB_MAP_VALID(CUSTOM_DPM),
197 TAB_MAP_VALID(DPMCLOCKS),
198 };
199
200 static struct cmn2asic_mapping vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
201 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
202 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
203 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
204 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
205 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
206 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CAPPED, WORKLOAD_PPLIB_CAPPED_BIT),
207 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_UNCAPPED, WORKLOAD_PPLIB_UNCAPPED_BIT),
208 };
209
210 static const uint8_t vangogh_throttler_map[] = {
211 [THROTTLER_STATUS_BIT_SPL] = (SMU_THROTTLER_SPL_BIT),
212 [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT),
213 [THROTTLER_STATUS_BIT_SPPT] = (SMU_THROTTLER_SPPT_BIT),
214 [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT),
215 [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT),
216 [THROTTLER_STATUS_BIT_THM_GFX] = (SMU_THROTTLER_TEMP_GPU_BIT),
217 [THROTTLER_STATUS_BIT_THM_SOC] = (SMU_THROTTLER_TEMP_SOC_BIT),
218 [THROTTLER_STATUS_BIT_TDC_VDD] = (SMU_THROTTLER_TDC_VDD_BIT),
219 [THROTTLER_STATUS_BIT_TDC_SOC] = (SMU_THROTTLER_TDC_SOC_BIT),
220 [THROTTLER_STATUS_BIT_TDC_GFX] = (SMU_THROTTLER_TDC_GFX_BIT),
221 [THROTTLER_STATUS_BIT_TDC_CVIP] = (SMU_THROTTLER_TDC_CVIP_BIT),
222 };
223
vangogh_tables_init(struct smu_context * smu)224 static int vangogh_tables_init(struct smu_context *smu)
225 {
226 struct smu_table_context *smu_table = &smu->smu_table;
227 struct smu_table *tables = smu_table->tables;
228
229 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
230 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
231 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
232 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
233 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
234 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
235 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, sizeof(DpmActivityMonitorCoeffExt_t),
236 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
237 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, max(sizeof(SmuMetrics_t), sizeof(SmuMetrics_legacy_t)),
238 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
239
240 smu_table->metrics_table = kzalloc(max(sizeof(SmuMetrics_t), sizeof(SmuMetrics_legacy_t)), GFP_KERNEL);
241 if (!smu_table->metrics_table)
242 goto err0_out;
243 smu_table->metrics_time = 0;
244
245 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2);
246 smu_table->gpu_metrics_table_size = max(smu_table->gpu_metrics_table_size, sizeof(struct gpu_metrics_v2_3));
247 smu_table->gpu_metrics_table_size = max(smu_table->gpu_metrics_table_size, sizeof(struct gpu_metrics_v2_4));
248 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
249 if (!smu_table->gpu_metrics_table)
250 goto err1_out;
251
252 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
253 if (!smu_table->watermarks_table)
254 goto err2_out;
255
256 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
257 if (!smu_table->clocks_table)
258 goto err3_out;
259
260 return 0;
261
262 err3_out:
263 kfree(smu_table->watermarks_table);
264 err2_out:
265 kfree(smu_table->gpu_metrics_table);
266 err1_out:
267 kfree(smu_table->metrics_table);
268 err0_out:
269 return -ENOMEM;
270 }
271
vangogh_get_legacy_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)272 static int vangogh_get_legacy_smu_metrics_data(struct smu_context *smu,
273 MetricsMember_t member,
274 uint32_t *value)
275 {
276 struct smu_table_context *smu_table = &smu->smu_table;
277 SmuMetrics_legacy_t *metrics = (SmuMetrics_legacy_t *)smu_table->metrics_table;
278 int ret = 0;
279
280 ret = smu_cmn_get_metrics_table(smu,
281 NULL,
282 false);
283 if (ret)
284 return ret;
285
286 switch (member) {
287 case METRICS_CURR_GFXCLK:
288 *value = metrics->GfxclkFrequency;
289 break;
290 case METRICS_AVERAGE_SOCCLK:
291 *value = metrics->SocclkFrequency;
292 break;
293 case METRICS_AVERAGE_VCLK:
294 *value = metrics->VclkFrequency;
295 break;
296 case METRICS_AVERAGE_DCLK:
297 *value = metrics->DclkFrequency;
298 break;
299 case METRICS_CURR_UCLK:
300 *value = metrics->MemclkFrequency;
301 break;
302 case METRICS_AVERAGE_GFXACTIVITY:
303 *value = metrics->GfxActivity / 100;
304 break;
305 case METRICS_AVERAGE_VCNACTIVITY:
306 *value = metrics->UvdActivity / 100;
307 break;
308 case METRICS_AVERAGE_SOCKETPOWER:
309 *value = (metrics->CurrentSocketPower << 8) /
310 1000 ;
311 break;
312 case METRICS_TEMPERATURE_EDGE:
313 *value = metrics->GfxTemperature / 100 *
314 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
315 break;
316 case METRICS_TEMPERATURE_HOTSPOT:
317 *value = metrics->SocTemperature / 100 *
318 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
319 break;
320 case METRICS_THROTTLER_STATUS:
321 *value = metrics->ThrottlerStatus;
322 break;
323 case METRICS_VOLTAGE_VDDGFX:
324 *value = metrics->Voltage[2];
325 break;
326 case METRICS_VOLTAGE_VDDSOC:
327 *value = metrics->Voltage[1];
328 break;
329 case METRICS_AVERAGE_CPUCLK:
330 memcpy(value, &metrics->CoreFrequency[0],
331 smu->cpu_core_num * sizeof(uint16_t));
332 break;
333 default:
334 *value = UINT_MAX;
335 break;
336 }
337
338 return ret;
339 }
340
vangogh_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)341 static int vangogh_get_smu_metrics_data(struct smu_context *smu,
342 MetricsMember_t member,
343 uint32_t *value)
344 {
345 struct smu_table_context *smu_table = &smu->smu_table;
346 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
347 int ret = 0;
348
349 ret = smu_cmn_get_metrics_table(smu,
350 NULL,
351 false);
352 if (ret)
353 return ret;
354
355 switch (member) {
356 case METRICS_CURR_GFXCLK:
357 *value = metrics->Current.GfxclkFrequency;
358 break;
359 case METRICS_AVERAGE_SOCCLK:
360 *value = metrics->Current.SocclkFrequency;
361 break;
362 case METRICS_AVERAGE_VCLK:
363 *value = metrics->Current.VclkFrequency;
364 break;
365 case METRICS_AVERAGE_DCLK:
366 *value = metrics->Current.DclkFrequency;
367 break;
368 case METRICS_CURR_UCLK:
369 *value = metrics->Current.MemclkFrequency;
370 break;
371 case METRICS_AVERAGE_GFXACTIVITY:
372 *value = metrics->Current.GfxActivity;
373 break;
374 case METRICS_AVERAGE_VCNACTIVITY:
375 *value = metrics->Current.UvdActivity;
376 break;
377 case METRICS_AVERAGE_SOCKETPOWER:
378 *value = (metrics->Average.CurrentSocketPower << 8) /
379 1000;
380 break;
381 case METRICS_CURR_SOCKETPOWER:
382 *value = (metrics->Current.CurrentSocketPower << 8) /
383 1000;
384 break;
385 case METRICS_TEMPERATURE_EDGE:
386 *value = metrics->Current.GfxTemperature / 100 *
387 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
388 break;
389 case METRICS_TEMPERATURE_HOTSPOT:
390 *value = metrics->Current.SocTemperature / 100 *
391 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
392 break;
393 case METRICS_THROTTLER_STATUS:
394 *value = metrics->Current.ThrottlerStatus;
395 break;
396 case METRICS_VOLTAGE_VDDGFX:
397 *value = metrics->Current.Voltage[2];
398 break;
399 case METRICS_VOLTAGE_VDDSOC:
400 *value = metrics->Current.Voltage[1];
401 break;
402 case METRICS_AVERAGE_CPUCLK:
403 memcpy(value, &metrics->Current.CoreFrequency[0],
404 smu->cpu_core_num * sizeof(uint16_t));
405 break;
406 default:
407 *value = UINT_MAX;
408 break;
409 }
410
411 return ret;
412 }
413
vangogh_common_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)414 static int vangogh_common_get_smu_metrics_data(struct smu_context *smu,
415 MetricsMember_t member,
416 uint32_t *value)
417 {
418 int ret = 0;
419
420 if (smu->smc_fw_if_version < 0x3)
421 ret = vangogh_get_legacy_smu_metrics_data(smu, member, value);
422 else
423 ret = vangogh_get_smu_metrics_data(smu, member, value);
424
425 return ret;
426 }
427
vangogh_allocate_dpm_context(struct smu_context * smu)428 static int vangogh_allocate_dpm_context(struct smu_context *smu)
429 {
430 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
431
432 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
433 GFP_KERNEL);
434 if (!smu_dpm->dpm_context)
435 return -ENOMEM;
436
437 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
438
439 return 0;
440 }
441
vangogh_init_smc_tables(struct smu_context * smu)442 static int vangogh_init_smc_tables(struct smu_context *smu)
443 {
444 int ret = 0;
445
446 ret = vangogh_tables_init(smu);
447 if (ret)
448 return ret;
449
450 ret = vangogh_allocate_dpm_context(smu);
451 if (ret)
452 return ret;
453
454 #ifdef CONFIG_X86
455 /* AMD x86 APU only */
456 #ifdef __linux__
457 smu->cpu_core_num = topology_num_cores_per_package();
458 #else
459 {
460 uint32_t eax, ebx, ecx, edx;
461 CPUID_LEAF(4, 0, eax, ebx, ecx, edx);
462 smu->cpu_core_num = ((eax >> 26) & 0x3f) + 1;
463 }
464 #endif
465 #else
466 smu->cpu_core_num = 4;
467 #endif
468
469 return smu_v11_0_init_smc_tables(smu);
470 }
471
vangogh_dpm_set_vcn_enable(struct smu_context * smu,bool enable)472 static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
473 {
474 int ret = 0;
475
476 if (enable) {
477 /* vcn dpm on is a prerequisite for vcn power gate messages */
478 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
479 if (ret)
480 return ret;
481 } else {
482 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
483 if (ret)
484 return ret;
485 }
486
487 return ret;
488 }
489
vangogh_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)490 static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
491 {
492 int ret = 0;
493
494 if (enable) {
495 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
496 if (ret)
497 return ret;
498 } else {
499 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
500 if (ret)
501 return ret;
502 }
503
504 return ret;
505 }
506
vangogh_is_dpm_running(struct smu_context * smu)507 static bool vangogh_is_dpm_running(struct smu_context *smu)
508 {
509 struct amdgpu_device *adev = smu->adev;
510 int ret = 0;
511 uint64_t feature_enabled;
512
513 /* we need to re-init after suspend so return false */
514 if (adev->in_suspend)
515 return false;
516
517 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
518
519 if (ret)
520 return false;
521
522 return !!(feature_enabled & SMC_DPM_FEATURE);
523 }
524
vangogh_get_dpm_clk_limited(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t dpm_level,uint32_t * freq)525 static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
526 uint32_t dpm_level, uint32_t *freq)
527 {
528 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
529
530 if (!clk_table || clk_type >= SMU_CLK_COUNT)
531 return -EINVAL;
532
533 switch (clk_type) {
534 case SMU_SOCCLK:
535 if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
536 return -EINVAL;
537 *freq = clk_table->SocClocks[dpm_level];
538 break;
539 case SMU_VCLK:
540 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
541 return -EINVAL;
542 *freq = clk_table->VcnClocks[dpm_level].vclk;
543 break;
544 case SMU_DCLK:
545 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
546 return -EINVAL;
547 *freq = clk_table->VcnClocks[dpm_level].dclk;
548 break;
549 case SMU_UCLK:
550 case SMU_MCLK:
551 if (dpm_level >= clk_table->NumDfPstatesEnabled)
552 return -EINVAL;
553 *freq = clk_table->DfPstateTable[dpm_level].memclk;
554
555 break;
556 case SMU_FCLK:
557 if (dpm_level >= clk_table->NumDfPstatesEnabled)
558 return -EINVAL;
559 *freq = clk_table->DfPstateTable[dpm_level].fclk;
560 break;
561 default:
562 return -EINVAL;
563 }
564
565 return 0;
566 }
567
vangogh_print_legacy_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)568 static int vangogh_print_legacy_clk_levels(struct smu_context *smu,
569 enum smu_clk_type clk_type, char *buf)
570 {
571 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
572 SmuMetrics_legacy_t metrics;
573 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
574 int i, idx, size = 0, ret = 0;
575 uint32_t cur_value = 0, value = 0, count = 0;
576 bool cur_value_match_level = false;
577
578 memset(&metrics, 0, sizeof(metrics));
579
580 ret = smu_cmn_get_metrics_table(smu, &metrics, false);
581 if (ret)
582 return ret;
583
584 smu_cmn_get_sysfs_buf(&buf, &size);
585
586 switch (clk_type) {
587 case SMU_OD_SCLK:
588 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
589 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
590 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
591 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
592 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
593 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
594 }
595 break;
596 case SMU_OD_CCLK:
597 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
598 size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select);
599 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
600 (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
601 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
602 (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
603 }
604 break;
605 case SMU_OD_RANGE:
606 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
607 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
608 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
609 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
610 size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n",
611 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq);
612 }
613 break;
614 case SMU_SOCCLK:
615 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */
616 count = clk_table->NumSocClkLevelsEnabled;
617 cur_value = metrics.SocclkFrequency;
618 break;
619 case SMU_VCLK:
620 count = clk_table->VcnClkLevelsEnabled;
621 cur_value = metrics.VclkFrequency;
622 break;
623 case SMU_DCLK:
624 count = clk_table->VcnClkLevelsEnabled;
625 cur_value = metrics.DclkFrequency;
626 break;
627 case SMU_MCLK:
628 count = clk_table->NumDfPstatesEnabled;
629 cur_value = metrics.MemclkFrequency;
630 break;
631 case SMU_FCLK:
632 count = clk_table->NumDfPstatesEnabled;
633 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value);
634 if (ret)
635 return ret;
636 break;
637 default:
638 break;
639 }
640
641 switch (clk_type) {
642 case SMU_SOCCLK:
643 case SMU_VCLK:
644 case SMU_DCLK:
645 case SMU_MCLK:
646 case SMU_FCLK:
647 for (i = 0; i < count; i++) {
648 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
649 ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value);
650 if (ret)
651 return ret;
652 if (!value)
653 continue;
654 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
655 cur_value == value ? "*" : "");
656 if (cur_value == value)
657 cur_value_match_level = true;
658 }
659
660 if (!cur_value_match_level)
661 size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value);
662 break;
663 default:
664 break;
665 }
666
667 return size;
668 }
669
vangogh_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)670 static int vangogh_print_clk_levels(struct smu_context *smu,
671 enum smu_clk_type clk_type, char *buf)
672 {
673 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
674 SmuMetrics_t metrics;
675 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
676 int i, idx, size = 0, ret = 0;
677 uint32_t cur_value = 0, value = 0, count = 0;
678 bool cur_value_match_level = false;
679 uint32_t min, max;
680
681 memset(&metrics, 0, sizeof(metrics));
682
683 ret = smu_cmn_get_metrics_table(smu, &metrics, false);
684 if (ret)
685 return ret;
686
687 smu_cmn_get_sysfs_buf(&buf, &size);
688
689 switch (clk_type) {
690 case SMU_OD_SCLK:
691 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
692 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
693 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
694 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
695 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
696 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
697 }
698 break;
699 case SMU_OD_CCLK:
700 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
701 size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select);
702 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
703 (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
704 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
705 (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
706 }
707 break;
708 case SMU_OD_RANGE:
709 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
710 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
711 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
712 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
713 size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n",
714 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq);
715 }
716 break;
717 case SMU_SOCCLK:
718 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */
719 count = clk_table->NumSocClkLevelsEnabled;
720 cur_value = metrics.Current.SocclkFrequency;
721 break;
722 case SMU_VCLK:
723 count = clk_table->VcnClkLevelsEnabled;
724 cur_value = metrics.Current.VclkFrequency;
725 break;
726 case SMU_DCLK:
727 count = clk_table->VcnClkLevelsEnabled;
728 cur_value = metrics.Current.DclkFrequency;
729 break;
730 case SMU_MCLK:
731 count = clk_table->NumDfPstatesEnabled;
732 cur_value = metrics.Current.MemclkFrequency;
733 break;
734 case SMU_FCLK:
735 count = clk_table->NumDfPstatesEnabled;
736 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value);
737 if (ret)
738 return ret;
739 break;
740 case SMU_GFXCLK:
741 case SMU_SCLK:
742 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetGfxclkFrequency, 0, &cur_value);
743 if (ret) {
744 return ret;
745 }
746 break;
747 default:
748 break;
749 }
750
751 switch (clk_type) {
752 case SMU_SOCCLK:
753 case SMU_VCLK:
754 case SMU_DCLK:
755 case SMU_MCLK:
756 case SMU_FCLK:
757 for (i = 0; i < count; i++) {
758 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
759 ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value);
760 if (ret)
761 return ret;
762 if (!value)
763 continue;
764 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
765 cur_value == value ? "*" : "");
766 if (cur_value == value)
767 cur_value_match_level = true;
768 }
769
770 if (!cur_value_match_level)
771 size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value);
772 break;
773 case SMU_GFXCLK:
774 case SMU_SCLK:
775 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
776 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
777 if (cur_value == max)
778 i = 2;
779 else if (cur_value == min)
780 i = 0;
781 else
782 i = 1;
783 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
784 i == 0 ? "*" : "");
785 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
786 i == 1 ? cur_value : VANGOGH_UMD_PSTATE_STANDARD_GFXCLK,
787 i == 1 ? "*" : "");
788 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
789 i == 2 ? "*" : "");
790 break;
791 default:
792 break;
793 }
794
795 return size;
796 }
797
vangogh_common_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)798 static int vangogh_common_print_clk_levels(struct smu_context *smu,
799 enum smu_clk_type clk_type, char *buf)
800 {
801 int ret = 0;
802
803 if (smu->smc_fw_if_version < 0x3)
804 ret = vangogh_print_legacy_clk_levels(smu, clk_type, buf);
805 else
806 ret = vangogh_print_clk_levels(smu, clk_type, buf);
807
808 return ret;
809 }
810
vangogh_get_profiling_clk_mask(struct smu_context * smu,enum amd_dpm_forced_level level,uint32_t * vclk_mask,uint32_t * dclk_mask,uint32_t * mclk_mask,uint32_t * fclk_mask,uint32_t * soc_mask)811 static int vangogh_get_profiling_clk_mask(struct smu_context *smu,
812 enum amd_dpm_forced_level level,
813 uint32_t *vclk_mask,
814 uint32_t *dclk_mask,
815 uint32_t *mclk_mask,
816 uint32_t *fclk_mask,
817 uint32_t *soc_mask)
818 {
819 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
820
821 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
822 if (mclk_mask)
823 *mclk_mask = clk_table->NumDfPstatesEnabled - 1;
824
825 if (fclk_mask)
826 *fclk_mask = clk_table->NumDfPstatesEnabled - 1;
827
828 if (soc_mask)
829 *soc_mask = 0;
830 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
831 if (mclk_mask)
832 *mclk_mask = 0;
833
834 if (fclk_mask)
835 *fclk_mask = 0;
836
837 if (soc_mask)
838 *soc_mask = 1;
839
840 if (vclk_mask)
841 *vclk_mask = 1;
842
843 if (dclk_mask)
844 *dclk_mask = 1;
845 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) {
846 if (mclk_mask)
847 *mclk_mask = 0;
848
849 if (fclk_mask)
850 *fclk_mask = 0;
851
852 if (soc_mask)
853 *soc_mask = 1;
854
855 if (vclk_mask)
856 *vclk_mask = 1;
857
858 if (dclk_mask)
859 *dclk_mask = 1;
860 }
861
862 return 0;
863 }
864
vangogh_clk_dpm_is_enabled(struct smu_context * smu,enum smu_clk_type clk_type)865 static bool vangogh_clk_dpm_is_enabled(struct smu_context *smu,
866 enum smu_clk_type clk_type)
867 {
868 enum smu_feature_mask feature_id = 0;
869
870 switch (clk_type) {
871 case SMU_MCLK:
872 case SMU_UCLK:
873 case SMU_FCLK:
874 feature_id = SMU_FEATURE_DPM_FCLK_BIT;
875 break;
876 case SMU_GFXCLK:
877 case SMU_SCLK:
878 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
879 break;
880 case SMU_SOCCLK:
881 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
882 break;
883 case SMU_VCLK:
884 case SMU_DCLK:
885 feature_id = SMU_FEATURE_VCN_DPM_BIT;
886 break;
887 default:
888 return true;
889 }
890
891 if (!smu_cmn_feature_is_enabled(smu, feature_id))
892 return false;
893
894 return true;
895 }
896
vangogh_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)897 static int vangogh_get_dpm_ultimate_freq(struct smu_context *smu,
898 enum smu_clk_type clk_type,
899 uint32_t *min,
900 uint32_t *max)
901 {
902 int ret = 0;
903 uint32_t soc_mask;
904 uint32_t vclk_mask;
905 uint32_t dclk_mask;
906 uint32_t mclk_mask;
907 uint32_t fclk_mask;
908 uint32_t clock_limit;
909
910 if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) {
911 switch (clk_type) {
912 case SMU_MCLK:
913 case SMU_UCLK:
914 clock_limit = smu->smu_table.boot_values.uclk;
915 break;
916 case SMU_FCLK:
917 clock_limit = smu->smu_table.boot_values.fclk;
918 break;
919 case SMU_GFXCLK:
920 case SMU_SCLK:
921 clock_limit = smu->smu_table.boot_values.gfxclk;
922 break;
923 case SMU_SOCCLK:
924 clock_limit = smu->smu_table.boot_values.socclk;
925 break;
926 case SMU_VCLK:
927 clock_limit = smu->smu_table.boot_values.vclk;
928 break;
929 case SMU_DCLK:
930 clock_limit = smu->smu_table.boot_values.dclk;
931 break;
932 default:
933 clock_limit = 0;
934 break;
935 }
936
937 /* clock in Mhz unit */
938 if (min)
939 *min = clock_limit / 100;
940 if (max)
941 *max = clock_limit / 100;
942
943 return 0;
944 }
945 if (max) {
946 ret = vangogh_get_profiling_clk_mask(smu,
947 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
948 &vclk_mask,
949 &dclk_mask,
950 &mclk_mask,
951 &fclk_mask,
952 &soc_mask);
953 if (ret)
954 goto failed;
955
956 switch (clk_type) {
957 case SMU_UCLK:
958 case SMU_MCLK:
959 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
960 if (ret)
961 goto failed;
962 break;
963 case SMU_SOCCLK:
964 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
965 if (ret)
966 goto failed;
967 break;
968 case SMU_FCLK:
969 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, max);
970 if (ret)
971 goto failed;
972 break;
973 case SMU_VCLK:
974 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, max);
975 if (ret)
976 goto failed;
977 break;
978 case SMU_DCLK:
979 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, max);
980 if (ret)
981 goto failed;
982 break;
983 default:
984 ret = -EINVAL;
985 goto failed;
986 }
987 }
988 if (min) {
989 ret = vangogh_get_profiling_clk_mask(smu,
990 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK,
991 NULL,
992 NULL,
993 &mclk_mask,
994 &fclk_mask,
995 &soc_mask);
996 if (ret)
997 goto failed;
998
999 vclk_mask = dclk_mask = 0;
1000
1001 switch (clk_type) {
1002 case SMU_UCLK:
1003 case SMU_MCLK:
1004 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, min);
1005 if (ret)
1006 goto failed;
1007 break;
1008 case SMU_SOCCLK:
1009 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, min);
1010 if (ret)
1011 goto failed;
1012 break;
1013 case SMU_FCLK:
1014 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, min);
1015 if (ret)
1016 goto failed;
1017 break;
1018 case SMU_VCLK:
1019 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, min);
1020 if (ret)
1021 goto failed;
1022 break;
1023 case SMU_DCLK:
1024 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, min);
1025 if (ret)
1026 goto failed;
1027 break;
1028 default:
1029 ret = -EINVAL;
1030 goto failed;
1031 }
1032 }
1033 failed:
1034 return ret;
1035 }
1036
vangogh_get_power_profile_mode(struct smu_context * smu,char * buf)1037 static int vangogh_get_power_profile_mode(struct smu_context *smu,
1038 char *buf)
1039 {
1040 uint32_t i, size = 0;
1041 int16_t workload_type = 0;
1042
1043 if (!buf)
1044 return -EINVAL;
1045
1046 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) {
1047 /*
1048 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1049 * Not all profile modes are supported on vangogh.
1050 */
1051 workload_type = smu_cmn_to_asic_specific_index(smu,
1052 CMN2ASIC_MAPPING_WORKLOAD,
1053 i);
1054
1055 if (workload_type < 0)
1056 continue;
1057
1058 size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
1059 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1060 }
1061
1062 return size;
1063 }
1064
vangogh_set_power_profile_mode(struct smu_context * smu,u32 workload_mask,long * custom_params,u32 custom_params_max_idx)1065 static int vangogh_set_power_profile_mode(struct smu_context *smu,
1066 u32 workload_mask,
1067 long *custom_params,
1068 u32 custom_params_max_idx)
1069 {
1070 u32 backend_workload_mask = 0;
1071 int ret;
1072
1073 smu_cmn_get_backend_workload_mask(smu, workload_mask,
1074 &backend_workload_mask);
1075
1076 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
1077 backend_workload_mask,
1078 NULL);
1079 if (ret) {
1080 dev_err_once(smu->adev->dev, "Fail to set workload mask 0x%08x\n",
1081 workload_mask);
1082 return ret;
1083 }
1084
1085 return ret;
1086 }
1087
vangogh_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1088 static int vangogh_set_soft_freq_limited_range(struct smu_context *smu,
1089 enum smu_clk_type clk_type,
1090 uint32_t min,
1091 uint32_t max)
1092 {
1093 int ret = 0;
1094
1095 if (!vangogh_clk_dpm_is_enabled(smu, clk_type))
1096 return 0;
1097
1098 switch (clk_type) {
1099 case SMU_GFXCLK:
1100 case SMU_SCLK:
1101 ret = smu_cmn_send_smc_msg_with_param(smu,
1102 SMU_MSG_SetHardMinGfxClk,
1103 min, NULL);
1104 if (ret)
1105 return ret;
1106
1107 ret = smu_cmn_send_smc_msg_with_param(smu,
1108 SMU_MSG_SetSoftMaxGfxClk,
1109 max, NULL);
1110 if (ret)
1111 return ret;
1112 break;
1113 case SMU_FCLK:
1114 ret = smu_cmn_send_smc_msg_with_param(smu,
1115 SMU_MSG_SetHardMinFclkByFreq,
1116 min, NULL);
1117 if (ret)
1118 return ret;
1119
1120 ret = smu_cmn_send_smc_msg_with_param(smu,
1121 SMU_MSG_SetSoftMaxFclkByFreq,
1122 max, NULL);
1123 if (ret)
1124 return ret;
1125 break;
1126 case SMU_SOCCLK:
1127 ret = smu_cmn_send_smc_msg_with_param(smu,
1128 SMU_MSG_SetHardMinSocclkByFreq,
1129 min, NULL);
1130 if (ret)
1131 return ret;
1132
1133 ret = smu_cmn_send_smc_msg_with_param(smu,
1134 SMU_MSG_SetSoftMaxSocclkByFreq,
1135 max, NULL);
1136 if (ret)
1137 return ret;
1138 break;
1139 case SMU_VCLK:
1140 ret = smu_cmn_send_smc_msg_with_param(smu,
1141 SMU_MSG_SetHardMinVcn,
1142 min << 16, NULL);
1143 if (ret)
1144 return ret;
1145 ret = smu_cmn_send_smc_msg_with_param(smu,
1146 SMU_MSG_SetSoftMaxVcn,
1147 max << 16, NULL);
1148 if (ret)
1149 return ret;
1150 break;
1151 case SMU_DCLK:
1152 ret = smu_cmn_send_smc_msg_with_param(smu,
1153 SMU_MSG_SetHardMinVcn,
1154 min, NULL);
1155 if (ret)
1156 return ret;
1157 ret = smu_cmn_send_smc_msg_with_param(smu,
1158 SMU_MSG_SetSoftMaxVcn,
1159 max, NULL);
1160 if (ret)
1161 return ret;
1162 break;
1163 default:
1164 return -EINVAL;
1165 }
1166
1167 return ret;
1168 }
1169
vangogh_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1170 static int vangogh_force_clk_levels(struct smu_context *smu,
1171 enum smu_clk_type clk_type, uint32_t mask)
1172 {
1173 uint32_t soft_min_level = 0, soft_max_level = 0;
1174 uint32_t min_freq = 0, max_freq = 0;
1175 int ret = 0 ;
1176
1177 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1178 soft_max_level = mask ? (fls(mask) - 1) : 0;
1179
1180 switch (clk_type) {
1181 case SMU_SOCCLK:
1182 ret = vangogh_get_dpm_clk_limited(smu, clk_type,
1183 soft_min_level, &min_freq);
1184 if (ret)
1185 return ret;
1186 ret = vangogh_get_dpm_clk_limited(smu, clk_type,
1187 soft_max_level, &max_freq);
1188 if (ret)
1189 return ret;
1190 ret = smu_cmn_send_smc_msg_with_param(smu,
1191 SMU_MSG_SetSoftMaxSocclkByFreq,
1192 max_freq, NULL);
1193 if (ret)
1194 return ret;
1195 ret = smu_cmn_send_smc_msg_with_param(smu,
1196 SMU_MSG_SetHardMinSocclkByFreq,
1197 min_freq, NULL);
1198 if (ret)
1199 return ret;
1200 break;
1201 case SMU_FCLK:
1202 ret = vangogh_get_dpm_clk_limited(smu,
1203 clk_type, soft_min_level, &min_freq);
1204 if (ret)
1205 return ret;
1206 ret = vangogh_get_dpm_clk_limited(smu,
1207 clk_type, soft_max_level, &max_freq);
1208 if (ret)
1209 return ret;
1210 ret = smu_cmn_send_smc_msg_with_param(smu,
1211 SMU_MSG_SetSoftMaxFclkByFreq,
1212 max_freq, NULL);
1213 if (ret)
1214 return ret;
1215 ret = smu_cmn_send_smc_msg_with_param(smu,
1216 SMU_MSG_SetHardMinFclkByFreq,
1217 min_freq, NULL);
1218 if (ret)
1219 return ret;
1220 break;
1221 case SMU_VCLK:
1222 ret = vangogh_get_dpm_clk_limited(smu,
1223 clk_type, soft_min_level, &min_freq);
1224 if (ret)
1225 return ret;
1226
1227 ret = vangogh_get_dpm_clk_limited(smu,
1228 clk_type, soft_max_level, &max_freq);
1229 if (ret)
1230 return ret;
1231
1232
1233 ret = smu_cmn_send_smc_msg_with_param(smu,
1234 SMU_MSG_SetHardMinVcn,
1235 min_freq << 16, NULL);
1236 if (ret)
1237 return ret;
1238
1239 ret = smu_cmn_send_smc_msg_with_param(smu,
1240 SMU_MSG_SetSoftMaxVcn,
1241 max_freq << 16, NULL);
1242 if (ret)
1243 return ret;
1244
1245 break;
1246 case SMU_DCLK:
1247 ret = vangogh_get_dpm_clk_limited(smu,
1248 clk_type, soft_min_level, &min_freq);
1249 if (ret)
1250 return ret;
1251
1252 ret = vangogh_get_dpm_clk_limited(smu,
1253 clk_type, soft_max_level, &max_freq);
1254 if (ret)
1255 return ret;
1256
1257 ret = smu_cmn_send_smc_msg_with_param(smu,
1258 SMU_MSG_SetHardMinVcn,
1259 min_freq, NULL);
1260 if (ret)
1261 return ret;
1262
1263 ret = smu_cmn_send_smc_msg_with_param(smu,
1264 SMU_MSG_SetSoftMaxVcn,
1265 max_freq, NULL);
1266 if (ret)
1267 return ret;
1268
1269 break;
1270 default:
1271 break;
1272 }
1273
1274 return ret;
1275 }
1276
vangogh_force_dpm_limit_value(struct smu_context * smu,bool highest)1277 static int vangogh_force_dpm_limit_value(struct smu_context *smu, bool highest)
1278 {
1279 int ret = 0, i = 0;
1280 uint32_t min_freq, max_freq, force_freq;
1281 enum smu_clk_type clk_type;
1282
1283 enum smu_clk_type clks[] = {
1284 SMU_SOCCLK,
1285 SMU_VCLK,
1286 SMU_DCLK,
1287 SMU_FCLK,
1288 };
1289
1290 for (i = 0; i < ARRAY_SIZE(clks); i++) {
1291 clk_type = clks[i];
1292 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
1293 if (ret)
1294 return ret;
1295
1296 force_freq = highest ? max_freq : min_freq;
1297 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq);
1298 if (ret)
1299 return ret;
1300 }
1301
1302 return ret;
1303 }
1304
vangogh_unforce_dpm_levels(struct smu_context * smu)1305 static int vangogh_unforce_dpm_levels(struct smu_context *smu)
1306 {
1307 int ret = 0, i = 0;
1308 uint32_t min_freq, max_freq;
1309 enum smu_clk_type clk_type;
1310
1311 struct clk_feature_map {
1312 enum smu_clk_type clk_type;
1313 uint32_t feature;
1314 } clk_feature_map[] = {
1315 {SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT},
1316 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
1317 {SMU_VCLK, SMU_FEATURE_VCN_DPM_BIT},
1318 {SMU_DCLK, SMU_FEATURE_VCN_DPM_BIT},
1319 };
1320
1321 for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
1322
1323 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature))
1324 continue;
1325
1326 clk_type = clk_feature_map[i].clk_type;
1327
1328 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
1329
1330 if (ret)
1331 return ret;
1332
1333 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1334
1335 if (ret)
1336 return ret;
1337 }
1338
1339 return ret;
1340 }
1341
vangogh_set_peak_clock_by_device(struct smu_context * smu)1342 static int vangogh_set_peak_clock_by_device(struct smu_context *smu)
1343 {
1344 int ret = 0;
1345 uint32_t socclk_freq = 0, fclk_freq = 0;
1346 uint32_t vclk_freq = 0, dclk_freq = 0;
1347
1348 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_freq);
1349 if (ret)
1350 return ret;
1351
1352 ret = vangogh_set_soft_freq_limited_range(smu, SMU_FCLK, fclk_freq, fclk_freq);
1353 if (ret)
1354 return ret;
1355
1356 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_freq);
1357 if (ret)
1358 return ret;
1359
1360 ret = vangogh_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk_freq, socclk_freq);
1361 if (ret)
1362 return ret;
1363
1364 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_freq);
1365 if (ret)
1366 return ret;
1367
1368 ret = vangogh_set_soft_freq_limited_range(smu, SMU_VCLK, vclk_freq, vclk_freq);
1369 if (ret)
1370 return ret;
1371
1372 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_freq);
1373 if (ret)
1374 return ret;
1375
1376 ret = vangogh_set_soft_freq_limited_range(smu, SMU_DCLK, dclk_freq, dclk_freq);
1377 if (ret)
1378 return ret;
1379
1380 return ret;
1381 }
1382
vangogh_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1383 static int vangogh_set_performance_level(struct smu_context *smu,
1384 enum amd_dpm_forced_level level)
1385 {
1386 int ret = 0, i;
1387 uint32_t soc_mask, mclk_mask, fclk_mask;
1388 uint32_t vclk_mask = 0, dclk_mask = 0;
1389
1390 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
1391 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
1392
1393 switch (level) {
1394 case AMD_DPM_FORCED_LEVEL_HIGH:
1395 smu->gfx_actual_hard_min_freq = smu->gfx_default_soft_max_freq;
1396 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1397
1398
1399 ret = vangogh_force_dpm_limit_value(smu, true);
1400 if (ret)
1401 return ret;
1402 break;
1403 case AMD_DPM_FORCED_LEVEL_LOW:
1404 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1405 smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq;
1406
1407 ret = vangogh_force_dpm_limit_value(smu, false);
1408 if (ret)
1409 return ret;
1410 break;
1411 case AMD_DPM_FORCED_LEVEL_AUTO:
1412 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1413 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1414
1415 ret = vangogh_unforce_dpm_levels(smu);
1416 if (ret)
1417 return ret;
1418 break;
1419 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1420 smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK;
1421 smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK;
1422
1423 ret = vangogh_get_profiling_clk_mask(smu, level,
1424 &vclk_mask,
1425 &dclk_mask,
1426 &mclk_mask,
1427 &fclk_mask,
1428 &soc_mask);
1429 if (ret)
1430 return ret;
1431
1432 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
1433 vangogh_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
1434 vangogh_force_clk_levels(smu, SMU_VCLK, 1 << vclk_mask);
1435 vangogh_force_clk_levels(smu, SMU_DCLK, 1 << dclk_mask);
1436 break;
1437 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1438 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1439 smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq;
1440 break;
1441 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1442 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1443 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1444
1445 ret = vangogh_get_profiling_clk_mask(smu, level,
1446 NULL,
1447 NULL,
1448 &mclk_mask,
1449 &fclk_mask,
1450 NULL);
1451 if (ret)
1452 return ret;
1453
1454 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
1455 break;
1456 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1457 smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK;
1458 smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK;
1459
1460 ret = vangogh_set_peak_clock_by_device(smu);
1461 if (ret)
1462 return ret;
1463 break;
1464 case AMD_DPM_FORCED_LEVEL_MANUAL:
1465 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1466 default:
1467 return 0;
1468 }
1469
1470 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
1471 smu->gfx_actual_hard_min_freq, NULL);
1472 if (ret)
1473 return ret;
1474
1475 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
1476 smu->gfx_actual_soft_max_freq, NULL);
1477 if (ret)
1478 return ret;
1479
1480 if (smu->adev->pm.fw_version >= 0x43f1b00) {
1481 for (i = 0; i < smu->cpu_core_num; i++) {
1482 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
1483 ((i << 20)
1484 | smu->cpu_actual_soft_min_freq),
1485 NULL);
1486 if (ret)
1487 return ret;
1488
1489 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk,
1490 ((i << 20)
1491 | smu->cpu_actual_soft_max_freq),
1492 NULL);
1493 if (ret)
1494 return ret;
1495 }
1496 }
1497
1498 return ret;
1499 }
1500
vangogh_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1501 static int vangogh_read_sensor(struct smu_context *smu,
1502 enum amd_pp_sensors sensor,
1503 void *data, uint32_t *size)
1504 {
1505 int ret = 0;
1506
1507 if (!data || !size)
1508 return -EINVAL;
1509
1510 switch (sensor) {
1511 case AMDGPU_PP_SENSOR_GPU_LOAD:
1512 ret = vangogh_common_get_smu_metrics_data(smu,
1513 METRICS_AVERAGE_GFXACTIVITY,
1514 (uint32_t *)data);
1515 *size = 4;
1516 break;
1517 case AMDGPU_PP_SENSOR_VCN_LOAD:
1518 ret = vangogh_common_get_smu_metrics_data(smu,
1519 METRICS_AVERAGE_VCNACTIVITY,
1520 (uint32_t *)data);
1521 *size = 4;
1522 break;
1523 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1524 ret = vangogh_common_get_smu_metrics_data(smu,
1525 METRICS_AVERAGE_SOCKETPOWER,
1526 (uint32_t *)data);
1527 *size = 4;
1528 break;
1529 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1530 ret = vangogh_common_get_smu_metrics_data(smu,
1531 METRICS_CURR_SOCKETPOWER,
1532 (uint32_t *)data);
1533 *size = 4;
1534 break;
1535 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1536 ret = vangogh_common_get_smu_metrics_data(smu,
1537 METRICS_TEMPERATURE_EDGE,
1538 (uint32_t *)data);
1539 *size = 4;
1540 break;
1541 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1542 ret = vangogh_common_get_smu_metrics_data(smu,
1543 METRICS_TEMPERATURE_HOTSPOT,
1544 (uint32_t *)data);
1545 *size = 4;
1546 break;
1547 case AMDGPU_PP_SENSOR_GFX_MCLK:
1548 ret = vangogh_common_get_smu_metrics_data(smu,
1549 METRICS_CURR_UCLK,
1550 (uint32_t *)data);
1551 *(uint32_t *)data *= 100;
1552 *size = 4;
1553 break;
1554 case AMDGPU_PP_SENSOR_GFX_SCLK:
1555 ret = vangogh_common_get_smu_metrics_data(smu,
1556 METRICS_CURR_GFXCLK,
1557 (uint32_t *)data);
1558 *(uint32_t *)data *= 100;
1559 *size = 4;
1560 break;
1561 case AMDGPU_PP_SENSOR_VDDGFX:
1562 ret = vangogh_common_get_smu_metrics_data(smu,
1563 METRICS_VOLTAGE_VDDGFX,
1564 (uint32_t *)data);
1565 *size = 4;
1566 break;
1567 case AMDGPU_PP_SENSOR_VDDNB:
1568 ret = vangogh_common_get_smu_metrics_data(smu,
1569 METRICS_VOLTAGE_VDDSOC,
1570 (uint32_t *)data);
1571 *size = 4;
1572 break;
1573 case AMDGPU_PP_SENSOR_CPU_CLK:
1574 ret = vangogh_common_get_smu_metrics_data(smu,
1575 METRICS_AVERAGE_CPUCLK,
1576 (uint32_t *)data);
1577 *size = smu->cpu_core_num * sizeof(uint16_t);
1578 break;
1579 default:
1580 ret = -EOPNOTSUPP;
1581 break;
1582 }
1583
1584 return ret;
1585 }
1586
vangogh_get_apu_thermal_limit(struct smu_context * smu,uint32_t * limit)1587 static int vangogh_get_apu_thermal_limit(struct smu_context *smu, uint32_t *limit)
1588 {
1589 return smu_cmn_send_smc_msg_with_param(smu,
1590 SMU_MSG_GetThermalLimit,
1591 0, limit);
1592 }
1593
vangogh_set_apu_thermal_limit(struct smu_context * smu,uint32_t limit)1594 static int vangogh_set_apu_thermal_limit(struct smu_context *smu, uint32_t limit)
1595 {
1596 return smu_cmn_send_smc_msg_with_param(smu,
1597 SMU_MSG_SetReducedThermalLimit,
1598 limit, NULL);
1599 }
1600
1601
vangogh_set_watermarks_table(struct smu_context * smu,struct pp_smu_wm_range_sets * clock_ranges)1602 static int vangogh_set_watermarks_table(struct smu_context *smu,
1603 struct pp_smu_wm_range_sets *clock_ranges)
1604 {
1605 int i;
1606 int ret = 0;
1607 Watermarks_t *table = smu->smu_table.watermarks_table;
1608
1609 if (!table || !clock_ranges)
1610 return -EINVAL;
1611
1612 if (clock_ranges) {
1613 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1614 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1615 return -EINVAL;
1616
1617 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1618 table->WatermarkRow[WM_DCFCLK][i].MinClock =
1619 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1620 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
1621 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1622 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
1623 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1624 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
1625 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1626
1627 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
1628 clock_ranges->reader_wm_sets[i].wm_inst;
1629 }
1630
1631 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1632 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1633 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1634 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1635 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1636 table->WatermarkRow[WM_SOCCLK][i].MinMclk =
1637 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1638 table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
1639 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1640
1641 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1642 clock_ranges->writer_wm_sets[i].wm_inst;
1643 }
1644
1645 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1646 }
1647
1648 /* pass data to smu controller */
1649 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1650 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1651 ret = smu_cmn_write_watermarks_table(smu);
1652 if (ret) {
1653 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1654 return ret;
1655 }
1656 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1657 }
1658
1659 return 0;
1660 }
1661
vangogh_get_legacy_gpu_metrics_v2_3(struct smu_context * smu,void ** table)1662 static ssize_t vangogh_get_legacy_gpu_metrics_v2_3(struct smu_context *smu,
1663 void **table)
1664 {
1665 struct smu_table_context *smu_table = &smu->smu_table;
1666 struct gpu_metrics_v2_3 *gpu_metrics =
1667 (struct gpu_metrics_v2_3 *)smu_table->gpu_metrics_table;
1668 SmuMetrics_legacy_t metrics;
1669 int ret = 0;
1670
1671 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1672 if (ret)
1673 return ret;
1674
1675 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 3);
1676
1677 gpu_metrics->temperature_gfx = metrics.GfxTemperature;
1678 gpu_metrics->temperature_soc = metrics.SocTemperature;
1679 memcpy(&gpu_metrics->temperature_core[0],
1680 &metrics.CoreTemperature[0],
1681 sizeof(uint16_t) * 4);
1682 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
1683
1684 gpu_metrics->average_gfx_activity = metrics.GfxActivity;
1685 gpu_metrics->average_mm_activity = metrics.UvdActivity;
1686
1687 gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
1688 gpu_metrics->average_cpu_power = metrics.Power[0];
1689 gpu_metrics->average_soc_power = metrics.Power[1];
1690 gpu_metrics->average_gfx_power = metrics.Power[2];
1691 memcpy(&gpu_metrics->average_core_power[0],
1692 &metrics.CorePower[0],
1693 sizeof(uint16_t) * 4);
1694
1695 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
1696 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
1697 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
1698 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
1699 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
1700 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
1701
1702 memcpy(&gpu_metrics->current_coreclk[0],
1703 &metrics.CoreFrequency[0],
1704 sizeof(uint16_t) * 4);
1705 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
1706
1707 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1708 gpu_metrics->indep_throttle_status =
1709 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1710 vangogh_throttler_map);
1711
1712 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1713
1714 *table = (void *)gpu_metrics;
1715
1716 return sizeof(struct gpu_metrics_v2_3);
1717 }
1718
vangogh_get_legacy_gpu_metrics(struct smu_context * smu,void ** table)1719 static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context *smu,
1720 void **table)
1721 {
1722 struct smu_table_context *smu_table = &smu->smu_table;
1723 struct gpu_metrics_v2_2 *gpu_metrics =
1724 (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
1725 SmuMetrics_legacy_t metrics;
1726 int ret = 0;
1727
1728 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1729 if (ret)
1730 return ret;
1731
1732 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
1733
1734 gpu_metrics->temperature_gfx = metrics.GfxTemperature;
1735 gpu_metrics->temperature_soc = metrics.SocTemperature;
1736 memcpy(&gpu_metrics->temperature_core[0],
1737 &metrics.CoreTemperature[0],
1738 sizeof(uint16_t) * 4);
1739 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
1740
1741 gpu_metrics->average_gfx_activity = metrics.GfxActivity;
1742 gpu_metrics->average_mm_activity = metrics.UvdActivity;
1743
1744 gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
1745 gpu_metrics->average_cpu_power = metrics.Power[0];
1746 gpu_metrics->average_soc_power = metrics.Power[1];
1747 gpu_metrics->average_gfx_power = metrics.Power[2];
1748 memcpy(&gpu_metrics->average_core_power[0],
1749 &metrics.CorePower[0],
1750 sizeof(uint16_t) * 4);
1751
1752 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
1753 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
1754 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
1755 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
1756 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
1757 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
1758
1759 memcpy(&gpu_metrics->current_coreclk[0],
1760 &metrics.CoreFrequency[0],
1761 sizeof(uint16_t) * 4);
1762 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
1763
1764 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1765 gpu_metrics->indep_throttle_status =
1766 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1767 vangogh_throttler_map);
1768
1769 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1770
1771 *table = (void *)gpu_metrics;
1772
1773 return sizeof(struct gpu_metrics_v2_2);
1774 }
1775
vangogh_get_gpu_metrics_v2_3(struct smu_context * smu,void ** table)1776 static ssize_t vangogh_get_gpu_metrics_v2_3(struct smu_context *smu,
1777 void **table)
1778 {
1779 struct smu_table_context *smu_table = &smu->smu_table;
1780 struct gpu_metrics_v2_3 *gpu_metrics =
1781 (struct gpu_metrics_v2_3 *)smu_table->gpu_metrics_table;
1782 SmuMetrics_t metrics;
1783 int ret = 0;
1784
1785 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1786 if (ret)
1787 return ret;
1788
1789 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 3);
1790
1791 gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
1792 gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
1793 memcpy(&gpu_metrics->temperature_core[0],
1794 &metrics.Current.CoreTemperature[0],
1795 sizeof(uint16_t) * 4);
1796 gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0];
1797
1798 gpu_metrics->average_temperature_gfx = metrics.Average.GfxTemperature;
1799 gpu_metrics->average_temperature_soc = metrics.Average.SocTemperature;
1800 memcpy(&gpu_metrics->average_temperature_core[0],
1801 &metrics.Average.CoreTemperature[0],
1802 sizeof(uint16_t) * 4);
1803 gpu_metrics->average_temperature_l3[0] = metrics.Average.L3Temperature[0];
1804
1805 gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity;
1806 gpu_metrics->average_mm_activity = metrics.Current.UvdActivity;
1807
1808 gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower;
1809 gpu_metrics->average_cpu_power = metrics.Current.Power[0];
1810 gpu_metrics->average_soc_power = metrics.Current.Power[1];
1811 gpu_metrics->average_gfx_power = metrics.Current.Power[2];
1812 memcpy(&gpu_metrics->average_core_power[0],
1813 &metrics.Average.CorePower[0],
1814 sizeof(uint16_t) * 4);
1815
1816 gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency;
1817 gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency;
1818 gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency;
1819 gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency;
1820 gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency;
1821 gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency;
1822
1823 gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency;
1824 gpu_metrics->current_socclk = metrics.Current.SocclkFrequency;
1825 gpu_metrics->current_uclk = metrics.Current.MemclkFrequency;
1826 gpu_metrics->current_fclk = metrics.Current.MemclkFrequency;
1827 gpu_metrics->current_vclk = metrics.Current.VclkFrequency;
1828 gpu_metrics->current_dclk = metrics.Current.DclkFrequency;
1829
1830 memcpy(&gpu_metrics->current_coreclk[0],
1831 &metrics.Current.CoreFrequency[0],
1832 sizeof(uint16_t) * 4);
1833 gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
1834
1835 gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
1836 gpu_metrics->indep_throttle_status =
1837 smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
1838 vangogh_throttler_map);
1839
1840 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1841
1842 *table = (void *)gpu_metrics;
1843
1844 return sizeof(struct gpu_metrics_v2_3);
1845 }
1846
vangogh_get_gpu_metrics_v2_4(struct smu_context * smu,void ** table)1847 static ssize_t vangogh_get_gpu_metrics_v2_4(struct smu_context *smu,
1848 void **table)
1849 {
1850 SmuMetrics_t metrics;
1851 struct smu_table_context *smu_table = &smu->smu_table;
1852 struct gpu_metrics_v2_4 *gpu_metrics =
1853 (struct gpu_metrics_v2_4 *)smu_table->gpu_metrics_table;
1854 int ret = 0;
1855
1856 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1857 if (ret)
1858 return ret;
1859
1860 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 4);
1861
1862 gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
1863 gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
1864 memcpy(&gpu_metrics->temperature_core[0],
1865 &metrics.Current.CoreTemperature[0],
1866 sizeof(uint16_t) * 4);
1867 gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0];
1868
1869 gpu_metrics->average_temperature_gfx = metrics.Average.GfxTemperature;
1870 gpu_metrics->average_temperature_soc = metrics.Average.SocTemperature;
1871 memcpy(&gpu_metrics->average_temperature_core[0],
1872 &metrics.Average.CoreTemperature[0],
1873 sizeof(uint16_t) * 4);
1874 gpu_metrics->average_temperature_l3[0] = metrics.Average.L3Temperature[0];
1875
1876 gpu_metrics->average_gfx_activity = metrics.Average.GfxActivity;
1877 gpu_metrics->average_mm_activity = metrics.Average.UvdActivity;
1878
1879 gpu_metrics->average_socket_power = metrics.Average.CurrentSocketPower;
1880 gpu_metrics->average_cpu_power = metrics.Average.Power[0];
1881 gpu_metrics->average_soc_power = metrics.Average.Power[1];
1882 gpu_metrics->average_gfx_power = metrics.Average.Power[2];
1883
1884 gpu_metrics->average_cpu_voltage = metrics.Average.Voltage[0];
1885 gpu_metrics->average_soc_voltage = metrics.Average.Voltage[1];
1886 gpu_metrics->average_gfx_voltage = metrics.Average.Voltage[2];
1887
1888 gpu_metrics->average_cpu_current = metrics.Average.Current[0];
1889 gpu_metrics->average_soc_current = metrics.Average.Current[1];
1890 gpu_metrics->average_gfx_current = metrics.Average.Current[2];
1891
1892 memcpy(&gpu_metrics->average_core_power[0],
1893 &metrics.Average.CorePower[0],
1894 sizeof(uint16_t) * 4);
1895
1896 gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency;
1897 gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency;
1898 gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency;
1899 gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency;
1900 gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency;
1901 gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency;
1902
1903 gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency;
1904 gpu_metrics->current_socclk = metrics.Current.SocclkFrequency;
1905 gpu_metrics->current_uclk = metrics.Current.MemclkFrequency;
1906 gpu_metrics->current_fclk = metrics.Current.MemclkFrequency;
1907 gpu_metrics->current_vclk = metrics.Current.VclkFrequency;
1908 gpu_metrics->current_dclk = metrics.Current.DclkFrequency;
1909
1910 memcpy(&gpu_metrics->current_coreclk[0],
1911 &metrics.Current.CoreFrequency[0],
1912 sizeof(uint16_t) * 4);
1913 gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
1914
1915 gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
1916 gpu_metrics->indep_throttle_status =
1917 smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
1918 vangogh_throttler_map);
1919
1920 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1921
1922 *table = (void *)gpu_metrics;
1923
1924 return sizeof(struct gpu_metrics_v2_4);
1925 }
1926
vangogh_get_gpu_metrics(struct smu_context * smu,void ** table)1927 static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu,
1928 void **table)
1929 {
1930 struct smu_table_context *smu_table = &smu->smu_table;
1931 struct gpu_metrics_v2_2 *gpu_metrics =
1932 (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
1933 SmuMetrics_t metrics;
1934 int ret = 0;
1935
1936 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1937 if (ret)
1938 return ret;
1939
1940 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
1941
1942 gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
1943 gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
1944 memcpy(&gpu_metrics->temperature_core[0],
1945 &metrics.Current.CoreTemperature[0],
1946 sizeof(uint16_t) * 4);
1947 gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0];
1948
1949 gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity;
1950 gpu_metrics->average_mm_activity = metrics.Current.UvdActivity;
1951
1952 gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower;
1953 gpu_metrics->average_cpu_power = metrics.Current.Power[0];
1954 gpu_metrics->average_soc_power = metrics.Current.Power[1];
1955 gpu_metrics->average_gfx_power = metrics.Current.Power[2];
1956 memcpy(&gpu_metrics->average_core_power[0],
1957 &metrics.Average.CorePower[0],
1958 sizeof(uint16_t) * 4);
1959
1960 gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency;
1961 gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency;
1962 gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency;
1963 gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency;
1964 gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency;
1965 gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency;
1966
1967 gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency;
1968 gpu_metrics->current_socclk = metrics.Current.SocclkFrequency;
1969 gpu_metrics->current_uclk = metrics.Current.MemclkFrequency;
1970 gpu_metrics->current_fclk = metrics.Current.MemclkFrequency;
1971 gpu_metrics->current_vclk = metrics.Current.VclkFrequency;
1972 gpu_metrics->current_dclk = metrics.Current.DclkFrequency;
1973
1974 memcpy(&gpu_metrics->current_coreclk[0],
1975 &metrics.Current.CoreFrequency[0],
1976 sizeof(uint16_t) * 4);
1977 gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
1978
1979 gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
1980 gpu_metrics->indep_throttle_status =
1981 smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
1982 vangogh_throttler_map);
1983
1984 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1985
1986 *table = (void *)gpu_metrics;
1987
1988 return sizeof(struct gpu_metrics_v2_2);
1989 }
1990
vangogh_common_get_gpu_metrics(struct smu_context * smu,void ** table)1991 static ssize_t vangogh_common_get_gpu_metrics(struct smu_context *smu,
1992 void **table)
1993 {
1994 uint32_t smu_program;
1995 uint32_t fw_version;
1996 int ret = 0;
1997
1998 smu_program = (smu->smc_fw_version >> 24) & 0xff;
1999 fw_version = smu->smc_fw_version & 0xffffff;
2000 if (smu_program == 6) {
2001 if (fw_version >= 0x3F0800)
2002 ret = vangogh_get_gpu_metrics_v2_4(smu, table);
2003 else
2004 ret = vangogh_get_gpu_metrics_v2_3(smu, table);
2005
2006 } else {
2007 if (smu->smc_fw_version >= 0x043F3E00) {
2008 if (smu->smc_fw_if_version < 0x3)
2009 ret = vangogh_get_legacy_gpu_metrics_v2_3(smu, table);
2010 else
2011 ret = vangogh_get_gpu_metrics_v2_3(smu, table);
2012 } else {
2013 if (smu->smc_fw_if_version < 0x3)
2014 ret = vangogh_get_legacy_gpu_metrics(smu, table);
2015 else
2016 ret = vangogh_get_gpu_metrics(smu, table);
2017 }
2018 }
2019
2020 return ret;
2021 }
2022
vangogh_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2023 static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
2024 long input[], uint32_t size)
2025 {
2026 int ret = 0;
2027 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2028
2029 if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) {
2030 dev_warn(smu->adev->dev,
2031 "pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n");
2032 return -EINVAL;
2033 }
2034
2035 switch (type) {
2036 case PP_OD_EDIT_CCLK_VDDC_TABLE:
2037 if (size != 3) {
2038 dev_err(smu->adev->dev, "Input parameter number not correct (should be 4 for processor)\n");
2039 return -EINVAL;
2040 }
2041 if (input[0] >= smu->cpu_core_num) {
2042 dev_err(smu->adev->dev, "core index is overflow, should be less than %d\n",
2043 smu->cpu_core_num);
2044 }
2045 smu->cpu_core_id_select = input[0];
2046 if (input[1] == 0) {
2047 if (input[2] < smu->cpu_default_soft_min_freq) {
2048 dev_warn(smu->adev->dev, "Fine grain setting minimum cclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2049 input[2], smu->cpu_default_soft_min_freq);
2050 return -EINVAL;
2051 }
2052 smu->cpu_actual_soft_min_freq = input[2];
2053 } else if (input[1] == 1) {
2054 if (input[2] > smu->cpu_default_soft_max_freq) {
2055 dev_warn(smu->adev->dev, "Fine grain setting maximum cclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2056 input[2], smu->cpu_default_soft_max_freq);
2057 return -EINVAL;
2058 }
2059 smu->cpu_actual_soft_max_freq = input[2];
2060 } else {
2061 return -EINVAL;
2062 }
2063 break;
2064 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2065 if (size != 2) {
2066 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2067 return -EINVAL;
2068 }
2069
2070 if (input[0] == 0) {
2071 if (input[1] < smu->gfx_default_hard_min_freq) {
2072 dev_warn(smu->adev->dev,
2073 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2074 input[1], smu->gfx_default_hard_min_freq);
2075 return -EINVAL;
2076 }
2077 smu->gfx_actual_hard_min_freq = input[1];
2078 } else if (input[0] == 1) {
2079 if (input[1] > smu->gfx_default_soft_max_freq) {
2080 dev_warn(smu->adev->dev,
2081 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2082 input[1], smu->gfx_default_soft_max_freq);
2083 return -EINVAL;
2084 }
2085 smu->gfx_actual_soft_max_freq = input[1];
2086 } else {
2087 return -EINVAL;
2088 }
2089 break;
2090 case PP_OD_RESTORE_DEFAULT_TABLE:
2091 if (size != 0) {
2092 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2093 return -EINVAL;
2094 } else {
2095 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
2096 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
2097 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
2098 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
2099 }
2100 break;
2101 case PP_OD_COMMIT_DPM_TABLE:
2102 if (size != 0) {
2103 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2104 return -EINVAL;
2105 } else {
2106 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
2107 dev_err(smu->adev->dev,
2108 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
2109 smu->gfx_actual_hard_min_freq,
2110 smu->gfx_actual_soft_max_freq);
2111 return -EINVAL;
2112 }
2113
2114 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
2115 smu->gfx_actual_hard_min_freq, NULL);
2116 if (ret) {
2117 dev_err(smu->adev->dev, "Set hard min sclk failed!");
2118 return ret;
2119 }
2120
2121 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
2122 smu->gfx_actual_soft_max_freq, NULL);
2123 if (ret) {
2124 dev_err(smu->adev->dev, "Set soft max sclk failed!");
2125 return ret;
2126 }
2127
2128 if (smu->adev->pm.fw_version < 0x43f1b00) {
2129 dev_warn(smu->adev->dev, "CPUSoftMax/CPUSoftMin are not supported, please update SBIOS!\n");
2130 break;
2131 }
2132
2133 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
2134 ((smu->cpu_core_id_select << 20)
2135 | smu->cpu_actual_soft_min_freq),
2136 NULL);
2137 if (ret) {
2138 dev_err(smu->adev->dev, "Set hard min cclk failed!");
2139 return ret;
2140 }
2141
2142 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk,
2143 ((smu->cpu_core_id_select << 20)
2144 | smu->cpu_actual_soft_max_freq),
2145 NULL);
2146 if (ret) {
2147 dev_err(smu->adev->dev, "Set soft max cclk failed!");
2148 return ret;
2149 }
2150 }
2151 break;
2152 default:
2153 return -ENOSYS;
2154 }
2155
2156 return ret;
2157 }
2158
vangogh_set_default_dpm_tables(struct smu_context * smu)2159 static int vangogh_set_default_dpm_tables(struct smu_context *smu)
2160 {
2161 struct smu_table_context *smu_table = &smu->smu_table;
2162
2163 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
2164 }
2165
vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context * smu)2166 static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
2167 {
2168 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
2169
2170 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
2171 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
2172 smu->gfx_actual_hard_min_freq = 0;
2173 smu->gfx_actual_soft_max_freq = 0;
2174
2175 smu->cpu_default_soft_min_freq = 1400;
2176 smu->cpu_default_soft_max_freq = 3500;
2177 smu->cpu_actual_soft_min_freq = 0;
2178 smu->cpu_actual_soft_max_freq = 0;
2179
2180 return 0;
2181 }
2182
vangogh_get_dpm_clock_table(struct smu_context * smu,struct dpm_clocks * clock_table)2183 static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table)
2184 {
2185 DpmClocks_t *table = smu->smu_table.clocks_table;
2186 int i;
2187
2188 if (!clock_table || !table)
2189 return -EINVAL;
2190
2191 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) {
2192 clock_table->SocClocks[i].Freq = table->SocClocks[i];
2193 clock_table->SocClocks[i].Vol = table->SocVoltage[i];
2194 }
2195
2196 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
2197 clock_table->FClocks[i].Freq = table->DfPstateTable[i].fclk;
2198 clock_table->FClocks[i].Vol = table->DfPstateTable[i].voltage;
2199 }
2200
2201 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
2202 clock_table->MemClocks[i].Freq = table->DfPstateTable[i].memclk;
2203 clock_table->MemClocks[i].Vol = table->DfPstateTable[i].voltage;
2204 }
2205
2206 return 0;
2207 }
2208
vangogh_notify_rlc_state(struct smu_context * smu,bool en)2209 static int vangogh_notify_rlc_state(struct smu_context *smu, bool en)
2210 {
2211 struct amdgpu_device *adev = smu->adev;
2212 int ret = 0;
2213
2214 if (adev->pm.fw_version >= 0x43f1700 && !en)
2215 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify,
2216 RLC_STATUS_OFF, NULL);
2217
2218 return ret;
2219 }
2220
vangogh_post_smu_init(struct smu_context * smu)2221 static int vangogh_post_smu_init(struct smu_context *smu)
2222 {
2223 struct amdgpu_device *adev = smu->adev;
2224 uint32_t tmp;
2225 int ret = 0;
2226 uint8_t aon_bits = 0;
2227 /* Two CUs in one WGP */
2228 uint32_t req_active_wgps = adev->gfx.cu_info.number/2;
2229 uint32_t total_cu = adev->gfx.config.max_cu_per_sh *
2230 adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;
2231
2232 /* allow message will be sent after enable message on Vangogh*/
2233 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
2234 (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2235 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL);
2236 if (ret) {
2237 dev_err(adev->dev, "Failed to Enable GfxOff!\n");
2238 return ret;
2239 }
2240 } else {
2241 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2242 dev_info(adev->dev, "If GFX DPM or power gate disabled, disable GFXOFF\n");
2243 }
2244
2245 /* if all CUs are active, no need to power off any WGPs */
2246 if (total_cu == adev->gfx.cu_info.number)
2247 return 0;
2248
2249 /*
2250 * Calculate the total bits number of always on WGPs for all SA/SEs in
2251 * RLC_PG_ALWAYS_ON_WGP_MASK.
2252 */
2253 tmp = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_ALWAYS_ON_WGP_MASK));
2254 tmp &= RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK;
2255
2256 aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;
2257
2258 /* Do not request any WGPs less than set in the AON_WGP_MASK */
2259 if (aon_bits > req_active_wgps) {
2260 dev_info(adev->dev, "Number of always on WGPs greater than active WGPs: WGP power save not requested.\n");
2261 return 0;
2262 } else {
2263 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RequestActiveWgp, req_active_wgps, NULL);
2264 }
2265 }
2266
vangogh_mode_reset(struct smu_context * smu,int type)2267 static int vangogh_mode_reset(struct smu_context *smu, int type)
2268 {
2269 int ret = 0, index = 0;
2270
2271 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2272 SMU_MSG_GfxDeviceDriverReset);
2273 if (index < 0)
2274 return index == -EACCES ? 0 : index;
2275
2276 mutex_lock(&smu->message_lock);
2277
2278 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type);
2279
2280 mutex_unlock(&smu->message_lock);
2281
2282 mdelay(10);
2283
2284 return ret;
2285 }
2286
vangogh_mode2_reset(struct smu_context * smu)2287 static int vangogh_mode2_reset(struct smu_context *smu)
2288 {
2289 return vangogh_mode_reset(smu, SMU_RESET_MODE_2);
2290 }
2291
2292 /**
2293 * vangogh_get_gfxoff_status - Get gfxoff status
2294 *
2295 * @smu: amdgpu_device pointer
2296 *
2297 * Get current gfxoff status
2298 *
2299 * Return:
2300 * * 0 - GFXOFF (default if enabled).
2301 * * 1 - Transition out of GFX State.
2302 * * 2 - Not in GFXOFF.
2303 * * 3 - Transition into GFXOFF.
2304 */
vangogh_get_gfxoff_status(struct smu_context * smu)2305 static u32 vangogh_get_gfxoff_status(struct smu_context *smu)
2306 {
2307 struct amdgpu_device *adev = smu->adev;
2308 u32 reg, gfxoff_status;
2309
2310 reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_GFX_MISC_CNTL);
2311 gfxoff_status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
2312 >> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT;
2313
2314 return gfxoff_status;
2315 }
2316
vangogh_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)2317 static int vangogh_get_power_limit(struct smu_context *smu,
2318 uint32_t *current_power_limit,
2319 uint32_t *default_power_limit,
2320 uint32_t *max_power_limit,
2321 uint32_t *min_power_limit)
2322 {
2323 struct smu_11_5_power_context *power_context =
2324 smu->smu_power.power_context;
2325 uint32_t ppt_limit;
2326 int ret = 0;
2327
2328 if (smu->adev->pm.fw_version < 0x43f1e00)
2329 return ret;
2330
2331 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSlowPPTLimit, &ppt_limit);
2332 if (ret) {
2333 dev_err(smu->adev->dev, "Get slow PPT limit failed!\n");
2334 return ret;
2335 }
2336 /* convert from milliwatt to watt */
2337 if (current_power_limit)
2338 *current_power_limit = ppt_limit / 1000;
2339 if (default_power_limit)
2340 *default_power_limit = ppt_limit / 1000;
2341 if (max_power_limit)
2342 *max_power_limit = 29;
2343 if (min_power_limit)
2344 *min_power_limit = 0;
2345
2346 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPPTLimit, &ppt_limit);
2347 if (ret) {
2348 dev_err(smu->adev->dev, "Get fast PPT limit failed!\n");
2349 return ret;
2350 }
2351 /* convert from milliwatt to watt */
2352 power_context->current_fast_ppt_limit =
2353 power_context->default_fast_ppt_limit = ppt_limit / 1000;
2354 power_context->max_fast_ppt_limit = 30;
2355
2356 return ret;
2357 }
2358
vangogh_get_ppt_limit(struct smu_context * smu,uint32_t * ppt_limit,enum smu_ppt_limit_type type,enum smu_ppt_limit_level level)2359 static int vangogh_get_ppt_limit(struct smu_context *smu,
2360 uint32_t *ppt_limit,
2361 enum smu_ppt_limit_type type,
2362 enum smu_ppt_limit_level level)
2363 {
2364 struct smu_11_5_power_context *power_context =
2365 smu->smu_power.power_context;
2366
2367 if (!power_context)
2368 return -EOPNOTSUPP;
2369
2370 if (type == SMU_FAST_PPT_LIMIT) {
2371 switch (level) {
2372 case SMU_PPT_LIMIT_MAX:
2373 *ppt_limit = power_context->max_fast_ppt_limit;
2374 break;
2375 case SMU_PPT_LIMIT_CURRENT:
2376 *ppt_limit = power_context->current_fast_ppt_limit;
2377 break;
2378 case SMU_PPT_LIMIT_DEFAULT:
2379 *ppt_limit = power_context->default_fast_ppt_limit;
2380 break;
2381 default:
2382 break;
2383 }
2384 }
2385
2386 return 0;
2387 }
2388
vangogh_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t ppt_limit)2389 static int vangogh_set_power_limit(struct smu_context *smu,
2390 enum smu_ppt_limit_type limit_type,
2391 uint32_t ppt_limit)
2392 {
2393 struct smu_11_5_power_context *power_context =
2394 smu->smu_power.power_context;
2395 int ret = 0;
2396
2397 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
2398 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
2399 return -EOPNOTSUPP;
2400 }
2401
2402 switch (limit_type) {
2403 case SMU_DEFAULT_PPT_LIMIT:
2404 ret = smu_cmn_send_smc_msg_with_param(smu,
2405 SMU_MSG_SetSlowPPTLimit,
2406 ppt_limit * 1000, /* convert from watt to milliwatt */
2407 NULL);
2408 if (ret)
2409 return ret;
2410
2411 smu->current_power_limit = ppt_limit;
2412 break;
2413 case SMU_FAST_PPT_LIMIT:
2414 ppt_limit &= ~(SMU_FAST_PPT_LIMIT << 24);
2415 if (ppt_limit > power_context->max_fast_ppt_limit) {
2416 dev_err(smu->adev->dev,
2417 "New power limit (%d) is over the max allowed %d\n",
2418 ppt_limit, power_context->max_fast_ppt_limit);
2419 return ret;
2420 }
2421
2422 ret = smu_cmn_send_smc_msg_with_param(smu,
2423 SMU_MSG_SetFastPPTLimit,
2424 ppt_limit * 1000, /* convert from watt to milliwatt */
2425 NULL);
2426 if (ret)
2427 return ret;
2428
2429 power_context->current_fast_ppt_limit = ppt_limit;
2430 break;
2431 default:
2432 return -EINVAL;
2433 }
2434
2435 return ret;
2436 }
2437
2438 /**
2439 * vangogh_set_gfxoff_residency
2440 *
2441 * @smu: amdgpu_device pointer
2442 * @start: start/stop residency log
2443 *
2444 * This function will be used to log gfxoff residency
2445 *
2446 *
2447 * Returns standard response codes.
2448 */
vangogh_set_gfxoff_residency(struct smu_context * smu,bool start)2449 static u32 vangogh_set_gfxoff_residency(struct smu_context *smu, bool start)
2450 {
2451 int ret = 0;
2452 u32 residency;
2453 struct amdgpu_device *adev = smu->adev;
2454
2455 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
2456 return 0;
2457
2458 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LogGfxOffResidency,
2459 start, &residency);
2460 if (ret)
2461 return ret;
2462
2463 if (!start)
2464 adev->gfx.gfx_off_residency = residency;
2465
2466 return ret;
2467 }
2468
2469 /**
2470 * vangogh_get_gfxoff_residency
2471 *
2472 * @smu: amdgpu_device pointer
2473 * @residency: placeholder for return value
2474 *
2475 * This function will be used to get gfxoff residency.
2476 *
2477 * Returns standard response codes.
2478 */
vangogh_get_gfxoff_residency(struct smu_context * smu,uint32_t * residency)2479 static u32 vangogh_get_gfxoff_residency(struct smu_context *smu, uint32_t *residency)
2480 {
2481 struct amdgpu_device *adev = smu->adev;
2482
2483 *residency = adev->gfx.gfx_off_residency;
2484
2485 return 0;
2486 }
2487
2488 /**
2489 * vangogh_get_gfxoff_entrycount - get gfxoff entry count
2490 *
2491 * @smu: amdgpu_device pointer
2492 * @entrycount: placeholder for return value
2493 *
2494 * This function will be used to get gfxoff entry count
2495 *
2496 * Returns standard response codes.
2497 */
vangogh_get_gfxoff_entrycount(struct smu_context * smu,uint64_t * entrycount)2498 static u32 vangogh_get_gfxoff_entrycount(struct smu_context *smu, uint64_t *entrycount)
2499 {
2500 int ret = 0, value = 0;
2501 struct amdgpu_device *adev = smu->adev;
2502
2503 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
2504 return 0;
2505
2506 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetGfxOffEntryCount, &value);
2507 *entrycount = value + adev->gfx.gfx_off_entrycount;
2508
2509 return ret;
2510 }
2511
2512 static const struct pptable_funcs vangogh_ppt_funcs = {
2513
2514 .check_fw_status = smu_v11_0_check_fw_status,
2515 .check_fw_version = smu_v11_0_check_fw_version,
2516 .init_smc_tables = vangogh_init_smc_tables,
2517 .fini_smc_tables = smu_v11_0_fini_smc_tables,
2518 .init_power = smu_v11_0_init_power,
2519 .fini_power = smu_v11_0_fini_power,
2520 .register_irq_handler = smu_v11_0_register_irq_handler,
2521 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2522 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2523 .send_smc_msg = smu_cmn_send_smc_msg,
2524 .dpm_set_vcn_enable = vangogh_dpm_set_vcn_enable,
2525 .dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable,
2526 .is_dpm_running = vangogh_is_dpm_running,
2527 .read_sensor = vangogh_read_sensor,
2528 .get_apu_thermal_limit = vangogh_get_apu_thermal_limit,
2529 .set_apu_thermal_limit = vangogh_set_apu_thermal_limit,
2530 .get_enabled_mask = smu_cmn_get_enabled_mask,
2531 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2532 .set_watermarks_table = vangogh_set_watermarks_table,
2533 .set_driver_table_location = smu_v11_0_set_driver_table_location,
2534 .interrupt_work = smu_v11_0_interrupt_work,
2535 .get_gpu_metrics = vangogh_common_get_gpu_metrics,
2536 .od_edit_dpm_table = vangogh_od_edit_dpm_table,
2537 .print_clk_levels = vangogh_common_print_clk_levels,
2538 .set_default_dpm_table = vangogh_set_default_dpm_tables,
2539 .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters,
2540 .notify_rlc_state = vangogh_notify_rlc_state,
2541 .feature_is_enabled = smu_cmn_feature_is_enabled,
2542 .set_power_profile_mode = vangogh_set_power_profile_mode,
2543 .get_power_profile_mode = vangogh_get_power_profile_mode,
2544 .get_dpm_clock_table = vangogh_get_dpm_clock_table,
2545 .force_clk_levels = vangogh_force_clk_levels,
2546 .set_performance_level = vangogh_set_performance_level,
2547 .post_init = vangogh_post_smu_init,
2548 .mode2_reset = vangogh_mode2_reset,
2549 .gfx_off_control = smu_v11_0_gfx_off_control,
2550 .get_gfx_off_status = vangogh_get_gfxoff_status,
2551 .get_gfx_off_entrycount = vangogh_get_gfxoff_entrycount,
2552 .get_gfx_off_residency = vangogh_get_gfxoff_residency,
2553 .set_gfx_off_residency = vangogh_set_gfxoff_residency,
2554 .get_ppt_limit = vangogh_get_ppt_limit,
2555 .get_power_limit = vangogh_get_power_limit,
2556 .set_power_limit = vangogh_set_power_limit,
2557 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2558 };
2559
vangogh_set_ppt_funcs(struct smu_context * smu)2560 void vangogh_set_ppt_funcs(struct smu_context *smu)
2561 {
2562 smu->ppt_funcs = &vangogh_ppt_funcs;
2563 smu->message_map = vangogh_message_map;
2564 smu->feature_map = vangogh_feature_mask_map;
2565 smu->table_map = vangogh_table_map;
2566 smu->workload_map = vangogh_workload_map;
2567 smu->is_apu = true;
2568 smu_v11_0_set_smu_mailbox_registers(smu);
2569 }
2570