1 /* 2 * Copyright © 2012-2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DPLL_MGR_H_ 26 #define _INTEL_DPLL_MGR_H_ 27 28 #include <linux/types.h> 29 30 #include "intel_display_power.h" 31 #include "intel_wakeref.h" 32 33 #define for_each_shared_dpll(__i915, __pll, __i) \ 34 for ((__i) = 0; (__i) < (__i915)->display.dpll.num_shared_dpll && \ 35 ((__pll) = &(__i915)->display.dpll.shared_dplls[(__i)]) ; (__i)++) 36 37 /*FIXME: Move this to a more appropriate place. */ 38 #define abs_diff(a, b) ({ \ 39 typeof(a) __a = (a); \ 40 typeof(b) __b = (b); \ 41 (void) (&__a == &__b); \ 42 __a > __b ? (__a - __b) : (__b - __a); }) 43 44 enum tc_port; 45 struct drm_i915_private; 46 struct drm_printer; 47 struct intel_atomic_state; 48 struct intel_crtc; 49 struct intel_crtc_state; 50 struct intel_encoder; 51 struct intel_shared_dpll; 52 struct intel_shared_dpll_funcs; 53 54 /** 55 * enum intel_dpll_id - possible DPLL ids 56 * 57 * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0. 58 */ 59 enum intel_dpll_id { 60 /** 61 * @DPLL_ID_PRIVATE: non-shared dpll in use 62 */ 63 DPLL_ID_PRIVATE = -1, 64 65 /** 66 * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB 67 */ 68 DPLL_ID_PCH_PLL_A = 0, 69 /** 70 * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB 71 */ 72 DPLL_ID_PCH_PLL_B = 1, 73 74 75 /** 76 * @DPLL_ID_WRPLL1: HSW and BDW WRPLL1 77 */ 78 DPLL_ID_WRPLL1 = 0, 79 /** 80 * @DPLL_ID_WRPLL2: HSW and BDW WRPLL2 81 */ 82 DPLL_ID_WRPLL2 = 1, 83 /** 84 * @DPLL_ID_SPLL: HSW and BDW SPLL 85 */ 86 DPLL_ID_SPLL = 2, 87 /** 88 * @DPLL_ID_LCPLL_810: HSW and BDW 0.81 GHz LCPLL 89 */ 90 DPLL_ID_LCPLL_810 = 3, 91 /** 92 * @DPLL_ID_LCPLL_1350: HSW and BDW 1.35 GHz LCPLL 93 */ 94 DPLL_ID_LCPLL_1350 = 4, 95 /** 96 * @DPLL_ID_LCPLL_2700: HSW and BDW 2.7 GHz LCPLL 97 */ 98 DPLL_ID_LCPLL_2700 = 5, 99 100 101 /** 102 * @DPLL_ID_SKL_DPLL0: SKL and later DPLL0 103 */ 104 DPLL_ID_SKL_DPLL0 = 0, 105 /** 106 * @DPLL_ID_SKL_DPLL1: SKL and later DPLL1 107 */ 108 DPLL_ID_SKL_DPLL1 = 1, 109 /** 110 * @DPLL_ID_SKL_DPLL2: SKL and later DPLL2 111 */ 112 DPLL_ID_SKL_DPLL2 = 2, 113 /** 114 * @DPLL_ID_SKL_DPLL3: SKL and later DPLL3 115 */ 116 DPLL_ID_SKL_DPLL3 = 3, 117 118 119 /** 120 * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0 121 */ 122 DPLL_ID_ICL_DPLL0 = 0, 123 /** 124 * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1 125 */ 126 DPLL_ID_ICL_DPLL1 = 1, 127 /** 128 * @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4 129 */ 130 DPLL_ID_EHL_DPLL4 = 2, 131 /** 132 * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL 133 */ 134 DPLL_ID_ICL_TBTPLL = 2, 135 /** 136 * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C), 137 * TGL TC PLL 1 port 1 (TC1) 138 */ 139 DPLL_ID_ICL_MGPLL1 = 3, 140 /** 141 * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D) 142 * TGL TC PLL 1 port 2 (TC2) 143 */ 144 DPLL_ID_ICL_MGPLL2 = 4, 145 /** 146 * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E) 147 * TGL TC PLL 1 port 3 (TC3) 148 */ 149 DPLL_ID_ICL_MGPLL3 = 5, 150 /** 151 * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F) 152 * TGL TC PLL 1 port 4 (TC4) 153 */ 154 DPLL_ID_ICL_MGPLL4 = 6, 155 /** 156 * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5) 157 */ 158 DPLL_ID_TGL_MGPLL5 = 7, 159 /** 160 * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6) 161 */ 162 DPLL_ID_TGL_MGPLL6 = 8, 163 164 /** 165 * @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0 166 */ 167 DPLL_ID_DG1_DPLL0 = 0, 168 /** 169 * @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1 170 */ 171 DPLL_ID_DG1_DPLL1 = 1, 172 /** 173 * @DPLL_ID_DG1_DPLL2: DG1 combo PHY DPLL2 174 */ 175 DPLL_ID_DG1_DPLL2 = 2, 176 /** 177 * @DPLL_ID_DG1_DPLL3: DG1 combo PHY DPLL3 178 */ 179 DPLL_ID_DG1_DPLL3 = 3, 180 }; 181 182 #define I915_NUM_PLLS 9 183 184 enum icl_port_dpll_id { 185 ICL_PORT_DPLL_DEFAULT, 186 ICL_PORT_DPLL_MG_PHY, 187 188 ICL_PORT_DPLL_COUNT, 189 }; 190 191 struct i9xx_dpll_hw_state { 192 u32 dpll; 193 u32 dpll_md; 194 u32 fp0; 195 u32 fp1; 196 }; 197 198 struct hsw_dpll_hw_state { 199 u32 wrpll; 200 u32 spll; 201 }; 202 203 struct skl_dpll_hw_state { 204 /* 205 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in 206 * lower part of ctrl1 and they get shifted into position when writing 207 * the register. This allows us to easily compare the state to share 208 * the DPLL. 209 */ 210 u32 ctrl1; 211 /* HDMI only, 0 when used for DP */ 212 u32 cfgcr1, cfgcr2; 213 }; 214 215 struct bxt_dpll_hw_state { 216 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; 217 }; 218 219 struct icl_dpll_hw_state { 220 u32 cfgcr0, cfgcr1; 221 222 /* tgl */ 223 u32 div0; 224 225 u32 mg_refclkin_ctl; 226 u32 mg_clktop2_coreclkctl1; 227 u32 mg_clktop2_hsclkctl; 228 u32 mg_pll_div0; 229 u32 mg_pll_div1; 230 u32 mg_pll_lf; 231 u32 mg_pll_frac_lock; 232 u32 mg_pll_ssc; 233 u32 mg_pll_bias; 234 u32 mg_pll_tdc_coldst_bias; 235 u32 mg_pll_bias_mask; 236 u32 mg_pll_tdc_coldst_bias_mask; 237 }; 238 239 struct intel_mpllb_state { 240 u32 clock; /* in KHz */ 241 u32 ref_control; 242 u32 mpllb_cp; 243 u32 mpllb_div; 244 u32 mpllb_div2; 245 u32 mpllb_fracn1; 246 u32 mpllb_fracn2; 247 u32 mpllb_sscen; 248 u32 mpllb_sscstep; 249 }; 250 251 struct intel_c10pll_state { 252 u32 clock; /* in KHz */ 253 u8 tx; 254 u8 cmn; 255 u8 pll[20]; 256 }; 257 258 struct intel_c20pll_state { 259 u32 clock; /* in kHz */ 260 u16 tx[3]; 261 u16 cmn[4]; 262 union { 263 u16 mplla[10]; 264 u16 mpllb[11]; 265 }; 266 }; 267 268 struct intel_cx0pll_state { 269 union { 270 struct intel_c10pll_state c10; 271 struct intel_c20pll_state c20; 272 }; 273 bool ssc_enabled; 274 bool use_c10; 275 bool tbt_mode; 276 }; 277 278 struct intel_dpll_hw_state { 279 union { 280 struct i9xx_dpll_hw_state i9xx; 281 struct hsw_dpll_hw_state hsw; 282 struct skl_dpll_hw_state skl; 283 struct bxt_dpll_hw_state bxt; 284 struct icl_dpll_hw_state icl; 285 struct intel_mpllb_state mpllb; 286 struct intel_cx0pll_state cx0pll; 287 }; 288 }; 289 290 /** 291 * struct intel_shared_dpll_state - hold the DPLL atomic state 292 * 293 * This structure holds an atomic state for the DPLL, that can represent 294 * either its current state (in struct &intel_shared_dpll) or a desired 295 * future state which would be applied by an atomic mode set (stored in 296 * a struct &intel_atomic_state). 297 * 298 * See also intel_reserve_shared_dplls() and intel_release_shared_dplls(). 299 */ 300 struct intel_shared_dpll_state { 301 /** 302 * @pipe_mask: mask of pipes using this DPLL, active or not 303 */ 304 u8 pipe_mask; 305 306 /** 307 * @hw_state: hardware configuration for the DPLL stored in 308 * struct &intel_dpll_hw_state. 309 */ 310 struct intel_dpll_hw_state hw_state; 311 }; 312 313 /** 314 * struct dpll_info - display PLL platform specific info 315 */ 316 struct dpll_info { 317 /** 318 * @name: DPLL name; used for logging 319 */ 320 const char *name; 321 322 /** 323 * @funcs: platform specific hooks 324 */ 325 const struct intel_shared_dpll_funcs *funcs; 326 327 /** 328 * @id: unique indentifier for this DPLL 329 */ 330 enum intel_dpll_id id; 331 332 /** 333 * @power_domain: extra power domain required by the DPLL 334 */ 335 enum intel_display_power_domain power_domain; 336 337 /** 338 * @always_on: 339 * 340 * Inform the state checker that the DPLL is kept enabled even if 341 * not in use by any CRTC. 342 */ 343 bool always_on; 344 345 /** 346 * @is_alt_port_dpll: 347 * 348 * Inform the state checker that the DPLL can be used as a fallback 349 * (for TC->TBT fallback). 350 */ 351 bool is_alt_port_dpll; 352 }; 353 354 /** 355 * struct intel_shared_dpll - display PLL with tracked state and users 356 */ 357 struct intel_shared_dpll { 358 /** 359 * @state: 360 * 361 * Store the state for the pll, including its hw state 362 * and CRTCs using it. 363 */ 364 struct intel_shared_dpll_state state; 365 366 /** 367 * @index: index for atomic state 368 */ 369 u8 index; 370 371 /** 372 * @active_mask: mask of active pipes (i.e. DPMS on) using this DPLL 373 */ 374 u8 active_mask; 375 376 /** 377 * @on: is the PLL actually active? Disabled during modeset 378 */ 379 bool on; 380 381 /** 382 * @info: platform specific info 383 */ 384 const struct dpll_info *info; 385 386 /** 387 * @wakeref: In some platforms a device-level runtime pm reference may 388 * need to be grabbed to disable DC states while this DPLL is enabled 389 */ 390 intel_wakeref_t wakeref; 391 }; 392 393 #define SKL_DPLL0 0 394 #define SKL_DPLL1 1 395 #define SKL_DPLL2 2 396 #define SKL_DPLL3 3 397 398 /* shared dpll functions */ 399 struct intel_shared_dpll * 400 intel_get_shared_dpll_by_id(struct drm_i915_private *i915, 401 enum intel_dpll_id id); 402 void assert_shared_dpll(struct drm_i915_private *i915, 403 struct intel_shared_dpll *pll, 404 bool state); 405 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) 406 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) 407 int intel_compute_shared_dplls(struct intel_atomic_state *state, 408 struct intel_crtc *crtc, 409 struct intel_encoder *encoder); 410 int intel_reserve_shared_dplls(struct intel_atomic_state *state, 411 struct intel_crtc *crtc, 412 struct intel_encoder *encoder); 413 void intel_release_shared_dplls(struct intel_atomic_state *state, 414 struct intel_crtc *crtc); 415 void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc, 416 const struct intel_shared_dpll *pll, 417 struct intel_shared_dpll_state *shared_dpll_state); 418 void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, 419 enum icl_port_dpll_id port_dpll_id); 420 void intel_update_active_dpll(struct intel_atomic_state *state, 421 struct intel_crtc *crtc, 422 struct intel_encoder *encoder); 423 int intel_dpll_get_freq(struct drm_i915_private *i915, 424 const struct intel_shared_dpll *pll, 425 const struct intel_dpll_hw_state *dpll_hw_state); 426 bool intel_dpll_get_hw_state(struct drm_i915_private *i915, 427 struct intel_shared_dpll *pll, 428 struct intel_dpll_hw_state *dpll_hw_state); 429 void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state); 430 void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state); 431 void intel_shared_dpll_swap_state(struct intel_atomic_state *state); 432 void intel_shared_dpll_init(struct drm_i915_private *i915); 433 void intel_dpll_update_ref_clks(struct drm_i915_private *i915); 434 void intel_dpll_readout_hw_state(struct drm_i915_private *i915); 435 void intel_dpll_sanitize_state(struct drm_i915_private *i915); 436 437 void intel_dpll_dump_hw_state(struct drm_i915_private *i915, 438 struct drm_printer *p, 439 const struct intel_dpll_hw_state *dpll_hw_state); 440 bool intel_dpll_compare_hw_state(struct drm_i915_private *i915, 441 const struct intel_dpll_hw_state *a, 442 const struct intel_dpll_hw_state *b); 443 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port); 444 bool intel_dpll_is_combophy(enum intel_dpll_id id); 445 446 void intel_shared_dpll_state_verify(struct intel_atomic_state *state, 447 struct intel_crtc *crtc); 448 void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state); 449 450 #endif /* _INTEL_DPLL_MGR_H_ */ 451