1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_sisreg.h,v 1.1.4.11 2003/02/05 21:49:01 mbr Exp $ 33 * $DragonFly: src/sys/dev/netif/sis/if_sisreg.h,v 1.7 2006/08/01 18:09:37 swildner Exp $ 34 */ 35 36 /* 37 * Register definitions for the SiS 900 and SiS 7016 chipsets. The 38 * 7016 is actually an older chip and some of its registers differ 39 * from the 900, however the core operational registers are the same: 40 * the differences lie in the OnNow/Wake on LAN stuff which we don't 41 * use anyway. The 7016 needs an external MII compliant PHY while the 42 * SiS 900 has one built in. All registers are 32-bits wide. 43 */ 44 45 /* Registers common to SiS 900 and SiS 7016 */ 46 #define SIS_CSR 0x00 47 #define SIS_CFG 0x04 48 #define SIS_EECTL 0x08 49 #define SIS_PCICTL 0x0C 50 #define SIS_ISR 0x10 51 #define SIS_IMR 0x14 52 #define SIS_IER 0x18 53 #define SIS_PHYCTL 0x1C 54 #define SIS_TX_LISTPTR 0x20 55 #define SIS_TX_CFG 0x24 56 #define SIS_RX_LISTPTR 0x30 57 #define SIS_RX_CFG 0x34 58 #define SIS_FLOWCTL 0x38 59 #define SIS_RXFILT_CTL 0x48 60 #define SIS_RXFILT_DATA 0x4C 61 #define SIS_PWRMAN_CTL 0xB0 62 #define SIS_PWERMAN_WKUP_EVENT 0xB4 63 #define SIS_WKUP_FRAME_CRC 0xBC 64 #define SIS_WKUP_FRAME_MASK0 0xC0 65 #define SIS_WKUP_FRAME_MASKXX 0xEC 66 67 /* SiS 7016 specific registers */ 68 #define SIS_SILICON_REV 0x5C 69 #define SIS_MIB_CTL0 0x60 70 #define SIS_MIB_CTL1 0x64 71 #define SIS_MIB_CTL2 0x68 72 #define SIS_MIB_CTL3 0x6C 73 #define SIS_MIB 0x80 74 #define SIS_LINKSTS 0xA0 75 #define SIS_TIMEUNIT 0xA4 76 #define SIS_GPIO 0xB8 77 78 /* NS DP83815 registers */ 79 #define NS_CLKRUN 0x3C 80 #define NS_BMCR 0x80 81 #define NS_BMSR 0x84 82 #define NS_PHYIDR1 0x88 83 #define NS_PHYIDR2 0x8C 84 #define NS_ANAR 0x90 85 #define NS_ANLPAR 0x94 86 #define NS_ANER 0x98 87 #define NS_ANNPTR 0x9C 88 89 #define NS_PHY_CR 0xE4 90 #define NS_PHY_10BTSCR 0xE8 91 #define NS_PHY_PAGE 0xCC 92 #define NS_PHY_EXTCFG 0xF0 93 #define NS_PHY_DSPCFG 0xF4 94 #define NS_PHY_SDCFG 0xF8 95 #define NS_PHY_TDATA 0xFC 96 97 #define NS_CLKRUN_PMESTS 0x00008000 98 #define NS_CLKRUN_PMEENB 0x00000100 99 #define NS_CLNRUN_CLKRUN_ENB 0x00000001 100 101 #define SIS_CSR_TX_ENABLE 0x00000001 102 #define SIS_CSR_TX_DISABLE 0x00000002 103 #define SIS_CSR_RX_ENABLE 0x00000004 104 #define SIS_CSR_RX_DISABLE 0x00000008 105 #define SIS_CSR_TX_RESET 0x00000010 106 #define SIS_CSR_RX_RESET 0x00000020 107 #define SIS_CSR_SOFTINTR 0x00000080 108 #define SIS_CSR_RESET 0x00000100 109 #define SIS_CSR_ACCESS_MODE 0x00000200 110 #define SIS_CSR_RELOAD 0x00000400 111 112 #define SIS_CFG_BIGENDIAN 0x00000001 113 #define SIS_CFG_PERR_DETECT 0x00000008 114 #define SIS_CFG_DEFER_DISABLE 0x00000010 115 #define SIS_CFG_OUTOFWIN_TIMER 0x00000020 116 #define SIS_CFG_SINGLE_BACKOFF 0x00000040 117 #define SIS_CFG_PCIREQ_ALG 0x00000080 118 #define SIS_CFG_FAIR_BACKOFF 0x00000200 /* 635 & 900B Specific */ 119 #define SIS_CFG_RND_CNT 0x00000400 /* 635 & 900B Specific */ 120 #define SIS_CFG_EDB_MASTER_EN 0x00002000 121 122 #define SIS_EECTL_DIN 0x00000001 123 #define SIS_EECTL_DOUT 0x00000002 124 #define SIS_EECTL_CLK 0x00000004 125 #define SIS_EECTL_CSEL 0x00000008 126 127 #define SIS_MII_CLK 0x00000040 128 #define SIS_MII_DIR 0x00000020 129 #define SIS_MII_DATA 0x00000010 130 131 #define SIS_EECMD_WRITE 0x140 132 #define SIS_EECMD_READ 0x180 133 #define SIS_EECMD_ERASE 0x1c0 134 135 /* 136 * EEPROM Commands for SiS96x 137 * chipsets. 138 */ 139 #define SIS_EECMD_REQ 0x00000400 140 #define SIS_EECMD_DONE 0x00000200 141 #define SIS_EECMD_GNT 0x00000100 142 143 #define SIS_EE_NODEADDR 0x8 144 #define NS_EE_NODEADDR 0x6 145 146 #define SIS_PCICTL_SRAMADDR 0x0000001F 147 #define SIS_PCICTL_RAMTSTENB 0x00000020 148 #define SIS_PCICTL_TXTSTENB 0x00000040 149 #define SIS_PCICTL_RXTSTENB 0x00000080 150 #define SIS_PCICTL_BMTSTENB 0x00000200 151 #define SIS_PCICTL_RAMADDR 0x001F0000 152 #define SIS_PCICTL_ROMTIME 0x0F000000 153 #define SIS_PCICTL_DISCTEST 0x40000000 154 155 #define SIS_ISR_RX_OK 0x00000001 156 #define SIS_ISR_RX_DESC_OK 0x00000002 157 #define SIS_ISR_RX_ERR 0x00000004 158 #define SIS_ISR_RX_EARLY 0x00000008 159 #define SIS_ISR_RX_IDLE 0x00000010 160 #define SIS_ISR_RX_OFLOW 0x00000020 161 #define SIS_ISR_TX_OK 0x00000040 162 #define SIS_ISR_TX_DESC_OK 0x00000080 163 #define SIS_ISR_TX_ERR 0x00000100 164 #define SIS_ISR_TX_IDLE 0x00000200 165 #define SIS_ISR_TX_UFLOW 0x00000400 166 #define SIS_ISR_SOFTINTR 0x00000800 167 #define SIS_ISR_HIBITS 0x00008000 168 #define SIS_ISR_RX_FIFO_OFLOW 0x00010000 169 #define SIS_ISR_TGT_ABRT 0x00100000 170 #define SIS_ISR_BM_ABRT 0x00200000 171 #define SIS_ISR_SYSERR 0x00400000 172 #define SIS_ISR_PARITY_ERR 0x00800000 173 #define SIS_ISR_RX_RESET_DONE 0x01000000 174 #define SIS_ISR_TX_RESET_DONE 0x02000000 175 #define SIS_ISR_TX_PAUSE_START 0x04000000 176 #define SIS_ISR_TX_PAUSE_DONE 0x08000000 177 #define SIS_ISR_WAKE_EVENT 0x10000000 178 179 #define SIS_IMR_RX_OK 0x00000001 180 #define SIS_IMR_RX_DESC_OK 0x00000002 181 #define SIS_IMR_RX_ERR 0x00000004 182 #define SIS_IMR_RX_EARLY 0x00000008 183 #define SIS_IMR_RX_IDLE 0x00000010 184 #define SIS_IMR_RX_OFLOW 0x00000020 185 #define SIS_IMR_TX_OK 0x00000040 186 #define SIS_IMR_TX_DESC_OK 0x00000080 187 #define SIS_IMR_TX_ERR 0x00000100 188 #define SIS_IMR_TX_IDLE 0x00000200 189 #define SIS_IMR_TX_UFLOW 0x00000400 190 #define SIS_IMR_SOFTINTR 0x00000800 191 #define SIS_IMR_HIBITS 0x00008000 192 #define SIS_IMR_RX_FIFO_OFLOW 0x00010000 193 #define SIS_IMR_TGT_ABRT 0x00100000 194 #define SIS_IMR_BM_ABRT 0x00200000 195 #define SIS_IMR_SYSERR 0x00400000 196 #define SIS_IMR_PARITY_ERR 0x00800000 197 #define SIS_IMR_RX_RESET_DONE 0x01000000 198 #define SIS_IMR_TX_RESET_DONE 0x02000000 199 #define SIS_IMR_TX_PAUSE_START 0x04000000 200 #define SIS_IMR_TX_PAUSE_DONE 0x08000000 201 #define SIS_IMR_WAKE_EVENT 0x10000000 202 203 #define SIS_INTRS \ 204 (SIS_IMR_RX_OFLOW|SIS_IMR_TX_UFLOW|SIS_IMR_TX_OK|\ 205 SIS_IMR_TX_IDLE|SIS_IMR_RX_OK|SIS_IMR_RX_ERR|\ 206 SIS_IMR_RX_IDLE|\ 207 SIS_IMR_SYSERR) 208 209 #define SIS_IER_INTRENB 0x00000001 210 211 #define SIS_PHYCTL_ACCESS 0x00000010 212 #define SIS_PHYCTL_OP 0x00000020 213 #define SIS_PHYCTL_REGADDR 0x000007C0 214 #define SIS_PHYCTL_PHYADDR 0x0000F800 215 #define SIS_PHYCTL_PHYDATA 0xFFFF0000 216 217 #define SIS_PHYOP_READ 0x00000020 218 #define SIS_PHYOP_WRITE 0x00000000 219 220 #define SIS_TXCFG_DRAIN_THRESH 0x0000003F /* 32-byte units */ 221 #define SIS_TXCFG_FILL_THRESH 0x00003F00 /* 32-byte units */ 222 #define SIS_TXCFG_DMABURST 0x00700000 223 #define SIS_TXCFG_AUTOPAD 0x10000000 224 #define SIS_TXCFG_LOOPBK 0x20000000 225 #define SIS_TXCFG_IGN_HBEAT 0x40000000 226 #define SIS_TXCFG_IGN_CARR 0x80000000 227 228 #define SIS_TXCFG_DRAIN(x) (((x) >> 5) & SIS_TXCFG_DRAIN_THRESH) 229 #define SIS_TXCFG_FILL(x) ((((x) >> 5) << 8) & SIS_TXCFG_FILL_THRESH) 230 231 #define SIS_TXDMA_512BYTES 0x00000000 232 #define SIS_TXDMA_4BYTES 0x00100000 233 #define SIS_TXDMA_8BYTES 0x00200000 234 #define SIS_TXDMA_16BYTES 0x00300000 235 #define SIS_TXDMA_32BYTES 0x00400000 236 #define SIS_TXDMA_64BYTES 0x00500000 237 #define SIS_TXDMA_128BYTES 0x00600000 238 #define SIS_TXDMA_256BYTES 0x00700000 239 240 #define SIS_TXCFG_100 \ 241 (SIS_TXDMA_64BYTES|SIS_TXCFG_AUTOPAD|\ 242 SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1536)) 243 244 #define SIS_TXCFG_10 \ 245 (SIS_TXDMA_32BYTES|SIS_TXCFG_AUTOPAD|\ 246 SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1536)) 247 248 #define SIS_RXCFG_DRAIN_THRESH 0x0000003E /* 8-byte units */ 249 #define SIS_RXCFG_DMABURST 0x00700000 250 #define SIS_RXCFG_RX_JABBER 0x08000000 251 #define SIS_RXCFG_RX_TXPKTS 0x10000000 252 #define SIS_RXCFG_RX_RUNTS 0x40000000 253 #define SIS_RXCFG_RX_GIANTS 0x80000000 254 255 #define SIS_RXCFG_DRAIN(x) ((((x) >> 3) << 1) & SIS_RXCFG_DRAIN_THRESH) 256 257 #define SIS_RXDMA_512BYTES 0x00000000 258 #define SIS_RXDMA_4BYTES 0x00100000 259 #define SIS_RXDMA_8BYTES 0x00200000 260 #define SIS_RXDMA_16BYTES 0x00300000 261 #define SIS_RXDMA_32BYTES 0x00400000 262 #define SIS_RXDMA_64BYTES 0x00500000 263 #define SIS_RXDMA_128BYTES 0x00600000 264 #define SIS_RXDMA_256BYTES 0x00700000 265 266 #define SIS_RXCFG256 \ 267 (SIS_RXCFG_DRAIN(64) | SIS_RXDMA_256BYTES) 268 #define SIS_RXCFG64 \ 269 (SIS_RXCFG_DRAIN(64) | SIS_RXDMA_64BYTES) 270 271 #define SIS_RXFILTCTL_ADDR 0x000F0000 272 #define NS_RXFILTCTL_MCHASH 0x00200000 273 #define NS_RXFILTCTL_ARP 0x00400000 274 #define NS_RXFILTCTL_PERFECT 0x08000000 275 #define SIS_RXFILTCTL_ALLPHYS 0x10000000 276 #define SIS_RXFILTCTL_ALLMULTI 0x20000000 277 #define SIS_RXFILTCTL_BROAD 0x40000000 278 #define SIS_RXFILTCTL_ENABLE 0x80000000 279 280 #define SIS_FILTADDR_PAR0 0x00000000 281 #define SIS_FILTADDR_PAR1 0x00010000 282 #define SIS_FILTADDR_PAR2 0x00020000 283 #define SIS_FILTADDR_MAR0 0x00040000 284 #define SIS_FILTADDR_MAR1 0x00050000 285 #define SIS_FILTADDR_MAR2 0x00060000 286 #define SIS_FILTADDR_MAR3 0x00070000 287 #define SIS_FILTADDR_MAR4 0x00080000 288 #define SIS_FILTADDR_MAR5 0x00090000 289 #define SIS_FILTADDR_MAR6 0x000A0000 290 #define SIS_FILTADDR_MAR7 0x000B0000 291 292 #define NS_FILTADDR_PAR0 0x00000000 293 #define NS_FILTADDR_PAR1 0x00000002 294 #define NS_FILTADDR_PAR2 0x00000004 295 296 #define NS_FILTADDR_FMEM_LO 0x00000200 297 #define NS_FILTADDR_FMEM_HI 0x000003FE 298 299 /* 300 * DMA descriptor structures. 301 */ 302 struct sis_desc { 303 /* SiS hardware descriptor section */ 304 uint32_t sis_next; 305 uint32_t sis_cmdsts; 306 #define sis_rxstat sis_cmdsts 307 #define sis_txstat sis_cmdsts 308 #define sis_ctl sis_cmdsts 309 uint32_t sis_ptr; 310 }; 311 312 #define SIS_RING_ALIGN 4 313 314 #define SIS_CMDSTS_BUFLEN 0x00000FFF 315 #define SIS_CMDSTS_PKT_OK 0x08000000 316 #define SIS_CMDSTS_CRC 0x10000000 317 #define SIS_CMDSTS_INTR 0x20000000 318 #define SIS_CMDSTS_MORE 0x40000000 319 #define SIS_CMDSTS_OWN 0x80000000 320 321 #define SIS_LASTDESC(x) (!((x)->sis_ctl & SIS_CMDSTS_MORE))) 322 #define SIS_OWNDESC(x) ((x)->sis_ctl & SIS_CMDSTS_OWN) 323 #define SIS_INC(x, y) (x) = ((x) == ((y)-1)) ? 0 : (x)+1 324 #define SIS_RXBYTES(x) (((x)->sis_ctl & SIS_CMDSTS_BUFLEN) - ETHER_CRC_LEN) 325 326 #define SIS_RXSTAT_COLL 0x00010000 327 #define SIS_RXSTAT_LOOPBK 0x00020000 328 #define SIS_RXSTAT_ALIGNERR 0x00040000 329 #define SIS_RXSTAT_CRCERR 0x00080000 330 #define SIS_RXSTAT_SYMBOLERR 0x00100000 331 #define SIS_RXSTAT_RUNT 0x00200000 332 #define SIS_RXSTAT_GIANT 0x00400000 333 #define SIS_RXSTAT_DSTCLASS 0x01800000 334 #define SIS_RXSTAT_OVERRUN 0x02000000 335 #define SIS_RXSTAT_RX_ABORT 0x04000000 336 337 #define SIS_DSTCLASS_REJECT 0x00000000 338 #define SIS_DSTCLASS_UNICAST 0x00800000 339 #define SIS_DSTCLASS_MULTICAST 0x01000000 340 #define SIS_DSTCLASS_BROADCAST 0x02000000 341 342 #define SIS_TXSTAT_COLLCNT 0x000F0000 343 #define SIS_TXSTAT_EXCESSCOLLS 0x00100000 344 #define SIS_TXSTAT_OUTOFWINCOLL 0x00200000 345 #define SIS_TXSTAT_EXCESS_DEFER 0x00400000 346 #define SIS_TXSTAT_DEFERED 0x00800000 347 #define SIS_TXSTAT_CARR_LOST 0x01000000 348 #define SIS_TXSTAT_UNDERRUN 0x02000000 349 #define SIS_TXSTAT_TX_ABORT 0x04000000 350 351 #define SIS_RX_LIST_CNT 64 352 #define SIS_TX_LIST_CNT 128 353 354 #define SIS_RX_LIST_SZ (SIS_RX_LIST_CNT * sizeof(struct sis_desc)) 355 #define SIS_TX_LIST_SZ (SIS_TX_LIST_CNT * sizeof(struct sis_desc)) 356 357 struct sis_list_data { 358 bus_dma_tag_t sis_rx_tag; 359 bus_dmamap_t sis_rx_dmamap; 360 struct sis_desc *sis_rx_list; 361 bus_addr_t sis_rx_paddr; 362 363 bus_dma_tag_t sis_tx_tag; 364 bus_dmamap_t sis_tx_dmamap; 365 struct sis_desc *sis_tx_list; 366 bus_addr_t sis_tx_paddr; 367 }; 368 369 struct sis_rx_data { 370 struct mbuf *sis_mbuf; 371 bus_dmamap_t sis_map; 372 bus_addr_t sis_paddr; 373 }; 374 375 struct sis_tx_data { 376 struct mbuf *sis_mbuf; 377 bus_dmamap_t sis_map; 378 }; 379 380 struct sis_chain_data { 381 bus_dma_tag_t sis_rxbuf_tag; 382 bus_dmamap_t sis_rx_tmpmap; 383 struct sis_rx_data sis_rx_data[SIS_RX_LIST_CNT]; 384 int sis_rx_prod; 385 386 bus_dma_tag_t sis_txbuf_tag; 387 struct sis_tx_data sis_tx_data[SIS_TX_LIST_CNT]; 388 int sis_tx_prod; 389 int sis_tx_cons; 390 int sis_tx_cnt; 391 }; 392 393 /* 394 * SiS 900 PCI revision codes. 395 */ 396 #define SIS_REV_900B 0x0003 397 #define SIS_REV_630A 0x0080 398 #define SIS_REV_630E 0x0081 399 #define SIS_REV_630S 0x0082 400 #define SIS_REV_630EA1 0x0083 401 #define SIS_REV_630ET 0x0084 402 #define SIS_REV_635 0x0090 403 #define SIS_REV_96x 0x0091 404 405 struct sis_type { 406 uint16_t sis_vid; 407 uint16_t sis_did; 408 char *sis_name; 409 }; 410 411 struct sis_mii_frame { 412 uint8_t mii_stdelim; 413 uint8_t mii_opcode; 414 uint8_t mii_phyaddr; 415 uint8_t mii_regaddr; 416 uint8_t mii_turnaround; 417 uint16_t mii_data; 418 }; 419 420 /* 421 * MII constants 422 */ 423 #define SIS_MII_STARTDELIM 0x01 424 #define SIS_MII_READOP 0x02 425 #define SIS_MII_WRITEOP 0x01 426 #define SIS_MII_TURNAROUND 0x02 427 428 #define SIS_TYPE_900 1 429 #define SIS_TYPE_7016 2 430 #define SIS_TYPE_83815 3 431 432 struct sis_softc { 433 struct arpcom arpcom; /* interface info */ 434 bus_space_handle_t sis_bhandle; 435 bus_space_tag_t sis_btag; 436 struct resource *sis_res; 437 struct resource *sis_irq; 438 void *sis_intrhand; 439 device_t sis_miibus; 440 uint8_t sis_type; 441 uint8_t sis_rev; 442 uint8_t sis_link; 443 struct ifpoll_compat sis_npoll; 444 struct sis_list_data sis_ldata; 445 bus_dma_tag_t sis_parent_tag; 446 struct sis_chain_data sis_cdata; 447 struct callout sis_timer; 448 int rxcycles; 449 }; 450 451 #define SIS_RXBUF_ALIGN 4 452 #define SIS_NSEGS 32 /* XXX limitted by TX desc cnt */ 453 #define SIS_NSEGS_RESERVED 1 454 455 #define SIS_IS_OACTIVE(sc) \ 456 ((sc)->sis_cdata.sis_tx_cnt + SIS_NSEGS_RESERVED >= SIS_TX_LIST_CNT) 457 458 /* 459 * register space access macros 460 */ 461 #define CSR_WRITE_4(sc, reg, val) \ 462 bus_space_write_4(sc->sis_btag, sc->sis_bhandle, reg, val) 463 464 #define CSR_READ_4(sc, reg) \ 465 bus_space_read_4(sc->sis_btag, sc->sis_bhandle, reg) 466 467 #define CSR_READ_2(sc, reg) \ 468 bus_space_read_2(sc->sis_btag, sc->sis_bhandle, reg) 469 470 #define SIS_TIMEOUT 1000 471 #define ETHER_ALIGN 2 472 #define SIS_RXLEN 1536 473 #define SIS_MIN_FRAMELEN 60 474 475 /* 476 * PCI low memory base and low I/O base register, and 477 * other PCI registers. 478 */ 479 480 #define SIS_PCI_VENDOR_ID 0x00 481 #define SIS_PCI_DEVICE_ID 0x02 482 #define SIS_PCI_COMMAND 0x04 483 #define SIS_PCI_STATUS 0x06 484 #define SIS_PCI_REVID 0x08 485 #define SIS_PCI_CLASSCODE 0x09 486 #define SIS_PCI_CACHELEN 0x0C 487 #define SIS_PCI_LATENCY_TIMER 0x0D 488 #define SIS_PCI_HEADER_TYPE 0x0E 489 #define SIS_PCI_LOIO 0x10 490 #define SIS_PCI_LOMEM 0x14 491 #define SIS_PCI_BIOSROM 0x30 492 #define SIS_PCI_INTLINE 0x3C 493 #define SIS_PCI_INTPIN 0x3D 494 #define SIS_PCI_MINGNT 0x3E 495 #define SIS_PCI_MINLAT 0x0F 496 #define SIS_PCI_RESETOPT 0x48 497 #define SIS_PCI_EEPROM_DATA 0x4C 498 499 /* power management registers */ 500 #define SIS_PCI_CAPID 0x50 /* 8 bits */ 501 #define SIS_PCI_NEXTPTR 0x51 /* 8 bits */ 502 #define SIS_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 503 #define SIS_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 504 505 #define SIS_PSTATE_MASK 0x0003 506 #define SIS_PSTATE_D0 0x0000 507 #define SIS_PSTATE_D1 0x0001 508 #define SIS_PSTATE_D2 0x0002 509 #define SIS_PSTATE_D3 0x0003 510 #define SIS_PME_EN 0x0010 511 #define SIS_PME_STATUS 0x8000 512