1 /*-
2 * Device driver optimized for the Symbios/LSI 53C896/53C895A/53C1010
3 * PCI-SCSI controllers.
4 *
5 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr>
6 *
7 * This driver also supports the following Symbios/LSI PCI-SCSI chips:
8 * 53C810A, 53C825A, 53C860, 53C875, 53C876, 53C885, 53C895,
9 * 53C810, 53C815, 53C825 and the 53C1510D is 53C8XX mode.
10 *
11 *
12 * This driver for FreeBSD-CAM is derived from the Linux sym53c8xx driver.
13 * Copyright (C) 1998-1999 Gerard Roudier
14 *
15 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been
16 * a port of the FreeBSD ncr driver to Linux-1.2.13.
17 *
18 * The original ncr driver has been written for 386bsd and FreeBSD by
19 * Wolfgang Stanglmeier <wolf@cologne.de>
20 * Stefan Esser <se@mi.Uni-Koeln.de>
21 * Copyright (C) 1994 Wolfgang Stanglmeier
22 *
23 * The initialisation code, and part of the code that addresses
24 * FreeBSD-CAM services is based on the aic7xxx driver for FreeBSD-CAM
25 * written by Justin T. Gibbs.
26 *
27 * Other major contributions:
28 *
29 * NVRAM detection and reading.
30 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
31 *
32 *-----------------------------------------------------------------------------
33 *
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
36 * are met:
37 * 1. Redistributions of source code must retain the above copyright
38 * notice, this list of conditions and the following disclaimer.
39 * 2. Redistributions in binary form must reproduce the above copyright
40 * notice, this list of conditions and the following disclaimer in the
41 * documentation and/or other materials provided with the distribution.
42 * 3. The name of the author may not be used to endorse or promote products
43 * derived from this software without specific prior written permission.
44 *
45 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
49 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
55 * SUCH DAMAGE.
56 *
57 * $FreeBSD: src/sys/dev/sym/sym_hipd.c,v 1.76 2011/10/07 08:59:54 marius Exp $
58 */
59
60 #define SYM_DRIVER_NAME "sym-1.6.5-20000902"
61
62 /* #define SYM_DEBUG_GENERIC_SUPPORT */
63
64 #include <sys/param.h>
65
66 /*
67 * Driver configuration options.
68 */
69 #include "opt_sym.h"
70 #include <dev/disk/sym/sym_conf.h>
71
72
73 #include <sys/systm.h>
74 #include <sys/malloc.h>
75 #include <sys/endian.h>
76 #include <sys/kernel.h>
77 #include <sys/lock.h>
78 #include <sys/module.h>
79 #include <sys/bus.h>
80
81 #include <sys/proc.h>
82
83 #include <bus/pci/pcireg.h>
84 #include <bus/pci/pcivar.h>
85
86 #include <sys/rman.h>
87
88 #include <bus/cam/cam.h>
89 #include <bus/cam/cam_ccb.h>
90 #include <bus/cam/cam_sim.h>
91 #include <bus/cam/cam_xpt.h>
92 #include <bus/cam/cam_xpt_sim.h>
93 #include <bus/cam/cam_xpt_periph.h>
94 #include <bus/cam/cam_debug.h>
95
96
97 #include <bus/cam/scsi/scsi_all.h>
98 #include <bus/cam/scsi/scsi_message.h>
99
100 /* Short and quite clear integer types */
101 typedef int8_t s8;
102 typedef int16_t s16;
103 typedef int32_t s32;
104 typedef u_int8_t u8;
105 typedef u_int16_t u16;
106 typedef u_int32_t u32;
107
108 /*
109 * Driver definitions.
110 */
111 #include <dev/disk/sym/sym_defs.h>
112 #include <dev/disk/sym/sym_fw.h>
113
114 /*
115 * IA32 architecture does not reorder STORES and prevents
116 * LOADS from passing STORES. It is called `program order'
117 * by Intel and allows device drivers to deal with memory
118 * ordering by only ensuring that the code is not reordered
119 * by the compiler when ordering is required.
120 * Other architectures implement a weaker ordering that
121 * requires memory barriers (and also IO barriers when they
122 * make sense) to be used.
123 */
124
125 #if defined __x86_64__
126 #define MEMORY_BARRIER() do { ; } while(0)
127 #else
128 #error "Not supported platform"
129 #endif
130
131 /*
132 * A la VMS/CAM-3 queue management.
133 */
134
135 typedef struct sym_quehead {
136 struct sym_quehead *flink; /* Forward pointer */
137 struct sym_quehead *blink; /* Backward pointer */
138 } SYM_QUEHEAD;
139
140 #define sym_que_init(ptr) do { \
141 (ptr)->flink = (ptr); (ptr)->blink = (ptr); \
142 } while (0)
143
sym_que_first(struct sym_quehead * head)144 static __inline struct sym_quehead *sym_que_first(struct sym_quehead *head)
145 {
146 return (head->flink == head) ? NULL : head->flink;
147 }
148
sym_que_last(struct sym_quehead * head)149 static __inline struct sym_quehead *sym_que_last(struct sym_quehead *head)
150 {
151 return (head->blink == head) ? NULL : head->blink;
152 }
153
__sym_que_add(struct sym_quehead * new,struct sym_quehead * blink,struct sym_quehead * flink)154 static __inline void __sym_que_add(struct sym_quehead * new,
155 struct sym_quehead * blink,
156 struct sym_quehead * flink)
157 {
158 flink->blink = new;
159 new->flink = flink;
160 new->blink = blink;
161 blink->flink = new;
162 }
163
__sym_que_del(struct sym_quehead * blink,struct sym_quehead * flink)164 static __inline void __sym_que_del(struct sym_quehead * blink,
165 struct sym_quehead * flink)
166 {
167 flink->blink = blink;
168 blink->flink = flink;
169 }
170
sym_que_empty(struct sym_quehead * head)171 static __inline int sym_que_empty(struct sym_quehead *head)
172 {
173 return head->flink == head;
174 }
175
sym_que_splice(struct sym_quehead * list,struct sym_quehead * head)176 static __inline void sym_que_splice(struct sym_quehead *list,
177 struct sym_quehead *head)
178 {
179 struct sym_quehead *first = list->flink;
180
181 if (first != list) {
182 struct sym_quehead *last = list->blink;
183 struct sym_quehead *at = head->flink;
184
185 first->blink = head;
186 head->flink = first;
187
188 last->flink = at;
189 at->blink = last;
190 }
191 }
192
193 #define sym_que_entry(ptr, type, member) \
194 ((type *)((char *)(ptr)-(size_t)(&((type *)0)->member)))
195
196
197 #define sym_insque(new, pos) __sym_que_add(new, pos, (pos)->flink)
198
199 #define sym_remque(el) __sym_que_del((el)->blink, (el)->flink)
200
201 #define sym_insque_head(new, head) __sym_que_add(new, head, (head)->flink)
202
sym_remque_head(struct sym_quehead * head)203 static __inline struct sym_quehead *sym_remque_head(struct sym_quehead *head)
204 {
205 struct sym_quehead *elem = head->flink;
206
207 if (elem != head)
208 __sym_que_del(head, elem->flink);
209 else
210 elem = NULL;
211 return elem;
212 }
213
214 #define sym_insque_tail(new, head) __sym_que_add(new, (head)->blink, head)
215
sym_remque_tail(struct sym_quehead * head)216 static __inline struct sym_quehead *sym_remque_tail(struct sym_quehead *head)
217 {
218 struct sym_quehead *elem = head->blink;
219
220 if (elem != head)
221 __sym_que_del(elem->blink, head);
222 else
223 elem = NULL;
224 return elem;
225 }
226
227 /*
228 * This one may be useful.
229 */
230 #define FOR_EACH_QUEUED_ELEMENT(head, qp) \
231 for (qp = (head)->flink; qp != (head); qp = qp->flink)
232 /*
233 * FreeBSD does not offer our kind of queue in the CAM CCB.
234 * So, we have to cast.
235 */
236 #define sym_qptr(p) ((struct sym_quehead *) (p))
237
238 /*
239 * Simple bitmap operations.
240 */
241 #define sym_set_bit(p, n) (((u32 *)(p))[(n)>>5] |= (1<<((n)&0x1f)))
242 #define sym_clr_bit(p, n) (((u32 *)(p))[(n)>>5] &= ~(1<<((n)&0x1f)))
243 #define sym_is_bit(p, n) (((u32 *)(p))[(n)>>5] & (1<<((n)&0x1f)))
244
245 /*
246 * Number of tasks per device we want to handle.
247 */
248 #if SYM_CONF_MAX_TAG_ORDER > 8
249 #error "more than 256 tags per logical unit not allowed."
250 #endif
251 #define SYM_CONF_MAX_TASK (1<<SYM_CONF_MAX_TAG_ORDER)
252
253 /*
254 * Donnot use more tasks that we can handle.
255 */
256 #ifndef SYM_CONF_MAX_TAG
257 #define SYM_CONF_MAX_TAG SYM_CONF_MAX_TASK
258 #endif
259 #if SYM_CONF_MAX_TAG > SYM_CONF_MAX_TASK
260 #undef SYM_CONF_MAX_TAG
261 #define SYM_CONF_MAX_TAG SYM_CONF_MAX_TASK
262 #endif
263
264 /*
265 * This one means 'NO TAG for this job'
266 */
267 #define NO_TAG (256)
268
269 /*
270 * Number of SCSI targets.
271 */
272 #if SYM_CONF_MAX_TARGET > 16
273 #error "more than 16 targets not allowed."
274 #endif
275
276 /*
277 * Number of logical units per target.
278 */
279 #if SYM_CONF_MAX_LUN > 64
280 #error "more than 64 logical units per target not allowed."
281 #endif
282
283 /*
284 * Asynchronous pre-scaler (ns). Shall be 40 for
285 * the SCSI timings to be compliant.
286 */
287 #define SYM_CONF_MIN_ASYNC (40)
288
289 /*
290 * Number of entries in the START and DONE queues.
291 *
292 * We limit to 1 PAGE in order to succeed allocation of
293 * these queues. Each entry is 8 bytes long (2 DWORDS).
294 */
295 #ifdef SYM_CONF_MAX_START
296 #define SYM_CONF_MAX_QUEUE (SYM_CONF_MAX_START+2)
297 #else
298 #define SYM_CONF_MAX_QUEUE (7*SYM_CONF_MAX_TASK+2)
299 #define SYM_CONF_MAX_START (SYM_CONF_MAX_QUEUE-2)
300 #endif
301
302 #if SYM_CONF_MAX_QUEUE > PAGE_SIZE/8
303 #undef SYM_CONF_MAX_QUEUE
304 #define SYM_CONF_MAX_QUEUE PAGE_SIZE/8
305 #undef SYM_CONF_MAX_START
306 #define SYM_CONF_MAX_START (SYM_CONF_MAX_QUEUE-2)
307 #endif
308
309 /*
310 * For this one, we want a short name :-)
311 */
312 #define MAX_QUEUE SYM_CONF_MAX_QUEUE
313
314 /*
315 * Active debugging tags and verbosity.
316 */
317 #define DEBUG_ALLOC (0x0001)
318 #define DEBUG_PHASE (0x0002)
319 #define DEBUG_POLL (0x0004)
320 #define DEBUG_QUEUE (0x0008)
321 #define DEBUG_RESULT (0x0010)
322 #define DEBUG_SCATTER (0x0020)
323 #define DEBUG_SCRIPT (0x0040)
324 #define DEBUG_TINY (0x0080)
325 #define DEBUG_TIMING (0x0100)
326 #define DEBUG_NEGO (0x0200)
327 #define DEBUG_TAGS (0x0400)
328 #define DEBUG_POINTER (0x0800)
329
330 #if 0
331 static int sym_debug = 0;
332 #define DEBUG_FLAGS sym_debug
333 #else
334 /* #define DEBUG_FLAGS (0x0631) */
335 #define DEBUG_FLAGS (0x0000)
336
337 #endif
338 #define sym_verbose (np->verbose)
339
340 /*
341 * Insert a delay in micro-seconds and milli-seconds.
342 */
UDELAY(int us)343 static void UDELAY(int us) { DELAY(us); }
MDELAY(int ms)344 static void MDELAY(int ms) { while (ms--) UDELAY(1000); }
345
346 /*
347 * Simple power of two buddy-like allocator.
348 *
349 * This simple code is not intended to be fast, but to
350 * provide power of 2 aligned memory allocations.
351 * Since the SCRIPTS processor only supplies 8 bit arithmetic,
352 * this allocator allows simple and fast address calculations
353 * from the SCRIPTS code. In addition, cache line alignment
354 * is guaranteed for power of 2 cache line size.
355 *
356 * This allocator has been developed for the Linux sym53c8xx
357 * driver, since this O/S does not provide naturally aligned
358 * allocations.
359 * It has the advantage of allowing the driver to use private
360 * pages of memory that will be useful if we ever need to deal
361 * with IO MMUs for PCI.
362 */
363
364 #define MEMO_SHIFT 4 /* 16 bytes minimum memory chunk */
365 #define MEMO_PAGE_ORDER 0 /* 1 PAGE maximum */
366 #if 0
367 #define MEMO_FREE_UNUSED /* Free unused pages immediately */
368 #endif
369 #define MEMO_WARN 1
370 #define MEMO_CLUSTER_SHIFT (PAGE_SHIFT+MEMO_PAGE_ORDER)
371 #define MEMO_CLUSTER_SIZE (1UL << MEMO_CLUSTER_SHIFT)
372 #define MEMO_CLUSTER_MASK (MEMO_CLUSTER_SIZE-1)
373
374 #define get_pages() kmalloc(MEMO_CLUSTER_SIZE, M_DEVBUF, M_INTWAIT)
375 #define free_pages(p) kfree((p), M_DEVBUF)
376
377 typedef u_long m_addr_t; /* Enough bits to bit-hack addresses */
378
379 typedef struct m_link { /* Link between free memory chunks */
380 struct m_link *next;
381 } m_link_s;
382
383 typedef struct m_vtob { /* Virtual to Bus address translation */
384 struct m_vtob *next;
385 bus_dmamap_t dmamap; /* Map for this chunk */
386 m_addr_t vaddr; /* Virtual address */
387 m_addr_t baddr; /* Bus physical address */
388 } m_vtob_s;
389 /* Hash this stuff a bit to speed up translations */
390 #define VTOB_HASH_SHIFT 5
391 #define VTOB_HASH_SIZE (1UL << VTOB_HASH_SHIFT)
392 #define VTOB_HASH_MASK (VTOB_HASH_SIZE-1)
393 #define VTOB_HASH_CODE(m) \
394 ((((m_addr_t) (m)) >> MEMO_CLUSTER_SHIFT) & VTOB_HASH_MASK)
395
396 typedef struct m_pool { /* Memory pool of a given kind */
397 bus_dma_tag_t dev_dmat; /* Identifies the pool */
398 bus_dma_tag_t dmat; /* Tag for our fixed allocations */
399 m_addr_t (*getp)(struct m_pool *);
400 #ifdef MEMO_FREE_UNUSED
401 void (*freep)(struct m_pool *, m_addr_t);
402 #endif
403 #define M_GETP() mp->getp(mp)
404 #define M_FREEP(p) mp->freep(mp, p)
405 int nump;
406 m_vtob_s *(vtob[VTOB_HASH_SIZE]);
407 struct m_pool *next;
408 struct m_link h[MEMO_CLUSTER_SHIFT - MEMO_SHIFT + 1];
409 } m_pool_s;
410
___sym_malloc(m_pool_s * mp,int size)411 static void *___sym_malloc(m_pool_s *mp, int size)
412 {
413 int i = 0;
414 int s = (1 << MEMO_SHIFT);
415 int j;
416 m_addr_t a;
417 m_link_s *h = mp->h;
418
419 if (size > MEMO_CLUSTER_SIZE)
420 return NULL;
421
422 while (size > s) {
423 s <<= 1;
424 ++i;
425 }
426
427 j = i;
428 while (!h[j].next) {
429 if (s == MEMO_CLUSTER_SIZE) {
430 h[j].next = (m_link_s *) M_GETP();
431 if (h[j].next)
432 h[j].next->next = NULL;
433 break;
434 }
435 ++j;
436 s <<= 1;
437 }
438 a = (m_addr_t) h[j].next;
439 if (a) {
440 h[j].next = h[j].next->next;
441 while (j > i) {
442 j -= 1;
443 s >>= 1;
444 h[j].next = (m_link_s *) (a+s);
445 h[j].next->next = NULL;
446 }
447 }
448 #ifdef DEBUG
449 kprintf("___sym_malloc(%d) = %p\n", size, (void *) a);
450 #endif
451 return (void *) a;
452 }
453
___sym_mfree(m_pool_s * mp,void * ptr,int size)454 static void ___sym_mfree(m_pool_s *mp, void *ptr, int size)
455 {
456 int i = 0;
457 int s = (1 << MEMO_SHIFT);
458 m_link_s *q;
459 m_addr_t a, b;
460 m_link_s *h = mp->h;
461
462 #ifdef DEBUG
463 kprintf("___sym_mfree(%p, %d)\n", ptr, size);
464 #endif
465
466 if (size > MEMO_CLUSTER_SIZE)
467 return;
468
469 while (size > s) {
470 s <<= 1;
471 ++i;
472 }
473
474 a = (m_addr_t) ptr;
475
476 while (1) {
477 #ifdef MEMO_FREE_UNUSED
478 if (s == MEMO_CLUSTER_SIZE) {
479 M_FREEP(a);
480 break;
481 }
482 #endif
483 b = a ^ s;
484 q = &h[i];
485 while (q->next && q->next != (m_link_s *) b) {
486 q = q->next;
487 }
488 if (!q->next) {
489 ((m_link_s *) a)->next = h[i].next;
490 h[i].next = (m_link_s *) a;
491 break;
492 }
493 q->next = q->next->next;
494 a = a & b;
495 s <<= 1;
496 ++i;
497 }
498 }
499
__sym_calloc2(m_pool_s * mp,int size,char * name,int uflags)500 static void *__sym_calloc2(m_pool_s *mp, int size, char *name, int uflags)
501 {
502 void *p;
503
504 p = ___sym_malloc(mp, size);
505
506 if (DEBUG_FLAGS & DEBUG_ALLOC)
507 kprintf ("new %-10s[%4d] @%p.\n", name, size, p);
508
509 if (p)
510 bzero(p, size);
511 else if (uflags & MEMO_WARN)
512 kprintf ("__sym_calloc2: failed to allocate %s[%d]\n", name, size);
513
514 return p;
515 }
516
517 #define __sym_calloc(mp, s, n) __sym_calloc2(mp, s, n, MEMO_WARN)
518
__sym_mfree(m_pool_s * mp,void * ptr,int size,char * name)519 static void __sym_mfree(m_pool_s *mp, void *ptr, int size, char *name)
520 {
521 if (DEBUG_FLAGS & DEBUG_ALLOC)
522 kprintf ("freeing %-10s[%4d] @%p.\n", name, size, ptr);
523
524 ___sym_mfree(mp, ptr, size);
525
526 }
527
528 /*
529 * Default memory pool we donnot need to involve in DMA.
530 */
531 /*
532 * With the `bus dma abstraction', we use a separate pool for
533 * memory we donnot need to involve in DMA.
534 */
___mp0_getp(m_pool_s * mp)535 static m_addr_t ___mp0_getp(m_pool_s *mp)
536 {
537 m_addr_t m = (m_addr_t) get_pages();
538 if (m)
539 ++mp->nump;
540 return m;
541 }
542
543 #ifdef MEMO_FREE_UNUSED
___mp0_freep(m_pool_s * mp,m_addr_t m)544 static void ___mp0_freep(m_pool_s *mp, m_addr_t m)
545 {
546 free_pages(m);
547 --mp->nump;
548 }
549 #endif
550
551 #ifdef MEMO_FREE_UNUSED
552 static m_pool_s mp0 = {0, 0, ___mp0_getp, ___mp0_freep};
553 #else
554 static m_pool_s mp0 = {0, 0, ___mp0_getp};
555 #endif
556
557
558 /*
559 * Actual memory allocation routine for non-DMAed memory.
560 */
sym_calloc(int size,char * name)561 static void *sym_calloc(int size, char *name)
562 {
563 void *m;
564 /* Lock */
565 m = __sym_calloc(&mp0, size, name);
566 /* Unlock */
567 return m;
568 }
569
570 /*
571 * Actual memory allocation routine for non-DMAed memory.
572 */
sym_mfree(void * ptr,int size,char * name)573 static void sym_mfree(void *ptr, int size, char *name)
574 {
575 /* Lock */
576 __sym_mfree(&mp0, ptr, size, name);
577 /* Unlock */
578 }
579
580 /*
581 * DMAable pools.
582 */
583 /*
584 * With `bus dma abstraction', we use a separate pool per parent
585 * BUS handle. A reverse table (hashed) is maintained for virtual
586 * to BUS address translation.
587 */
getbaddrcb(void * arg,bus_dma_segment_t * segs,int nseg,int error)588 static void getbaddrcb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
589 {
590 bus_addr_t *baddr;
591 baddr = (bus_addr_t *)arg;
592 *baddr = segs->ds_addr;
593 }
594
___dma_getp(m_pool_s * mp)595 static m_addr_t ___dma_getp(m_pool_s *mp)
596 {
597 m_vtob_s *vbp;
598 void *vaddr = NULL;
599 bus_addr_t baddr = 0;
600
601 vbp = __sym_calloc(&mp0, sizeof(*vbp), "VTOB");
602 if (!vbp)
603 goto out_err;
604
605 if (bus_dmamem_alloc(mp->dmat, &vaddr,
606 BUS_DMA_COHERENT | BUS_DMA_WAITOK, &vbp->dmamap))
607 goto out_err;
608 bus_dmamap_load(mp->dmat, vbp->dmamap, vaddr,
609 MEMO_CLUSTER_SIZE, getbaddrcb, &baddr, BUS_DMA_NOWAIT);
610 if (baddr) {
611 int hc = VTOB_HASH_CODE(vaddr);
612 vbp->vaddr = (m_addr_t) vaddr;
613 vbp->baddr = (m_addr_t) baddr;
614 vbp->next = mp->vtob[hc];
615 mp->vtob[hc] = vbp;
616 ++mp->nump;
617 return (m_addr_t) vaddr;
618 }
619 out_err:
620 if (baddr)
621 bus_dmamap_unload(mp->dmat, vbp->dmamap);
622 if (vaddr)
623 bus_dmamem_free(mp->dmat, vaddr, vbp->dmamap);
624 if (vbp) {
625 if (vbp->dmamap)
626 bus_dmamap_destroy(mp->dmat, vbp->dmamap);
627 __sym_mfree(&mp0, vbp, sizeof(*vbp), "VTOB");
628 }
629 return 0;
630 }
631
632 #ifdef MEMO_FREE_UNUSED
___dma_freep(m_pool_s * mp,m_addr_t m)633 static void ___dma_freep(m_pool_s *mp, m_addr_t m)
634 {
635 m_vtob_s **vbpp, *vbp;
636 int hc = VTOB_HASH_CODE(m);
637
638 vbpp = &mp->vtob[hc];
639 while (*vbpp && (*vbpp)->vaddr != m)
640 vbpp = &(*vbpp)->next;
641 if (*vbpp) {
642 vbp = *vbpp;
643 *vbpp = (*vbpp)->next;
644 bus_dmamap_unload(mp->dmat, vbp->dmamap);
645 bus_dmamem_free(mp->dmat, (void *) vbp->vaddr, vbp->dmamap);
646 bus_dmamap_destroy(mp->dmat, vbp->dmamap);
647 __sym_mfree(&mp0, vbp, sizeof(*vbp), "VTOB");
648 --mp->nump;
649 }
650 }
651 #endif
652
___get_dma_pool(bus_dma_tag_t dev_dmat)653 static __inline m_pool_s *___get_dma_pool(bus_dma_tag_t dev_dmat)
654 {
655 m_pool_s *mp;
656 for (mp = mp0.next; mp && mp->dev_dmat != dev_dmat; mp = mp->next);
657 return mp;
658 }
659
___cre_dma_pool(bus_dma_tag_t dev_dmat)660 static m_pool_s *___cre_dma_pool(bus_dma_tag_t dev_dmat)
661 {
662 m_pool_s *mp = NULL;
663
664 mp = __sym_calloc(&mp0, sizeof(*mp), "MPOOL");
665 if (mp) {
666 mp->dev_dmat = dev_dmat;
667 if (!bus_dma_tag_create(dev_dmat, 1, MEMO_CLUSTER_SIZE,
668 BUS_SPACE_MAXADDR_32BIT,
669 BUS_SPACE_MAXADDR,
670 MEMO_CLUSTER_SIZE, 1,
671 MEMO_CLUSTER_SIZE, 0,
672 &mp->dmat)) {
673 mp->getp = ___dma_getp;
674 #ifdef MEMO_FREE_UNUSED
675 mp->freep = ___dma_freep;
676 #endif
677 mp->next = mp0.next;
678 mp0.next = mp;
679 return mp;
680 }
681 }
682 if (mp)
683 __sym_mfree(&mp0, mp, sizeof(*mp), "MPOOL");
684 return NULL;
685 }
686
687 #ifdef MEMO_FREE_UNUSED
___del_dma_pool(m_pool_s * p)688 static void ___del_dma_pool(m_pool_s *p)
689 {
690 struct m_pool **pp = &mp0.next;
691
692 while (*pp && *pp != p)
693 pp = &(*pp)->next;
694 if (*pp) {
695 *pp = (*pp)->next;
696 bus_dma_tag_destroy(p->dmat);
697 __sym_mfree(&mp0, p, sizeof(*p), "MPOOL");
698 }
699 }
700 #endif
701
__sym_calloc_dma(bus_dma_tag_t dev_dmat,int size,char * name)702 static void *__sym_calloc_dma(bus_dma_tag_t dev_dmat, int size, char *name)
703 {
704 struct m_pool *mp;
705 void *m = NULL;
706
707 /* Lock */
708 mp = ___get_dma_pool(dev_dmat);
709 if (!mp)
710 mp = ___cre_dma_pool(dev_dmat);
711 if (mp)
712 m = __sym_calloc(mp, size, name);
713 #ifdef MEMO_FREE_UNUSED
714 if (mp && !mp->nump)
715 ___del_dma_pool(mp);
716 #endif
717 /* Unlock */
718
719 return m;
720 }
721
722 static void
__sym_mfree_dma(bus_dma_tag_t dev_dmat,void * m,int size,char * name)723 __sym_mfree_dma(bus_dma_tag_t dev_dmat, void *m, int size, char *name)
724 {
725 struct m_pool *mp;
726
727 /* Lock */
728 mp = ___get_dma_pool(dev_dmat);
729 if (mp)
730 __sym_mfree(mp, m, size, name);
731 #ifdef MEMO_FREE_UNUSED
732 if (mp && !mp->nump)
733 ___del_dma_pool(mp);
734 #endif
735 /* Unlock */
736 }
737
__vtobus(bus_dma_tag_t dev_dmat,void * m)738 static m_addr_t __vtobus(bus_dma_tag_t dev_dmat, void *m)
739 {
740 m_pool_s *mp;
741 int hc = VTOB_HASH_CODE(m);
742 m_vtob_s *vp = NULL;
743 m_addr_t a = ((m_addr_t) m) & ~MEMO_CLUSTER_MASK;
744
745 /* Lock */
746 mp = ___get_dma_pool(dev_dmat);
747 if (mp) {
748 vp = mp->vtob[hc];
749 while (vp && vp->vaddr != a)
750 vp = vp->next;
751 }
752 /* Unlock */
753 if (!vp)
754 panic("sym: VTOBUS FAILED!");
755 return vp ? vp->baddr + (((m_addr_t) m) - a) : 0;
756 }
757
758
759 /*
760 * Verbs for DMAable memory handling.
761 * The _uvptv_ macro avoids a nasty warning about pointer to volatile
762 * being discarded.
763 */
764 #define _uvptv_(p) ((void *)((vm_offset_t)(p)))
765 #define _sym_calloc_dma(np, s, n) __sym_calloc_dma(np->bus_dmat, s, n)
766 #define _sym_mfree_dma(np, p, s, n) \
767 __sym_mfree_dma(np->bus_dmat, _uvptv_(p), s, n)
768 #define sym_calloc_dma(s, n) _sym_calloc_dma(np, s, n)
769 #define sym_mfree_dma(p, s, n) _sym_mfree_dma(np, p, s, n)
770 #define _vtobus(np, p) __vtobus(np->bus_dmat, _uvptv_(p))
771 #define vtobus(p) _vtobus(np, p)
772
773
774 /*
775 * Print a buffer in hexadecimal format.
776 */
sym_printb_hex(u_char * p,int n)777 static void sym_printb_hex (u_char *p, int n)
778 {
779 while (n-- > 0)
780 kprintf (" %x", *p++);
781 }
782
783 /*
784 * Same with a label at beginning and .\n at end.
785 */
sym_printl_hex(char * label,u_char * p,int n)786 static void sym_printl_hex (char *label, u_char *p, int n)
787 {
788 kprintf ("%s", label);
789 sym_printb_hex (p, n);
790 kprintf (".\n");
791 }
792
793 /*
794 * Return a string for SCSI BUS mode.
795 */
sym_scsi_bus_mode(int mode)796 static const char *sym_scsi_bus_mode(int mode)
797 {
798 switch(mode) {
799 case SMODE_HVD: return "HVD";
800 case SMODE_SE: return "SE";
801 case SMODE_LVD: return "LVD";
802 }
803 return "??";
804 }
805
806 /*
807 * Some poor and bogus sync table that refers to Tekram NVRAM layout.
808 */
809 #ifdef SYM_CONF_NVRAM_SUPPORT
810 static const u_char Tekram_sync[16] =
811 {25,31,37,43, 50,62,75,125, 12,15,18,21, 6,7,9,10};
812 #endif
813
814 /*
815 * Union of supported NVRAM formats.
816 */
817 struct sym_nvram {
818 int type;
819 #define SYM_SYMBIOS_NVRAM (1)
820 #define SYM_TEKRAM_NVRAM (2)
821 #ifdef SYM_CONF_NVRAM_SUPPORT
822 union {
823 Symbios_nvram Symbios;
824 Tekram_nvram Tekram;
825 } data;
826 #endif
827 };
828
829 /*
830 * This one is hopefully useless, but actually useful. :-)
831 */
832 #ifndef assert
833 #define assert(expression) { \
834 if (!(expression)) { \
835 (void)panic( \
836 "assertion \"%s\" failed: file \"%s\", line %d", \
837 #expression, \
838 __FILE__, __LINE__); \
839 } \
840 }
841 #endif
842
843 /*
844 * Some provision for a possible big endian mode supported by
845 * Symbios chips (never seen, by the way).
846 * For now, this stuff does not deserve any comments. :)
847 */
848
849 #define sym_offb(o) (o)
850 #define sym_offw(o) (o)
851
852 /*
853 * Some provision for support for BIG ENDIAN CPU.
854 */
855
856 #define cpu_to_scr(dw) htole32(dw)
857 #define scr_to_cpu(dw) le32toh(dw)
858
859 /*
860 * Access to the chip IO registers and on-chip RAM.
861 * We use the `bus space' interface under FreeBSD-4 and
862 * later kernel versions.
863 */
864
865
866 #if defined(SYM_CONF_IOMAPPED)
867
868 #define INB_OFF(o) bus_read_1(np->io_res, (o))
869 #define INW_OFF(o) bus_read_2(np->io_res, (o))
870 #define INL_OFF(o) bus_read_4(np->io_res, (o))
871
872 #define OUTB_OFF(o, v) bus_write_1(np->io_res, (o), (v))
873 #define OUTW_OFF(o, v) bus_write_2(np->io_res, (o), (v))
874 #define OUTL_OFF(o, v) bus_write_4(np->io_res, (o), (v))
875
876 #else /* Memory mapped IO */
877
878 #define INB_OFF(o) bus_read_1(np->mmio_res, (o))
879 #define INW_OFF(o) bus_read_2(np->mmio_res, (o))
880 #define INL_OFF(o) bus_read_4(np->mmio_res, (o))
881
882 #define OUTB_OFF(o, v) bus_write_1(np->mmio_res, (o), (v))
883 #define OUTW_OFF(o, v) bus_write_2(np->mmio_res, (o), (v))
884 #define OUTL_OFF(o, v) bus_write_4(np->mmio_res, (o), (v))
885
886 #endif /* SYM_CONF_IOMAPPED */
887
888 #define OUTRAM_OFF(o, a, l) \
889 bus_write_region_1(np->ram_res, (o), (a), (l))
890
891
892 /*
893 * Common definitions for both bus space and legacy IO methods.
894 */
895 #define INB(r) INB_OFF(offsetof(struct sym_reg,r))
896 #define INW(r) INW_OFF(offsetof(struct sym_reg,r))
897 #define INL(r) INL_OFF(offsetof(struct sym_reg,r))
898
899 #define OUTB(r, v) OUTB_OFF(offsetof(struct sym_reg,r), (v))
900 #define OUTW(r, v) OUTW_OFF(offsetof(struct sym_reg,r), (v))
901 #define OUTL(r, v) OUTL_OFF(offsetof(struct sym_reg,r), (v))
902
903 #define OUTONB(r, m) OUTB(r, INB(r) | (m))
904 #define OUTOFFB(r, m) OUTB(r, INB(r) & ~(m))
905 #define OUTONW(r, m) OUTW(r, INW(r) | (m))
906 #define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m))
907 #define OUTONL(r, m) OUTL(r, INL(r) | (m))
908 #define OUTOFFL(r, m) OUTL(r, INL(r) & ~(m))
909
910 /*
911 * We normally want the chip to have a consistent view
912 * of driver internal data structures when we restart it.
913 * Thus these macros.
914 */
915 #define OUTL_DSP(v) \
916 do { \
917 MEMORY_BARRIER(); \
918 OUTL (nc_dsp, (v)); \
919 } while (0)
920
921 #define OUTONB_STD() \
922 do { \
923 MEMORY_BARRIER(); \
924 OUTONB (nc_dcntl, (STD|NOCOM)); \
925 } while (0)
926
927 /*
928 * Command control block states.
929 */
930 #define HS_IDLE (0)
931 #define HS_BUSY (1)
932 #define HS_NEGOTIATE (2) /* sync/wide data transfer*/
933 #define HS_DISCONNECT (3) /* Disconnected by target */
934 #define HS_WAIT (4) /* waiting for resource */
935
936 #define HS_DONEMASK (0x80)
937 #define HS_COMPLETE (4|HS_DONEMASK)
938 #define HS_SEL_TIMEOUT (5|HS_DONEMASK) /* Selection timeout */
939 #define HS_UNEXPECTED (6|HS_DONEMASK) /* Unexpected disconnect */
940 #define HS_COMP_ERR (7|HS_DONEMASK) /* Completed with error */
941
942 /*
943 * Software Interrupt Codes
944 */
945 #define SIR_BAD_SCSI_STATUS (1)
946 #define SIR_SEL_ATN_NO_MSG_OUT (2)
947 #define SIR_MSG_RECEIVED (3)
948 #define SIR_MSG_WEIRD (4)
949 #define SIR_NEGO_FAILED (5)
950 #define SIR_NEGO_PROTO (6)
951 #define SIR_SCRIPT_STOPPED (7)
952 #define SIR_REJECT_TO_SEND (8)
953 #define SIR_SWIDE_OVERRUN (9)
954 #define SIR_SODL_UNDERRUN (10)
955 #define SIR_RESEL_NO_MSG_IN (11)
956 #define SIR_RESEL_NO_IDENTIFY (12)
957 #define SIR_RESEL_BAD_LUN (13)
958 #define SIR_TARGET_SELECTED (14)
959 #define SIR_RESEL_BAD_I_T_L (15)
960 #define SIR_RESEL_BAD_I_T_L_Q (16)
961 #define SIR_ABORT_SENT (17)
962 #define SIR_RESEL_ABORTED (18)
963 #define SIR_MSG_OUT_DONE (19)
964 #define SIR_COMPLETE_ERROR (20)
965 #define SIR_DATA_OVERRUN (21)
966 #define SIR_BAD_PHASE (22)
967 #define SIR_MAX (22)
968
969 /*
970 * Extended error bit codes.
971 * xerr_status field of struct sym_ccb.
972 */
973 #define XE_EXTRA_DATA (1) /* unexpected data phase */
974 #define XE_BAD_PHASE (1<<1) /* illegal phase (4/5) */
975 #define XE_PARITY_ERR (1<<2) /* unrecovered SCSI parity error */
976 #define XE_SODL_UNRUN (1<<3) /* ODD transfer in DATA OUT phase */
977 #define XE_SWIDE_OVRUN (1<<4) /* ODD transfer in DATA IN phase */
978
979 /*
980 * Negotiation status.
981 * nego_status field of struct sym_ccb.
982 */
983 #define NS_SYNC (1)
984 #define NS_WIDE (2)
985 #define NS_PPR (3)
986
987 /*
988 * A CCB hashed table is used to retrieve CCB address
989 * from DSA value.
990 */
991 #define CCB_HASH_SHIFT 8
992 #define CCB_HASH_SIZE (1UL << CCB_HASH_SHIFT)
993 #define CCB_HASH_MASK (CCB_HASH_SIZE-1)
994 #define CCB_HASH_CODE(dsa) (((dsa) >> 9) & CCB_HASH_MASK)
995
996 /*
997 * Device flags.
998 */
999 #define SYM_DISC_ENABLED (1)
1000 #define SYM_TAGS_ENABLED (1<<1)
1001 #define SYM_SCAN_BOOT_DISABLED (1<<2)
1002 #define SYM_SCAN_LUNS_DISABLED (1<<3)
1003
1004 /*
1005 * Host adapter miscellaneous flags.
1006 */
1007 #define SYM_AVOID_BUS_RESET (1)
1008 #define SYM_SCAN_TARGETS_HILO (1<<1)
1009
1010 /*
1011 * Device quirks.
1012 * Some devices, for example the CHEETAH 2 LVD, disconnects without
1013 * saving the DATA POINTER then reselects and terminates the IO.
1014 * On reselection, the automatic RESTORE DATA POINTER makes the
1015 * CURRENT DATA POINTER not point at the end of the IO.
1016 * This behaviour just breaks our calculation of the residual.
1017 * For now, we just force an AUTO SAVE on disconnection and will
1018 * fix that in a further driver version.
1019 */
1020 #define SYM_QUIRK_AUTOSAVE 1
1021
1022 /*
1023 * Misc.
1024 */
1025 #define SYM_LOCK() lockmgr(&np->lock, LK_EXCLUSIVE)
1026 #define SYM_LOCK_ASSERT(_what) KKASSERT(lockstatus(&np->lock, curthread) == (_what))
1027 #define SYM_LOCK_DESTROY() lockuninit(&np->lock)
1028 #define SYM_LOCK_INIT() lockinit(&np->lock, "sym_lock", 0, LK_CANRECURSE)
1029 #if 0 /* XXX swildner */
1030 #define SYM_LOCK_INITIALIZED() mtx_initialized(&np->lock)
1031 #endif
1032 #define SYM_UNLOCK() lockmgr(&np->lock, LK_RELEASE)
1033
1034 #define SYM_SNOOP_TIMEOUT (10000000)
1035 #define SYM_PCI_IO PCIR_BAR(0)
1036 #define SYM_PCI_MMIO PCIR_BAR(1)
1037 #define SYM_PCI_RAM PCIR_BAR(2)
1038 #define SYM_PCI_RAM64 PCIR_BAR(3)
1039
1040 /*
1041 * Back-pointer from the CAM CCB to our data structures.
1042 */
1043 #define sym_hcb_ptr spriv_ptr0
1044 /* #define sym_ccb_ptr spriv_ptr1 */
1045
1046 /*
1047 * We mostly have to deal with pointers.
1048 * Thus these typedef's.
1049 */
1050 typedef struct sym_tcb *tcb_p;
1051 typedef struct sym_lcb *lcb_p;
1052 typedef struct sym_ccb *ccb_p;
1053 typedef struct sym_hcb *hcb_p;
1054
1055 /*
1056 * Gather negotiable parameters value
1057 */
1058 struct sym_trans {
1059 u8 scsi_version;
1060 u8 spi_version;
1061 u8 period;
1062 u8 offset;
1063 u8 width;
1064 u8 options; /* PPR options */
1065 };
1066
1067 struct sym_tinfo {
1068 struct sym_trans current;
1069 struct sym_trans goal;
1070 struct sym_trans user;
1071 };
1072
1073 #define BUS_8_BIT MSG_EXT_WDTR_BUS_8_BIT
1074 #define BUS_16_BIT MSG_EXT_WDTR_BUS_16_BIT
1075
1076 /*
1077 * Global TCB HEADER.
1078 *
1079 * Due to lack of indirect addressing on earlier NCR chips,
1080 * this substructure is copied from the TCB to a global
1081 * address after selection.
1082 * For SYMBIOS chips that support LOAD/STORE this copy is
1083 * not needed and thus not performed.
1084 */
1085 struct sym_tcbh {
1086 /*
1087 * Scripts bus addresses of LUN table accessed from scripts.
1088 * LUN #0 is a special case, since multi-lun devices are rare,
1089 * and we we want to speed-up the general case and not waste
1090 * resources.
1091 */
1092 u32 luntbl_sa; /* bus address of this table */
1093 u32 lun0_sa; /* bus address of LCB #0 */
1094 /*
1095 * Actual SYNC/WIDE IO registers value for this target.
1096 * 'sval', 'wval' and 'uval' are read from SCRIPTS and
1097 * so have alignment constraints.
1098 */
1099 /*0*/ u_char uval; /* -> SCNTL4 register */
1100 /*1*/ u_char sval; /* -> SXFER io register */
1101 /*2*/ u_char filler1;
1102 /*3*/ u_char wval; /* -> SCNTL3 io register */
1103 };
1104
1105 /*
1106 * Target Control Block
1107 */
1108 struct sym_tcb {
1109 /*
1110 * TCB header.
1111 * Assumed at offset 0.
1112 */
1113 /*0*/ struct sym_tcbh head;
1114
1115 /*
1116 * LUN table used by the SCRIPTS processor.
1117 * An array of bus addresses is used on reselection.
1118 */
1119 u32 *luntbl; /* LCBs bus address table */
1120
1121 /*
1122 * LUN table used by the C code.
1123 */
1124 lcb_p lun0p; /* LCB of LUN #0 (usual case) */
1125 #if SYM_CONF_MAX_LUN > 1
1126 lcb_p *lunmp; /* Other LCBs [1..MAX_LUN] */
1127 #endif
1128
1129 /*
1130 * Bitmap that tells about LUNs that succeeded at least
1131 * 1 IO and therefore assumed to be a real device.
1132 * Avoid useless allocation of the LCB structure.
1133 */
1134 u32 lun_map[(SYM_CONF_MAX_LUN+31)/32];
1135
1136 /*
1137 * Bitmap that tells about LUNs that haven't yet an LCB
1138 * allocated (not discovered or LCB allocation failed).
1139 */
1140 u32 busy0_map[(SYM_CONF_MAX_LUN+31)/32];
1141
1142 /*
1143 * Transfer capabilities (SIP)
1144 */
1145 struct sym_tinfo tinfo;
1146
1147 /*
1148 * Keep track of the CCB used for the negotiation in order
1149 * to ensure that only 1 negotiation is queued at a time.
1150 */
1151 ccb_p nego_cp; /* CCB used for the nego */
1152
1153 /*
1154 * Set when we want to reset the device.
1155 */
1156 u_char to_reset;
1157
1158 /*
1159 * Other user settable limits and options.
1160 * These limits are read from the NVRAM if present.
1161 */
1162 u_char usrflags;
1163 u_short usrtags;
1164 };
1165
1166 /*
1167 * Global LCB HEADER.
1168 *
1169 * Due to lack of indirect addressing on earlier NCR chips,
1170 * this substructure is copied from the LCB to a global
1171 * address after selection.
1172 * For SYMBIOS chips that support LOAD/STORE this copy is
1173 * not needed and thus not performed.
1174 */
1175 struct sym_lcbh {
1176 /*
1177 * SCRIPTS address jumped by SCRIPTS on reselection.
1178 * For not probed logical units, this address points to
1179 * SCRIPTS that deal with bad LU handling (must be at
1180 * offset zero of the LCB for that reason).
1181 */
1182 /*0*/ u32 resel_sa;
1183
1184 /*
1185 * Task (bus address of a CCB) read from SCRIPTS that points
1186 * to the unique ITL nexus allowed to be disconnected.
1187 */
1188 u32 itl_task_sa;
1189
1190 /*
1191 * Task table bus address (read from SCRIPTS).
1192 */
1193 u32 itlq_tbl_sa;
1194 };
1195
1196 /*
1197 * Logical Unit Control Block
1198 */
1199 struct sym_lcb {
1200 /*
1201 * TCB header.
1202 * Assumed at offset 0.
1203 */
1204 /*0*/ struct sym_lcbh head;
1205
1206 /*
1207 * Task table read from SCRIPTS that contains pointers to
1208 * ITLQ nexuses. The bus address read from SCRIPTS is
1209 * inside the header.
1210 */
1211 u32 *itlq_tbl; /* Kernel virtual address */
1212
1213 /*
1214 * Busy CCBs management.
1215 */
1216 u_short busy_itlq; /* Number of busy tagged CCBs */
1217 u_short busy_itl; /* Number of busy untagged CCBs */
1218
1219 /*
1220 * Circular tag allocation buffer.
1221 */
1222 u_short ia_tag; /* Tag allocation index */
1223 u_short if_tag; /* Tag release index */
1224 u_char *cb_tags; /* Circular tags buffer */
1225
1226 /*
1227 * Set when we want to clear all tasks.
1228 */
1229 u_char to_clear;
1230
1231 /*
1232 * Capabilities.
1233 */
1234 u_char user_flags;
1235 u_char current_flags;
1236 };
1237
1238 /*
1239 * Action from SCRIPTS on a task.
1240 * Is part of the CCB, but is also used separately to plug
1241 * error handling action to perform from SCRIPTS.
1242 */
1243 struct sym_actscr {
1244 u32 start; /* Jumped by SCRIPTS after selection */
1245 u32 restart; /* Jumped by SCRIPTS on relection */
1246 };
1247
1248 /*
1249 * Phase mismatch context.
1250 *
1251 * It is part of the CCB and is used as parameters for the
1252 * DATA pointer. We need two contexts to handle correctly the
1253 * SAVED DATA POINTER.
1254 */
1255 struct sym_pmc {
1256 struct sym_tblmove sg; /* Updated interrupted SG block */
1257 u32 ret; /* SCRIPT return address */
1258 };
1259
1260 /*
1261 * LUN control block lookup.
1262 * We use a direct pointer for LUN #0, and a table of
1263 * pointers which is only allocated for devices that support
1264 * LUN(s) > 0.
1265 */
1266 #if SYM_CONF_MAX_LUN <= 1
1267 #define sym_lp(np, tp, lun) (!lun) ? (tp)->lun0p : 0
1268 #else
1269 #define sym_lp(np, tp, lun) \
1270 (!lun) ? (tp)->lun0p : (tp)->lunmp ? (tp)->lunmp[(lun)] : 0
1271 #endif
1272
1273 /*
1274 * Status are used by the host and the script processor.
1275 *
1276 * The last four bytes (status[4]) are copied to the
1277 * scratchb register (declared as scr0..scr3) just after the
1278 * select/reselect, and copied back just after disconnecting.
1279 * Inside the script the XX_REG are used.
1280 */
1281
1282 /*
1283 * Last four bytes (script)
1284 */
1285 #define QU_REG scr0
1286 #define HS_REG scr1
1287 #define HS_PRT nc_scr1
1288 #define SS_REG scr2
1289 #define SS_PRT nc_scr2
1290 #define HF_REG scr3
1291 #define HF_PRT nc_scr3
1292
1293 /*
1294 * Last four bytes (host)
1295 */
1296 #define actualquirks phys.head.status[0]
1297 #define host_status phys.head.status[1]
1298 #define ssss_status phys.head.status[2]
1299 #define host_flags phys.head.status[3]
1300
1301 /*
1302 * Host flags
1303 */
1304 #define HF_IN_PM0 1u
1305 #define HF_IN_PM1 (1u<<1)
1306 #define HF_ACT_PM (1u<<2)
1307 #define HF_DP_SAVED (1u<<3)
1308 #define HF_SENSE (1u<<4)
1309 #define HF_EXT_ERR (1u<<5)
1310 #define HF_DATA_IN (1u<<6)
1311 #ifdef SYM_CONF_IARB_SUPPORT
1312 #define HF_HINT_IARB (1u<<7)
1313 #endif
1314
1315 /*
1316 * Global CCB HEADER.
1317 *
1318 * Due to lack of indirect addressing on earlier NCR chips,
1319 * this substructure is copied from the ccb to a global
1320 * address after selection (or reselection) and copied back
1321 * before disconnect.
1322 * For SYMBIOS chips that support LOAD/STORE this copy is
1323 * not needed and thus not performed.
1324 */
1325
1326 struct sym_ccbh {
1327 /*
1328 * Start and restart SCRIPTS addresses (must be at 0).
1329 */
1330 /*0*/ struct sym_actscr go;
1331
1332 /*
1333 * SCRIPTS jump address that deal with data pointers.
1334 * 'savep' points to the position in the script responsible
1335 * for the actual transfer of data.
1336 * It's written on reception of a SAVE_DATA_POINTER message.
1337 */
1338 u32 savep; /* Jump address to saved data pointer */
1339 u32 lastp; /* SCRIPTS address at end of data */
1340 u32 goalp; /* Not accessed for now from SCRIPTS */
1341
1342 /*
1343 * Status fields.
1344 */
1345 u8 status[4];
1346 };
1347
1348 /*
1349 * Data Structure Block
1350 *
1351 * During execution of a ccb by the script processor, the
1352 * DSA (data structure address) register points to this
1353 * substructure of the ccb.
1354 */
1355 struct sym_dsb {
1356 /*
1357 * CCB header.
1358 * Also assumed at offset 0 of the sym_ccb structure.
1359 */
1360 /*0*/ struct sym_ccbh head;
1361
1362 /*
1363 * Phase mismatch contexts.
1364 * We need two to handle correctly the SAVED DATA POINTER.
1365 * MUST BOTH BE AT OFFSET < 256, due to using 8 bit arithmetic
1366 * for address calculation from SCRIPTS.
1367 */
1368 struct sym_pmc pm0;
1369 struct sym_pmc pm1;
1370
1371 /*
1372 * Table data for Script
1373 */
1374 struct sym_tblsel select;
1375 struct sym_tblmove smsg;
1376 struct sym_tblmove smsg_ext;
1377 struct sym_tblmove cmd;
1378 struct sym_tblmove sense;
1379 struct sym_tblmove wresid;
1380 struct sym_tblmove data [SYM_CONF_MAX_SG];
1381 };
1382
1383 /*
1384 * Our Command Control Block
1385 */
1386 struct sym_ccb {
1387 /*
1388 * This is the data structure which is pointed by the DSA
1389 * register when it is executed by the script processor.
1390 * It must be the first entry.
1391 */
1392 struct sym_dsb phys;
1393
1394 /*
1395 * Pointer to CAM ccb and related stuff.
1396 */
1397 struct callout ch; /* callout handle */
1398 union ccb *cam_ccb; /* CAM scsiio ccb */
1399 u8 cdb_buf[16]; /* Copy of CDB */
1400 u8 *sns_bbuf; /* Bounce buffer for sense data */
1401 #define SYM_SNS_BBUF_LEN sizeof(struct scsi_sense_data)
1402 int data_len; /* Total data length */
1403 int segments; /* Number of SG segments */
1404
1405 /*
1406 * Miscellaneous status'.
1407 */
1408 u_char nego_status; /* Negotiation status */
1409 u_char xerr_status; /* Extended error flags */
1410 u32 extra_bytes; /* Extraneous bytes transferred */
1411
1412 /*
1413 * Message areas.
1414 * We prepare a message to be sent after selection.
1415 * We may use a second one if the command is rescheduled
1416 * due to CHECK_CONDITION or COMMAND TERMINATED.
1417 * Contents are IDENTIFY and SIMPLE_TAG.
1418 * While negotiating sync or wide transfer,
1419 * a SDTR or WDTR message is appended.
1420 */
1421 u_char scsi_smsg [12];
1422 u_char scsi_smsg2[12];
1423
1424 /*
1425 * Auto request sense related fields.
1426 */
1427 u_char sensecmd[6]; /* Request Sense command */
1428 u_char sv_scsi_status; /* Saved SCSI status */
1429 u_char sv_xerr_status; /* Saved extended status */
1430 int sv_resid; /* Saved residual */
1431
1432 /*
1433 * Map for the DMA of user data.
1434 */
1435 void *arg; /* Argument for some callback */
1436 bus_dmamap_t dmamap; /* DMA map for user data */
1437 u_char dmamapped;
1438 #define SYM_DMA_NONE 0
1439 #define SYM_DMA_READ 1
1440 #define SYM_DMA_WRITE 2
1441 /*
1442 * Other fields.
1443 */
1444 u32 ccb_ba; /* BUS address of this CCB */
1445 u_short tag; /* Tag for this transfer */
1446 /* NO_TAG means no tag */
1447 u_char target;
1448 u_char lun;
1449 ccb_p link_ccbh; /* Host adapter CCB hash chain */
1450 SYM_QUEHEAD
1451 link_ccbq; /* Link to free/busy CCB queue */
1452 u32 startp; /* Initial data pointer */
1453 int ext_sg; /* Extreme data pointer, used */
1454 int ext_ofs; /* to calculate the residual. */
1455 u_char to_abort; /* Want this IO to be aborted */
1456 };
1457
1458 #define CCB_BA(cp,lbl) (cp->ccb_ba + offsetof(struct sym_ccb, lbl))
1459
1460 /*
1461 * Host Control Block
1462 */
1463 struct sym_hcb {
1464 struct lock lock;
1465
1466 /*
1467 * Global headers.
1468 * Due to poorness of addressing capabilities, earlier
1469 * chips (810, 815, 825) copy part of the data structures
1470 * (CCB, TCB and LCB) in fixed areas.
1471 */
1472 #ifdef SYM_CONF_GENERIC_SUPPORT
1473 struct sym_ccbh ccb_head;
1474 struct sym_tcbh tcb_head;
1475 struct sym_lcbh lcb_head;
1476 #endif
1477 /*
1478 * Idle task and invalid task actions and
1479 * their bus addresses.
1480 */
1481 struct sym_actscr idletask, notask, bad_itl, bad_itlq;
1482 vm_offset_t idletask_ba, notask_ba, bad_itl_ba, bad_itlq_ba;
1483
1484 /*
1485 * Dummy lun table to protect us against target
1486 * returning bad lun number on reselection.
1487 */
1488 u32 *badluntbl; /* Table physical address */
1489 u32 badlun_sa; /* SCRIPT handler BUS address */
1490
1491 /*
1492 * Bus address of this host control block.
1493 */
1494 u32 hcb_ba;
1495
1496 /*
1497 * Bit 32-63 of the on-chip RAM bus address in LE format.
1498 * The START_RAM64 script loads the MMRS and MMWS from this
1499 * field.
1500 */
1501 u32 scr_ram_seg;
1502
1503 /*
1504 * Chip and controller indentification.
1505 */
1506 device_t device;
1507
1508 /*
1509 * Initial value of some IO register bits.
1510 * These values are assumed to have been set by BIOS, and may
1511 * be used to probe adapter implementation differences.
1512 */
1513 u_char sv_scntl0, sv_scntl3, sv_dmode, sv_dcntl, sv_ctest3, sv_ctest4,
1514 sv_ctest5, sv_gpcntl, sv_stest2, sv_stest4, sv_scntl4,
1515 sv_stest1;
1516
1517 /*
1518 * Actual initial value of IO register bits used by the
1519 * driver. They are loaded at initialisation according to
1520 * features that are to be enabled/disabled.
1521 */
1522 u_char rv_scntl0, rv_scntl3, rv_dmode, rv_dcntl, rv_ctest3, rv_ctest4,
1523 rv_ctest5, rv_stest2, rv_ccntl0, rv_ccntl1, rv_scntl4;
1524
1525 /*
1526 * Target data.
1527 */
1528 #ifdef __x86_64__
1529 struct sym_tcb *target;
1530 #else
1531 struct sym_tcb target[SYM_CONF_MAX_TARGET];
1532 #endif
1533
1534 /*
1535 * Target control block bus address array used by the SCRIPT
1536 * on reselection.
1537 */
1538 u32 *targtbl;
1539 u32 targtbl_ba;
1540
1541 /*
1542 * CAM SIM information for this instance.
1543 */
1544 struct cam_sim *sim;
1545 struct cam_path *path;
1546
1547 /*
1548 * Allocated hardware resources.
1549 */
1550 struct resource *irq_res;
1551 struct resource *io_res;
1552 struct resource *mmio_res;
1553 struct resource *ram_res;
1554 int ram_id;
1555 void *intr;
1556
1557 /*
1558 * Bus stuff.
1559 *
1560 * My understanding of PCI is that all agents must share the
1561 * same addressing range and model.
1562 * But some hardware architecture guys provide complex and
1563 * brain-deaded stuff that makes shit.
1564 * This driver only support PCI compliant implementations and
1565 * deals with part of the BUS stuff complexity only to fit O/S
1566 * requirements.
1567 */
1568
1569 /*
1570 * DMA stuff.
1571 */
1572 bus_dma_tag_t bus_dmat; /* DMA tag from parent BUS */
1573 bus_dma_tag_t data_dmat; /* DMA tag for user data */
1574 /*
1575 * BUS addresses of the chip
1576 */
1577 vm_offset_t mmio_ba; /* MMIO BUS address */
1578 int mmio_ws; /* MMIO Window size */
1579
1580 vm_offset_t ram_ba; /* RAM BUS address */
1581 int ram_ws; /* RAM window size */
1582
1583 /*
1584 * SCRIPTS virtual and physical bus addresses.
1585 * 'script' is loaded in the on-chip RAM if present.
1586 * 'scripth' stays in main memory for all chips except the
1587 * 53C895A, 53C896 and 53C1010 that provide 8K on-chip RAM.
1588 */
1589 u_char *scripta0; /* Copies of script and scripth */
1590 u_char *scriptb0; /* Copies of script and scripth */
1591 vm_offset_t scripta_ba; /* Actual script and scripth */
1592 vm_offset_t scriptb_ba; /* bus addresses. */
1593 vm_offset_t scriptb0_ba;
1594 u_short scripta_sz; /* Actual size of script A */
1595 u_short scriptb_sz; /* Actual size of script B */
1596
1597 /*
1598 * Bus addresses, setup and patch methods for
1599 * the selected firmware.
1600 */
1601 struct sym_fwa_ba fwa_bas; /* Useful SCRIPTA bus addresses */
1602 struct sym_fwb_ba fwb_bas; /* Useful SCRIPTB bus addresses */
1603 void (*fw_setup)(hcb_p np, const struct sym_fw *fw);
1604 void (*fw_patch)(hcb_p np);
1605 const char *fw_name;
1606
1607 /*
1608 * General controller parameters and configuration.
1609 */
1610 u_short device_id; /* PCI device id */
1611 u_char revision_id; /* PCI device revision id */
1612 u_int features; /* Chip features map */
1613 u_char myaddr; /* SCSI id of the adapter */
1614 u_char maxburst; /* log base 2 of dwords burst */
1615 u_char maxwide; /* Maximum transfer width */
1616 u_char minsync; /* Min sync period factor (ST) */
1617 u_char maxsync; /* Max sync period factor (ST) */
1618 u_char maxoffs; /* Max scsi offset (ST) */
1619 u_char minsync_dt; /* Min sync period factor (DT) */
1620 u_char maxsync_dt; /* Max sync period factor (DT) */
1621 u_char maxoffs_dt; /* Max scsi offset (DT) */
1622 u_char multiplier; /* Clock multiplier (1,2,4) */
1623 u_char clock_divn; /* Number of clock divisors */
1624 u32 clock_khz; /* SCSI clock frequency in KHz */
1625 u32 pciclk_khz; /* Estimated PCI clock in KHz */
1626 /*
1627 * Start queue management.
1628 * It is filled up by the host processor and accessed by the
1629 * SCRIPTS processor in order to start SCSI commands.
1630 */
1631 volatile /* Prevent code optimizations */
1632 u32 *squeue; /* Start queue virtual address */
1633 u32 squeue_ba; /* Start queue BUS address */
1634 u_short squeueput; /* Next free slot of the queue */
1635 u_short actccbs; /* Number of allocated CCBs */
1636
1637 /*
1638 * Command completion queue.
1639 * It is the same size as the start queue to avoid overflow.
1640 */
1641 u_short dqueueget; /* Next position to scan */
1642 volatile /* Prevent code optimizations */
1643 u32 *dqueue; /* Completion (done) queue */
1644 u32 dqueue_ba; /* Done queue BUS address */
1645
1646 /*
1647 * Miscellaneous buffers accessed by the scripts-processor.
1648 * They shall be DWORD aligned, because they may be read or
1649 * written with a script command.
1650 */
1651 u_char msgout[8]; /* Buffer for MESSAGE OUT */
1652 u_char msgin [8]; /* Buffer for MESSAGE IN */
1653 u32 lastmsg; /* Last SCSI message sent */
1654 u_char scratch; /* Scratch for SCSI receive */
1655
1656 /*
1657 * Miscellaneous configuration and status parameters.
1658 */
1659 u_char usrflags; /* Miscellaneous user flags */
1660 u_char scsi_mode; /* Current SCSI BUS mode */
1661 u_char verbose; /* Verbosity for this controller*/
1662 u32 cache; /* Used for cache test at init. */
1663
1664 /*
1665 * CCB lists and queue.
1666 */
1667 ccb_p ccbh[CCB_HASH_SIZE]; /* CCB hashed by DSA value */
1668 SYM_QUEHEAD free_ccbq; /* Queue of available CCBs */
1669 SYM_QUEHEAD busy_ccbq; /* Queue of busy CCBs */
1670
1671 /*
1672 * During error handling and/or recovery,
1673 * active CCBs that are to be completed with
1674 * error or requeued are moved from the busy_ccbq
1675 * to the comp_ccbq prior to completion.
1676 */
1677 SYM_QUEHEAD comp_ccbq;
1678
1679 /*
1680 * CAM CCB pending queue.
1681 */
1682 SYM_QUEHEAD cam_ccbq;
1683
1684 /*
1685 * IMMEDIATE ARBITRATION (IARB) control.
1686 *
1687 * We keep track in 'last_cp' of the last CCB that has been
1688 * queued to the SCRIPTS processor and clear 'last_cp' when
1689 * this CCB completes. If last_cp is not zero at the moment
1690 * we queue a new CCB, we set a flag in 'last_cp' that is
1691 * used by the SCRIPTS as a hint for setting IARB.
1692 * We donnot set more than 'iarb_max' consecutive hints for
1693 * IARB in order to leave devices a chance to reselect.
1694 * By the way, any non zero value of 'iarb_max' is unfair. :)
1695 */
1696 #ifdef SYM_CONF_IARB_SUPPORT
1697 u_short iarb_max; /* Max. # consecutive IARB hints*/
1698 u_short iarb_count; /* Actual # of these hints */
1699 ccb_p last_cp;
1700 #endif
1701
1702 /*
1703 * Command abort handling.
1704 * We need to synchronize tightly with the SCRIPTS
1705 * processor in order to handle things correctly.
1706 */
1707 u_char abrt_msg[4]; /* Message to send buffer */
1708 struct sym_tblmove abrt_tbl; /* Table for the MOV of it */
1709 struct sym_tblsel abrt_sel; /* Sync params for selection */
1710 u_char istat_sem; /* Tells the chip to stop (SEM) */
1711 };
1712
1713 #define HCB_BA(np, lbl) (np->hcb_ba + offsetof(struct sym_hcb, lbl))
1714
1715 /*
1716 * Return the name of the controller.
1717 */
sym_name(hcb_p np)1718 static __inline const char *sym_name(hcb_p np)
1719 {
1720 return device_get_nameunit(np->device);
1721 }
1722
1723 /*--------------------------------------------------------------------------*/
1724 /*------------------------------ FIRMWARES ---------------------------------*/
1725 /*--------------------------------------------------------------------------*/
1726
1727 /*
1728 * This stuff will be moved to a separate source file when
1729 * the driver will be broken into several source modules.
1730 */
1731
1732 /*
1733 * Macros used for all firmwares.
1734 */
1735 #define SYM_GEN_A(s, label) ((short) offsetof(s, label)),
1736 #define SYM_GEN_B(s, label) ((short) offsetof(s, label)),
1737 #define PADDR_A(label) SYM_GEN_PADDR_A(struct SYM_FWA_SCR, label)
1738 #define PADDR_B(label) SYM_GEN_PADDR_B(struct SYM_FWB_SCR, label)
1739
1740
1741 #ifdef SYM_CONF_GENERIC_SUPPORT
1742 /*
1743 * Allocate firmware #1 script area.
1744 */
1745 #define SYM_FWA_SCR sym_fw1a_scr
1746 #define SYM_FWB_SCR sym_fw1b_scr
1747 #include <dev/disk/sym/sym_fw1.h>
1748 static const struct sym_fwa_ofs sym_fw1a_ofs = {
1749 SYM_GEN_FW_A(struct SYM_FWA_SCR)
1750 };
1751 static const struct sym_fwb_ofs sym_fw1b_ofs = {
1752 SYM_GEN_FW_B(struct SYM_FWB_SCR)
1753 };
1754 #undef SYM_FWA_SCR
1755 #undef SYM_FWB_SCR
1756 #endif /* SYM_CONF_GENERIC_SUPPORT */
1757
1758 /*
1759 * Allocate firmware #2 script area.
1760 */
1761 #define SYM_FWA_SCR sym_fw2a_scr
1762 #define SYM_FWB_SCR sym_fw2b_scr
1763 #include <dev/disk/sym/sym_fw2.h>
1764 static const struct sym_fwa_ofs sym_fw2a_ofs = {
1765 SYM_GEN_FW_A(struct SYM_FWA_SCR)
1766 };
1767 static const struct sym_fwb_ofs sym_fw2b_ofs = {
1768 SYM_GEN_FW_B(struct SYM_FWB_SCR)
1769 SYM_GEN_B(struct SYM_FWB_SCR, start64)
1770 SYM_GEN_B(struct SYM_FWB_SCR, pm_handle)
1771 };
1772 #undef SYM_FWA_SCR
1773 #undef SYM_FWB_SCR
1774
1775 #undef SYM_GEN_A
1776 #undef SYM_GEN_B
1777 #undef PADDR_A
1778 #undef PADDR_B
1779
1780 #ifdef SYM_CONF_GENERIC_SUPPORT
1781 /*
1782 * Patch routine for firmware #1.
1783 */
1784 static void
sym_fw1_patch(hcb_p np)1785 sym_fw1_patch(hcb_p np)
1786 {
1787 struct sym_fw1a_scr *scripta0;
1788 struct sym_fw1b_scr *scriptb0;
1789
1790 scripta0 = (struct sym_fw1a_scr *) np->scripta0;
1791 scriptb0 = (struct sym_fw1b_scr *) np->scriptb0;
1792
1793 /*
1794 * Remove LED support if not needed.
1795 */
1796 if (!(np->features & FE_LED0)) {
1797 scripta0->idle[0] = cpu_to_scr(SCR_NO_OP);
1798 scripta0->reselected[0] = cpu_to_scr(SCR_NO_OP);
1799 scripta0->start[0] = cpu_to_scr(SCR_NO_OP);
1800 }
1801
1802 #ifdef SYM_CONF_IARB_SUPPORT
1803 /*
1804 * If user does not want to use IMMEDIATE ARBITRATION
1805 * when we are reselected while attempting to arbitrate,
1806 * patch the SCRIPTS accordingly with a SCRIPT NO_OP.
1807 */
1808 if (!SYM_CONF_SET_IARB_ON_ARB_LOST)
1809 scripta0->ungetjob[0] = cpu_to_scr(SCR_NO_OP);
1810 #endif
1811 /*
1812 * Patch some data in SCRIPTS.
1813 * - start and done queue initial bus address.
1814 * - target bus address table bus address.
1815 */
1816 scriptb0->startpos[0] = cpu_to_scr(np->squeue_ba);
1817 scriptb0->done_pos[0] = cpu_to_scr(np->dqueue_ba);
1818 scriptb0->targtbl[0] = cpu_to_scr(np->targtbl_ba);
1819 }
1820 #endif /* SYM_CONF_GENERIC_SUPPORT */
1821
1822 /*
1823 * Patch routine for firmware #2.
1824 */
1825 static void
sym_fw2_patch(hcb_p np)1826 sym_fw2_patch(hcb_p np)
1827 {
1828 struct sym_fw2a_scr *scripta0;
1829 struct sym_fw2b_scr *scriptb0;
1830
1831 scripta0 = (struct sym_fw2a_scr *) np->scripta0;
1832 scriptb0 = (struct sym_fw2b_scr *) np->scriptb0;
1833
1834 /*
1835 * Remove LED support if not needed.
1836 */
1837 if (!(np->features & FE_LED0)) {
1838 scripta0->idle[0] = cpu_to_scr(SCR_NO_OP);
1839 scripta0->reselected[0] = cpu_to_scr(SCR_NO_OP);
1840 scripta0->start[0] = cpu_to_scr(SCR_NO_OP);
1841 }
1842
1843 #ifdef SYM_CONF_IARB_SUPPORT
1844 /*
1845 * If user does not want to use IMMEDIATE ARBITRATION
1846 * when we are reselected while attempting to arbitrate,
1847 * patch the SCRIPTS accordingly with a SCRIPT NO_OP.
1848 */
1849 if (!SYM_CONF_SET_IARB_ON_ARB_LOST)
1850 scripta0->ungetjob[0] = cpu_to_scr(SCR_NO_OP);
1851 #endif
1852 /*
1853 * Patch some variable in SCRIPTS.
1854 * - start and done queue initial bus address.
1855 * - target bus address table bus address.
1856 */
1857 scriptb0->startpos[0] = cpu_to_scr(np->squeue_ba);
1858 scriptb0->done_pos[0] = cpu_to_scr(np->dqueue_ba);
1859 scriptb0->targtbl[0] = cpu_to_scr(np->targtbl_ba);
1860
1861 /*
1862 * Remove the load of SCNTL4 on reselection if not a C10.
1863 */
1864 if (!(np->features & FE_C10)) {
1865 scripta0->resel_scntl4[0] = cpu_to_scr(SCR_NO_OP);
1866 scripta0->resel_scntl4[1] = cpu_to_scr(0);
1867 }
1868
1869 /*
1870 * Remove a couple of work-arounds specific to C1010 if
1871 * they are not desirable. See `sym_fw2.h' for more details.
1872 */
1873 if (!(np->device_id == PCI_ID_LSI53C1010_2 &&
1874 np->revision_id < 0x1 &&
1875 np->pciclk_khz < 60000)) {
1876 scripta0->datao_phase[0] = cpu_to_scr(SCR_NO_OP);
1877 scripta0->datao_phase[1] = cpu_to_scr(0);
1878 }
1879 if (!(np->device_id == PCI_ID_LSI53C1010 &&
1880 /* np->revision_id < 0xff */ 1)) {
1881 scripta0->sel_done[0] = cpu_to_scr(SCR_NO_OP);
1882 scripta0->sel_done[1] = cpu_to_scr(0);
1883 }
1884
1885 /*
1886 * Patch some other variables in SCRIPTS.
1887 * These ones are loaded by the SCRIPTS processor.
1888 */
1889 scriptb0->pm0_data_addr[0] =
1890 cpu_to_scr(np->scripta_ba +
1891 offsetof(struct sym_fw2a_scr, pm0_data));
1892 scriptb0->pm1_data_addr[0] =
1893 cpu_to_scr(np->scripta_ba +
1894 offsetof(struct sym_fw2a_scr, pm1_data));
1895 }
1896
1897 /*
1898 * Fill the data area in scripts.
1899 * To be done for all firmwares.
1900 */
1901 static void
sym_fw_fill_data(u32 * in,u32 * out)1902 sym_fw_fill_data (u32 *in, u32 *out)
1903 {
1904 int i;
1905
1906 for (i = 0; i < SYM_CONF_MAX_SG; i++) {
1907 *in++ = SCR_CHMOV_TBL ^ SCR_DATA_IN;
1908 *in++ = offsetof (struct sym_dsb, data[i]);
1909 *out++ = SCR_CHMOV_TBL ^ SCR_DATA_OUT;
1910 *out++ = offsetof (struct sym_dsb, data[i]);
1911 }
1912 }
1913
1914 /*
1915 * Setup useful script bus addresses.
1916 * To be done for all firmwares.
1917 */
1918 static void
sym_fw_setup_bus_addresses(hcb_p np,const struct sym_fw * fw)1919 sym_fw_setup_bus_addresses(hcb_p np, const struct sym_fw *fw)
1920 {
1921 u32 *pa;
1922 const u_short *po;
1923 int i;
1924
1925 /*
1926 * Build the bus address table for script A
1927 * from the script A offset table.
1928 */
1929 po = (const u_short *) fw->a_ofs;
1930 pa = (u32 *) &np->fwa_bas;
1931 for (i = 0 ; i < sizeof(np->fwa_bas)/sizeof(u32) ; i++)
1932 pa[i] = np->scripta_ba + po[i];
1933
1934 /*
1935 * Same for script B.
1936 */
1937 po = (const u_short *) fw->b_ofs;
1938 pa = (u32 *) &np->fwb_bas;
1939 for (i = 0 ; i < sizeof(np->fwb_bas)/sizeof(u32) ; i++)
1940 pa[i] = np->scriptb_ba + po[i];
1941 }
1942
1943 #ifdef SYM_CONF_GENERIC_SUPPORT
1944 /*
1945 * Setup routine for firmware #1.
1946 */
1947 static void
sym_fw1_setup(hcb_p np,const struct sym_fw * fw)1948 sym_fw1_setup(hcb_p np, const struct sym_fw *fw)
1949 {
1950 struct sym_fw1a_scr *scripta0;
1951
1952 scripta0 = (struct sym_fw1a_scr *) np->scripta0;
1953
1954 /*
1955 * Fill variable parts in scripts.
1956 */
1957 sym_fw_fill_data(scripta0->data_in, scripta0->data_out);
1958
1959 /*
1960 * Setup bus addresses used from the C code..
1961 */
1962 sym_fw_setup_bus_addresses(np, fw);
1963 }
1964 #endif /* SYM_CONF_GENERIC_SUPPORT */
1965
1966 /*
1967 * Setup routine for firmware #2.
1968 */
1969 static void
sym_fw2_setup(hcb_p np,const struct sym_fw * fw)1970 sym_fw2_setup(hcb_p np, const struct sym_fw *fw)
1971 {
1972 struct sym_fw2a_scr *scripta0;
1973
1974 scripta0 = (struct sym_fw2a_scr *) np->scripta0;
1975
1976 /*
1977 * Fill variable parts in scripts.
1978 */
1979 sym_fw_fill_data(scripta0->data_in, scripta0->data_out);
1980
1981 /*
1982 * Setup bus addresses used from the C code..
1983 */
1984 sym_fw_setup_bus_addresses(np, fw);
1985 }
1986
1987 /*
1988 * Allocate firmware descriptors.
1989 */
1990 #ifdef SYM_CONF_GENERIC_SUPPORT
1991 static const struct sym_fw sym_fw1 = SYM_FW_ENTRY(sym_fw1, "NCR-generic");
1992 #endif /* SYM_CONF_GENERIC_SUPPORT */
1993 static const struct sym_fw sym_fw2 = SYM_FW_ENTRY(sym_fw2, "LOAD/STORE-based");
1994
1995 /*
1996 * Find the most appropriate firmware for a chip.
1997 */
1998 static const struct sym_fw *
sym_find_firmware(const struct sym_pci_chip * chip)1999 sym_find_firmware(const struct sym_pci_chip *chip)
2000 {
2001 if (chip->features & FE_LDSTR)
2002 return &sym_fw2;
2003 #ifdef SYM_CONF_GENERIC_SUPPORT
2004 else if (!(chip->features & (FE_PFEN|FE_NOPM|FE_DAC)))
2005 return &sym_fw1;
2006 #endif
2007 else
2008 return NULL;
2009 }
2010
2011 /*
2012 * Bind a script to physical addresses.
2013 */
sym_fw_bind_script(hcb_p np,u32 * start,int len)2014 static void sym_fw_bind_script (hcb_p np, u32 *start, int len)
2015 {
2016 u32 opcode, new, old, tmp1, tmp2;
2017 u32 *end, *cur;
2018 int relocs;
2019
2020 cur = start;
2021 end = start + len/4;
2022
2023 while (cur < end) {
2024
2025 opcode = *cur;
2026
2027 /*
2028 * If we forget to change the length
2029 * in scripts, a field will be
2030 * padded with 0. This is an illegal
2031 * command.
2032 */
2033 if (opcode == 0) {
2034 kprintf ("%s: ERROR0 IN SCRIPT at %d.\n",
2035 sym_name(np), (int) (cur-start));
2036 MDELAY (10000);
2037 ++cur;
2038 continue;
2039 }
2040
2041 /*
2042 * We use the bogus value 0xf00ff00f ;-)
2043 * to reserve data area in SCRIPTS.
2044 */
2045 if (opcode == SCR_DATA_ZERO) {
2046 *cur++ = 0;
2047 continue;
2048 }
2049
2050 if (DEBUG_FLAGS & DEBUG_SCRIPT)
2051 kprintf ("%d: <%x>\n", (int) (cur-start),
2052 (unsigned)opcode);
2053
2054 /*
2055 * We don't have to decode ALL commands
2056 */
2057 switch (opcode >> 28) {
2058 case 0xf:
2059 /*
2060 * LOAD / STORE DSA relative, don't relocate.
2061 */
2062 relocs = 0;
2063 break;
2064 case 0xe:
2065 /*
2066 * LOAD / STORE absolute.
2067 */
2068 relocs = 1;
2069 break;
2070 case 0xc:
2071 /*
2072 * COPY has TWO arguments.
2073 */
2074 relocs = 2;
2075 tmp1 = cur[1];
2076 tmp2 = cur[2];
2077 if ((tmp1 ^ tmp2) & 3) {
2078 kprintf ("%s: ERROR1 IN SCRIPT at %d.\n",
2079 sym_name(np), (int) (cur-start));
2080 MDELAY (10000);
2081 }
2082 /*
2083 * If PREFETCH feature not enabled, remove
2084 * the NO FLUSH bit if present.
2085 */
2086 if ((opcode & SCR_NO_FLUSH) &&
2087 !(np->features & FE_PFEN)) {
2088 opcode = (opcode & ~SCR_NO_FLUSH);
2089 }
2090 break;
2091 case 0x0:
2092 /*
2093 * MOVE/CHMOV (absolute address)
2094 */
2095 if (!(np->features & FE_WIDE))
2096 opcode = (opcode | OPC_MOVE);
2097 relocs = 1;
2098 break;
2099 case 0x1:
2100 /*
2101 * MOVE/CHMOV (table indirect)
2102 */
2103 if (!(np->features & FE_WIDE))
2104 opcode = (opcode | OPC_MOVE);
2105 relocs = 0;
2106 break;
2107 case 0x8:
2108 /*
2109 * JUMP / CALL
2110 * dont't relocate if relative :-)
2111 */
2112 if (opcode & 0x00800000)
2113 relocs = 0;
2114 else if ((opcode & 0xf8400000) == 0x80400000)/*JUMP64*/
2115 relocs = 2;
2116 else
2117 relocs = 1;
2118 break;
2119 case 0x4:
2120 case 0x5:
2121 case 0x6:
2122 case 0x7:
2123 relocs = 1;
2124 break;
2125 default:
2126 relocs = 0;
2127 break;
2128 }
2129
2130 /*
2131 * Scriptify:) the opcode.
2132 */
2133 *cur++ = cpu_to_scr(opcode);
2134
2135 /*
2136 * If no relocation, assume 1 argument
2137 * and just scriptize:) it.
2138 */
2139 if (!relocs) {
2140 *cur = cpu_to_scr(*cur);
2141 ++cur;
2142 continue;
2143 }
2144
2145 /*
2146 * Otherwise performs all needed relocations.
2147 */
2148 while (relocs--) {
2149 old = *cur;
2150
2151 switch (old & RELOC_MASK) {
2152 case RELOC_REGISTER:
2153 new = (old & ~RELOC_MASK) + np->mmio_ba;
2154 break;
2155 case RELOC_LABEL_A:
2156 new = (old & ~RELOC_MASK) + np->scripta_ba;
2157 break;
2158 case RELOC_LABEL_B:
2159 new = (old & ~RELOC_MASK) + np->scriptb_ba;
2160 break;
2161 case RELOC_SOFTC:
2162 new = (old & ~RELOC_MASK) + np->hcb_ba;
2163 break;
2164 case 0:
2165 /*
2166 * Don't relocate a 0 address.
2167 * They are mostly used for patched or
2168 * script self-modified areas.
2169 */
2170 if (old == 0) {
2171 new = old;
2172 break;
2173 }
2174 /* fall through */
2175 default:
2176 new = 0;
2177 panic("sym_fw_bind_script: "
2178 "weird relocation %x\n", old);
2179 break;
2180 }
2181
2182 *cur++ = cpu_to_scr(new);
2183 }
2184 }
2185 }
2186
2187 /*---------------------------------------------------------------------------*/
2188 /*--------------------------- END OF FIRMWARES -----------------------------*/
2189 /*---------------------------------------------------------------------------*/
2190
2191 /*
2192 * Function prototypes.
2193 */
2194 static void sym_save_initial_setting (hcb_p np);
2195 static int sym_prepare_setting (hcb_p np, struct sym_nvram *nvram);
2196 static int sym_prepare_nego (hcb_p np, ccb_p cp, int nego, u_char *msgptr);
2197 static void sym_put_start_queue (hcb_p np, ccb_p cp);
2198 static void sym_chip_reset (hcb_p np);
2199 static void sym_soft_reset (hcb_p np);
2200 static void sym_start_reset (hcb_p np);
2201 static int sym_reset_scsi_bus (hcb_p np, int enab_int);
2202 static int sym_wakeup_done (hcb_p np);
2203 static void sym_flush_busy_queue (hcb_p np, int cam_status);
2204 static void sym_flush_comp_queue (hcb_p np, int cam_status);
2205 static void sym_init (hcb_p np, int reason);
2206 static int sym_getsync(hcb_p np, u_char dt, u_char sfac, u_char *divp,
2207 u_char *fakp);
2208 static void sym_setsync (hcb_p np, ccb_p cp, u_char ofs, u_char per,
2209 u_char div, u_char fak);
2210 static void sym_setwide (hcb_p np, ccb_p cp, u_char wide);
2211 static void sym_setpprot(hcb_p np, ccb_p cp, u_char dt, u_char ofs,
2212 u_char per, u_char wide, u_char div, u_char fak);
2213 static void sym_settrans(hcb_p np, ccb_p cp, u_char dt, u_char ofs,
2214 u_char per, u_char wide, u_char div, u_char fak);
2215 static void sym_log_hard_error (hcb_p np, u_short sist, u_char dstat);
2216 static void sym_intr (void *arg);
2217 static void sym_poll (struct cam_sim *sim);
2218 static void sym_recover_scsi_int (hcb_p np, u_char hsts);
2219 static void sym_int_sto (hcb_p np);
2220 static void sym_int_udc (hcb_p np);
2221 static void sym_int_sbmc (hcb_p np);
2222 static void sym_int_par (hcb_p np, u_short sist);
2223 static void sym_int_ma (hcb_p np);
2224 static int sym_dequeue_from_squeue(hcb_p np, int i, int target, int lun,
2225 int task);
2226 static void sym_sir_bad_scsi_status (hcb_p np, int num, ccb_p cp);
2227 static int sym_clear_tasks (hcb_p np, int status, int targ, int lun, int task);
2228 static void sym_sir_task_recovery (hcb_p np, int num);
2229 static int sym_evaluate_dp (hcb_p np, ccb_p cp, u32 scr, int *ofs);
2230 static void sym_modify_dp (hcb_p np, tcb_p tp, ccb_p cp, int ofs);
2231 static int sym_compute_residual (hcb_p np, ccb_p cp);
2232 static int sym_show_msg (u_char * msg);
2233 static void sym_print_msg (ccb_p cp, char *label, u_char *msg);
2234 static void sym_sync_nego (hcb_p np, tcb_p tp, ccb_p cp);
2235 static void sym_ppr_nego (hcb_p np, tcb_p tp, ccb_p cp);
2236 static void sym_wide_nego (hcb_p np, tcb_p tp, ccb_p cp);
2237 static void sym_nego_default (hcb_p np, tcb_p tp, ccb_p cp);
2238 static void sym_nego_rejected (hcb_p np, tcb_p tp, ccb_p cp);
2239 static void sym_int_sir (hcb_p np);
2240 static void sym_free_ccb (hcb_p np, ccb_p cp);
2241 static ccb_p sym_get_ccb (hcb_p np, u_char tn, u_char ln, u_char tag_order);
2242 static ccb_p sym_alloc_ccb (hcb_p np);
2243 static ccb_p sym_ccb_from_dsa (hcb_p np, u32 dsa);
2244 static lcb_p sym_alloc_lcb (hcb_p np, u_char tn, u_char ln);
2245 static void sym_alloc_lcb_tags (hcb_p np, u_char tn, u_char ln);
2246 static int sym_snooptest (hcb_p np);
2247 static void sym_selectclock(hcb_p np, u_char scntl3);
2248 static void sym_getclock (hcb_p np, int mult);
2249 static int sym_getpciclock (hcb_p np);
2250 static void sym_complete_ok (hcb_p np, ccb_p cp);
2251 static void sym_complete_error (hcb_p np, ccb_p cp);
2252 static void sym_callout (void *arg);
2253 static int sym_abort_scsiio (hcb_p np, union ccb *ccb, int timed_out);
2254 static void sym_reset_dev (hcb_p np, union ccb *ccb);
2255 static void sym_action (struct cam_sim *sim, union ccb *ccb);
2256 static int sym_setup_cdb (hcb_p np, struct ccb_scsiio *csio, ccb_p cp);
2257 static void sym_setup_data_and_start (hcb_p np, struct ccb_scsiio *csio,
2258 ccb_p cp);
2259 static int sym_fast_scatter_sg_physical(hcb_p np, ccb_p cp,
2260 bus_dma_segment_t *psegs, int nsegs);
2261 static int sym_scatter_sg_physical (hcb_p np, ccb_p cp,
2262 bus_dma_segment_t *psegs, int nsegs);
2263 static void sym_action2 (struct cam_sim *sim, union ccb *ccb);
2264 static void sym_update_trans (hcb_p np, tcb_p tp, struct sym_trans *tip,
2265 struct ccb_trans_settings *cts);
2266 static void sym_update_dflags(hcb_p np, u_char *flags,
2267 struct ccb_trans_settings *cts);
2268
2269 static const struct sym_pci_chip *sym_find_pci_chip (device_t dev);
2270 static int sym_pci_probe (device_t dev);
2271 static int sym_pci_attach (device_t dev);
2272
2273 static void sym_pci_free (hcb_p np);
2274 static int sym_cam_attach (hcb_p np);
2275 static void sym_cam_free (hcb_p np);
2276
2277 static void sym_nvram_setup_host (hcb_p np, struct sym_nvram *nvram);
2278 static void sym_nvram_setup_target (hcb_p np, int targ, struct sym_nvram *nvp);
2279 static int sym_read_nvram (hcb_p np, struct sym_nvram *nvp);
2280
2281 /*
2282 * Print something which allows to retrieve the controller type,
2283 * unit, target, lun concerned by a kernel message.
2284 */
PRINT_TARGET(hcb_p np,int target)2285 static void PRINT_TARGET (hcb_p np, int target)
2286 {
2287 kprintf ("%s:%d:", sym_name(np), target);
2288 }
2289
PRINT_LUN(hcb_p np,int target,int lun)2290 static void PRINT_LUN(hcb_p np, int target, int lun)
2291 {
2292 kprintf ("%s:%d:%d:", sym_name(np), target, lun);
2293 }
2294
PRINT_ADDR(ccb_p cp)2295 static void PRINT_ADDR (ccb_p cp)
2296 {
2297 if (cp && cp->cam_ccb)
2298 xpt_print_path(cp->cam_ccb->ccb_h.path);
2299 }
2300
2301 /*
2302 * Take into account this ccb in the freeze count.
2303 */
sym_freeze_cam_ccb(union ccb * ccb)2304 static void sym_freeze_cam_ccb(union ccb *ccb)
2305 {
2306 if (!(ccb->ccb_h.flags & CAM_DEV_QFRZDIS)) {
2307 if (!(ccb->ccb_h.status & CAM_DEV_QFRZN)) {
2308 ccb->ccb_h.status |= CAM_DEV_QFRZN;
2309 xpt_freeze_devq(ccb->ccb_h.path, 1);
2310 }
2311 }
2312 }
2313
2314 /*
2315 * Set the status field of a CAM CCB.
2316 */
sym_set_cam_status(union ccb * ccb,cam_status status)2317 static __inline void sym_set_cam_status(union ccb *ccb, cam_status status)
2318 {
2319 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2320 ccb->ccb_h.status |= status;
2321 }
2322
2323 /*
2324 * Get the status field of a CAM CCB.
2325 */
sym_get_cam_status(union ccb * ccb)2326 static __inline int sym_get_cam_status(union ccb *ccb)
2327 {
2328 return ccb->ccb_h.status & CAM_STATUS_MASK;
2329 }
2330
2331 /*
2332 * Enqueue a CAM CCB.
2333 */
sym_enqueue_cam_ccb(ccb_p cp)2334 static void sym_enqueue_cam_ccb(ccb_p cp)
2335 {
2336 hcb_p np;
2337 union ccb *ccb;
2338
2339 ccb = cp->cam_ccb;
2340 np = (hcb_p) cp->arg;
2341
2342 assert(!(ccb->ccb_h.status & CAM_SIM_QUEUED));
2343 ccb->ccb_h.status = CAM_REQ_INPROG;
2344
2345 callout_reset(&cp->ch, ccb->ccb_h.timeout * hz / 1000, sym_callout,
2346 (caddr_t) ccb);
2347 ccb->ccb_h.status |= CAM_SIM_QUEUED;
2348 ccb->ccb_h.sym_hcb_ptr = np;
2349
2350 sym_insque_tail(sym_qptr(&ccb->ccb_h.sim_links), &np->cam_ccbq);
2351 }
2352
2353 /*
2354 * Complete a pending CAM CCB.
2355 */
_sym_xpt_done(hcb_p np,union ccb * ccb)2356 static void _sym_xpt_done(hcb_p np, union ccb *ccb)
2357 {
2358 SYM_LOCK_ASSERT(LK_EXCLUSIVE);
2359
2360 KASSERT((ccb->ccb_h.status & CAM_SIM_QUEUED) == 0,
2361 ("%s: status=CAM_SIM_QUEUED", __func__));
2362
2363 if (ccb->ccb_h.flags & CAM_DEV_QFREEZE)
2364 sym_freeze_cam_ccb(ccb);
2365 xpt_done(ccb);
2366 }
2367
sym_xpt_done(hcb_p np,union ccb * ccb,ccb_p cp)2368 static void sym_xpt_done(hcb_p np, union ccb *ccb, ccb_p cp)
2369 {
2370 SYM_LOCK_ASSERT(LK_EXCLUSIVE);
2371
2372 if (ccb->ccb_h.status & CAM_SIM_QUEUED) {
2373 callout_stop(&cp->ch);
2374 sym_remque(sym_qptr(&ccb->ccb_h.sim_links));
2375 ccb->ccb_h.status &= ~CAM_SIM_QUEUED;
2376 ccb->ccb_h.sym_hcb_ptr = NULL;
2377 }
2378 _sym_xpt_done(np, ccb);
2379 }
2380
sym_xpt_done2(hcb_p np,union ccb * ccb,int cam_status)2381 static void sym_xpt_done2(hcb_p np, union ccb *ccb, int cam_status)
2382 {
2383 SYM_LOCK_ASSERT(LK_EXCLUSIVE);
2384
2385 sym_set_cam_status(ccb, cam_status);
2386 _sym_xpt_done(np, ccb);
2387 }
2388
2389 /*
2390 * SYMBIOS chip clock divisor table.
2391 *
2392 * Divisors are multiplied by 10,000,000 in order to make
2393 * calculations more simple.
2394 */
2395 #define _5M 5000000
2396 static const u32 div_10M[] =
2397 {2*_5M, 3*_5M, 4*_5M, 6*_5M, 8*_5M, 12*_5M, 16*_5M};
2398
2399 /*
2400 * SYMBIOS chips allow burst lengths of 2, 4, 8, 16, 32, 64,
2401 * 128 transfers. All chips support at least 16 transfers
2402 * bursts. The 825A, 875 and 895 chips support bursts of up
2403 * to 128 transfers and the 895A and 896 support bursts of up
2404 * to 64 transfers. All other chips support up to 16
2405 * transfers bursts.
2406 *
2407 * For PCI 32 bit data transfers each transfer is a DWORD.
2408 * It is a QUADWORD (8 bytes) for PCI 64 bit data transfers.
2409 *
2410 * We use log base 2 (burst length) as internal code, with
2411 * value 0 meaning "burst disabled".
2412 */
2413
2414 /*
2415 * Burst length from burst code.
2416 */
2417 #define burst_length(bc) (!(bc))? 0 : 1 << (bc)
2418
2419 /*
2420 * Burst code from io register bits.
2421 */
2422 #define burst_code(dmode, ctest4, ctest5) \
2423 (ctest4) & 0x80? 0 : (((dmode) & 0xc0) >> 6) + ((ctest5) & 0x04) + 1
2424
2425 /*
2426 * Set initial io register bits from burst code.
2427 */
sym_init_burst(hcb_p np,u_char bc)2428 static __inline void sym_init_burst(hcb_p np, u_char bc)
2429 {
2430 np->rv_ctest4 &= ~0x80;
2431 np->rv_dmode &= ~(0x3 << 6);
2432 np->rv_ctest5 &= ~0x4;
2433
2434 if (!bc) {
2435 np->rv_ctest4 |= 0x80;
2436 }
2437 else {
2438 --bc;
2439 np->rv_dmode |= ((bc & 0x3) << 6);
2440 np->rv_ctest5 |= (bc & 0x4);
2441 }
2442 }
2443
2444
2445 /*
2446 * Print out the list of targets that have some flag disabled by user.
2447 */
sym_print_targets_flag(hcb_p np,int mask,char * msg)2448 static void sym_print_targets_flag(hcb_p np, int mask, char *msg)
2449 {
2450 int cnt;
2451 int i;
2452
2453 for (cnt = 0, i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) {
2454 if (i == np->myaddr)
2455 continue;
2456 if (np->target[i].usrflags & mask) {
2457 if (!cnt++)
2458 kprintf("%s: %s disabled for targets",
2459 sym_name(np), msg);
2460 kprintf(" %d", i);
2461 }
2462 }
2463 if (cnt)
2464 kprintf(".\n");
2465 }
2466
2467 /*
2468 * Save initial settings of some IO registers.
2469 * Assumed to have been set by BIOS.
2470 * We cannot reset the chip prior to reading the
2471 * IO registers, since informations will be lost.
2472 * Since the SCRIPTS processor may be running, this
2473 * is not safe on paper, but it seems to work quite
2474 * well. :)
2475 */
sym_save_initial_setting(hcb_p np)2476 static void sym_save_initial_setting (hcb_p np)
2477 {
2478 np->sv_scntl0 = INB(nc_scntl0) & 0x0a;
2479 np->sv_scntl3 = INB(nc_scntl3) & 0x07;
2480 np->sv_dmode = INB(nc_dmode) & 0xce;
2481 np->sv_dcntl = INB(nc_dcntl) & 0xa8;
2482 np->sv_ctest3 = INB(nc_ctest3) & 0x01;
2483 np->sv_ctest4 = INB(nc_ctest4) & 0x80;
2484 np->sv_gpcntl = INB(nc_gpcntl);
2485 np->sv_stest1 = INB(nc_stest1);
2486 np->sv_stest2 = INB(nc_stest2) & 0x20;
2487 np->sv_stest4 = INB(nc_stest4);
2488 if (np->features & FE_C10) { /* Always large DMA fifo + ultra3 */
2489 np->sv_scntl4 = INB(nc_scntl4);
2490 np->sv_ctest5 = INB(nc_ctest5) & 0x04;
2491 }
2492 else
2493 np->sv_ctest5 = INB(nc_ctest5) & 0x24;
2494 }
2495
2496 /*
2497 * Prepare io register values used by sym_init() according
2498 * to selected and supported features.
2499 */
sym_prepare_setting(hcb_p np,struct sym_nvram * nvram)2500 static int sym_prepare_setting(hcb_p np, struct sym_nvram *nvram)
2501 {
2502 u_char burst_max;
2503 u32 period;
2504 int i;
2505
2506 /*
2507 * Wide ?
2508 */
2509 np->maxwide = (np->features & FE_WIDE)? 1 : 0;
2510
2511 /*
2512 * Get the frequency of the chip's clock.
2513 */
2514 if (np->features & FE_QUAD)
2515 np->multiplier = 4;
2516 else if (np->features & FE_DBLR)
2517 np->multiplier = 2;
2518 else
2519 np->multiplier = 1;
2520
2521 np->clock_khz = (np->features & FE_CLK80)? 80000 : 40000;
2522 np->clock_khz *= np->multiplier;
2523
2524 if (np->clock_khz != 40000)
2525 sym_getclock(np, np->multiplier);
2526
2527 /*
2528 * Divisor to be used for async (timer pre-scaler).
2529 */
2530 i = np->clock_divn - 1;
2531 while (--i >= 0) {
2532 if (10ul * SYM_CONF_MIN_ASYNC * np->clock_khz > div_10M[i]) {
2533 ++i;
2534 break;
2535 }
2536 }
2537 np->rv_scntl3 = i+1;
2538
2539 /*
2540 * The C1010 uses hardwired divisors for async.
2541 * So, we just throw away, the async. divisor.:-)
2542 */
2543 if (np->features & FE_C10)
2544 np->rv_scntl3 = 0;
2545
2546 /*
2547 * Minimum synchronous period factor supported by the chip.
2548 * Btw, 'period' is in tenths of nanoseconds.
2549 */
2550 period = (4 * div_10M[0] + np->clock_khz - 1) / np->clock_khz;
2551 if (period <= 250) np->minsync = 10;
2552 else if (period <= 303) np->minsync = 11;
2553 else if (period <= 500) np->minsync = 12;
2554 else np->minsync = (period + 40 - 1) / 40;
2555
2556 /*
2557 * Check against chip SCSI standard support (SCSI-2,ULTRA,ULTRA2).
2558 */
2559 if (np->minsync < 25 &&
2560 !(np->features & (FE_ULTRA|FE_ULTRA2|FE_ULTRA3)))
2561 np->minsync = 25;
2562 else if (np->minsync < 12 &&
2563 !(np->features & (FE_ULTRA2|FE_ULTRA3)))
2564 np->minsync = 12;
2565
2566 /*
2567 * Maximum synchronous period factor supported by the chip.
2568 */
2569 period = (11 * div_10M[np->clock_divn - 1]) / (4 * np->clock_khz);
2570 np->maxsync = period > 2540 ? 254 : period / 10;
2571
2572 /*
2573 * If chip is a C1010, guess the sync limits in DT mode.
2574 */
2575 if ((np->features & (FE_C10|FE_ULTRA3)) == (FE_C10|FE_ULTRA3)) {
2576 if (np->clock_khz == 160000) {
2577 np->minsync_dt = 9;
2578 np->maxsync_dt = 50;
2579 np->maxoffs_dt = 62;
2580 }
2581 }
2582
2583 /*
2584 * 64 bit addressing (895A/896/1010) ?
2585 */
2586 if (np->features & FE_DAC)
2587 #ifdef __LP64__
2588 np->rv_ccntl1 |= (XTIMOD | EXTIBMV);
2589 #else
2590 np->rv_ccntl1 |= (DDAC);
2591 #endif
2592
2593 /*
2594 * Phase mismatch handled by SCRIPTS (895A/896/1010) ?
2595 */
2596 if (np->features & FE_NOPM)
2597 np->rv_ccntl0 |= (ENPMJ);
2598
2599 /*
2600 * C1010 Errata.
2601 * In dual channel mode, contention occurs if internal cycles
2602 * are used. Disable internal cycles.
2603 */
2604 if (np->device_id == PCI_ID_LSI53C1010 &&
2605 np->revision_id < 0x2)
2606 np->rv_ccntl0 |= DILS;
2607
2608 /*
2609 * Select burst length (dwords)
2610 */
2611 burst_max = SYM_SETUP_BURST_ORDER;
2612 if (burst_max == 255)
2613 burst_max = burst_code(np->sv_dmode, np->sv_ctest4,
2614 np->sv_ctest5);
2615 if (burst_max > 7)
2616 burst_max = 7;
2617 if (burst_max > np->maxburst)
2618 burst_max = np->maxburst;
2619
2620 /*
2621 * DEL 352 - 53C810 Rev x11 - Part Number 609-0392140 - ITEM 2.
2622 * This chip and the 860 Rev 1 may wrongly use PCI cache line
2623 * based transactions on LOAD/STORE instructions. So we have
2624 * to prevent these chips from using such PCI transactions in
2625 * this driver. The generic ncr driver that does not use
2626 * LOAD/STORE instructions does not need this work-around.
2627 */
2628 if ((np->device_id == PCI_ID_SYM53C810 &&
2629 np->revision_id >= 0x10 && np->revision_id <= 0x11) ||
2630 (np->device_id == PCI_ID_SYM53C860 &&
2631 np->revision_id <= 0x1))
2632 np->features &= ~(FE_WRIE|FE_ERL|FE_ERMP);
2633
2634 /*
2635 * Select all supported special features.
2636 * If we are using on-board RAM for scripts, prefetch (PFEN)
2637 * does not help, but burst op fetch (BOF) does.
2638 * Disabling PFEN makes sure BOF will be used.
2639 */
2640 if (np->features & FE_ERL)
2641 np->rv_dmode |= ERL; /* Enable Read Line */
2642 if (np->features & FE_BOF)
2643 np->rv_dmode |= BOF; /* Burst Opcode Fetch */
2644 if (np->features & FE_ERMP)
2645 np->rv_dmode |= ERMP; /* Enable Read Multiple */
2646 #if 1
2647 if ((np->features & FE_PFEN) && !np->ram_ba)
2648 #else
2649 if (np->features & FE_PFEN)
2650 #endif
2651 np->rv_dcntl |= PFEN; /* Prefetch Enable */
2652 if (np->features & FE_CLSE)
2653 np->rv_dcntl |= CLSE; /* Cache Line Size Enable */
2654 if (np->features & FE_WRIE)
2655 np->rv_ctest3 |= WRIE; /* Write and Invalidate */
2656 if (np->features & FE_DFS)
2657 np->rv_ctest5 |= DFS; /* Dma Fifo Size */
2658
2659 /*
2660 * Select some other
2661 */
2662 if (SYM_SETUP_PCI_PARITY)
2663 np->rv_ctest4 |= MPEE; /* Master parity checking */
2664 if (SYM_SETUP_SCSI_PARITY)
2665 np->rv_scntl0 |= 0x0a; /* full arb., ena parity, par->ATN */
2666
2667 /*
2668 * Get parity checking, host ID and verbose mode from NVRAM
2669 */
2670 np->myaddr = 255;
2671 sym_nvram_setup_host (np, nvram);
2672
2673 /*
2674 * Get SCSI addr of host adapter (set by bios?).
2675 */
2676 if (np->myaddr == 255) {
2677 np->myaddr = INB(nc_scid) & 0x07;
2678 if (!np->myaddr)
2679 np->myaddr = SYM_SETUP_HOST_ID;
2680 }
2681
2682 /*
2683 * Prepare initial io register bits for burst length
2684 */
2685 sym_init_burst(np, burst_max);
2686
2687 /*
2688 * Set SCSI BUS mode.
2689 * - LVD capable chips (895/895A/896/1010) report the
2690 * current BUS mode through the STEST4 IO register.
2691 * - For previous generation chips (825/825A/875),
2692 * user has to tell us how to check against HVD,
2693 * since a 100% safe algorithm is not possible.
2694 */
2695 np->scsi_mode = SMODE_SE;
2696 if (np->features & (FE_ULTRA2|FE_ULTRA3))
2697 np->scsi_mode = (np->sv_stest4 & SMODE);
2698 else if (np->features & FE_DIFF) {
2699 if (SYM_SETUP_SCSI_DIFF == 1) {
2700 if (np->sv_scntl3) {
2701 if (np->sv_stest2 & 0x20)
2702 np->scsi_mode = SMODE_HVD;
2703 }
2704 else if (nvram->type == SYM_SYMBIOS_NVRAM) {
2705 if (!(INB(nc_gpreg) & 0x08))
2706 np->scsi_mode = SMODE_HVD;
2707 }
2708 }
2709 else if (SYM_SETUP_SCSI_DIFF == 2)
2710 np->scsi_mode = SMODE_HVD;
2711 }
2712 if (np->scsi_mode == SMODE_HVD)
2713 np->rv_stest2 |= 0x20;
2714
2715 /*
2716 * Set LED support from SCRIPTS.
2717 * Ignore this feature for boards known to use a
2718 * specific GPIO wiring and for the 895A, 896
2719 * and 1010 that drive the LED directly.
2720 */
2721 if ((SYM_SETUP_SCSI_LED ||
2722 (nvram->type == SYM_SYMBIOS_NVRAM ||
2723 (nvram->type == SYM_TEKRAM_NVRAM &&
2724 np->device_id == PCI_ID_SYM53C895))) &&
2725 !(np->features & FE_LEDC) && !(np->sv_gpcntl & 0x01))
2726 np->features |= FE_LED0;
2727
2728 /*
2729 * Set irq mode.
2730 */
2731 switch(SYM_SETUP_IRQ_MODE & 3) {
2732 case 2:
2733 np->rv_dcntl |= IRQM;
2734 break;
2735 case 1:
2736 np->rv_dcntl |= (np->sv_dcntl & IRQM);
2737 break;
2738 default:
2739 break;
2740 }
2741
2742 /*
2743 * Configure targets according to driver setup.
2744 * If NVRAM present get targets setup from NVRAM.
2745 */
2746 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) {
2747 tcb_p tp = &np->target[i];
2748
2749 tp->tinfo.user.scsi_version = tp->tinfo.current.scsi_version= 2;
2750 tp->tinfo.user.spi_version = tp->tinfo.current.spi_version = 2;
2751 tp->tinfo.user.period = np->minsync;
2752 if (np->features & FE_ULTRA3)
2753 tp->tinfo.user.period = np->minsync_dt;
2754 tp->tinfo.user.offset = np->maxoffs;
2755 tp->tinfo.user.width = np->maxwide ? BUS_16_BIT : BUS_8_BIT;
2756 tp->usrflags |= (SYM_DISC_ENABLED | SYM_TAGS_ENABLED);
2757 tp->usrtags = SYM_SETUP_MAX_TAG;
2758
2759 sym_nvram_setup_target (np, i, nvram);
2760
2761 /*
2762 * For now, guess PPR/DT support from the period
2763 * and BUS width.
2764 */
2765 if (np->features & FE_ULTRA3) {
2766 if (tp->tinfo.user.period <= 9 &&
2767 tp->tinfo.user.width == BUS_16_BIT) {
2768 tp->tinfo.user.options |= PPR_OPT_DT;
2769 tp->tinfo.user.offset = np->maxoffs_dt;
2770 tp->tinfo.user.spi_version = 3;
2771 }
2772 }
2773
2774 if (!tp->usrtags)
2775 tp->usrflags &= ~SYM_TAGS_ENABLED;
2776 }
2777
2778 /*
2779 * Let user know about the settings.
2780 */
2781 i = nvram->type;
2782 kprintf("%s: %s NVRAM, ID %d, Fast-%d, %s, %s\n", sym_name(np),
2783 i == SYM_SYMBIOS_NVRAM ? "Symbios" :
2784 (i == SYM_TEKRAM_NVRAM ? "Tekram" : "No"),
2785 np->myaddr,
2786 (np->features & FE_ULTRA3) ? 80 :
2787 (np->features & FE_ULTRA2) ? 40 :
2788 (np->features & FE_ULTRA) ? 20 : 10,
2789 sym_scsi_bus_mode(np->scsi_mode),
2790 (np->rv_scntl0 & 0xa) ? "parity checking" : "NO parity");
2791 /*
2792 * Tell him more on demand.
2793 */
2794 if (sym_verbose) {
2795 kprintf("%s: %s IRQ line driver%s\n",
2796 sym_name(np),
2797 np->rv_dcntl & IRQM ? "totem pole" : "open drain",
2798 np->ram_ba ? ", using on-chip SRAM" : "");
2799 kprintf("%s: using %s firmware.\n", sym_name(np), np->fw_name);
2800 if (np->features & FE_NOPM)
2801 kprintf("%s: handling phase mismatch from SCRIPTS.\n",
2802 sym_name(np));
2803 }
2804 /*
2805 * And still more.
2806 */
2807 if (sym_verbose > 1) {
2808 kprintf ("%s: initial SCNTL3/DMODE/DCNTL/CTEST3/4/5 = "
2809 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n",
2810 sym_name(np), np->sv_scntl3, np->sv_dmode, np->sv_dcntl,
2811 np->sv_ctest3, np->sv_ctest4, np->sv_ctest5);
2812
2813 kprintf ("%s: final SCNTL3/DMODE/DCNTL/CTEST3/4/5 = "
2814 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n",
2815 sym_name(np), np->rv_scntl3, np->rv_dmode, np->rv_dcntl,
2816 np->rv_ctest3, np->rv_ctest4, np->rv_ctest5);
2817 }
2818 /*
2819 * Let user be aware of targets that have some disable flags set.
2820 */
2821 sym_print_targets_flag(np, SYM_SCAN_BOOT_DISABLED, "SCAN AT BOOT");
2822 if (sym_verbose)
2823 sym_print_targets_flag(np, SYM_SCAN_LUNS_DISABLED,
2824 "SCAN FOR LUNS");
2825
2826 return 0;
2827 }
2828
2829 /*
2830 * Prepare the next negotiation message if needed.
2831 *
2832 * Fill in the part of message buffer that contains the
2833 * negotiation and the nego_status field of the CCB.
2834 * Returns the size of the message in bytes.
2835 */
2836
sym_prepare_nego(hcb_p np,ccb_p cp,int nego,u_char * msgptr)2837 static int sym_prepare_nego(hcb_p np, ccb_p cp, int nego, u_char *msgptr)
2838 {
2839 tcb_p tp = &np->target[cp->target];
2840 int msglen = 0;
2841
2842 /*
2843 * Early C1010 chips need a work-around for DT
2844 * data transfer to work.
2845 */
2846 if (!(np->features & FE_U3EN))
2847 tp->tinfo.goal.options = 0;
2848 /*
2849 * negotiate using PPR ?
2850 */
2851 if (tp->tinfo.goal.options & PPR_OPT_MASK)
2852 nego = NS_PPR;
2853 /*
2854 * negotiate wide transfers ?
2855 */
2856 else if (tp->tinfo.current.width != tp->tinfo.goal.width)
2857 nego = NS_WIDE;
2858 /*
2859 * negotiate synchronous transfers?
2860 */
2861 else if (tp->tinfo.current.period != tp->tinfo.goal.period ||
2862 tp->tinfo.current.offset != tp->tinfo.goal.offset)
2863 nego = NS_SYNC;
2864
2865 switch (nego) {
2866 case NS_SYNC:
2867 msgptr[msglen++] = M_EXTENDED;
2868 msgptr[msglen++] = 3;
2869 msgptr[msglen++] = M_X_SYNC_REQ;
2870 msgptr[msglen++] = tp->tinfo.goal.period;
2871 msgptr[msglen++] = tp->tinfo.goal.offset;
2872 break;
2873 case NS_WIDE:
2874 msgptr[msglen++] = M_EXTENDED;
2875 msgptr[msglen++] = 2;
2876 msgptr[msglen++] = M_X_WIDE_REQ;
2877 msgptr[msglen++] = tp->tinfo.goal.width;
2878 break;
2879 case NS_PPR:
2880 msgptr[msglen++] = M_EXTENDED;
2881 msgptr[msglen++] = 6;
2882 msgptr[msglen++] = M_X_PPR_REQ;
2883 msgptr[msglen++] = tp->tinfo.goal.period;
2884 msgptr[msglen++] = 0;
2885 msgptr[msglen++] = tp->tinfo.goal.offset;
2886 msgptr[msglen++] = tp->tinfo.goal.width;
2887 msgptr[msglen++] = tp->tinfo.goal.options & PPR_OPT_DT;
2888 break;
2889 }
2890
2891 cp->nego_status = nego;
2892
2893 if (nego) {
2894 tp->nego_cp = cp; /* Keep track a nego will be performed */
2895 if (DEBUG_FLAGS & DEBUG_NEGO) {
2896 sym_print_msg(cp, nego == NS_SYNC ? "sync msgout" :
2897 nego == NS_WIDE ? "wide msgout" :
2898 "ppr msgout", msgptr);
2899 }
2900 }
2901
2902 return msglen;
2903 }
2904
2905 /*
2906 * Insert a job into the start queue.
2907 */
sym_put_start_queue(hcb_p np,ccb_p cp)2908 static void sym_put_start_queue(hcb_p np, ccb_p cp)
2909 {
2910 u_short qidx;
2911
2912 #ifdef SYM_CONF_IARB_SUPPORT
2913 /*
2914 * If the previously queued CCB is not yet done,
2915 * set the IARB hint. The SCRIPTS will go with IARB
2916 * for this job when starting the previous one.
2917 * We leave devices a chance to win arbitration by
2918 * not using more than 'iarb_max' consecutive
2919 * immediate arbitrations.
2920 */
2921 if (np->last_cp && np->iarb_count < np->iarb_max) {
2922 np->last_cp->host_flags |= HF_HINT_IARB;
2923 ++np->iarb_count;
2924 }
2925 else
2926 np->iarb_count = 0;
2927 np->last_cp = cp;
2928 #endif
2929
2930 /*
2931 * Insert first the idle task and then our job.
2932 * The MB should ensure proper ordering.
2933 */
2934 qidx = np->squeueput + 2;
2935 if (qidx >= MAX_QUEUE*2) qidx = 0;
2936
2937 np->squeue [qidx] = cpu_to_scr(np->idletask_ba);
2938 MEMORY_BARRIER();
2939 np->squeue [np->squeueput] = cpu_to_scr(cp->ccb_ba);
2940
2941 np->squeueput = qidx;
2942
2943 if (DEBUG_FLAGS & DEBUG_QUEUE)
2944 kprintf ("%s: queuepos=%d.\n", sym_name (np), np->squeueput);
2945
2946 /*
2947 * Script processor may be waiting for reselect.
2948 * Wake it up.
2949 */
2950 MEMORY_BARRIER();
2951 OUTB (nc_istat, SIGP|np->istat_sem);
2952 }
2953
2954
2955 /*
2956 * Soft reset the chip.
2957 *
2958 * Raising SRST when the chip is running may cause
2959 * problems on dual function chips (see below).
2960 * On the other hand, LVD devices need some delay
2961 * to settle and report actual BUS mode in STEST4.
2962 */
sym_chip_reset(hcb_p np)2963 static void sym_chip_reset (hcb_p np)
2964 {
2965 OUTB (nc_istat, SRST);
2966 UDELAY (10);
2967 OUTB (nc_istat, 0);
2968 UDELAY(2000); /* For BUS MODE to settle */
2969 }
2970
2971 /*
2972 * Soft reset the chip.
2973 *
2974 * Some 896 and 876 chip revisions may hang-up if we set
2975 * the SRST (soft reset) bit at the wrong time when SCRIPTS
2976 * are running.
2977 * So, we need to abort the current operation prior to
2978 * soft resetting the chip.
2979 */
sym_soft_reset(hcb_p np)2980 static void sym_soft_reset (hcb_p np)
2981 {
2982 u_char istat;
2983 int i;
2984
2985 OUTB (nc_istat, CABRT);
2986 for (i = 1000000 ; i ; --i) {
2987 istat = INB (nc_istat);
2988 if (istat & SIP) {
2989 INW (nc_sist);
2990 continue;
2991 }
2992 if (istat & DIP) {
2993 OUTB (nc_istat, 0);
2994 INB (nc_dstat);
2995 break;
2996 }
2997 }
2998 if (!i)
2999 kprintf("%s: unable to abort current chip operation.\n",
3000 sym_name(np));
3001 sym_chip_reset (np);
3002 }
3003
3004 /*
3005 * Start reset process.
3006 *
3007 * The interrupt handler will reinitialize the chip.
3008 */
sym_start_reset(hcb_p np)3009 static void sym_start_reset(hcb_p np)
3010 {
3011 (void) sym_reset_scsi_bus(np, 1);
3012 }
3013
sym_reset_scsi_bus(hcb_p np,int enab_int)3014 static int sym_reset_scsi_bus(hcb_p np, int enab_int)
3015 {
3016 u32 term;
3017 int retv = 0;
3018
3019 sym_soft_reset(np); /* Soft reset the chip */
3020 if (enab_int)
3021 OUTW (nc_sien, RST);
3022 /*
3023 * Enable Tolerant, reset IRQD if present and
3024 * properly set IRQ mode, prior to resetting the bus.
3025 */
3026 OUTB (nc_stest3, TE);
3027 OUTB (nc_dcntl, (np->rv_dcntl & IRQM));
3028 OUTB (nc_scntl1, CRST);
3029 UDELAY (200);
3030
3031 if (!SYM_SETUP_SCSI_BUS_CHECK)
3032 goto out;
3033 /*
3034 * Check for no terminators or SCSI bus shorts to ground.
3035 * Read SCSI data bus, data parity bits and control signals.
3036 * We are expecting RESET to be TRUE and other signals to be
3037 * FALSE.
3038 */
3039 term = INB(nc_sstat0);
3040 term = ((term & 2) << 7) + ((term & 1) << 17); /* rst sdp0 */
3041 term |= ((INB(nc_sstat2) & 0x01) << 26) | /* sdp1 */
3042 ((INW(nc_sbdl) & 0xff) << 9) | /* d7-0 */
3043 ((INW(nc_sbdl) & 0xff00) << 10) | /* d15-8 */
3044 INB(nc_sbcl); /* req ack bsy sel atn msg cd io */
3045
3046 if (!(np->features & FE_WIDE))
3047 term &= 0x3ffff;
3048
3049 if (term != (2<<7)) {
3050 kprintf("%s: suspicious SCSI data while resetting the BUS.\n",
3051 sym_name(np));
3052 kprintf("%s: %sdp0,d7-0,rst,req,ack,bsy,sel,atn,msg,c/d,i/o = "
3053 "0x%lx, expecting 0x%lx\n",
3054 sym_name(np),
3055 (np->features & FE_WIDE) ? "dp1,d15-8," : "",
3056 (u_long)term, (u_long)(2<<7));
3057 if (SYM_SETUP_SCSI_BUS_CHECK == 1)
3058 retv = 1;
3059 }
3060 out:
3061 OUTB (nc_scntl1, 0);
3062 /* MDELAY(100); */
3063 return retv;
3064 }
3065
3066 /*
3067 * The chip may have completed jobs. Look at the DONE QUEUE.
3068 *
3069 * On architectures that may reorder LOAD/STORE operations,
3070 * a memory barrier may be needed after the reading of the
3071 * so-called `flag' and prior to dealing with the data.
3072 */
sym_wakeup_done(hcb_p np)3073 static int sym_wakeup_done (hcb_p np)
3074 {
3075 ccb_p cp;
3076 int i, n;
3077 u32 dsa;
3078
3079 SYM_LOCK_ASSERT(LK_EXCLUSIVE);
3080
3081 n = 0;
3082 i = np->dqueueget;
3083 while (1) {
3084 dsa = scr_to_cpu(np->dqueue[i]);
3085 if (!dsa)
3086 break;
3087 np->dqueue[i] = 0;
3088 if ((i = i+2) >= MAX_QUEUE*2)
3089 i = 0;
3090
3091 cp = sym_ccb_from_dsa(np, dsa);
3092 if (cp) {
3093 MEMORY_BARRIER();
3094 sym_complete_ok (np, cp);
3095 ++n;
3096 }
3097 else
3098 kprintf ("%s: bad DSA (%x) in done queue.\n",
3099 sym_name(np), (u_int) dsa);
3100 }
3101 np->dqueueget = i;
3102
3103 return n;
3104 }
3105
3106 /*
3107 * Complete all active CCBs with error.
3108 * Used on CHIP/SCSI RESET.
3109 */
sym_flush_busy_queue(hcb_p np,int cam_status)3110 static void sym_flush_busy_queue (hcb_p np, int cam_status)
3111 {
3112 /*
3113 * Move all active CCBs to the COMP queue
3114 * and flush this queue.
3115 */
3116 sym_que_splice(&np->busy_ccbq, &np->comp_ccbq);
3117 sym_que_init(&np->busy_ccbq);
3118 sym_flush_comp_queue(np, cam_status);
3119 }
3120
3121 /*
3122 * Start chip.
3123 *
3124 * 'reason' means:
3125 * 0: initialisation.
3126 * 1: SCSI BUS RESET delivered or received.
3127 * 2: SCSI BUS MODE changed.
3128 */
sym_init(hcb_p np,int reason)3129 static void sym_init (hcb_p np, int reason)
3130 {
3131 int i;
3132 u32 phys;
3133
3134 SYM_LOCK_ASSERT(LK_EXCLUSIVE);
3135
3136 /*
3137 * Reset chip if asked, otherwise just clear fifos.
3138 */
3139 if (reason == 1)
3140 sym_soft_reset(np);
3141 else {
3142 OUTB (nc_stest3, TE|CSF);
3143 OUTONB (nc_ctest3, CLF);
3144 }
3145
3146 /*
3147 * Clear Start Queue
3148 */
3149 phys = np->squeue_ba;
3150 for (i = 0; i < MAX_QUEUE*2; i += 2) {
3151 np->squeue[i] = cpu_to_scr(np->idletask_ba);
3152 np->squeue[i+1] = cpu_to_scr(phys + (i+2)*4);
3153 }
3154 np->squeue[MAX_QUEUE*2-1] = cpu_to_scr(phys);
3155
3156 /*
3157 * Start at first entry.
3158 */
3159 np->squeueput = 0;
3160
3161 /*
3162 * Clear Done Queue
3163 */
3164 phys = np->dqueue_ba;
3165 for (i = 0; i < MAX_QUEUE*2; i += 2) {
3166 np->dqueue[i] = 0;
3167 np->dqueue[i+1] = cpu_to_scr(phys + (i+2)*4);
3168 }
3169 np->dqueue[MAX_QUEUE*2-1] = cpu_to_scr(phys);
3170
3171 /*
3172 * Start at first entry.
3173 */
3174 np->dqueueget = 0;
3175
3176 /*
3177 * Install patches in scripts.
3178 * This also let point to first position the start
3179 * and done queue pointers used from SCRIPTS.
3180 */
3181 np->fw_patch(np);
3182
3183 /*
3184 * Wakeup all pending jobs.
3185 */
3186 sym_flush_busy_queue(np, CAM_SCSI_BUS_RESET);
3187
3188 /*
3189 * Init chip.
3190 */
3191 OUTB (nc_istat, 0x00 ); /* Remove Reset, abort */
3192 UDELAY (2000); /* The 895 needs time for the bus mode to settle */
3193
3194 OUTB (nc_scntl0, np->rv_scntl0 | 0xc0);
3195 /* full arb., ena parity, par->ATN */
3196 OUTB (nc_scntl1, 0x00); /* odd parity, and remove CRST!! */
3197
3198 sym_selectclock(np, np->rv_scntl3); /* Select SCSI clock */
3199
3200 OUTB (nc_scid , RRE|np->myaddr); /* Adapter SCSI address */
3201 OUTW (nc_respid, 1ul<<np->myaddr); /* Id to respond to */
3202 OUTB (nc_istat , SIGP ); /* Signal Process */
3203 OUTB (nc_dmode , np->rv_dmode); /* Burst length, dma mode */
3204 OUTB (nc_ctest5, np->rv_ctest5); /* Large fifo + large burst */
3205
3206 OUTB (nc_dcntl , NOCOM|np->rv_dcntl); /* Protect SFBR */
3207 OUTB (nc_ctest3, np->rv_ctest3); /* Write and invalidate */
3208 OUTB (nc_ctest4, np->rv_ctest4); /* Master parity checking */
3209
3210 /* Extended Sreq/Sack filtering not supported on the C10 */
3211 if (np->features & FE_C10)
3212 OUTB (nc_stest2, np->rv_stest2);
3213 else
3214 OUTB (nc_stest2, EXT|np->rv_stest2);
3215
3216 OUTB (nc_stest3, TE); /* TolerANT enable */
3217 OUTB (nc_stime0, 0x0c); /* HTH disabled STO 0.25 sec */
3218
3219 /*
3220 * For now, disable AIP generation on C1010-66.
3221 */
3222 if (np->device_id == PCI_ID_LSI53C1010_2)
3223 OUTB (nc_aipcntl1, DISAIP);
3224
3225 /*
3226 * C10101 Errata.
3227 * Errant SGE's when in narrow. Write bits 4 & 5 of
3228 * STEST1 register to disable SGE. We probably should do
3229 * that from SCRIPTS for each selection/reselection, but
3230 * I just don't want. :)
3231 */
3232 if (np->device_id == PCI_ID_LSI53C1010 &&
3233 /* np->revision_id < 0xff */ 1)
3234 OUTB (nc_stest1, INB(nc_stest1) | 0x30);
3235
3236 /*
3237 * DEL 441 - 53C876 Rev 5 - Part Number 609-0392787/2788 - ITEM 2.
3238 * Disable overlapped arbitration for some dual function devices,
3239 * regardless revision id (kind of post-chip-design feature. ;-))
3240 */
3241 if (np->device_id == PCI_ID_SYM53C875)
3242 OUTB (nc_ctest0, (1<<5));
3243 else if (np->device_id == PCI_ID_SYM53C896)
3244 np->rv_ccntl0 |= DPR;
3245
3246 /*
3247 * Write CCNTL0/CCNTL1 for chips capable of 64 bit addressing
3248 * and/or hardware phase mismatch, since only such chips
3249 * seem to support those IO registers.
3250 */
3251 if (np->features & (FE_DAC|FE_NOPM)) {
3252 OUTB (nc_ccntl0, np->rv_ccntl0);
3253 OUTB (nc_ccntl1, np->rv_ccntl1);
3254 }
3255
3256 /*
3257 * If phase mismatch handled by scripts (895A/896/1010),
3258 * set PM jump addresses.
3259 */
3260 if (np->features & FE_NOPM) {
3261 OUTL (nc_pmjad1, SCRIPTB_BA (np, pm_handle));
3262 OUTL (nc_pmjad2, SCRIPTB_BA (np, pm_handle));
3263 }
3264
3265 /*
3266 * Enable GPIO0 pin for writing if LED support from SCRIPTS.
3267 * Also set GPIO5 and clear GPIO6 if hardware LED control.
3268 */
3269 if (np->features & FE_LED0)
3270 OUTB(nc_gpcntl, INB(nc_gpcntl) & ~0x01);
3271 else if (np->features & FE_LEDC)
3272 OUTB(nc_gpcntl, (INB(nc_gpcntl) & ~0x41) | 0x20);
3273
3274 /*
3275 * enable ints
3276 */
3277 OUTW (nc_sien , STO|HTH|MA|SGE|UDC|RST|PAR);
3278 OUTB (nc_dien , MDPE|BF|SSI|SIR|IID);
3279
3280 /*
3281 * For 895/6 enable SBMC interrupt and save current SCSI bus mode.
3282 * Try to eat the spurious SBMC interrupt that may occur when
3283 * we reset the chip but not the SCSI BUS (at initialization).
3284 */
3285 if (np->features & (FE_ULTRA2|FE_ULTRA3)) {
3286 OUTONW (nc_sien, SBMC);
3287 if (reason == 0) {
3288 MDELAY(100);
3289 INW (nc_sist);
3290 }
3291 np->scsi_mode = INB (nc_stest4) & SMODE;
3292 }
3293
3294 /*
3295 * Fill in target structure.
3296 * Reinitialize usrsync.
3297 * Reinitialize usrwide.
3298 * Prepare sync negotiation according to actual SCSI bus mode.
3299 */
3300 for (i=0;i<SYM_CONF_MAX_TARGET;i++) {
3301 tcb_p tp = &np->target[i];
3302
3303 tp->to_reset = 0;
3304 tp->head.sval = 0;
3305 tp->head.wval = np->rv_scntl3;
3306 tp->head.uval = 0;
3307
3308 tp->tinfo.current.period = 0;
3309 tp->tinfo.current.offset = 0;
3310 tp->tinfo.current.width = BUS_8_BIT;
3311 tp->tinfo.current.options = 0;
3312 }
3313
3314 /*
3315 * Download SCSI SCRIPTS to on-chip RAM if present,
3316 * and start script processor.
3317 */
3318 if (np->ram_ba) {
3319 if (sym_verbose > 1)
3320 kprintf ("%s: Downloading SCSI SCRIPTS.\n",
3321 sym_name(np));
3322 if (np->ram_ws == 8192) {
3323 OUTRAM_OFF(4096, np->scriptb0, np->scriptb_sz);
3324 OUTL (nc_mmws, np->scr_ram_seg);
3325 OUTL (nc_mmrs, np->scr_ram_seg);
3326 OUTL (nc_sfs, np->scr_ram_seg);
3327 phys = SCRIPTB_BA (np, start64);
3328 }
3329 else
3330 phys = SCRIPTA_BA (np, init);
3331 OUTRAM_OFF(0, np->scripta0, np->scripta_sz);
3332 }
3333 else
3334 phys = SCRIPTA_BA (np, init);
3335
3336 np->istat_sem = 0;
3337
3338 OUTL (nc_dsa, np->hcb_ba);
3339 OUTL_DSP (phys);
3340
3341 /*
3342 * Notify the XPT about the RESET condition.
3343 */
3344 if (reason != 0)
3345 xpt_async(AC_BUS_RESET, np->path, NULL);
3346 }
3347
3348 /*
3349 * Get clock factor and sync divisor for a given
3350 * synchronous factor period.
3351 */
3352 static int
sym_getsync(hcb_p np,u_char dt,u_char sfac,u_char * divp,u_char * fakp)3353 sym_getsync(hcb_p np, u_char dt, u_char sfac, u_char *divp, u_char *fakp)
3354 {
3355 u32 clk = np->clock_khz; /* SCSI clock frequency in kHz */
3356 int div = np->clock_divn; /* Number of divisors supported */
3357 u32 fak; /* Sync factor in sxfer */
3358 u32 per; /* Period in tenths of ns */
3359 u32 kpc; /* (per * clk) */
3360 int ret;
3361
3362 /*
3363 * Compute the synchronous period in tenths of nano-seconds
3364 */
3365 if (dt && sfac <= 9) per = 125;
3366 else if (sfac <= 10) per = 250;
3367 else if (sfac == 11) per = 303;
3368 else if (sfac == 12) per = 500;
3369 else per = 40 * sfac;
3370 ret = per;
3371
3372 kpc = per * clk;
3373 if (dt)
3374 kpc <<= 1;
3375
3376 /*
3377 * For earliest C10 revision 0, we cannot use extra
3378 * clocks for the setting of the SCSI clocking.
3379 * Note that this limits the lowest sync data transfer
3380 * to 5 Mega-transfers per second and may result in
3381 * using higher clock divisors.
3382 */
3383 #if 1
3384 if ((np->features & (FE_C10|FE_U3EN)) == FE_C10) {
3385 /*
3386 * Look for the lowest clock divisor that allows an
3387 * output speed not faster than the period.
3388 */
3389 while (div > 0) {
3390 --div;
3391 if (kpc > (div_10M[div] << 2)) {
3392 ++div;
3393 break;
3394 }
3395 }
3396 fak = 0; /* No extra clocks */
3397 if (div == np->clock_divn) { /* Are we too fast ? */
3398 ret = -1;
3399 }
3400 *divp = div;
3401 *fakp = fak;
3402 return ret;
3403 }
3404 #endif
3405
3406 /*
3407 * Look for the greatest clock divisor that allows an
3408 * input speed faster than the period.
3409 */
3410 while (div-- > 0)
3411 if (kpc >= (div_10M[div] << 2)) break;
3412
3413 /*
3414 * Calculate the lowest clock factor that allows an output
3415 * speed not faster than the period, and the max output speed.
3416 * If fak >= 1 we will set both XCLKH_ST and XCLKH_DT.
3417 * If fak >= 2 we will also set XCLKS_ST and XCLKS_DT.
3418 */
3419 if (dt) {
3420 fak = (kpc - 1) / (div_10M[div] << 1) + 1 - 2;
3421 /* ret = ((2+fak)*div_10M[div])/np->clock_khz; */
3422 }
3423 else {
3424 fak = (kpc - 1) / div_10M[div] + 1 - 4;
3425 /* ret = ((4+fak)*div_10M[div])/np->clock_khz; */
3426 }
3427
3428 /*
3429 * Check against our hardware limits, or bugs :).
3430 */
3431 if (fak < 0) {fak = 0; ret = -1;}
3432 if (fak > 2) {fak = 2; ret = -1;}
3433
3434 /*
3435 * Compute and return sync parameters.
3436 */
3437 *divp = div;
3438 *fakp = fak;
3439
3440 return ret;
3441 }
3442
3443 /*
3444 * Tell the SCSI layer about the new transfer parameters.
3445 */
3446 static void
sym_xpt_async_transfer_neg(hcb_p np,int target,u_int spi_valid)3447 sym_xpt_async_transfer_neg(hcb_p np, int target, u_int spi_valid)
3448 {
3449 struct ccb_trans_settings *cts;
3450 struct cam_path *path;
3451 int sts;
3452 tcb_p tp = &np->target[target];
3453
3454 sts = xpt_create_path(&path, NULL, cam_sim_path(np->sim), target,
3455 CAM_LUN_WILDCARD);
3456 if (sts != CAM_REQ_CMP)
3457 return;
3458
3459 cts = &xpt_alloc_ccb()->cts;
3460
3461 #define cts__scsi (cts->proto_specific.scsi)
3462 #define cts__spi (cts->xport_specific.spi)
3463
3464 cts->type = CTS_TYPE_CURRENT_SETTINGS;
3465 cts->protocol = PROTO_SCSI;
3466 cts->transport = XPORT_SPI;
3467 cts->protocol_version = tp->tinfo.current.scsi_version;
3468 cts->transport_version = tp->tinfo.current.spi_version;
3469
3470 cts__spi.valid = spi_valid;
3471 if (spi_valid & CTS_SPI_VALID_SYNC_RATE)
3472 cts__spi.sync_period = tp->tinfo.current.period;
3473 if (spi_valid & CTS_SPI_VALID_SYNC_OFFSET)
3474 cts__spi.sync_offset = tp->tinfo.current.offset;
3475 if (spi_valid & CTS_SPI_VALID_BUS_WIDTH)
3476 cts__spi.bus_width = tp->tinfo.current.width;
3477 if (spi_valid & CTS_SPI_VALID_PPR_OPTIONS)
3478 cts__spi.ppr_options = tp->tinfo.current.options;
3479 #undef cts__spi
3480 #undef cts__scsi
3481 xpt_setup_ccb(&cts->ccb_h, path, /*priority*/1);
3482 xpt_async(AC_TRANSFER_NEG, path, cts);
3483 xpt_free_path(path);
3484 xpt_free_ccb(&cts->ccb_h);
3485 }
3486
3487 #define SYM_SPI_VALID_WDTR \
3488 CTS_SPI_VALID_BUS_WIDTH | \
3489 CTS_SPI_VALID_SYNC_RATE | \
3490 CTS_SPI_VALID_SYNC_OFFSET
3491 #define SYM_SPI_VALID_SDTR \
3492 CTS_SPI_VALID_SYNC_RATE | \
3493 CTS_SPI_VALID_SYNC_OFFSET
3494 #define SYM_SPI_VALID_PPR \
3495 CTS_SPI_VALID_PPR_OPTIONS | \
3496 CTS_SPI_VALID_BUS_WIDTH | \
3497 CTS_SPI_VALID_SYNC_RATE | \
3498 CTS_SPI_VALID_SYNC_OFFSET
3499
3500 /*
3501 * We received a WDTR.
3502 * Let everything be aware of the changes.
3503 */
sym_setwide(hcb_p np,ccb_p cp,u_char wide)3504 static void sym_setwide(hcb_p np, ccb_p cp, u_char wide)
3505 {
3506 tcb_p tp = &np->target[cp->target];
3507
3508 sym_settrans(np, cp, 0, 0, 0, wide, 0, 0);
3509
3510 /*
3511 * Tell the SCSI layer about the new transfer parameters.
3512 */
3513 tp->tinfo.goal.width = tp->tinfo.current.width = wide;
3514 tp->tinfo.current.offset = 0;
3515 tp->tinfo.current.period = 0;
3516 tp->tinfo.current.options = 0;
3517
3518 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_WDTR);
3519 }
3520
3521 /*
3522 * We received a SDTR.
3523 * Let everything be aware of the changes.
3524 */
3525 static void
sym_setsync(hcb_p np,ccb_p cp,u_char ofs,u_char per,u_char div,u_char fak)3526 sym_setsync(hcb_p np, ccb_p cp, u_char ofs, u_char per, u_char div, u_char fak)
3527 {
3528 tcb_p tp = &np->target[cp->target];
3529 u_char wide = (cp->phys.select.sel_scntl3 & EWS) ? 1 : 0;
3530
3531 sym_settrans(np, cp, 0, ofs, per, wide, div, fak);
3532
3533 /*
3534 * Tell the SCSI layer about the new transfer parameters.
3535 */
3536 tp->tinfo.goal.period = tp->tinfo.current.period = per;
3537 tp->tinfo.goal.offset = tp->tinfo.current.offset = ofs;
3538 tp->tinfo.goal.options = tp->tinfo.current.options = 0;
3539
3540 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_SDTR);
3541 }
3542
3543 /*
3544 * We received a PPR.
3545 * Let everything be aware of the changes.
3546 */
sym_setpprot(hcb_p np,ccb_p cp,u_char dt,u_char ofs,u_char per,u_char wide,u_char div,u_char fak)3547 static void sym_setpprot(hcb_p np, ccb_p cp, u_char dt, u_char ofs,
3548 u_char per, u_char wide, u_char div, u_char fak)
3549 {
3550 tcb_p tp = &np->target[cp->target];
3551
3552 sym_settrans(np, cp, dt, ofs, per, wide, div, fak);
3553
3554 /*
3555 * Tell the SCSI layer about the new transfer parameters.
3556 */
3557 tp->tinfo.goal.width = tp->tinfo.current.width = wide;
3558 tp->tinfo.goal.period = tp->tinfo.current.period = per;
3559 tp->tinfo.goal.offset = tp->tinfo.current.offset = ofs;
3560 tp->tinfo.goal.options = tp->tinfo.current.options = dt;
3561
3562 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_PPR);
3563 }
3564
3565 /*
3566 * Switch trans mode for current job and it's target.
3567 */
sym_settrans(hcb_p np,ccb_p cp,u_char dt,u_char ofs,u_char per,u_char wide,u_char div,u_char fak)3568 static void sym_settrans(hcb_p np, ccb_p cp, u_char dt, u_char ofs,
3569 u_char per, u_char wide, u_char div, u_char fak)
3570 {
3571 SYM_QUEHEAD *qp;
3572 union ccb *ccb;
3573 tcb_p tp;
3574 u_char target = INB (nc_sdid) & 0x0f;
3575 u_char sval, wval, uval;
3576
3577 assert (cp);
3578 if (!cp) return;
3579 ccb = cp->cam_ccb;
3580 assert (ccb);
3581 if (!ccb) return;
3582 assert (target == (cp->target & 0xf));
3583 tp = &np->target[target];
3584
3585 sval = tp->head.sval;
3586 wval = tp->head.wval;
3587 uval = tp->head.uval;
3588
3589 #if 0
3590 kprintf("XXXX sval=%x wval=%x uval=%x (%x)\n",
3591 sval, wval, uval, np->rv_scntl3);
3592 #endif
3593 /*
3594 * Set the offset.
3595 */
3596 if (!(np->features & FE_C10))
3597 sval = (sval & ~0x1f) | ofs;
3598 else
3599 sval = (sval & ~0x3f) | ofs;
3600
3601 /*
3602 * Set the sync divisor and extra clock factor.
3603 */
3604 if (ofs != 0) {
3605 wval = (wval & ~0x70) | ((div+1) << 4);
3606 if (!(np->features & FE_C10))
3607 sval = (sval & ~0xe0) | (fak << 5);
3608 else {
3609 uval = uval & ~(XCLKH_ST|XCLKH_DT|XCLKS_ST|XCLKS_DT);
3610 if (fak >= 1) uval |= (XCLKH_ST|XCLKH_DT);
3611 if (fak >= 2) uval |= (XCLKS_ST|XCLKS_DT);
3612 }
3613 }
3614
3615 /*
3616 * Set the bus width.
3617 */
3618 wval = wval & ~EWS;
3619 if (wide != 0)
3620 wval |= EWS;
3621
3622 /*
3623 * Set misc. ultra enable bits.
3624 */
3625 if (np->features & FE_C10) {
3626 uval = uval & ~(U3EN|AIPCKEN);
3627 if (dt) {
3628 assert(np->features & FE_U3EN);
3629 uval |= U3EN;
3630 }
3631 }
3632 else {
3633 wval = wval & ~ULTRA;
3634 if (per <= 12) wval |= ULTRA;
3635 }
3636
3637 /*
3638 * Stop there if sync parameters are unchanged.
3639 */
3640 if (tp->head.sval == sval &&
3641 tp->head.wval == wval &&
3642 tp->head.uval == uval)
3643 return;
3644 tp->head.sval = sval;
3645 tp->head.wval = wval;
3646 tp->head.uval = uval;
3647
3648 /*
3649 * Disable extended Sreq/Sack filtering if per < 50.
3650 * Not supported on the C1010.
3651 */
3652 if (per < 50 && !(np->features & FE_C10))
3653 OUTOFFB (nc_stest2, EXT);
3654
3655 /*
3656 * set actual value and sync_status
3657 */
3658 OUTB (nc_sxfer, tp->head.sval);
3659 OUTB (nc_scntl3, tp->head.wval);
3660
3661 if (np->features & FE_C10) {
3662 OUTB (nc_scntl4, tp->head.uval);
3663 }
3664
3665 /*
3666 * patch ALL busy ccbs of this target.
3667 */
3668 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) {
3669 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
3670 if (cp->target != target)
3671 continue;
3672 cp->phys.select.sel_scntl3 = tp->head.wval;
3673 cp->phys.select.sel_sxfer = tp->head.sval;
3674 if (np->features & FE_C10) {
3675 cp->phys.select.sel_scntl4 = tp->head.uval;
3676 }
3677 }
3678 }
3679
3680 /*
3681 * log message for real hard errors
3682 *
3683 * sym0 targ 0?: ERROR (ds:si) (so-si-sd) (sxfer/scntl3) @ name (dsp:dbc).
3684 * reg: r0 r1 r2 r3 r4 r5 r6 ..... rf.
3685 *
3686 * exception register:
3687 * ds: dstat
3688 * si: sist
3689 *
3690 * SCSI bus lines:
3691 * so: control lines as driven by chip.
3692 * si: control lines as seen by chip.
3693 * sd: scsi data lines as seen by chip.
3694 *
3695 * wide/fastmode:
3696 * sxfer: (see the manual)
3697 * scntl3: (see the manual)
3698 *
3699 * current script command:
3700 * dsp: script address (relative to start of script).
3701 * dbc: first word of script command.
3702 *
3703 * First 24 register of the chip:
3704 * r0..rf
3705 */
sym_log_hard_error(hcb_p np,u_short sist,u_char dstat)3706 static void sym_log_hard_error(hcb_p np, u_short sist, u_char dstat)
3707 {
3708 u32 dsp;
3709 int script_ofs;
3710 int script_size;
3711 char *script_name;
3712 u_char *script_base;
3713 int i;
3714
3715 dsp = INL (nc_dsp);
3716
3717 if (dsp > np->scripta_ba &&
3718 dsp <= np->scripta_ba + np->scripta_sz) {
3719 script_ofs = dsp - np->scripta_ba;
3720 script_size = np->scripta_sz;
3721 script_base = np->scripta0;
3722 script_name = "scripta";
3723 }
3724 else if (np->scriptb_ba < dsp &&
3725 dsp <= np->scriptb_ba + np->scriptb_sz) {
3726 script_ofs = dsp - np->scriptb_ba;
3727 script_size = np->scriptb_sz;
3728 script_base = np->scriptb0;
3729 script_name = "scriptb";
3730 } else {
3731 script_ofs = dsp;
3732 script_size = 0;
3733 script_base = NULL;
3734 script_name = "mem";
3735 }
3736
3737 kprintf ("%s:%d: ERROR (%x:%x) (%x-%x-%x) (%x/%x) @ (%s %x:%08x).\n",
3738 sym_name (np), (unsigned)INB (nc_sdid)&0x0f, dstat, sist,
3739 (unsigned)INB (nc_socl), (unsigned)INB (nc_sbcl),
3740 (unsigned)INB (nc_sbdl), (unsigned)INB (nc_sxfer),
3741 (unsigned)INB (nc_scntl3), script_name, script_ofs,
3742 (unsigned)INL (nc_dbc));
3743
3744 if (((script_ofs & 3) == 0) &&
3745 (unsigned)script_ofs < script_size) {
3746 kprintf ("%s: script cmd = %08x\n", sym_name(np),
3747 scr_to_cpu((int) *(u32 *)(script_base + script_ofs)));
3748 }
3749
3750 kprintf ("%s: regdump:", sym_name(np));
3751 for (i=0; i<24;i++)
3752 kprintf (" %02x", (unsigned)INB_OFF(i));
3753 kprintf (".\n");
3754
3755 /*
3756 * PCI BUS error, read the PCI ststus register.
3757 */
3758 if (dstat & (MDPE|BF)) {
3759 u_short pci_sts;
3760 pci_sts = pci_read_config(np->device, PCIR_STATUS, 2);
3761 if (pci_sts & 0xf900) {
3762 pci_write_config(np->device, PCIR_STATUS, pci_sts, 2);
3763 kprintf("%s: PCI STATUS = 0x%04x\n",
3764 sym_name(np), pci_sts & 0xf900);
3765 }
3766 }
3767 }
3768
3769 /*
3770 * chip interrupt handler
3771 *
3772 * In normal situations, interrupt conditions occur one at
3773 * a time. But when something bad happens on the SCSI BUS,
3774 * the chip may raise several interrupt flags before
3775 * stopping and interrupting the CPU. The additionnal
3776 * interrupt flags are stacked in some extra registers
3777 * after the SIP and/or DIP flag has been raised in the
3778 * ISTAT. After the CPU has read the interrupt condition
3779 * flag from SIST or DSTAT, the chip unstacks the other
3780 * interrupt flags and sets the corresponding bits in
3781 * SIST or DSTAT. Since the chip starts stacking once the
3782 * SIP or DIP flag is set, there is a small window of time
3783 * where the stacking does not occur.
3784 *
3785 * Typically, multiple interrupt conditions may happen in
3786 * the following situations:
3787 *
3788 * - SCSI parity error + Phase mismatch (PAR|MA)
3789 * When a parity error is detected in input phase
3790 * and the device switches to msg-in phase inside a
3791 * block MOV.
3792 * - SCSI parity error + Unexpected disconnect (PAR|UDC)
3793 * When a stupid device does not want to handle the
3794 * recovery of an SCSI parity error.
3795 * - Some combinations of STO, PAR, UDC, ...
3796 * When using non compliant SCSI stuff, when user is
3797 * doing non compliant hot tampering on the BUS, when
3798 * something really bad happens to a device, etc ...
3799 *
3800 * The heuristic suggested by SYMBIOS to handle
3801 * multiple interrupts is to try unstacking all
3802 * interrupts conditions and to handle them on some
3803 * priority based on error severity.
3804 * This will work when the unstacking has been
3805 * successful, but we cannot be 100 % sure of that,
3806 * since the CPU may have been faster to unstack than
3807 * the chip is able to stack. Hmmm ... But it seems that
3808 * such a situation is very unlikely to happen.
3809 *
3810 * If this happen, for example STO caught by the CPU
3811 * then UDC happenning before the CPU have restarted
3812 * the SCRIPTS, the driver may wrongly complete the
3813 * same command on UDC, since the SCRIPTS didn't restart
3814 * and the DSA still points to the same command.
3815 * We avoid this situation by setting the DSA to an
3816 * invalid value when the CCB is completed and before
3817 * restarting the SCRIPTS.
3818 *
3819 * Another issue is that we need some section of our
3820 * recovery procedures to be somehow uninterruptible but
3821 * the SCRIPTS processor does not provides such a
3822 * feature. For this reason, we handle recovery preferently
3823 * from the C code and check against some SCRIPTS critical
3824 * sections from the C code.
3825 *
3826 * Hopefully, the interrupt handling of the driver is now
3827 * able to resist to weird BUS error conditions, but donnot
3828 * ask me for any guarantee that it will never fail. :-)
3829 * Use at your own decision and risk.
3830 */
3831
sym_intr1(hcb_p np)3832 static void sym_intr1 (hcb_p np)
3833 {
3834 u_char istat, istatc;
3835 u_char dstat;
3836 u_short sist;
3837
3838 SYM_LOCK_ASSERT(LK_EXCLUSIVE);
3839
3840 /*
3841 * interrupt on the fly ?
3842 *
3843 * A `dummy read' is needed to ensure that the
3844 * clear of the INTF flag reaches the device
3845 * before the scanning of the DONE queue.
3846 */
3847 istat = INB (nc_istat);
3848 if (istat & INTF) {
3849 OUTB (nc_istat, (istat & SIGP) | INTF | np->istat_sem);
3850 istat = INB (nc_istat); /* DUMMY READ */
3851 if (DEBUG_FLAGS & DEBUG_TINY) kprintf ("F ");
3852 (void)sym_wakeup_done (np);
3853 }
3854
3855 if (!(istat & (SIP|DIP)))
3856 return;
3857
3858 #if 0 /* We should never get this one */
3859 if (istat & CABRT)
3860 OUTB (nc_istat, CABRT);
3861 #endif
3862
3863 /*
3864 * PAR and MA interrupts may occur at the same time,
3865 * and we need to know of both in order to handle
3866 * this situation properly. We try to unstack SCSI
3867 * interrupts for that reason. BTW, I dislike a LOT
3868 * such a loop inside the interrupt routine.
3869 * Even if DMA interrupt stacking is very unlikely to
3870 * happen, we also try unstacking these ones, since
3871 * this has no performance impact.
3872 */
3873 sist = 0;
3874 dstat = 0;
3875 istatc = istat;
3876 do {
3877 if (istatc & SIP)
3878 sist |= INW (nc_sist);
3879 if (istatc & DIP)
3880 dstat |= INB (nc_dstat);
3881 istatc = INB (nc_istat);
3882 istat |= istatc;
3883 } while (istatc & (SIP|DIP));
3884
3885 if (DEBUG_FLAGS & DEBUG_TINY)
3886 kprintf ("<%d|%x:%x|%x:%x>",
3887 (int)INB(nc_scr0),
3888 dstat,sist,
3889 (unsigned)INL(nc_dsp),
3890 (unsigned)INL(nc_dbc));
3891 /*
3892 * On paper, a memory barrier may be needed here.
3893 * And since we are paranoid ... :)
3894 */
3895 MEMORY_BARRIER();
3896
3897 /*
3898 * First, interrupts we want to service cleanly.
3899 *
3900 * Phase mismatch (MA) is the most frequent interrupt
3901 * for chip earlier than the 896 and so we have to service
3902 * it as quickly as possible.
3903 * A SCSI parity error (PAR) may be combined with a phase
3904 * mismatch condition (MA).
3905 * Programmed interrupts (SIR) are used to call the C code
3906 * from SCRIPTS.
3907 * The single step interrupt (SSI) is not used in this
3908 * driver.
3909 */
3910 if (!(sist & (STO|GEN|HTH|SGE|UDC|SBMC|RST)) &&
3911 !(dstat & (MDPE|BF|ABRT|IID))) {
3912 if (sist & PAR) sym_int_par (np, sist);
3913 else if (sist & MA) sym_int_ma (np);
3914 else if (dstat & SIR) sym_int_sir (np);
3915 else if (dstat & SSI) OUTONB_STD ();
3916 else goto unknown_int;
3917 return;
3918 }
3919
3920 /*
3921 * Now, interrupts that donnot happen in normal
3922 * situations and that we may need to recover from.
3923 *
3924 * On SCSI RESET (RST), we reset everything.
3925 * On SCSI BUS MODE CHANGE (SBMC), we complete all
3926 * active CCBs with RESET status, prepare all devices
3927 * for negotiating again and restart the SCRIPTS.
3928 * On STO and UDC, we complete the CCB with the corres-
3929 * ponding status and restart the SCRIPTS.
3930 */
3931 if (sist & RST) {
3932 xpt_print_path(np->path);
3933 kprintf("SCSI BUS reset detected.\n");
3934 sym_init (np, 1);
3935 return;
3936 }
3937
3938 OUTB (nc_ctest3, np->rv_ctest3 | CLF); /* clear dma fifo */
3939 OUTB (nc_stest3, TE|CSF); /* clear scsi fifo */
3940
3941 if (!(sist & (GEN|HTH|SGE)) &&
3942 !(dstat & (MDPE|BF|ABRT|IID))) {
3943 if (sist & SBMC) sym_int_sbmc (np);
3944 else if (sist & STO) sym_int_sto (np);
3945 else if (sist & UDC) sym_int_udc (np);
3946 else goto unknown_int;
3947 return;
3948 }
3949
3950 /*
3951 * Now, interrupts we are not able to recover cleanly.
3952 *
3953 * Log message for hard errors.
3954 * Reset everything.
3955 */
3956
3957 sym_log_hard_error(np, sist, dstat);
3958
3959 if ((sist & (GEN|HTH|SGE)) ||
3960 (dstat & (MDPE|BF|ABRT|IID))) {
3961 sym_start_reset(np);
3962 return;
3963 }
3964
3965 unknown_int:
3966 /*
3967 * We just miss the cause of the interrupt. :(
3968 * Print a message. The timeout will do the real work.
3969 */
3970 kprintf( "%s: unknown interrupt(s) ignored, "
3971 "ISTAT=0x%x DSTAT=0x%x SIST=0x%x\n",
3972 sym_name(np), istat, dstat, sist);
3973 }
3974
sym_intr(void * arg)3975 static void sym_intr(void *arg)
3976 {
3977 hcb_p np = arg;
3978
3979 SYM_LOCK();
3980
3981 if (DEBUG_FLAGS & DEBUG_TINY) kprintf ("[");
3982 sym_intr1((hcb_p) arg);
3983 if (DEBUG_FLAGS & DEBUG_TINY) kprintf ("]");
3984
3985 SYM_UNLOCK();
3986 }
3987
sym_poll(struct cam_sim * sim)3988 static void sym_poll(struct cam_sim *sim)
3989 {
3990 sym_intr1(cam_sim_softc(sim));
3991 }
3992
3993
3994 /*
3995 * generic recovery from scsi interrupt
3996 *
3997 * The doc says that when the chip gets an SCSI interrupt,
3998 * it tries to stop in an orderly fashion, by completing
3999 * an instruction fetch that had started or by flushing
4000 * the DMA fifo for a write to memory that was executing.
4001 * Such a fashion is not enough to know if the instruction
4002 * that was just before the current DSP value has been
4003 * executed or not.
4004 *
4005 * There are some small SCRIPTS sections that deal with
4006 * the start queue and the done queue that may break any
4007 * assomption from the C code if we are interrupted
4008 * inside, so we reset if this happens. Btw, since these
4009 * SCRIPTS sections are executed while the SCRIPTS hasn't
4010 * started SCSI operations, it is very unlikely to happen.
4011 *
4012 * All the driver data structures are supposed to be
4013 * allocated from the same 4 GB memory window, so there
4014 * is a 1 to 1 relationship between DSA and driver data
4015 * structures. Since we are careful :) to invalidate the
4016 * DSA when we complete a command or when the SCRIPTS
4017 * pushes a DSA into a queue, we can trust it when it
4018 * points to a CCB.
4019 */
sym_recover_scsi_int(hcb_p np,u_char hsts)4020 static void sym_recover_scsi_int (hcb_p np, u_char hsts)
4021 {
4022 u32 dsp = INL (nc_dsp);
4023 u32 dsa = INL (nc_dsa);
4024 ccb_p cp = sym_ccb_from_dsa(np, dsa);
4025
4026 /*
4027 * If we haven't been interrupted inside the SCRIPTS
4028 * critical pathes, we can safely restart the SCRIPTS
4029 * and trust the DSA value if it matches a CCB.
4030 */
4031 if ((!(dsp > SCRIPTA_BA (np, getjob_begin) &&
4032 dsp < SCRIPTA_BA (np, getjob_end) + 1)) &&
4033 (!(dsp > SCRIPTA_BA (np, ungetjob) &&
4034 dsp < SCRIPTA_BA (np, reselect) + 1)) &&
4035 (!(dsp > SCRIPTB_BA (np, sel_for_abort) &&
4036 dsp < SCRIPTB_BA (np, sel_for_abort_1) + 1)) &&
4037 (!(dsp > SCRIPTA_BA (np, done) &&
4038 dsp < SCRIPTA_BA (np, done_end) + 1))) {
4039 OUTB (nc_ctest3, np->rv_ctest3 | CLF); /* clear dma fifo */
4040 OUTB (nc_stest3, TE|CSF); /* clear scsi fifo */
4041 /*
4042 * If we have a CCB, let the SCRIPTS call us back for
4043 * the handling of the error with SCRATCHA filled with
4044 * STARTPOS. This way, we will be able to freeze the
4045 * device queue and requeue awaiting IOs.
4046 */
4047 if (cp) {
4048 cp->host_status = hsts;
4049 OUTL_DSP (SCRIPTA_BA (np, complete_error));
4050 }
4051 /*
4052 * Otherwise just restart the SCRIPTS.
4053 */
4054 else {
4055 OUTL (nc_dsa, 0xffffff);
4056 OUTL_DSP (SCRIPTA_BA (np, start));
4057 }
4058 }
4059 else
4060 goto reset_all;
4061
4062 return;
4063
4064 reset_all:
4065 sym_start_reset(np);
4066 }
4067
4068 /*
4069 * chip exception handler for selection timeout
4070 */
sym_int_sto(hcb_p np)4071 static void sym_int_sto (hcb_p np)
4072 {
4073 u32 dsp = INL (nc_dsp);
4074
4075 if (DEBUG_FLAGS & DEBUG_TINY) kprintf ("T");
4076
4077 if (dsp == SCRIPTA_BA (np, wf_sel_done) + 8)
4078 sym_recover_scsi_int(np, HS_SEL_TIMEOUT);
4079 else
4080 sym_start_reset(np);
4081 }
4082
4083 /*
4084 * chip exception handler for unexpected disconnect
4085 */
sym_int_udc(hcb_p np)4086 static void sym_int_udc (hcb_p np)
4087 {
4088 kprintf ("%s: unexpected disconnect\n", sym_name(np));
4089 sym_recover_scsi_int(np, HS_UNEXPECTED);
4090 }
4091
4092 /*
4093 * chip exception handler for SCSI bus mode change
4094 *
4095 * spi2-r12 11.2.3 says a transceiver mode change must
4096 * generate a reset event and a device that detects a reset
4097 * event shall initiate a hard reset. It says also that a
4098 * device that detects a mode change shall set data transfer
4099 * mode to eight bit asynchronous, etc...
4100 * So, just reinitializing all except chip should be enough.
4101 */
sym_int_sbmc(hcb_p np)4102 static void sym_int_sbmc (hcb_p np)
4103 {
4104 u_char scsi_mode = INB (nc_stest4) & SMODE;
4105
4106 /*
4107 * Notify user.
4108 */
4109 xpt_print_path(np->path);
4110 kprintf("SCSI BUS mode change from %s to %s.\n",
4111 sym_scsi_bus_mode(np->scsi_mode), sym_scsi_bus_mode(scsi_mode));
4112
4113 /*
4114 * Should suspend command processing for a few seconds and
4115 * reinitialize all except the chip.
4116 */
4117 sym_init (np, 2);
4118 }
4119
4120 /*
4121 * chip exception handler for SCSI parity error.
4122 *
4123 * When the chip detects a SCSI parity error and is
4124 * currently executing a (CH)MOV instruction, it does
4125 * not interrupt immediately, but tries to finish the
4126 * transfer of the current scatter entry before
4127 * interrupting. The following situations may occur:
4128 *
4129 * - The complete scatter entry has been transferred
4130 * without the device having changed phase.
4131 * The chip will then interrupt with the DSP pointing
4132 * to the instruction that follows the MOV.
4133 *
4134 * - A phase mismatch occurs before the MOV finished
4135 * and phase errors are to be handled by the C code.
4136 * The chip will then interrupt with both PAR and MA
4137 * conditions set.
4138 *
4139 * - A phase mismatch occurs before the MOV finished and
4140 * phase errors are to be handled by SCRIPTS.
4141 * The chip will load the DSP with the phase mismatch
4142 * JUMP address and interrupt the host processor.
4143 */
sym_int_par(hcb_p np,u_short sist)4144 static void sym_int_par (hcb_p np, u_short sist)
4145 {
4146 u_char hsts = INB (HS_PRT);
4147 u32 dsp = INL (nc_dsp);
4148 u32 dbc = INL (nc_dbc);
4149 u32 dsa = INL (nc_dsa);
4150 u_char sbcl = INB (nc_sbcl);
4151 u_char cmd = dbc >> 24;
4152 int phase = cmd & 7;
4153 ccb_p cp = sym_ccb_from_dsa(np, dsa);
4154
4155 kprintf("%s: SCSI parity error detected: SCR1=%d DBC=%x SBCL=%x\n",
4156 sym_name(np), hsts, dbc, sbcl);
4157
4158 /*
4159 * Check that the chip is connected to the SCSI BUS.
4160 */
4161 if (!(INB (nc_scntl1) & ISCON)) {
4162 sym_recover_scsi_int(np, HS_UNEXPECTED);
4163 return;
4164 }
4165
4166 /*
4167 * If the nexus is not clearly identified, reset the bus.
4168 * We will try to do better later.
4169 */
4170 if (!cp)
4171 goto reset_all;
4172
4173 /*
4174 * Check instruction was a MOV, direction was INPUT and
4175 * ATN is asserted.
4176 */
4177 if ((cmd & 0xc0) || !(phase & 1) || !(sbcl & 0x8))
4178 goto reset_all;
4179
4180 /*
4181 * Keep track of the parity error.
4182 */
4183 OUTONB (HF_PRT, HF_EXT_ERR);
4184 cp->xerr_status |= XE_PARITY_ERR;
4185
4186 /*
4187 * Prepare the message to send to the device.
4188 */
4189 np->msgout[0] = (phase == 7) ? M_PARITY : M_ID_ERROR;
4190
4191 /*
4192 * If the old phase was DATA IN phase, we have to deal with
4193 * the 3 situations described above.
4194 * For other input phases (MSG IN and STATUS), the device
4195 * must resend the whole thing that failed parity checking
4196 * or signal error. So, jumping to dispatcher should be OK.
4197 */
4198 if (phase == 1 || phase == 5) {
4199 /* Phase mismatch handled by SCRIPTS */
4200 if (dsp == SCRIPTB_BA (np, pm_handle))
4201 OUTL_DSP (dsp);
4202 /* Phase mismatch handled by the C code */
4203 else if (sist & MA)
4204 sym_int_ma (np);
4205 /* No phase mismatch occurred */
4206 else {
4207 OUTL (nc_temp, dsp);
4208 OUTL_DSP (SCRIPTA_BA (np, dispatch));
4209 }
4210 }
4211 else
4212 OUTL_DSP (SCRIPTA_BA (np, clrack));
4213 return;
4214
4215 reset_all:
4216 sym_start_reset(np);
4217 }
4218
4219 /*
4220 * chip exception handler for phase errors.
4221 *
4222 * We have to construct a new transfer descriptor,
4223 * to transfer the rest of the current block.
4224 */
sym_int_ma(hcb_p np)4225 static void sym_int_ma (hcb_p np)
4226 {
4227 u32 dbc;
4228 u32 rest;
4229 u32 dsp;
4230 u32 dsa;
4231 u32 nxtdsp;
4232 u32 *vdsp;
4233 u32 oadr, olen;
4234 u32 *tblp;
4235 u32 newcmd;
4236 u_int delta;
4237 u_char cmd;
4238 u_char hflags, hflags0;
4239 struct sym_pmc *pm;
4240 ccb_p cp;
4241
4242 dsp = INL (nc_dsp);
4243 dbc = INL (nc_dbc);
4244 dsa = INL (nc_dsa);
4245
4246 cmd = dbc >> 24;
4247 rest = dbc & 0xffffff;
4248 delta = 0;
4249
4250 /*
4251 * locate matching cp if any.
4252 */
4253 cp = sym_ccb_from_dsa(np, dsa);
4254
4255 /*
4256 * Donnot take into account dma fifo and various buffers in
4257 * INPUT phase since the chip flushes everything before
4258 * raising the MA interrupt for interrupted INPUT phases.
4259 * For DATA IN phase, we will check for the SWIDE later.
4260 */
4261 if ((cmd & 7) != 1 && (cmd & 7) != 5) {
4262 u_char ss0, ss2;
4263
4264 if (np->features & FE_DFBC)
4265 delta = INW (nc_dfbc);
4266 else {
4267 u32 dfifo;
4268
4269 /*
4270 * Read DFIFO, CTEST[4-6] using 1 PCI bus ownership.
4271 */
4272 dfifo = INL(nc_dfifo);
4273
4274 /*
4275 * Calculate remaining bytes in DMA fifo.
4276 * (CTEST5 = dfifo >> 16)
4277 */
4278 if (dfifo & (DFS << 16))
4279 delta = ((((dfifo >> 8) & 0x300) |
4280 (dfifo & 0xff)) - rest) & 0x3ff;
4281 else
4282 delta = ((dfifo & 0xff) - rest) & 0x7f;
4283 }
4284
4285 /*
4286 * The data in the dma fifo has not been transferred to
4287 * the target -> add the amount to the rest
4288 * and clear the data.
4289 * Check the sstat2 register in case of wide transfer.
4290 */
4291 rest += delta;
4292 ss0 = INB (nc_sstat0);
4293 if (ss0 & OLF) rest++;
4294 if (!(np->features & FE_C10))
4295 if (ss0 & ORF) rest++;
4296 if (cp && (cp->phys.select.sel_scntl3 & EWS)) {
4297 ss2 = INB (nc_sstat2);
4298 if (ss2 & OLF1) rest++;
4299 if (!(np->features & FE_C10))
4300 if (ss2 & ORF1) rest++;
4301 }
4302
4303 /*
4304 * Clear fifos.
4305 */
4306 OUTB (nc_ctest3, np->rv_ctest3 | CLF); /* dma fifo */
4307 OUTB (nc_stest3, TE|CSF); /* scsi fifo */
4308 }
4309
4310 /*
4311 * log the information
4312 */
4313 if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_PHASE))
4314 kprintf ("P%x%x RL=%d D=%d ", cmd&7, INB(nc_sbcl)&7,
4315 (unsigned) rest, (unsigned) delta);
4316
4317 /*
4318 * try to find the interrupted script command,
4319 * and the address at which to continue.
4320 */
4321 vdsp = NULL;
4322 nxtdsp = 0;
4323 if (dsp > np->scripta_ba &&
4324 dsp <= np->scripta_ba + np->scripta_sz) {
4325 vdsp = (u32 *)((char*)np->scripta0 + (dsp-np->scripta_ba-8));
4326 nxtdsp = dsp;
4327 }
4328 else if (dsp > np->scriptb_ba &&
4329 dsp <= np->scriptb_ba + np->scriptb_sz) {
4330 vdsp = (u32 *)((char*)np->scriptb0 + (dsp-np->scriptb_ba-8));
4331 nxtdsp = dsp;
4332 }
4333
4334 /*
4335 * log the information
4336 */
4337 if (DEBUG_FLAGS & DEBUG_PHASE) {
4338 kprintf ("\nCP=%p DSP=%x NXT=%x VDSP=%p CMD=%x ",
4339 cp, (unsigned)dsp, (unsigned)nxtdsp, vdsp, cmd);
4340 }
4341
4342 if (!vdsp) {
4343 kprintf ("%s: interrupted SCRIPT address not found.\n",
4344 sym_name (np));
4345 goto reset_all;
4346 }
4347
4348 if (!cp) {
4349 kprintf ("%s: SCSI phase error fixup: CCB already dequeued.\n",
4350 sym_name (np));
4351 goto reset_all;
4352 }
4353
4354 /*
4355 * get old startaddress and old length.
4356 */
4357 oadr = scr_to_cpu(vdsp[1]);
4358
4359 if (cmd & 0x10) { /* Table indirect */
4360 tblp = (u32 *) ((char*) &cp->phys + oadr);
4361 olen = scr_to_cpu(tblp[0]);
4362 oadr = scr_to_cpu(tblp[1]);
4363 } else {
4364 tblp = NULL;
4365 olen = scr_to_cpu(vdsp[0]) & 0xffffff;
4366 }
4367
4368 if (DEBUG_FLAGS & DEBUG_PHASE) {
4369 kprintf ("OCMD=%x\nTBLP=%p OLEN=%x OADR=%x\n",
4370 (unsigned) (scr_to_cpu(vdsp[0]) >> 24),
4371 tblp,
4372 (unsigned) olen,
4373 (unsigned) oadr);
4374 }
4375
4376 /*
4377 * check cmd against assumed interrupted script command.
4378 * If dt data phase, the MOVE instruction hasn't bit 4 of
4379 * the phase.
4380 */
4381 if (((cmd & 2) ? cmd : (cmd & ~4)) != (scr_to_cpu(vdsp[0]) >> 24)) {
4382 PRINT_ADDR(cp);
4383 kprintf ("internal error: cmd=%02x != %02x=(vdsp[0] >> 24)\n",
4384 (unsigned)cmd, (unsigned)scr_to_cpu(vdsp[0]) >> 24);
4385
4386 goto reset_all;
4387 }
4388
4389 /*
4390 * if old phase not dataphase, leave here.
4391 */
4392 if (cmd & 2) {
4393 PRINT_ADDR(cp);
4394 kprintf ("phase change %x-%x %d@%08x resid=%d.\n",
4395 cmd&7, INB(nc_sbcl)&7, (unsigned)olen,
4396 (unsigned)oadr, (unsigned)rest);
4397 goto unexpected_phase;
4398 }
4399
4400 /*
4401 * Choose the correct PM save area.
4402 *
4403 * Look at the PM_SAVE SCRIPT if you want to understand
4404 * this stuff. The equivalent code is implemented in
4405 * SCRIPTS for the 895A, 896 and 1010 that are able to
4406 * handle PM from the SCRIPTS processor.
4407 */
4408 hflags0 = INB (HF_PRT);
4409 hflags = hflags0;
4410
4411 if (hflags & (HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED)) {
4412 if (hflags & HF_IN_PM0)
4413 nxtdsp = scr_to_cpu(cp->phys.pm0.ret);
4414 else if (hflags & HF_IN_PM1)
4415 nxtdsp = scr_to_cpu(cp->phys.pm1.ret);
4416
4417 if (hflags & HF_DP_SAVED)
4418 hflags ^= HF_ACT_PM;
4419 }
4420
4421 if (!(hflags & HF_ACT_PM)) {
4422 pm = &cp->phys.pm0;
4423 newcmd = SCRIPTA_BA (np, pm0_data);
4424 }
4425 else {
4426 pm = &cp->phys.pm1;
4427 newcmd = SCRIPTA_BA (np, pm1_data);
4428 }
4429
4430 hflags &= ~(HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED);
4431 if (hflags != hflags0)
4432 OUTB (HF_PRT, hflags);
4433
4434 /*
4435 * fillin the phase mismatch context
4436 */
4437 pm->sg.addr = cpu_to_scr(oadr + olen - rest);
4438 pm->sg.size = cpu_to_scr(rest);
4439 pm->ret = cpu_to_scr(nxtdsp);
4440
4441 /*
4442 * If we have a SWIDE,
4443 * - prepare the address to write the SWIDE from SCRIPTS,
4444 * - compute the SCRIPTS address to restart from,
4445 * - move current data pointer context by one byte.
4446 */
4447 nxtdsp = SCRIPTA_BA (np, dispatch);
4448 if ((cmd & 7) == 1 && cp && (cp->phys.select.sel_scntl3 & EWS) &&
4449 (INB (nc_scntl2) & WSR)) {
4450 u32 tmp;
4451
4452 /*
4453 * Set up the table indirect for the MOVE
4454 * of the residual byte and adjust the data
4455 * pointer context.
4456 */
4457 tmp = scr_to_cpu(pm->sg.addr);
4458 cp->phys.wresid.addr = cpu_to_scr(tmp);
4459 pm->sg.addr = cpu_to_scr(tmp + 1);
4460 tmp = scr_to_cpu(pm->sg.size);
4461 cp->phys.wresid.size = cpu_to_scr((tmp&0xff000000) | 1);
4462 pm->sg.size = cpu_to_scr(tmp - 1);
4463
4464 /*
4465 * If only the residual byte is to be moved,
4466 * no PM context is needed.
4467 */
4468 if ((tmp&0xffffff) == 1)
4469 newcmd = pm->ret;
4470
4471 /*
4472 * Prepare the address of SCRIPTS that will
4473 * move the residual byte to memory.
4474 */
4475 nxtdsp = SCRIPTB_BA (np, wsr_ma_helper);
4476 }
4477
4478 if (DEBUG_FLAGS & DEBUG_PHASE) {
4479 PRINT_ADDR(cp);
4480 kprintf ("PM %x %x %x / %x %x %x.\n",
4481 hflags0, hflags, newcmd,
4482 (unsigned)scr_to_cpu(pm->sg.addr),
4483 (unsigned)scr_to_cpu(pm->sg.size),
4484 (unsigned)scr_to_cpu(pm->ret));
4485 }
4486
4487 /*
4488 * Restart the SCRIPTS processor.
4489 */
4490 OUTL (nc_temp, newcmd);
4491 OUTL_DSP (nxtdsp);
4492 return;
4493
4494 /*
4495 * Unexpected phase changes that occurs when the current phase
4496 * is not a DATA IN or DATA OUT phase are due to error conditions.
4497 * Such event may only happen when the SCRIPTS is using a
4498 * multibyte SCSI MOVE.
4499 *
4500 * Phase change Some possible cause
4501 *
4502 * COMMAND --> MSG IN SCSI parity error detected by target.
4503 * COMMAND --> STATUS Bad command or refused by target.
4504 * MSG OUT --> MSG IN Message rejected by target.
4505 * MSG OUT --> COMMAND Bogus target that discards extended
4506 * negotiation messages.
4507 *
4508 * The code below does not care of the new phase and so
4509 * trusts the target. Why to annoy it ?
4510 * If the interrupted phase is COMMAND phase, we restart at
4511 * dispatcher.
4512 * If a target does not get all the messages after selection,
4513 * the code assumes blindly that the target discards extended
4514 * messages and clears the negotiation status.
4515 * If the target does not want all our response to negotiation,
4516 * we force a SIR_NEGO_PROTO interrupt (it is a hack that avoids
4517 * bloat for such a should_not_happen situation).
4518 * In all other situation, we reset the BUS.
4519 * Are these assumptions reasonnable ? (Wait and see ...)
4520 */
4521 unexpected_phase:
4522 dsp -= 8;
4523 nxtdsp = 0;
4524
4525 switch (cmd & 7) {
4526 case 2: /* COMMAND phase */
4527 nxtdsp = SCRIPTA_BA (np, dispatch);
4528 break;
4529 #if 0
4530 case 3: /* STATUS phase */
4531 nxtdsp = SCRIPTA_BA (np, dispatch);
4532 break;
4533 #endif
4534 case 6: /* MSG OUT phase */
4535 /*
4536 * If the device may want to use untagged when we want
4537 * tagged, we prepare an IDENTIFY without disc. granted,
4538 * since we will not be able to handle reselect.
4539 * Otherwise, we just don't care.
4540 */
4541 if (dsp == SCRIPTA_BA (np, send_ident)) {
4542 if (cp->tag != NO_TAG && olen - rest <= 3) {
4543 cp->host_status = HS_BUSY;
4544 np->msgout[0] = M_IDENTIFY | cp->lun;
4545 nxtdsp = SCRIPTB_BA (np, ident_break_atn);
4546 }
4547 else
4548 nxtdsp = SCRIPTB_BA (np, ident_break);
4549 }
4550 else if (dsp == SCRIPTB_BA (np, send_wdtr) ||
4551 dsp == SCRIPTB_BA (np, send_sdtr) ||
4552 dsp == SCRIPTB_BA (np, send_ppr)) {
4553 nxtdsp = SCRIPTB_BA (np, nego_bad_phase);
4554 }
4555 break;
4556 #if 0
4557 case 7: /* MSG IN phase */
4558 nxtdsp = SCRIPTA_BA (np, clrack);
4559 break;
4560 #endif
4561 }
4562
4563 if (nxtdsp) {
4564 OUTL_DSP (nxtdsp);
4565 return;
4566 }
4567
4568 reset_all:
4569 sym_start_reset(np);
4570 }
4571
4572 /*
4573 * Dequeue from the START queue all CCBs that match
4574 * a given target/lun/task condition (-1 means all),
4575 * and move them from the BUSY queue to the COMP queue
4576 * with CAM_REQUEUE_REQ status condition.
4577 * This function is used during error handling/recovery.
4578 * It is called with SCRIPTS not running.
4579 */
4580 static int
sym_dequeue_from_squeue(hcb_p np,int i,int target,int lun,int task)4581 sym_dequeue_from_squeue(hcb_p np, int i, int target, int lun, int task)
4582 {
4583 int j;
4584 ccb_p cp;
4585
4586 /*
4587 * Make sure the starting index is within range.
4588 */
4589 assert((i >= 0) && (i < 2*MAX_QUEUE));
4590
4591 /*
4592 * Walk until end of START queue and dequeue every job
4593 * that matches the target/lun/task condition.
4594 */
4595 j = i;
4596 while (i != np->squeueput) {
4597 cp = sym_ccb_from_dsa(np, scr_to_cpu(np->squeue[i]));
4598 assert(cp);
4599 #ifdef SYM_CONF_IARB_SUPPORT
4600 /* Forget hints for IARB, they may be no longer relevant */
4601 cp->host_flags &= ~HF_HINT_IARB;
4602 #endif
4603 if ((target == -1 || cp->target == target) &&
4604 (lun == -1 || cp->lun == lun) &&
4605 (task == -1 || cp->tag == task)) {
4606 sym_set_cam_status(cp->cam_ccb, CAM_REQUEUE_REQ);
4607 sym_remque(&cp->link_ccbq);
4608 sym_insque_tail(&cp->link_ccbq, &np->comp_ccbq);
4609 }
4610 else {
4611 if (i != j)
4612 np->squeue[j] = np->squeue[i];
4613 if ((j += 2) >= MAX_QUEUE*2) j = 0;
4614 }
4615 if ((i += 2) >= MAX_QUEUE*2) i = 0;
4616 }
4617 if (i != j) /* Copy back the idle task if needed */
4618 np->squeue[j] = np->squeue[i];
4619 np->squeueput = j; /* Update our current start queue pointer */
4620
4621 return (i - j) / 2;
4622 }
4623
4624 /*
4625 * Complete all CCBs queued to the COMP queue.
4626 *
4627 * These CCBs are assumed:
4628 * - Not to be referenced either by devices or
4629 * SCRIPTS-related queues and datas.
4630 * - To have to be completed with an error condition
4631 * or requeued.
4632 *
4633 * The device queue freeze count is incremented
4634 * for each CCB that does not prevent this.
4635 * This function is called when all CCBs involved
4636 * in error handling/recovery have been reaped.
4637 */
4638 static void
sym_flush_comp_queue(hcb_p np,int cam_status)4639 sym_flush_comp_queue(hcb_p np, int cam_status)
4640 {
4641 SYM_QUEHEAD *qp;
4642 ccb_p cp;
4643
4644 while ((qp = sym_remque_head(&np->comp_ccbq)) != NULL) {
4645 union ccb *ccb;
4646 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
4647 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq);
4648 /* Leave quiet CCBs waiting for resources */
4649 if (cp->host_status == HS_WAIT)
4650 continue;
4651 ccb = cp->cam_ccb;
4652 if (cam_status)
4653 sym_set_cam_status(ccb, cam_status);
4654 sym_freeze_cam_ccb(ccb);
4655 sym_xpt_done(np, ccb, cp);
4656 sym_free_ccb(np, cp);
4657 }
4658 }
4659
4660 /*
4661 * chip handler for bad SCSI status condition
4662 *
4663 * In case of bad SCSI status, we unqueue all the tasks
4664 * currently queued to the controller but not yet started
4665 * and then restart the SCRIPTS processor immediately.
4666 *
4667 * QUEUE FULL and BUSY conditions are handled the same way.
4668 * Basically all the not yet started tasks are requeued in
4669 * device queue and the queue is frozen until a completion.
4670 *
4671 * For CHECK CONDITION and COMMAND TERMINATED status, we use
4672 * the CCB of the failed command to prepare a REQUEST SENSE
4673 * SCSI command and queue it to the controller queue.
4674 *
4675 * SCRATCHA is assumed to have been loaded with STARTPOS
4676 * before the SCRIPTS called the C code.
4677 */
sym_sir_bad_scsi_status(hcb_p np,int num,ccb_p cp)4678 static void sym_sir_bad_scsi_status(hcb_p np, int num, ccb_p cp)
4679 {
4680 tcb_p tp = &np->target[cp->target];
4681 u32 startp;
4682 u_char s_status = cp->ssss_status;
4683 u_char h_flags = cp->host_flags;
4684 int msglen;
4685 int nego;
4686 int i;
4687
4688 SYM_LOCK_ASSERT(LK_EXCLUSIVE);
4689
4690 /*
4691 * Compute the index of the next job to start from SCRIPTS.
4692 */
4693 i = (INL (nc_scratcha) - np->squeue_ba) / 4;
4694
4695 /*
4696 * The last CCB queued used for IARB hint may be
4697 * no longer relevant. Forget it.
4698 */
4699 #ifdef SYM_CONF_IARB_SUPPORT
4700 if (np->last_cp)
4701 np->last_cp = NULL;
4702 #endif
4703
4704 /*
4705 * Now deal with the SCSI status.
4706 */
4707 switch(s_status) {
4708 case S_BUSY:
4709 case S_QUEUE_FULL:
4710 if (sym_verbose >= 2) {
4711 PRINT_ADDR(cp);
4712 kprintf (s_status == S_BUSY ? "BUSY" : "QUEUE FULL\n");
4713 }
4714 default: /* S_INT, S_INT_COND_MET, S_CONFLICT */
4715 sym_complete_error (np, cp);
4716 break;
4717 case S_TERMINATED:
4718 case S_CHECK_COND:
4719 /*
4720 * If we get an SCSI error when requesting sense, give up.
4721 */
4722 if (h_flags & HF_SENSE) {
4723 sym_complete_error (np, cp);
4724 break;
4725 }
4726
4727 /*
4728 * Dequeue all queued CCBs for that device not yet started,
4729 * and restart the SCRIPTS processor immediately.
4730 */
4731 (void) sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1);
4732 OUTL_DSP (SCRIPTA_BA (np, start));
4733
4734 /*
4735 * Save some info of the actual IO.
4736 * Compute the data residual.
4737 */
4738 cp->sv_scsi_status = cp->ssss_status;
4739 cp->sv_xerr_status = cp->xerr_status;
4740 cp->sv_resid = sym_compute_residual(np, cp);
4741
4742 /*
4743 * Prepare all needed data structures for
4744 * requesting sense data.
4745 */
4746
4747 /*
4748 * identify message
4749 */
4750 cp->scsi_smsg2[0] = M_IDENTIFY | cp->lun;
4751 msglen = 1;
4752
4753 /*
4754 * If we are currently using anything different from
4755 * async. 8 bit data transfers with that target,
4756 * start a negotiation, since the device may want
4757 * to report us a UNIT ATTENTION condition due to
4758 * a cause we currently ignore, and we donnot want
4759 * to be stuck with WIDE and/or SYNC data transfer.
4760 *
4761 * cp->nego_status is filled by sym_prepare_nego().
4762 */
4763 cp->nego_status = 0;
4764 nego = 0;
4765 if (tp->tinfo.current.options & PPR_OPT_MASK)
4766 nego = NS_PPR;
4767 else if (tp->tinfo.current.width != BUS_8_BIT)
4768 nego = NS_WIDE;
4769 else if (tp->tinfo.current.offset != 0)
4770 nego = NS_SYNC;
4771 if (nego)
4772 msglen +=
4773 sym_prepare_nego (np,cp, nego, &cp->scsi_smsg2[msglen]);
4774 /*
4775 * Message table indirect structure.
4776 */
4777 cp->phys.smsg.addr = cpu_to_scr(CCB_BA (cp, scsi_smsg2));
4778 cp->phys.smsg.size = cpu_to_scr(msglen);
4779
4780 /*
4781 * sense command
4782 */
4783 cp->phys.cmd.addr = cpu_to_scr(CCB_BA (cp, sensecmd));
4784 cp->phys.cmd.size = cpu_to_scr(6);
4785
4786 /*
4787 * patch requested size into sense command
4788 */
4789 cp->sensecmd[0] = 0x03;
4790 cp->sensecmd[1] = cp->lun << 5;
4791 if (tp->tinfo.current.scsi_version > 2 || cp->lun > 7)
4792 cp->sensecmd[1] = 0;
4793 cp->sensecmd[4] = SYM_SNS_BBUF_LEN;
4794 cp->data_len = SYM_SNS_BBUF_LEN;
4795
4796 /*
4797 * sense data
4798 */
4799 bzero(cp->sns_bbuf, SYM_SNS_BBUF_LEN);
4800 cp->phys.sense.addr = cpu_to_scr(vtobus(cp->sns_bbuf));
4801 cp->phys.sense.size = cpu_to_scr(SYM_SNS_BBUF_LEN);
4802
4803 /*
4804 * requeue the command.
4805 */
4806 startp = SCRIPTB_BA (np, sdata_in);
4807
4808 cp->phys.head.savep = cpu_to_scr(startp);
4809 cp->phys.head.goalp = cpu_to_scr(startp + 16);
4810 cp->phys.head.lastp = cpu_to_scr(startp);
4811 cp->startp = cpu_to_scr(startp);
4812
4813 cp->actualquirks = SYM_QUIRK_AUTOSAVE;
4814 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY;
4815 cp->ssss_status = S_ILLEGAL;
4816 cp->host_flags = (HF_SENSE|HF_DATA_IN);
4817 cp->xerr_status = 0;
4818 cp->extra_bytes = 0;
4819
4820 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA (np, select));
4821
4822 /*
4823 * Requeue the command.
4824 */
4825 sym_put_start_queue(np, cp);
4826
4827 /*
4828 * Give back to upper layer everything we have dequeued.
4829 */
4830 sym_flush_comp_queue(np, 0);
4831 break;
4832 }
4833 }
4834
4835 /*
4836 * After a device has accepted some management message
4837 * as BUS DEVICE RESET, ABORT TASK, etc ..., or when
4838 * a device signals a UNIT ATTENTION condition, some
4839 * tasks are thrown away by the device. We are required
4840 * to reflect that on our tasks list since the device
4841 * will never complete these tasks.
4842 *
4843 * This function move from the BUSY queue to the COMP
4844 * queue all disconnected CCBs for a given target that
4845 * match the following criteria:
4846 * - lun=-1 means any logical UNIT otherwise a given one.
4847 * - task=-1 means any task, otherwise a given one.
4848 */
4849 static int
sym_clear_tasks(hcb_p np,int cam_status,int target,int lun,int task)4850 sym_clear_tasks(hcb_p np, int cam_status, int target, int lun, int task)
4851 {
4852 SYM_QUEHEAD qtmp, *qp;
4853 int i = 0;
4854 ccb_p cp;
4855
4856 /*
4857 * Move the entire BUSY queue to our temporary queue.
4858 */
4859 sym_que_init(&qtmp);
4860 sym_que_splice(&np->busy_ccbq, &qtmp);
4861 sym_que_init(&np->busy_ccbq);
4862
4863 /*
4864 * Put all CCBs that matches our criteria into
4865 * the COMP queue and put back other ones into
4866 * the BUSY queue.
4867 */
4868 while ((qp = sym_remque_head(&qtmp)) != NULL) {
4869 union ccb *ccb;
4870 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
4871 ccb = cp->cam_ccb;
4872 if (cp->host_status != HS_DISCONNECT ||
4873 cp->target != target ||
4874 (lun != -1 && cp->lun != lun) ||
4875 (task != -1 &&
4876 (cp->tag != NO_TAG && cp->scsi_smsg[2] != task))) {
4877 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq);
4878 continue;
4879 }
4880 sym_insque_tail(&cp->link_ccbq, &np->comp_ccbq);
4881
4882 /* Preserve the software timeout condition */
4883 if (sym_get_cam_status(ccb) != CAM_CMD_TIMEOUT)
4884 sym_set_cam_status(ccb, cam_status);
4885 ++i;
4886 #if 0
4887 kprintf("XXXX TASK @%p CLEARED\n", cp);
4888 #endif
4889 }
4890 return i;
4891 }
4892
4893 /*
4894 * chip handler for TASKS recovery
4895 *
4896 * We cannot safely abort a command, while the SCRIPTS
4897 * processor is running, since we just would be in race
4898 * with it.
4899 *
4900 * As long as we have tasks to abort, we keep the SEM
4901 * bit set in the ISTAT. When this bit is set, the
4902 * SCRIPTS processor interrupts (SIR_SCRIPT_STOPPED)
4903 * each time it enters the scheduler.
4904 *
4905 * If we have to reset a target, clear tasks of a unit,
4906 * or to perform the abort of a disconnected job, we
4907 * restart the SCRIPTS for selecting the target. Once
4908 * selected, the SCRIPTS interrupts (SIR_TARGET_SELECTED).
4909 * If it loses arbitration, the SCRIPTS will interrupt again
4910 * the next time it will enter its scheduler, and so on ...
4911 *
4912 * On SIR_TARGET_SELECTED, we scan for the more
4913 * appropriate thing to do:
4914 *
4915 * - If nothing, we just sent a M_ABORT message to the
4916 * target to get rid of the useless SCSI bus ownership.
4917 * According to the specs, no tasks shall be affected.
4918 * - If the target is to be reset, we send it a M_RESET
4919 * message.
4920 * - If a logical UNIT is to be cleared , we send the
4921 * IDENTIFY(lun) + M_ABORT.
4922 * - If an untagged task is to be aborted, we send the
4923 * IDENTIFY(lun) + M_ABORT.
4924 * - If a tagged task is to be aborted, we send the
4925 * IDENTIFY(lun) + task attributes + M_ABORT_TAG.
4926 *
4927 * Once our 'kiss of death' :) message has been accepted
4928 * by the target, the SCRIPTS interrupts again
4929 * (SIR_ABORT_SENT). On this interrupt, we complete
4930 * all the CCBs that should have been aborted by the
4931 * target according to our message.
4932 */
sym_sir_task_recovery(hcb_p np,int num)4933 static void sym_sir_task_recovery(hcb_p np, int num)
4934 {
4935 SYM_QUEHEAD *qp;
4936 ccb_p cp;
4937 tcb_p tp;
4938 int target=-1, lun=-1, task;
4939 int i, k;
4940
4941 switch(num) {
4942 /*
4943 * The SCRIPTS processor stopped before starting
4944 * the next command in order to allow us to perform
4945 * some task recovery.
4946 */
4947 case SIR_SCRIPT_STOPPED:
4948 /*
4949 * Do we have any target to reset or unit to clear ?
4950 */
4951 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) {
4952 tp = &np->target[i];
4953 if (tp->to_reset ||
4954 (tp->lun0p && tp->lun0p->to_clear)) {
4955 target = i;
4956 break;
4957 }
4958 if (!tp->lunmp)
4959 continue;
4960 for (k = 1 ; k < SYM_CONF_MAX_LUN ; k++) {
4961 if (tp->lunmp[k] && tp->lunmp[k]->to_clear) {
4962 target = i;
4963 break;
4964 }
4965 }
4966 if (target != -1)
4967 break;
4968 }
4969
4970 /*
4971 * If not, walk the busy queue for any
4972 * disconnected CCB to be aborted.
4973 */
4974 if (target == -1) {
4975 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) {
4976 cp = sym_que_entry(qp,struct sym_ccb,link_ccbq);
4977 if (cp->host_status != HS_DISCONNECT)
4978 continue;
4979 if (cp->to_abort) {
4980 target = cp->target;
4981 break;
4982 }
4983 }
4984 }
4985
4986 /*
4987 * If some target is to be selected,
4988 * prepare and start the selection.
4989 */
4990 if (target != -1) {
4991 tp = &np->target[target];
4992 np->abrt_sel.sel_id = target;
4993 np->abrt_sel.sel_scntl3 = tp->head.wval;
4994 np->abrt_sel.sel_sxfer = tp->head.sval;
4995 OUTL(nc_dsa, np->hcb_ba);
4996 OUTL_DSP (SCRIPTB_BA (np, sel_for_abort));
4997 return;
4998 }
4999
5000 /*
5001 * Now look for a CCB to abort that haven't started yet.
5002 * Btw, the SCRIPTS processor is still stopped, so
5003 * we are not in race.
5004 */
5005 i = 0;
5006 cp = NULL;
5007 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) {
5008 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
5009 if (cp->host_status != HS_BUSY &&
5010 cp->host_status != HS_NEGOTIATE)
5011 continue;
5012 if (!cp->to_abort)
5013 continue;
5014 #ifdef SYM_CONF_IARB_SUPPORT
5015 /*
5016 * If we are using IMMEDIATE ARBITRATION, we donnot
5017 * want to cancel the last queued CCB, since the
5018 * SCRIPTS may have anticipated the selection.
5019 */
5020 if (cp == np->last_cp) {
5021 cp->to_abort = 0;
5022 continue;
5023 }
5024 #endif
5025 i = 1; /* Means we have found some */
5026 break;
5027 }
5028 if (!i) {
5029 /*
5030 * We are done, so we donnot need
5031 * to synchronize with the SCRIPTS anylonger.
5032 * Remove the SEM flag from the ISTAT.
5033 */
5034 np->istat_sem = 0;
5035 OUTB (nc_istat, SIGP);
5036 break;
5037 }
5038 /*
5039 * Compute index of next position in the start
5040 * queue the SCRIPTS intends to start and dequeue
5041 * all CCBs for that device that haven't been started.
5042 */
5043 i = (INL (nc_scratcha) - np->squeue_ba) / 4;
5044 i = sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1);
5045
5046 /*
5047 * Make sure at least our IO to abort has been dequeued.
5048 */
5049 assert(i && sym_get_cam_status(cp->cam_ccb) == CAM_REQUEUE_REQ);
5050
5051 /*
5052 * Keep track in cam status of the reason of the abort.
5053 */
5054 if (cp->to_abort == 2)
5055 sym_set_cam_status(cp->cam_ccb, CAM_CMD_TIMEOUT);
5056 else
5057 sym_set_cam_status(cp->cam_ccb, CAM_REQ_ABORTED);
5058
5059 /*
5060 * Complete with error everything that we have dequeued.
5061 */
5062 sym_flush_comp_queue(np, 0);
5063 break;
5064 /*
5065 * The SCRIPTS processor has selected a target
5066 * we may have some manual recovery to perform for.
5067 */
5068 case SIR_TARGET_SELECTED:
5069 target = (INB (nc_sdid) & 0xf);
5070 tp = &np->target[target];
5071
5072 np->abrt_tbl.addr = cpu_to_scr(vtobus(np->abrt_msg));
5073
5074 /*
5075 * If the target is to be reset, prepare a
5076 * M_RESET message and clear the to_reset flag
5077 * since we donnot expect this operation to fail.
5078 */
5079 if (tp->to_reset) {
5080 np->abrt_msg[0] = M_RESET;
5081 np->abrt_tbl.size = 1;
5082 tp->to_reset = 0;
5083 break;
5084 }
5085
5086 /*
5087 * Otherwise, look for some logical unit to be cleared.
5088 */
5089 if (tp->lun0p && tp->lun0p->to_clear)
5090 lun = 0;
5091 else if (tp->lunmp) {
5092 for (k = 1 ; k < SYM_CONF_MAX_LUN ; k++) {
5093 if (tp->lunmp[k] && tp->lunmp[k]->to_clear) {
5094 lun = k;
5095 break;
5096 }
5097 }
5098 }
5099
5100 /*
5101 * If a logical unit is to be cleared, prepare
5102 * an IDENTIFY(lun) + ABORT MESSAGE.
5103 */
5104 if (lun != -1) {
5105 lcb_p lp = sym_lp(np, tp, lun);
5106 lp->to_clear = 0; /* We donnot expect to fail here */
5107 np->abrt_msg[0] = M_IDENTIFY | lun;
5108 np->abrt_msg[1] = M_ABORT;
5109 np->abrt_tbl.size = 2;
5110 break;
5111 }
5112
5113 /*
5114 * Otherwise, look for some disconnected job to
5115 * abort for this target.
5116 */
5117 i = 0;
5118 cp = NULL;
5119 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) {
5120 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
5121 if (cp->host_status != HS_DISCONNECT)
5122 continue;
5123 if (cp->target != target)
5124 continue;
5125 if (!cp->to_abort)
5126 continue;
5127 i = 1; /* Means we have some */
5128 break;
5129 }
5130
5131 /*
5132 * If we have none, probably since the device has
5133 * completed the command before we won abitration,
5134 * send a M_ABORT message without IDENTIFY.
5135 * According to the specs, the device must just
5136 * disconnect the BUS and not abort any task.
5137 */
5138 if (!i) {
5139 np->abrt_msg[0] = M_ABORT;
5140 np->abrt_tbl.size = 1;
5141 break;
5142 }
5143
5144 /*
5145 * We have some task to abort.
5146 * Set the IDENTIFY(lun)
5147 */
5148 np->abrt_msg[0] = M_IDENTIFY | cp->lun;
5149
5150 /*
5151 * If we want to abort an untagged command, we
5152 * will send an IDENTIFY + M_ABORT.
5153 * Otherwise (tagged command), we will send
5154 * an IDENTIFY + task attributes + ABORT TAG.
5155 */
5156 if (cp->tag == NO_TAG) {
5157 np->abrt_msg[1] = M_ABORT;
5158 np->abrt_tbl.size = 2;
5159 }
5160 else {
5161 np->abrt_msg[1] = cp->scsi_smsg[1];
5162 np->abrt_msg[2] = cp->scsi_smsg[2];
5163 np->abrt_msg[3] = M_ABORT_TAG;
5164 np->abrt_tbl.size = 4;
5165 }
5166 /*
5167 * Keep track of software timeout condition, since the
5168 * peripheral driver may not count retries on abort
5169 * conditions not due to timeout.
5170 */
5171 if (cp->to_abort == 2)
5172 sym_set_cam_status(cp->cam_ccb, CAM_CMD_TIMEOUT);
5173 cp->to_abort = 0; /* We donnot expect to fail here */
5174 break;
5175
5176 /*
5177 * The target has accepted our message and switched
5178 * to BUS FREE phase as we expected.
5179 */
5180 case SIR_ABORT_SENT:
5181 target = (INB (nc_sdid) & 0xf);
5182 tp = &np->target[target];
5183
5184 /*
5185 ** If we didn't abort anything, leave here.
5186 */
5187 if (np->abrt_msg[0] == M_ABORT)
5188 break;
5189
5190 /*
5191 * If we sent a M_RESET, then a hardware reset has
5192 * been performed by the target.
5193 * - Reset everything to async 8 bit
5194 * - Tell ourself to negotiate next time :-)
5195 * - Prepare to clear all disconnected CCBs for
5196 * this target from our task list (lun=task=-1)
5197 */
5198 lun = -1;
5199 task = -1;
5200 if (np->abrt_msg[0] == M_RESET) {
5201 tp->head.sval = 0;
5202 tp->head.wval = np->rv_scntl3;
5203 tp->head.uval = 0;
5204 tp->tinfo.current.period = 0;
5205 tp->tinfo.current.offset = 0;
5206 tp->tinfo.current.width = BUS_8_BIT;
5207 tp->tinfo.current.options = 0;
5208 }
5209
5210 /*
5211 * Otherwise, check for the LUN and TASK(s)
5212 * concerned by the cancelation.
5213 * If it is not ABORT_TAG then it is CLEAR_QUEUE
5214 * or an ABORT message :-)
5215 */
5216 else {
5217 lun = np->abrt_msg[0] & 0x3f;
5218 if (np->abrt_msg[1] == M_ABORT_TAG)
5219 task = np->abrt_msg[2];
5220 }
5221
5222 /*
5223 * Complete all the CCBs the device should have
5224 * aborted due to our 'kiss of death' message.
5225 */
5226 i = (INL (nc_scratcha) - np->squeue_ba) / 4;
5227 (void) sym_dequeue_from_squeue(np, i, target, lun, -1);
5228 (void) sym_clear_tasks(np, CAM_REQ_ABORTED, target, lun, task);
5229 sym_flush_comp_queue(np, 0);
5230
5231 /*
5232 * If we sent a BDR, make uper layer aware of that.
5233 */
5234 if (np->abrt_msg[0] == M_RESET)
5235 xpt_async(AC_SENT_BDR, np->path, NULL);
5236 break;
5237 }
5238
5239 /*
5240 * Print to the log the message we intend to send.
5241 */
5242 if (num == SIR_TARGET_SELECTED) {
5243 PRINT_TARGET(np, target);
5244 sym_printl_hex("control msgout:", np->abrt_msg,
5245 np->abrt_tbl.size);
5246 np->abrt_tbl.size = cpu_to_scr(np->abrt_tbl.size);
5247 }
5248
5249 /*
5250 * Let the SCRIPTS processor continue.
5251 */
5252 OUTONB_STD ();
5253 }
5254
5255 /*
5256 * Gerard's alchemy:) that deals with with the data
5257 * pointer for both MDP and the residual calculation.
5258 *
5259 * I didn't want to bloat the code by more than 200
5260 * lignes for the handling of both MDP and the residual.
5261 * This has been achieved by using a data pointer
5262 * representation consisting in an index in the data
5263 * array (dp_sg) and a negative offset (dp_ofs) that
5264 * have the following meaning:
5265 *
5266 * - dp_sg = SYM_CONF_MAX_SG
5267 * we are at the end of the data script.
5268 * - dp_sg < SYM_CONF_MAX_SG
5269 * dp_sg points to the next entry of the scatter array
5270 * we want to transfer.
5271 * - dp_ofs < 0
5272 * dp_ofs represents the residual of bytes of the
5273 * previous entry scatter entry we will send first.
5274 * - dp_ofs = 0
5275 * no residual to send first.
5276 *
5277 * The function sym_evaluate_dp() accepts an arbitray
5278 * offset (basically from the MDP message) and returns
5279 * the corresponding values of dp_sg and dp_ofs.
5280 */
5281
sym_evaluate_dp(hcb_p np,ccb_p cp,u32 scr,int * ofs)5282 static int sym_evaluate_dp(hcb_p np, ccb_p cp, u32 scr, int *ofs)
5283 {
5284 u32 dp_scr;
5285 int dp_ofs, dp_sg, dp_sgmin;
5286 int tmp;
5287 struct sym_pmc *pm;
5288
5289 /*
5290 * Compute the resulted data pointer in term of a script
5291 * address within some DATA script and a signed byte offset.
5292 */
5293 dp_scr = scr;
5294 dp_ofs = *ofs;
5295 if (dp_scr == SCRIPTA_BA (np, pm0_data))
5296 pm = &cp->phys.pm0;
5297 else if (dp_scr == SCRIPTA_BA (np, pm1_data))
5298 pm = &cp->phys.pm1;
5299 else
5300 pm = NULL;
5301
5302 if (pm) {
5303 dp_scr = scr_to_cpu(pm->ret);
5304 dp_ofs -= scr_to_cpu(pm->sg.size);
5305 }
5306
5307 /*
5308 * If we are auto-sensing, then we are done.
5309 */
5310 if (cp->host_flags & HF_SENSE) {
5311 *ofs = dp_ofs;
5312 return 0;
5313 }
5314
5315 /*
5316 * Deduce the index of the sg entry.
5317 * Keep track of the index of the first valid entry.
5318 * If result is dp_sg = SYM_CONF_MAX_SG, then we are at the
5319 * end of the data.
5320 */
5321 tmp = scr_to_cpu(cp->phys.head.goalp);
5322 dp_sg = SYM_CONF_MAX_SG;
5323 if (dp_scr != tmp)
5324 dp_sg -= (tmp - 8 - (int)dp_scr) / (2*4);
5325 dp_sgmin = SYM_CONF_MAX_SG - cp->segments;
5326
5327 /*
5328 * Move to the sg entry the data pointer belongs to.
5329 *
5330 * If we are inside the data area, we expect result to be:
5331 *
5332 * Either,
5333 * dp_ofs = 0 and dp_sg is the index of the sg entry
5334 * the data pointer belongs to (or the end of the data)
5335 * Or,
5336 * dp_ofs < 0 and dp_sg is the index of the sg entry
5337 * the data pointer belongs to + 1.
5338 */
5339 if (dp_ofs < 0) {
5340 int n;
5341 while (dp_sg > dp_sgmin) {
5342 --dp_sg;
5343 tmp = scr_to_cpu(cp->phys.data[dp_sg].size);
5344 n = dp_ofs + (tmp & 0xffffff);
5345 if (n > 0) {
5346 ++dp_sg;
5347 break;
5348 }
5349 dp_ofs = n;
5350 }
5351 }
5352 else if (dp_ofs > 0) {
5353 while (dp_sg < SYM_CONF_MAX_SG) {
5354 tmp = scr_to_cpu(cp->phys.data[dp_sg].size);
5355 dp_ofs -= (tmp & 0xffffff);
5356 ++dp_sg;
5357 if (dp_ofs <= 0)
5358 break;
5359 }
5360 }
5361
5362 /*
5363 * Make sure the data pointer is inside the data area.
5364 * If not, return some error.
5365 */
5366 if (dp_sg < dp_sgmin || (dp_sg == dp_sgmin && dp_ofs < 0))
5367 goto out_err;
5368 else if (dp_sg > SYM_CONF_MAX_SG ||
5369 (dp_sg == SYM_CONF_MAX_SG && dp_ofs > 0))
5370 goto out_err;
5371
5372 /*
5373 * Save the extreme pointer if needed.
5374 */
5375 if (dp_sg > cp->ext_sg ||
5376 (dp_sg == cp->ext_sg && dp_ofs > cp->ext_ofs)) {
5377 cp->ext_sg = dp_sg;
5378 cp->ext_ofs = dp_ofs;
5379 }
5380
5381 /*
5382 * Return data.
5383 */
5384 *ofs = dp_ofs;
5385 return dp_sg;
5386
5387 out_err:
5388 return -1;
5389 }
5390
5391 /*
5392 * chip handler for MODIFY DATA POINTER MESSAGE
5393 *
5394 * We also call this function on IGNORE WIDE RESIDUE
5395 * messages that do not match a SWIDE full condition.
5396 * Btw, we assume in that situation that such a message
5397 * is equivalent to a MODIFY DATA POINTER (offset=-1).
5398 */
5399
sym_modify_dp(hcb_p np,tcb_p tp,ccb_p cp,int ofs)5400 static void sym_modify_dp(hcb_p np, tcb_p tp, ccb_p cp, int ofs)
5401 {
5402 int dp_ofs = ofs;
5403 u32 dp_scr = INL (nc_temp);
5404 u32 dp_ret;
5405 u32 tmp;
5406 u_char hflags;
5407 int dp_sg;
5408 struct sym_pmc *pm;
5409
5410 /*
5411 * Not supported for auto-sense.
5412 */
5413 if (cp->host_flags & HF_SENSE)
5414 goto out_reject;
5415
5416 /*
5417 * Apply our alchemy:) (see comments in sym_evaluate_dp()),
5418 * to the resulted data pointer.
5419 */
5420 dp_sg = sym_evaluate_dp(np, cp, dp_scr, &dp_ofs);
5421 if (dp_sg < 0)
5422 goto out_reject;
5423
5424 /*
5425 * And our alchemy:) allows to easily calculate the data
5426 * script address we want to return for the next data phase.
5427 */
5428 dp_ret = cpu_to_scr(cp->phys.head.goalp);
5429 dp_ret = dp_ret - 8 - (SYM_CONF_MAX_SG - dp_sg) * (2*4);
5430
5431 /*
5432 * If offset / scatter entry is zero we donnot need
5433 * a context for the new current data pointer.
5434 */
5435 if (dp_ofs == 0) {
5436 dp_scr = dp_ret;
5437 goto out_ok;
5438 }
5439
5440 /*
5441 * Get a context for the new current data pointer.
5442 */
5443 hflags = INB (HF_PRT);
5444
5445 if (hflags & HF_DP_SAVED)
5446 hflags ^= HF_ACT_PM;
5447
5448 if (!(hflags & HF_ACT_PM)) {
5449 pm = &cp->phys.pm0;
5450 dp_scr = SCRIPTA_BA (np, pm0_data);
5451 }
5452 else {
5453 pm = &cp->phys.pm1;
5454 dp_scr = SCRIPTA_BA (np, pm1_data);
5455 }
5456
5457 hflags &= ~(HF_DP_SAVED);
5458
5459 OUTB (HF_PRT, hflags);
5460
5461 /*
5462 * Set up the new current data pointer.
5463 * ofs < 0 there, and for the next data phase, we
5464 * want to transfer part of the data of the sg entry
5465 * corresponding to index dp_sg-1 prior to returning
5466 * to the main data script.
5467 */
5468 pm->ret = cpu_to_scr(dp_ret);
5469 tmp = scr_to_cpu(cp->phys.data[dp_sg-1].addr);
5470 tmp += scr_to_cpu(cp->phys.data[dp_sg-1].size) + dp_ofs;
5471 pm->sg.addr = cpu_to_scr(tmp);
5472 pm->sg.size = cpu_to_scr(-dp_ofs);
5473
5474 out_ok:
5475 OUTL (nc_temp, dp_scr);
5476 OUTL_DSP (SCRIPTA_BA (np, clrack));
5477 return;
5478
5479 out_reject:
5480 OUTL_DSP (SCRIPTB_BA (np, msg_bad));
5481 }
5482
5483
5484 /*
5485 * chip calculation of the data residual.
5486 *
5487 * As I used to say, the requirement of data residual
5488 * in SCSI is broken, useless and cannot be achieved
5489 * without huge complexity.
5490 * But most OSes and even the official CAM require it.
5491 * When stupidity happens to be so widely spread inside
5492 * a community, it gets hard to convince.
5493 *
5494 * Anyway, I don't care, since I am not going to use
5495 * any software that considers this data residual as
5496 * a relevant information. :)
5497 */
5498
sym_compute_residual(hcb_p np,ccb_p cp)5499 static int sym_compute_residual(hcb_p np, ccb_p cp)
5500 {
5501 int dp_sg, resid = 0;
5502 int dp_ofs = 0;
5503
5504 /*
5505 * Check for some data lost or just thrown away.
5506 * We are not required to be quite accurate in this
5507 * situation. Btw, if we are odd for output and the
5508 * device claims some more data, it may well happen
5509 * than our residual be zero. :-)
5510 */
5511 if (cp->xerr_status & (XE_EXTRA_DATA|XE_SODL_UNRUN|XE_SWIDE_OVRUN)) {
5512 if (cp->xerr_status & XE_EXTRA_DATA)
5513 resid -= cp->extra_bytes;
5514 if (cp->xerr_status & XE_SODL_UNRUN)
5515 ++resid;
5516 if (cp->xerr_status & XE_SWIDE_OVRUN)
5517 --resid;
5518 }
5519
5520 /*
5521 * If all data has been transferred,
5522 * there is no residual.
5523 */
5524 if (cp->phys.head.lastp == cp->phys.head.goalp)
5525 return resid;
5526
5527 /*
5528 * If no data transfer occurs, or if the data
5529 * pointer is weird, return full residual.
5530 */
5531 if (cp->startp == cp->phys.head.lastp ||
5532 sym_evaluate_dp(np, cp, scr_to_cpu(cp->phys.head.lastp),
5533 &dp_ofs) < 0) {
5534 return cp->data_len;
5535 }
5536
5537 /*
5538 * If we were auto-sensing, then we are done.
5539 */
5540 if (cp->host_flags & HF_SENSE) {
5541 return -dp_ofs;
5542 }
5543
5544 /*
5545 * We are now full comfortable in the computation
5546 * of the data residual (2's complement).
5547 */
5548 resid = -cp->ext_ofs;
5549 for (dp_sg = cp->ext_sg; dp_sg < SYM_CONF_MAX_SG; ++dp_sg) {
5550 u_int tmp = scr_to_cpu(cp->phys.data[dp_sg].size);
5551 resid += (tmp & 0xffffff);
5552 }
5553
5554 /*
5555 * Hopefully, the result is not too wrong.
5556 */
5557 return resid;
5558 }
5559
5560 /*
5561 * Print out the content of a SCSI message.
5562 */
5563
sym_show_msg(u_char * msg)5564 static int sym_show_msg (u_char * msg)
5565 {
5566 u_char i;
5567 kprintf ("%x",*msg);
5568 if (*msg==M_EXTENDED) {
5569 for (i=1;i<8;i++) {
5570 if (i-1>msg[1]) break;
5571 kprintf ("-%x",msg[i]);
5572 }
5573 return (i+1);
5574 } else if ((*msg & 0xf0) == 0x20) {
5575 kprintf ("-%x",msg[1]);
5576 return (2);
5577 }
5578 return (1);
5579 }
5580
sym_print_msg(ccb_p cp,char * label,u_char * msg)5581 static void sym_print_msg (ccb_p cp, char *label, u_char *msg)
5582 {
5583 PRINT_ADDR(cp);
5584 if (label)
5585 kprintf ("%s: ", label);
5586
5587 (void) sym_show_msg (msg);
5588 kprintf (".\n");
5589 }
5590
5591 /*
5592 * Negotiation for WIDE and SYNCHRONOUS DATA TRANSFER.
5593 *
5594 * When we try to negotiate, we append the negotiation message
5595 * to the identify and (maybe) simple tag message.
5596 * The host status field is set to HS_NEGOTIATE to mark this
5597 * situation.
5598 *
5599 * If the target doesn't answer this message immediately
5600 * (as required by the standard), the SIR_NEGO_FAILED interrupt
5601 * will be raised eventually.
5602 * The handler removes the HS_NEGOTIATE status, and sets the
5603 * negotiated value to the default (async / nowide).
5604 *
5605 * If we receive a matching answer immediately, we check it
5606 * for validity, and set the values.
5607 *
5608 * If we receive a Reject message immediately, we assume the
5609 * negotiation has failed, and fall back to standard values.
5610 *
5611 * If we receive a negotiation message while not in HS_NEGOTIATE
5612 * state, it's a target initiated negotiation. We prepare a
5613 * (hopefully) valid answer, set our parameters, and send back
5614 * this answer to the target.
5615 *
5616 * If the target doesn't fetch the answer (no message out phase),
5617 * we assume the negotiation has failed, and fall back to default
5618 * settings (SIR_NEGO_PROTO interrupt).
5619 *
5620 * When we set the values, we adjust them in all ccbs belonging
5621 * to this target, in the controller's register, and in the "phys"
5622 * field of the controller's struct sym_hcb.
5623 */
5624
5625 /*
5626 * chip handler for SYNCHRONOUS DATA TRANSFER REQUEST (SDTR) message.
5627 */
sym_sync_nego(hcb_p np,tcb_p tp,ccb_p cp)5628 static void sym_sync_nego(hcb_p np, tcb_p tp, ccb_p cp)
5629 {
5630 u_char chg, ofs, per, fak, div;
5631 int req = 1;
5632
5633 /*
5634 * Synchronous request message received.
5635 */
5636 if (DEBUG_FLAGS & DEBUG_NEGO) {
5637 sym_print_msg(cp, "sync msgin", np->msgin);
5638 }
5639
5640 /*
5641 * request or answer ?
5642 */
5643 if (INB (HS_PRT) == HS_NEGOTIATE) {
5644 OUTB (HS_PRT, HS_BUSY);
5645 if (cp->nego_status && cp->nego_status != NS_SYNC)
5646 goto reject_it;
5647 req = 0;
5648 }
5649
5650 /*
5651 * get requested values.
5652 */
5653 chg = 0;
5654 per = np->msgin[3];
5655 ofs = np->msgin[4];
5656
5657 /*
5658 * check values against our limits.
5659 */
5660 if (ofs) {
5661 if (ofs > np->maxoffs)
5662 {chg = 1; ofs = np->maxoffs;}
5663 if (req) {
5664 if (ofs > tp->tinfo.user.offset)
5665 {chg = 1; ofs = tp->tinfo.user.offset;}
5666 }
5667 }
5668
5669 if (ofs) {
5670 if (per < np->minsync)
5671 {chg = 1; per = np->minsync;}
5672 if (req) {
5673 if (per < tp->tinfo.user.period)
5674 {chg = 1; per = tp->tinfo.user.period;}
5675 }
5676 }
5677
5678 div = fak = 0;
5679 if (ofs && sym_getsync(np, 0, per, &div, &fak) < 0)
5680 goto reject_it;
5681
5682 if (DEBUG_FLAGS & DEBUG_NEGO) {
5683 PRINT_ADDR(cp);
5684 kprintf ("sdtr: ofs=%d per=%d div=%d fak=%d chg=%d.\n",
5685 ofs, per, div, fak, chg);
5686 }
5687
5688 /*
5689 * This was an answer message
5690 */
5691 if (req == 0) {
5692 if (chg) /* Answer wasn't acceptable. */
5693 goto reject_it;
5694 sym_setsync (np, cp, ofs, per, div, fak);
5695 OUTL_DSP (SCRIPTA_BA (np, clrack));
5696 return;
5697 }
5698
5699 /*
5700 * It was a request. Set value and
5701 * prepare an answer message
5702 */
5703 sym_setsync (np, cp, ofs, per, div, fak);
5704
5705 np->msgout[0] = M_EXTENDED;
5706 np->msgout[1] = 3;
5707 np->msgout[2] = M_X_SYNC_REQ;
5708 np->msgout[3] = per;
5709 np->msgout[4] = ofs;
5710
5711 cp->nego_status = NS_SYNC;
5712
5713 if (DEBUG_FLAGS & DEBUG_NEGO) {
5714 sym_print_msg(cp, "sync msgout", np->msgout);
5715 }
5716
5717 np->msgin [0] = M_NOOP;
5718
5719 OUTL_DSP (SCRIPTB_BA (np, sdtr_resp));
5720 return;
5721 reject_it:
5722 sym_setsync (np, cp, 0, 0, 0, 0);
5723 OUTL_DSP (SCRIPTB_BA (np, msg_bad));
5724 }
5725
5726 /*
5727 * chip handler for PARALLEL PROTOCOL REQUEST (PPR) message.
5728 */
sym_ppr_nego(hcb_p np,tcb_p tp,ccb_p cp)5729 static void sym_ppr_nego(hcb_p np, tcb_p tp, ccb_p cp)
5730 {
5731 u_char chg, ofs, per, fak, dt, div, wide;
5732 int req = 1;
5733
5734 /*
5735 * Synchronous request message received.
5736 */
5737 if (DEBUG_FLAGS & DEBUG_NEGO) {
5738 sym_print_msg(cp, "ppr msgin", np->msgin);
5739 }
5740
5741 /*
5742 * get requested values.
5743 */
5744 chg = 0;
5745 per = np->msgin[3];
5746 ofs = np->msgin[5];
5747 wide = np->msgin[6];
5748 dt = np->msgin[7] & PPR_OPT_DT;
5749
5750 /*
5751 * request or answer ?
5752 */
5753 if (INB (HS_PRT) == HS_NEGOTIATE) {
5754 OUTB (HS_PRT, HS_BUSY);
5755 if (cp->nego_status && cp->nego_status != NS_PPR)
5756 goto reject_it;
5757 req = 0;
5758 }
5759
5760 /*
5761 * check values against our limits.
5762 */
5763 if (wide > np->maxwide)
5764 {chg = 1; wide = np->maxwide;}
5765 if (!wide || !(np->features & FE_ULTRA3))
5766 dt &= ~PPR_OPT_DT;
5767 if (req) {
5768 if (wide > tp->tinfo.user.width)
5769 {chg = 1; wide = tp->tinfo.user.width;}
5770 }
5771
5772 if (!(np->features & FE_U3EN)) /* Broken U3EN bit not supported */
5773 dt &= ~PPR_OPT_DT;
5774
5775 if (dt != (np->msgin[7] & PPR_OPT_MASK)) chg = 1;
5776
5777 if (ofs) {
5778 if (dt) {
5779 if (ofs > np->maxoffs_dt)
5780 {chg = 1; ofs = np->maxoffs_dt;}
5781 }
5782 else if (ofs > np->maxoffs)
5783 {chg = 1; ofs = np->maxoffs;}
5784 if (req) {
5785 if (ofs > tp->tinfo.user.offset)
5786 {chg = 1; ofs = tp->tinfo.user.offset;}
5787 }
5788 }
5789
5790 if (ofs) {
5791 if (dt) {
5792 if (per < np->minsync_dt)
5793 {chg = 1; per = np->minsync_dt;}
5794 }
5795 else if (per < np->minsync)
5796 {chg = 1; per = np->minsync;}
5797 if (req) {
5798 if (per < tp->tinfo.user.period)
5799 {chg = 1; per = tp->tinfo.user.period;}
5800 }
5801 }
5802
5803 div = fak = 0;
5804 if (ofs && sym_getsync(np, dt, per, &div, &fak) < 0)
5805 goto reject_it;
5806
5807 if (DEBUG_FLAGS & DEBUG_NEGO) {
5808 PRINT_ADDR(cp);
5809 kprintf ("ppr: "
5810 "dt=%x ofs=%d per=%d wide=%d div=%d fak=%d chg=%d.\n",
5811 dt, ofs, per, wide, div, fak, chg);
5812 }
5813
5814 /*
5815 * It was an answer.
5816 */
5817 if (req == 0) {
5818 if (chg) /* Answer wasn't acceptable */
5819 goto reject_it;
5820 sym_setpprot (np, cp, dt, ofs, per, wide, div, fak);
5821 OUTL_DSP (SCRIPTA_BA (np, clrack));
5822 return;
5823 }
5824
5825 /*
5826 * It was a request. Set value and
5827 * prepare an answer message
5828 */
5829 sym_setpprot (np, cp, dt, ofs, per, wide, div, fak);
5830
5831 np->msgout[0] = M_EXTENDED;
5832 np->msgout[1] = 6;
5833 np->msgout[2] = M_X_PPR_REQ;
5834 np->msgout[3] = per;
5835 np->msgout[4] = 0;
5836 np->msgout[5] = ofs;
5837 np->msgout[6] = wide;
5838 np->msgout[7] = dt;
5839
5840 cp->nego_status = NS_PPR;
5841
5842 if (DEBUG_FLAGS & DEBUG_NEGO) {
5843 sym_print_msg(cp, "ppr msgout", np->msgout);
5844 }
5845
5846 np->msgin [0] = M_NOOP;
5847
5848 OUTL_DSP (SCRIPTB_BA (np, ppr_resp));
5849 return;
5850 reject_it:
5851 sym_setpprot (np, cp, 0, 0, 0, 0, 0, 0);
5852 OUTL_DSP (SCRIPTB_BA (np, msg_bad));
5853 /*
5854 * If it was a device response that should result in
5855 * ST, we may want to try a legacy negotiation later.
5856 */
5857 if (!req && !dt) {
5858 tp->tinfo.goal.options = 0;
5859 tp->tinfo.goal.width = wide;
5860 tp->tinfo.goal.period = per;
5861 tp->tinfo.goal.offset = ofs;
5862 }
5863 }
5864
5865 /*
5866 * chip handler for WIDE DATA TRANSFER REQUEST (WDTR) message.
5867 */
sym_wide_nego(hcb_p np,tcb_p tp,ccb_p cp)5868 static void sym_wide_nego(hcb_p np, tcb_p tp, ccb_p cp)
5869 {
5870 u_char chg, wide;
5871 int req = 1;
5872
5873 /*
5874 * Wide request message received.
5875 */
5876 if (DEBUG_FLAGS & DEBUG_NEGO) {
5877 sym_print_msg(cp, "wide msgin", np->msgin);
5878 }
5879
5880 /*
5881 * Is it a request from the device?
5882 */
5883 if (INB (HS_PRT) == HS_NEGOTIATE) {
5884 OUTB (HS_PRT, HS_BUSY);
5885 if (cp->nego_status && cp->nego_status != NS_WIDE)
5886 goto reject_it;
5887 req = 0;
5888 }
5889
5890 /*
5891 * get requested values.
5892 */
5893 chg = 0;
5894 wide = np->msgin[3];
5895
5896 /*
5897 * check values against driver limits.
5898 */
5899 if (wide > np->maxwide)
5900 {chg = 1; wide = np->maxwide;}
5901 if (req) {
5902 if (wide > tp->tinfo.user.width)
5903 {chg = 1; wide = tp->tinfo.user.width;}
5904 }
5905
5906 if (DEBUG_FLAGS & DEBUG_NEGO) {
5907 PRINT_ADDR(cp);
5908 kprintf ("wdtr: wide=%d chg=%d.\n", wide, chg);
5909 }
5910
5911 /*
5912 * This was an answer message
5913 */
5914 if (req == 0) {
5915 if (chg) /* Answer wasn't acceptable. */
5916 goto reject_it;
5917 sym_setwide (np, cp, wide);
5918
5919 /*
5920 * Negotiate for SYNC immediately after WIDE response.
5921 * This allows to negotiate for both WIDE and SYNC on
5922 * a single SCSI command (Suggested by Justin Gibbs).
5923 */
5924 if (tp->tinfo.goal.offset) {
5925 np->msgout[0] = M_EXTENDED;
5926 np->msgout[1] = 3;
5927 np->msgout[2] = M_X_SYNC_REQ;
5928 np->msgout[3] = tp->tinfo.goal.period;
5929 np->msgout[4] = tp->tinfo.goal.offset;
5930
5931 if (DEBUG_FLAGS & DEBUG_NEGO) {
5932 sym_print_msg(cp, "sync msgout", np->msgout);
5933 }
5934
5935 cp->nego_status = NS_SYNC;
5936 OUTB (HS_PRT, HS_NEGOTIATE);
5937 OUTL_DSP (SCRIPTB_BA (np, sdtr_resp));
5938 return;
5939 }
5940
5941 OUTL_DSP (SCRIPTA_BA (np, clrack));
5942 return;
5943 }
5944
5945 /*
5946 * It was a request, set value and
5947 * prepare an answer message
5948 */
5949 sym_setwide (np, cp, wide);
5950
5951 np->msgout[0] = M_EXTENDED;
5952 np->msgout[1] = 2;
5953 np->msgout[2] = M_X_WIDE_REQ;
5954 np->msgout[3] = wide;
5955
5956 np->msgin [0] = M_NOOP;
5957
5958 cp->nego_status = NS_WIDE;
5959
5960 if (DEBUG_FLAGS & DEBUG_NEGO) {
5961 sym_print_msg(cp, "wide msgout", np->msgout);
5962 }
5963
5964 OUTL_DSP (SCRIPTB_BA (np, wdtr_resp));
5965 return;
5966 reject_it:
5967 OUTL_DSP (SCRIPTB_BA (np, msg_bad));
5968 }
5969
5970 /*
5971 * Reset SYNC or WIDE to default settings.
5972 *
5973 * Called when a negotiation does not succeed either
5974 * on rejection or on protocol error.
5975 *
5976 * If it was a PPR that made problems, we may want to
5977 * try a legacy negotiation later.
5978 */
sym_nego_default(hcb_p np,tcb_p tp,ccb_p cp)5979 static void sym_nego_default(hcb_p np, tcb_p tp, ccb_p cp)
5980 {
5981 /*
5982 * any error in negotiation:
5983 * fall back to default mode.
5984 */
5985 switch (cp->nego_status) {
5986 case NS_PPR:
5987 #if 0
5988 sym_setpprot (np, cp, 0, 0, 0, 0, 0, 0);
5989 #else
5990 tp->tinfo.goal.options = 0;
5991 if (tp->tinfo.goal.period < np->minsync)
5992 tp->tinfo.goal.period = np->minsync;
5993 if (tp->tinfo.goal.offset > np->maxoffs)
5994 tp->tinfo.goal.offset = np->maxoffs;
5995 #endif
5996 break;
5997 case NS_SYNC:
5998 sym_setsync (np, cp, 0, 0, 0, 0);
5999 break;
6000 case NS_WIDE:
6001 sym_setwide (np, cp, 0);
6002 break;
6003 }
6004 np->msgin [0] = M_NOOP;
6005 np->msgout[0] = M_NOOP;
6006 cp->nego_status = 0;
6007 }
6008
6009 /*
6010 * chip handler for MESSAGE REJECT received in response to
6011 * a WIDE or SYNCHRONOUS negotiation.
6012 */
sym_nego_rejected(hcb_p np,tcb_p tp,ccb_p cp)6013 static void sym_nego_rejected(hcb_p np, tcb_p tp, ccb_p cp)
6014 {
6015 sym_nego_default(np, tp, cp);
6016 OUTB (HS_PRT, HS_BUSY);
6017 }
6018
6019 /*
6020 * chip exception handler for programmed interrupts.
6021 */
sym_int_sir(hcb_p np)6022 static void sym_int_sir (hcb_p np)
6023 {
6024 u_char num = INB (nc_dsps);
6025 u32 dsa = INL (nc_dsa);
6026 ccb_p cp = sym_ccb_from_dsa(np, dsa);
6027 u_char target = INB (nc_sdid) & 0x0f;
6028 tcb_p tp = &np->target[target];
6029 int tmp;
6030
6031 SYM_LOCK_ASSERT(LK_EXCLUSIVE);
6032
6033 if (DEBUG_FLAGS & DEBUG_TINY) kprintf ("I#%d", num);
6034
6035 switch (num) {
6036 /*
6037 * Command has been completed with error condition
6038 * or has been auto-sensed.
6039 */
6040 case SIR_COMPLETE_ERROR:
6041 sym_complete_error(np, cp);
6042 return;
6043 /*
6044 * The C code is currently trying to recover from something.
6045 * Typically, user want to abort some command.
6046 */
6047 case SIR_SCRIPT_STOPPED:
6048 case SIR_TARGET_SELECTED:
6049 case SIR_ABORT_SENT:
6050 sym_sir_task_recovery(np, num);
6051 return;
6052 /*
6053 * The device didn't go to MSG OUT phase after having
6054 * been selected with ATN. We donnot want to handle
6055 * that.
6056 */
6057 case SIR_SEL_ATN_NO_MSG_OUT:
6058 kprintf ("%s:%d: No MSG OUT phase after selection with ATN.\n",
6059 sym_name (np), target);
6060 goto out_stuck;
6061 /*
6062 * The device didn't switch to MSG IN phase after
6063 * having reseleted the initiator.
6064 */
6065 case SIR_RESEL_NO_MSG_IN:
6066 kprintf ("%s:%d: No MSG IN phase after reselection.\n",
6067 sym_name (np), target);
6068 goto out_stuck;
6069 /*
6070 * After reselection, the device sent a message that wasn't
6071 * an IDENTIFY.
6072 */
6073 case SIR_RESEL_NO_IDENTIFY:
6074 kprintf ("%s:%d: No IDENTIFY after reselection.\n",
6075 sym_name (np), target);
6076 goto out_stuck;
6077 /*
6078 * The device reselected a LUN we donnot know about.
6079 */
6080 case SIR_RESEL_BAD_LUN:
6081 np->msgout[0] = M_RESET;
6082 goto out;
6083 /*
6084 * The device reselected for an untagged nexus and we
6085 * haven't any.
6086 */
6087 case SIR_RESEL_BAD_I_T_L:
6088 np->msgout[0] = M_ABORT;
6089 goto out;
6090 /*
6091 * The device reselected for a tagged nexus that we donnot
6092 * have.
6093 */
6094 case SIR_RESEL_BAD_I_T_L_Q:
6095 np->msgout[0] = M_ABORT_TAG;
6096 goto out;
6097 /*
6098 * The SCRIPTS let us know that the device has grabbed
6099 * our message and will abort the job.
6100 */
6101 case SIR_RESEL_ABORTED:
6102 np->lastmsg = np->msgout[0];
6103 np->msgout[0] = M_NOOP;
6104 kprintf ("%s:%d: message %x sent on bad reselection.\n",
6105 sym_name (np), target, np->lastmsg);
6106 goto out;
6107 /*
6108 * The SCRIPTS let us know that a message has been
6109 * successfully sent to the device.
6110 */
6111 case SIR_MSG_OUT_DONE:
6112 np->lastmsg = np->msgout[0];
6113 np->msgout[0] = M_NOOP;
6114 /* Should we really care of that */
6115 if (np->lastmsg == M_PARITY || np->lastmsg == M_ID_ERROR) {
6116 if (cp) {
6117 cp->xerr_status &= ~XE_PARITY_ERR;
6118 if (!cp->xerr_status)
6119 OUTOFFB (HF_PRT, HF_EXT_ERR);
6120 }
6121 }
6122 goto out;
6123 /*
6124 * The device didn't send a GOOD SCSI status.
6125 * We may have some work to do prior to allow
6126 * the SCRIPTS processor to continue.
6127 */
6128 case SIR_BAD_SCSI_STATUS:
6129 if (!cp)
6130 goto out;
6131 sym_sir_bad_scsi_status(np, num, cp);
6132 return;
6133 /*
6134 * We are asked by the SCRIPTS to prepare a
6135 * REJECT message.
6136 */
6137 case SIR_REJECT_TO_SEND:
6138 sym_print_msg(cp, "M_REJECT to send for ", np->msgin);
6139 np->msgout[0] = M_REJECT;
6140 goto out;
6141 /*
6142 * We have been ODD at the end of a DATA IN
6143 * transfer and the device didn't send a
6144 * IGNORE WIDE RESIDUE message.
6145 * It is a data overrun condition.
6146 */
6147 case SIR_SWIDE_OVERRUN:
6148 if (cp) {
6149 OUTONB (HF_PRT, HF_EXT_ERR);
6150 cp->xerr_status |= XE_SWIDE_OVRUN;
6151 }
6152 goto out;
6153 /*
6154 * We have been ODD at the end of a DATA OUT
6155 * transfer.
6156 * It is a data underrun condition.
6157 */
6158 case SIR_SODL_UNDERRUN:
6159 if (cp) {
6160 OUTONB (HF_PRT, HF_EXT_ERR);
6161 cp->xerr_status |= XE_SODL_UNRUN;
6162 }
6163 goto out;
6164 /*
6165 * The device wants us to tranfer more data than
6166 * expected or in the wrong direction.
6167 * The number of extra bytes is in scratcha.
6168 * It is a data overrun condition.
6169 */
6170 case SIR_DATA_OVERRUN:
6171 if (cp) {
6172 OUTONB (HF_PRT, HF_EXT_ERR);
6173 cp->xerr_status |= XE_EXTRA_DATA;
6174 cp->extra_bytes += INL (nc_scratcha);
6175 }
6176 goto out;
6177 /*
6178 * The device switched to an illegal phase (4/5).
6179 */
6180 case SIR_BAD_PHASE:
6181 if (cp) {
6182 OUTONB (HF_PRT, HF_EXT_ERR);
6183 cp->xerr_status |= XE_BAD_PHASE;
6184 }
6185 goto out;
6186 /*
6187 * We received a message.
6188 */
6189 case SIR_MSG_RECEIVED:
6190 if (!cp)
6191 goto out_stuck;
6192 switch (np->msgin [0]) {
6193 /*
6194 * We received an extended message.
6195 * We handle MODIFY DATA POINTER, SDTR, WDTR
6196 * and reject all other extended messages.
6197 */
6198 case M_EXTENDED:
6199 switch (np->msgin [2]) {
6200 case M_X_MODIFY_DP:
6201 if (DEBUG_FLAGS & DEBUG_POINTER)
6202 sym_print_msg(cp,"modify DP",np->msgin);
6203 tmp = (np->msgin[3]<<24) + (np->msgin[4]<<16) +
6204 (np->msgin[5]<<8) + (np->msgin[6]);
6205 sym_modify_dp(np, tp, cp, tmp);
6206 return;
6207 case M_X_SYNC_REQ:
6208 sym_sync_nego(np, tp, cp);
6209 return;
6210 case M_X_PPR_REQ:
6211 sym_ppr_nego(np, tp, cp);
6212 return;
6213 case M_X_WIDE_REQ:
6214 sym_wide_nego(np, tp, cp);
6215 return;
6216 default:
6217 goto out_reject;
6218 }
6219 break;
6220 /*
6221 * We received a 1/2 byte message not handled from SCRIPTS.
6222 * We are only expecting MESSAGE REJECT and IGNORE WIDE
6223 * RESIDUE messages that haven't been anticipated by
6224 * SCRIPTS on SWIDE full condition. Unanticipated IGNORE
6225 * WIDE RESIDUE messages are aliased as MODIFY DP (-1).
6226 */
6227 case M_IGN_RESIDUE:
6228 if (DEBUG_FLAGS & DEBUG_POINTER)
6229 sym_print_msg(cp,"ign wide residue", np->msgin);
6230 sym_modify_dp(np, tp, cp, -1);
6231 return;
6232 case M_REJECT:
6233 if (INB (HS_PRT) == HS_NEGOTIATE)
6234 sym_nego_rejected(np, tp, cp);
6235 else {
6236 PRINT_ADDR(cp);
6237 kprintf ("M_REJECT received (%x:%x).\n",
6238 scr_to_cpu(np->lastmsg), np->msgout[0]);
6239 }
6240 goto out_clrack;
6241 break;
6242 default:
6243 goto out_reject;
6244 }
6245 break;
6246 /*
6247 * We received an unknown message.
6248 * Ignore all MSG IN phases and reject it.
6249 */
6250 case SIR_MSG_WEIRD:
6251 sym_print_msg(cp, "WEIRD message received", np->msgin);
6252 OUTL_DSP (SCRIPTB_BA (np, msg_weird));
6253 return;
6254 /*
6255 * Negotiation failed.
6256 * Target does not send us the reply.
6257 * Remove the HS_NEGOTIATE status.
6258 */
6259 case SIR_NEGO_FAILED:
6260 OUTB (HS_PRT, HS_BUSY);
6261 /*
6262 * Negotiation failed.
6263 * Target does not want answer message.
6264 */
6265 case SIR_NEGO_PROTO:
6266 sym_nego_default(np, tp, cp);
6267 goto out;
6268 }
6269
6270 out:
6271 OUTONB_STD ();
6272 return;
6273 out_reject:
6274 OUTL_DSP (SCRIPTB_BA (np, msg_bad));
6275 return;
6276 out_clrack:
6277 OUTL_DSP (SCRIPTA_BA (np, clrack));
6278 return;
6279 out_stuck:
6280 return;
6281 }
6282
6283 /*
6284 * Acquire a control block
6285 */
sym_get_ccb(hcb_p np,u_char tn,u_char ln,u_char tag_order)6286 static ccb_p sym_get_ccb (hcb_p np, u_char tn, u_char ln, u_char tag_order)
6287 {
6288 tcb_p tp = &np->target[tn];
6289 lcb_p lp = sym_lp(np, tp, ln);
6290 u_short tag = NO_TAG;
6291 SYM_QUEHEAD *qp;
6292 ccb_p cp = NULL;
6293
6294 /*
6295 * Look for a free CCB
6296 */
6297 if (sym_que_empty(&np->free_ccbq))
6298 goto out;
6299 qp = sym_remque_head(&np->free_ccbq);
6300 if (!qp)
6301 goto out;
6302 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
6303
6304 /*
6305 * If the LCB is not yet available and the LUN
6306 * has been probed ok, try to allocate the LCB.
6307 */
6308 if (!lp && sym_is_bit(tp->lun_map, ln)) {
6309 lp = sym_alloc_lcb(np, tn, ln);
6310 if (!lp)
6311 goto out_free;
6312 }
6313
6314 /*
6315 * If the LCB is not available here, then the
6316 * logical unit is not yet discovered. For those
6317 * ones only accept 1 SCSI IO per logical unit,
6318 * since we cannot allow disconnections.
6319 */
6320 if (!lp) {
6321 if (!sym_is_bit(tp->busy0_map, ln))
6322 sym_set_bit(tp->busy0_map, ln);
6323 else
6324 goto out_free;
6325 } else {
6326 /*
6327 * If we have been asked for a tagged command.
6328 */
6329 if (tag_order) {
6330 /*
6331 * Debugging purpose.
6332 */
6333 assert(lp->busy_itl == 0);
6334 /*
6335 * Allocate resources for tags if not yet.
6336 */
6337 if (!lp->cb_tags) {
6338 sym_alloc_lcb_tags(np, tn, ln);
6339 if (!lp->cb_tags)
6340 goto out_free;
6341 }
6342 /*
6343 * Get a tag for this SCSI IO and set up
6344 * the CCB bus address for reselection,
6345 * and count it for this LUN.
6346 * Toggle reselect path to tagged.
6347 */
6348 if (lp->busy_itlq < SYM_CONF_MAX_TASK) {
6349 tag = lp->cb_tags[lp->ia_tag];
6350 if (++lp->ia_tag == SYM_CONF_MAX_TASK)
6351 lp->ia_tag = 0;
6352 lp->itlq_tbl[tag] = cpu_to_scr(cp->ccb_ba);
6353 ++lp->busy_itlq;
6354 lp->head.resel_sa =
6355 cpu_to_scr(SCRIPTA_BA (np, resel_tag));
6356 }
6357 else
6358 goto out_free;
6359 }
6360 /*
6361 * This command will not be tagged.
6362 * If we already have either a tagged or untagged
6363 * one, refuse to overlap this untagged one.
6364 */
6365 else {
6366 /*
6367 * Debugging purpose.
6368 */
6369 assert(lp->busy_itl == 0 && lp->busy_itlq == 0);
6370 /*
6371 * Count this nexus for this LUN.
6372 * Set up the CCB bus address for reselection.
6373 * Toggle reselect path to untagged.
6374 */
6375 if (++lp->busy_itl == 1) {
6376 lp->head.itl_task_sa = cpu_to_scr(cp->ccb_ba);
6377 lp->head.resel_sa =
6378 cpu_to_scr(SCRIPTA_BA (np, resel_no_tag));
6379 }
6380 else
6381 goto out_free;
6382 }
6383 }
6384 /*
6385 * Put the CCB into the busy queue.
6386 */
6387 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq);
6388
6389 /*
6390 * Remember all informations needed to free this CCB.
6391 */
6392 cp->to_abort = 0;
6393 cp->tag = tag;
6394 cp->target = tn;
6395 cp->lun = ln;
6396
6397 if (DEBUG_FLAGS & DEBUG_TAGS) {
6398 PRINT_LUN(np, tn, ln);
6399 kprintf ("ccb @%p using tag %d.\n", cp, tag);
6400 }
6401
6402 out:
6403 return cp;
6404 out_free:
6405 sym_insque_head(&cp->link_ccbq, &np->free_ccbq);
6406 return NULL;
6407 }
6408
6409 /*
6410 * Release one control block
6411 */
sym_free_ccb(hcb_p np,ccb_p cp)6412 static void sym_free_ccb (hcb_p np, ccb_p cp)
6413 {
6414 tcb_p tp = &np->target[cp->target];
6415 lcb_p lp = sym_lp(np, tp, cp->lun);
6416
6417 if (DEBUG_FLAGS & DEBUG_TAGS) {
6418 PRINT_LUN(np, cp->target, cp->lun);
6419 kprintf ("ccb @%p freeing tag %d.\n", cp, cp->tag);
6420 }
6421
6422 /*
6423 * If LCB available,
6424 */
6425 if (lp) {
6426 /*
6427 * If tagged, release the tag, set the relect path
6428 */
6429 if (cp->tag != NO_TAG) {
6430 /*
6431 * Free the tag value.
6432 */
6433 lp->cb_tags[lp->if_tag] = cp->tag;
6434 if (++lp->if_tag == SYM_CONF_MAX_TASK)
6435 lp->if_tag = 0;
6436 /*
6437 * Make the reselect path invalid,
6438 * and uncount this CCB.
6439 */
6440 lp->itlq_tbl[cp->tag] = cpu_to_scr(np->bad_itlq_ba);
6441 --lp->busy_itlq;
6442 } else { /* Untagged */
6443 /*
6444 * Make the reselect path invalid,
6445 * and uncount this CCB.
6446 */
6447 lp->head.itl_task_sa = cpu_to_scr(np->bad_itl_ba);
6448 --lp->busy_itl;
6449 }
6450 /*
6451 * If no JOB active, make the LUN reselect path invalid.
6452 */
6453 if (lp->busy_itlq == 0 && lp->busy_itl == 0)
6454 lp->head.resel_sa =
6455 cpu_to_scr(SCRIPTB_BA (np, resel_bad_lun));
6456 }
6457 /*
6458 * Otherwise, we only accept 1 IO per LUN.
6459 * Clear the bit that keeps track of this IO.
6460 */
6461 else
6462 sym_clr_bit(tp->busy0_map, cp->lun);
6463
6464 /*
6465 * We donnot queue more than 1 ccb per target
6466 * with negotiation at any time. If this ccb was
6467 * used for negotiation, clear this info in the tcb.
6468 */
6469 if (cp == tp->nego_cp)
6470 tp->nego_cp = NULL;
6471
6472 #ifdef SYM_CONF_IARB_SUPPORT
6473 /*
6474 * If we just complete the last queued CCB,
6475 * clear this info that is no longer relevant.
6476 */
6477 if (cp == np->last_cp)
6478 np->last_cp = NULL;
6479 #endif
6480
6481 /*
6482 * Unmap user data from DMA map if needed.
6483 */
6484 if (cp->dmamapped) {
6485 bus_dmamap_unload(np->data_dmat, cp->dmamap);
6486 cp->dmamapped = 0;
6487 }
6488
6489 /*
6490 * Make this CCB available.
6491 */
6492 cp->cam_ccb = NULL;
6493 cp->host_status = HS_IDLE;
6494 sym_remque(&cp->link_ccbq);
6495 sym_insque_head(&cp->link_ccbq, &np->free_ccbq);
6496 }
6497
6498 /*
6499 * Allocate a CCB from memory and initialize its fixed part.
6500 */
sym_alloc_ccb(hcb_p np)6501 static ccb_p sym_alloc_ccb(hcb_p np)
6502 {
6503 ccb_p cp = NULL;
6504 int hcode;
6505
6506 SYM_LOCK_ASSERT(0);
6507
6508 /*
6509 * Prevent from allocating more CCBs than we can
6510 * queue to the controller.
6511 */
6512 if (np->actccbs >= SYM_CONF_MAX_START)
6513 return NULL;
6514
6515 /*
6516 * Allocate memory for this CCB.
6517 */
6518 cp = sym_calloc_dma(sizeof(struct sym_ccb), "CCB");
6519 if (!cp)
6520 return NULL;
6521
6522 /*
6523 * Allocate a bounce buffer for sense data.
6524 */
6525 cp->sns_bbuf = sym_calloc_dma(SYM_SNS_BBUF_LEN, "SNS_BBUF");
6526 if (!cp->sns_bbuf)
6527 goto out_free;
6528
6529 /*
6530 * Allocate a map for the DMA of user data.
6531 */
6532 if (bus_dmamap_create(np->data_dmat, 0, &cp->dmamap))
6533 goto out_free;
6534 /*
6535 * Count it.
6536 */
6537 np->actccbs++;
6538
6539 /*
6540 * Initialize the callout.
6541 */
6542 callout_init(&cp->ch);
6543
6544 /*
6545 * Compute the bus address of this ccb.
6546 */
6547 cp->ccb_ba = vtobus(cp);
6548
6549 /*
6550 * Insert this ccb into the hashed list.
6551 */
6552 hcode = CCB_HASH_CODE(cp->ccb_ba);
6553 cp->link_ccbh = np->ccbh[hcode];
6554 np->ccbh[hcode] = cp;
6555
6556 /*
6557 * Initialize the start and restart actions.
6558 */
6559 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA (np, idle));
6560 cp->phys.head.go.restart = cpu_to_scr(SCRIPTB_BA (np, bad_i_t_l));
6561
6562 /*
6563 * Initilialyze some other fields.
6564 */
6565 cp->phys.smsg_ext.addr = cpu_to_scr(HCB_BA(np, msgin[2]));
6566
6567 /*
6568 * Chain into free ccb queue.
6569 */
6570 sym_insque_head(&cp->link_ccbq, &np->free_ccbq);
6571
6572 return cp;
6573 out_free:
6574 if (cp->sns_bbuf)
6575 sym_mfree_dma(cp->sns_bbuf, SYM_SNS_BBUF_LEN, "SNS_BBUF");
6576 sym_mfree_dma(cp, sizeof(*cp), "CCB");
6577 return NULL;
6578 }
6579
6580 /*
6581 * Look up a CCB from a DSA value.
6582 */
sym_ccb_from_dsa(hcb_p np,u32 dsa)6583 static ccb_p sym_ccb_from_dsa(hcb_p np, u32 dsa)
6584 {
6585 int hcode;
6586 ccb_p cp;
6587
6588 hcode = CCB_HASH_CODE(dsa);
6589 cp = np->ccbh[hcode];
6590 while (cp) {
6591 if (cp->ccb_ba == dsa)
6592 break;
6593 cp = cp->link_ccbh;
6594 }
6595
6596 return cp;
6597 }
6598
6599 /*
6600 * Target control block initialisation.
6601 * Nothing important to do at the moment.
6602 */
sym_init_tcb(hcb_p np,u_char tn)6603 static void sym_init_tcb (hcb_p np, u_char tn)
6604 {
6605 /*
6606 * Check some alignments required by the chip.
6607 */
6608 assert (((offsetof(struct sym_reg, nc_sxfer) ^
6609 offsetof(struct sym_tcb, head.sval)) &3) == 0);
6610 assert (((offsetof(struct sym_reg, nc_scntl3) ^
6611 offsetof(struct sym_tcb, head.wval)) &3) == 0);
6612 }
6613
6614 /*
6615 * Lun control block allocation and initialization.
6616 */
sym_alloc_lcb(hcb_p np,u_char tn,u_char ln)6617 static lcb_p sym_alloc_lcb (hcb_p np, u_char tn, u_char ln)
6618 {
6619 tcb_p tp = &np->target[tn];
6620 lcb_p lp = sym_lp(np, tp, ln);
6621
6622 /*
6623 * Already done, just return.
6624 */
6625 if (lp)
6626 return lp;
6627 /*
6628 * Check against some race.
6629 */
6630 assert(!sym_is_bit(tp->busy0_map, ln));
6631
6632 /*
6633 * Initialize the target control block if not yet.
6634 */
6635 sym_init_tcb (np, tn);
6636
6637 /*
6638 * Allocate the LCB bus address array.
6639 * Compute the bus address of this table.
6640 */
6641 if (ln && !tp->luntbl) {
6642 int i;
6643
6644 tp->luntbl = sym_calloc_dma(256, "LUNTBL");
6645 if (!tp->luntbl)
6646 goto fail;
6647 for (i = 0 ; i < 64 ; i++)
6648 tp->luntbl[i] = cpu_to_scr(vtobus(&np->badlun_sa));
6649 tp->head.luntbl_sa = cpu_to_scr(vtobus(tp->luntbl));
6650 }
6651
6652 /*
6653 * Allocate the table of pointers for LUN(s) > 0, if needed.
6654 */
6655 if (ln && !tp->lunmp) {
6656 tp->lunmp = sym_calloc(SYM_CONF_MAX_LUN * sizeof(lcb_p),
6657 "LUNMP");
6658 if (!tp->lunmp)
6659 goto fail;
6660 }
6661
6662 /*
6663 * Allocate the lcb.
6664 * Make it available to the chip.
6665 */
6666 lp = sym_calloc_dma(sizeof(struct sym_lcb), "LCB");
6667 if (!lp)
6668 goto fail;
6669 if (ln) {
6670 tp->lunmp[ln] = lp;
6671 tp->luntbl[ln] = cpu_to_scr(vtobus(lp));
6672 }
6673 else {
6674 tp->lun0p = lp;
6675 tp->head.lun0_sa = cpu_to_scr(vtobus(lp));
6676 }
6677
6678 /*
6679 * Let the itl task point to error handling.
6680 */
6681 lp->head.itl_task_sa = cpu_to_scr(np->bad_itl_ba);
6682
6683 /*
6684 * Set the reselect pattern to our default. :)
6685 */
6686 lp->head.resel_sa = cpu_to_scr(SCRIPTB_BA (np, resel_bad_lun));
6687
6688 /*
6689 * Set user capabilities.
6690 */
6691 lp->user_flags = tp->usrflags & (SYM_DISC_ENABLED | SYM_TAGS_ENABLED);
6692
6693 fail:
6694 return lp;
6695 }
6696
6697 /*
6698 * Allocate LCB resources for tagged command queuing.
6699 */
sym_alloc_lcb_tags(hcb_p np,u_char tn,u_char ln)6700 static void sym_alloc_lcb_tags (hcb_p np, u_char tn, u_char ln)
6701 {
6702 tcb_p tp = &np->target[tn];
6703 lcb_p lp = sym_lp(np, tp, ln);
6704 int i;
6705
6706 /*
6707 * If LCB not available, try to allocate it.
6708 */
6709 if (!lp && !(lp = sym_alloc_lcb(np, tn, ln)))
6710 return;
6711
6712 /*
6713 * Allocate the task table and and the tag allocation
6714 * circular buffer. We want both or none.
6715 */
6716 lp->itlq_tbl = sym_calloc_dma(SYM_CONF_MAX_TASK*4, "ITLQ_TBL");
6717 if (!lp->itlq_tbl)
6718 return;
6719 lp->cb_tags = sym_calloc(SYM_CONF_MAX_TASK, "CB_TAGS");
6720 if (!lp->cb_tags) {
6721 sym_mfree_dma(lp->itlq_tbl, SYM_CONF_MAX_TASK*4, "ITLQ_TBL");
6722 lp->itlq_tbl = NULL;
6723 return;
6724 }
6725
6726 /*
6727 * Initialize the task table with invalid entries.
6728 */
6729 for (i = 0 ; i < SYM_CONF_MAX_TASK ; i++)
6730 lp->itlq_tbl[i] = cpu_to_scr(np->notask_ba);
6731
6732 /*
6733 * Fill up the tag buffer with tag numbers.
6734 */
6735 for (i = 0 ; i < SYM_CONF_MAX_TASK ; i++)
6736 lp->cb_tags[i] = i;
6737
6738 /*
6739 * Make the task table available to SCRIPTS,
6740 * And accept tagged commands now.
6741 */
6742 lp->head.itlq_tbl_sa = cpu_to_scr(vtobus(lp->itlq_tbl));
6743 }
6744
6745 /*
6746 * Test the pci bus snoop logic :-(
6747 *
6748 * Has to be called with interrupts disabled.
6749 */
6750 #ifndef SYM_CONF_IOMAPPED
sym_regtest(hcb_p np)6751 static int sym_regtest (hcb_p np)
6752 {
6753 volatile u32 data;
6754 /*
6755 * chip registers may NOT be cached.
6756 * write 0xffffffff to a read only register area,
6757 * and try to read it back.
6758 */
6759 data = 0xffffffff;
6760 OUTL_OFF(offsetof(struct sym_reg, nc_dstat), data);
6761 data = INL_OFF(offsetof(struct sym_reg, nc_dstat));
6762 #if 1
6763 if (data == 0xffffffff) {
6764 #else
6765 if ((data & 0xe2f0fffd) != 0x02000080) {
6766 #endif
6767 kprintf ("CACHE TEST FAILED: reg dstat-sstat2 readback %x.\n",
6768 (unsigned) data);
6769 return (0x10);
6770 }
6771 return (0);
6772 }
6773 #endif
6774
6775 static int sym_snooptest (hcb_p np)
6776 {
6777 u32 sym_rd, sym_wr, sym_bk, host_rd, host_wr, pc, dstat;
6778 int i, err=0;
6779 #ifndef SYM_CONF_IOMAPPED
6780 err |= sym_regtest (np);
6781 if (err) return (err);
6782 #endif
6783 restart_test:
6784 /*
6785 * Enable Master Parity Checking as we intend
6786 * to enable it for normal operations.
6787 */
6788 OUTB (nc_ctest4, (np->rv_ctest4 & MPEE));
6789 /*
6790 * init
6791 */
6792 pc = SCRIPTB0_BA (np, snooptest);
6793 host_wr = 1;
6794 sym_wr = 2;
6795 /*
6796 * Set memory and register.
6797 */
6798 np->cache = cpu_to_scr(host_wr);
6799 OUTL (nc_temp, sym_wr);
6800 /*
6801 * Start script (exchange values)
6802 */
6803 OUTL (nc_dsa, np->hcb_ba);
6804 OUTL_DSP (pc);
6805 /*
6806 * Wait 'til done (with timeout)
6807 */
6808 for (i=0; i<SYM_SNOOP_TIMEOUT; i++)
6809 if (INB(nc_istat) & (INTF|SIP|DIP))
6810 break;
6811 if (i>=SYM_SNOOP_TIMEOUT) {
6812 kprintf ("CACHE TEST FAILED: timeout.\n");
6813 return (0x20);
6814 }
6815 /*
6816 * Check for fatal DMA errors.
6817 */
6818 dstat = INB (nc_dstat);
6819 #if 1 /* Band aiding for broken hardwares that fail PCI parity */
6820 if ((dstat & MDPE) && (np->rv_ctest4 & MPEE)) {
6821 kprintf ("%s: PCI DATA PARITY ERROR DETECTED - "
6822 "DISABLING MASTER DATA PARITY CHECKING.\n",
6823 sym_name(np));
6824 np->rv_ctest4 &= ~MPEE;
6825 goto restart_test;
6826 }
6827 #endif
6828 if (dstat & (MDPE|BF|IID)) {
6829 kprintf ("CACHE TEST FAILED: DMA error (dstat=0x%02x).", dstat);
6830 return (0x80);
6831 }
6832 /*
6833 * Save termination position.
6834 */
6835 pc = INL (nc_dsp);
6836 /*
6837 * Read memory and register.
6838 */
6839 host_rd = scr_to_cpu(np->cache);
6840 sym_rd = INL (nc_scratcha);
6841 sym_bk = INL (nc_temp);
6842
6843 /*
6844 * Check termination position.
6845 */
6846 if (pc != SCRIPTB0_BA (np, snoopend)+8) {
6847 kprintf ("CACHE TEST FAILED: script execution failed.\n");
6848 kprintf ("start=%08lx, pc=%08lx, end=%08lx\n",
6849 (u_long) SCRIPTB0_BA (np, snooptest), (u_long) pc,
6850 (u_long) SCRIPTB0_BA (np, snoopend) +8);
6851 return (0x40);
6852 }
6853 /*
6854 * Show results.
6855 */
6856 if (host_wr != sym_rd) {
6857 kprintf ("CACHE TEST FAILED: host wrote %d, chip read %d.\n",
6858 (int) host_wr, (int) sym_rd);
6859 err |= 1;
6860 }
6861 if (host_rd != sym_wr) {
6862 kprintf ("CACHE TEST FAILED: chip wrote %d, host read %d.\n",
6863 (int) sym_wr, (int) host_rd);
6864 err |= 2;
6865 }
6866 if (sym_bk != sym_wr) {
6867 kprintf ("CACHE TEST FAILED: chip wrote %d, read back %d.\n",
6868 (int) sym_wr, (int) sym_bk);
6869 err |= 4;
6870 }
6871
6872 return (err);
6873 }
6874
6875 /*
6876 * Determine the chip's clock frequency.
6877 *
6878 * This is essential for the negotiation of the synchronous
6879 * transfer rate.
6880 *
6881 * Note: we have to return the correct value.
6882 * THERE IS NO SAFE DEFAULT VALUE.
6883 *
6884 * Most NCR/SYMBIOS boards are delivered with a 40 Mhz clock.
6885 * 53C860 and 53C875 rev. 1 support fast20 transfers but
6886 * do not have a clock doubler and so are provided with a
6887 * 80 MHz clock. All other fast20 boards incorporate a doubler
6888 * and so should be delivered with a 40 MHz clock.
6889 * The recent fast40 chips (895/896/895A/1010) use a 40 Mhz base
6890 * clock and provide a clock quadrupler (160 Mhz).
6891 */
6892
6893 /*
6894 * Select SCSI clock frequency
6895 */
6896 static void sym_selectclock(hcb_p np, u_char scntl3)
6897 {
6898 /*
6899 * If multiplier not present or not selected, leave here.
6900 */
6901 if (np->multiplier <= 1) {
6902 OUTB(nc_scntl3, scntl3);
6903 return;
6904 }
6905
6906 if (sym_verbose >= 2)
6907 kprintf ("%s: enabling clock multiplier\n", sym_name(np));
6908
6909 OUTB(nc_stest1, DBLEN); /* Enable clock multiplier */
6910 /*
6911 * Wait for the LCKFRQ bit to be set if supported by the chip.
6912 * Otherwise wait 20 micro-seconds.
6913 */
6914 if (np->features & FE_LCKFRQ) {
6915 int i = 20;
6916 while (!(INB(nc_stest4) & LCKFRQ) && --i > 0)
6917 UDELAY (20);
6918 if (!i)
6919 kprintf("%s: the chip cannot lock the frequency\n",
6920 sym_name(np));
6921 } else
6922 UDELAY (20);
6923 OUTB(nc_stest3, HSC); /* Halt the scsi clock */
6924 OUTB(nc_scntl3, scntl3);
6925 OUTB(nc_stest1, (DBLEN|DBLSEL));/* Select clock multiplier */
6926 OUTB(nc_stest3, 0x00); /* Restart scsi clock */
6927 }
6928
6929 /*
6930 * calculate SCSI clock frequency (in KHz)
6931 */
6932 static unsigned getfreq (hcb_p np, int gen)
6933 {
6934 unsigned int ms = 0;
6935 unsigned int f;
6936
6937 /*
6938 * Measure GEN timer delay in order
6939 * to calculate SCSI clock frequency
6940 *
6941 * This code will never execute too
6942 * many loop iterations (if DELAY is
6943 * reasonably correct). It could get
6944 * too low a delay (too high a freq.)
6945 * if the CPU is slow executing the
6946 * loop for some reason (an NMI, for
6947 * example). For this reason we will
6948 * if multiple measurements are to be
6949 * performed trust the higher delay
6950 * (lower frequency returned).
6951 */
6952 OUTW (nc_sien , 0); /* mask all scsi interrupts */
6953 (void) INW (nc_sist); /* clear pending scsi interrupt */
6954 OUTB (nc_dien , 0); /* mask all dma interrupts */
6955 (void) INW (nc_sist); /* another one, just to be sure :) */
6956 OUTB (nc_scntl3, 4); /* set pre-scaler to divide by 3 */
6957 OUTB (nc_stime1, 0); /* disable general purpose timer */
6958 OUTB (nc_stime1, gen); /* set to nominal delay of 1<<gen * 125us */
6959 while (!(INW(nc_sist) & GEN) && ms++ < 100000)
6960 UDELAY (1000); /* count ms */
6961 OUTB (nc_stime1, 0); /* disable general purpose timer */
6962 /*
6963 * set prescaler to divide by whatever 0 means
6964 * 0 ought to choose divide by 2, but appears
6965 * to set divide by 3.5 mode in my 53c810 ...
6966 */
6967 OUTB (nc_scntl3, 0);
6968
6969 /*
6970 * adjust for prescaler, and convert into KHz
6971 */
6972 f = ms ? ((1 << gen) * 4340) / ms : 0;
6973
6974 if (sym_verbose >= 2)
6975 kprintf ("%s: Delay (GEN=%d): %u msec, %u KHz\n",
6976 sym_name(np), gen, ms, f);
6977
6978 return f;
6979 }
6980
6981 static unsigned sym_getfreq (hcb_p np)
6982 {
6983 u_int f1, f2;
6984 int gen = 11;
6985
6986 (void) getfreq (np, gen); /* throw away first result */
6987 f1 = getfreq (np, gen);
6988 f2 = getfreq (np, gen);
6989 if (f1 > f2) f1 = f2; /* trust lower result */
6990 return f1;
6991 }
6992
6993 /*
6994 * Get/probe chip SCSI clock frequency
6995 */
6996 static void sym_getclock (hcb_p np, int mult)
6997 {
6998 unsigned char scntl3 = np->sv_scntl3;
6999 unsigned char stest1 = np->sv_stest1;
7000 unsigned f1;
7001
7002 /*
7003 * For the C10 core, assume 40 MHz.
7004 */
7005 if (np->features & FE_C10) {
7006 np->multiplier = mult;
7007 np->clock_khz = 40000 * mult;
7008 return;
7009 }
7010
7011 np->multiplier = 1;
7012 f1 = 40000;
7013 /*
7014 * True with 875/895/896/895A with clock multiplier selected
7015 */
7016 if (mult > 1 && (stest1 & (DBLEN+DBLSEL)) == DBLEN+DBLSEL) {
7017 if (sym_verbose >= 2)
7018 kprintf ("%s: clock multiplier found\n", sym_name(np));
7019 np->multiplier = mult;
7020 }
7021
7022 /*
7023 * If multiplier not found or scntl3 not 7,5,3,
7024 * reset chip and get frequency from general purpose timer.
7025 * Otherwise trust scntl3 BIOS setting.
7026 */
7027 if (np->multiplier != mult || (scntl3 & 7) < 3 || !(scntl3 & 1)) {
7028 OUTB (nc_stest1, 0); /* make sure doubler is OFF */
7029 f1 = sym_getfreq (np);
7030
7031 if (sym_verbose)
7032 kprintf ("%s: chip clock is %uKHz\n", sym_name(np), f1);
7033
7034 if (f1 < 45000) f1 = 40000;
7035 else if (f1 < 55000) f1 = 50000;
7036 else f1 = 80000;
7037
7038 if (f1 < 80000 && mult > 1) {
7039 if (sym_verbose >= 2)
7040 kprintf ("%s: clock multiplier assumed\n",
7041 sym_name(np));
7042 np->multiplier = mult;
7043 }
7044 } else {
7045 if ((scntl3 & 7) == 3) f1 = 40000;
7046 else if ((scntl3 & 7) == 5) f1 = 80000;
7047 else f1 = 160000;
7048
7049 f1 /= np->multiplier;
7050 }
7051
7052 /*
7053 * Compute controller synchronous parameters.
7054 */
7055 f1 *= np->multiplier;
7056 np->clock_khz = f1;
7057 }
7058
7059 /*
7060 * Get/probe PCI clock frequency
7061 */
7062 static int sym_getpciclock (hcb_p np)
7063 {
7064 int f = 0;
7065
7066 /*
7067 * For the C1010-33, this doesn't work.
7068 * For the C1010-66, this will be tested when I'll have
7069 * such a beast to play with.
7070 */
7071 if (!(np->features & FE_C10)) {
7072 OUTB (nc_stest1, SCLK); /* Use the PCI clock as SCSI clock */
7073 f = (int) sym_getfreq (np);
7074 OUTB (nc_stest1, 0);
7075 }
7076 np->pciclk_khz = f;
7077
7078 return f;
7079 }
7080
7081 /*============= DRIVER ACTION/COMPLETION ====================*/
7082
7083 /*
7084 * Print something that tells about extended errors.
7085 */
7086 static void sym_print_xerr(ccb_p cp, int x_status)
7087 {
7088 if (x_status & XE_PARITY_ERR) {
7089 PRINT_ADDR(cp);
7090 kprintf ("unrecovered SCSI parity error.\n");
7091 }
7092 if (x_status & XE_EXTRA_DATA) {
7093 PRINT_ADDR(cp);
7094 kprintf ("extraneous data discarded.\n");
7095 }
7096 if (x_status & XE_BAD_PHASE) {
7097 PRINT_ADDR(cp);
7098 kprintf ("illegal scsi phase (4/5).\n");
7099 }
7100 if (x_status & XE_SODL_UNRUN) {
7101 PRINT_ADDR(cp);
7102 kprintf ("ODD transfer in DATA OUT phase.\n");
7103 }
7104 if (x_status & XE_SWIDE_OVRUN) {
7105 PRINT_ADDR(cp);
7106 kprintf ("ODD transfer in DATA IN phase.\n");
7107 }
7108 }
7109
7110 /*
7111 * Choose the more appropriate CAM status if
7112 * the IO encountered an extended error.
7113 */
7114 static int sym_xerr_cam_status(int cam_status, int x_status)
7115 {
7116 if (x_status) {
7117 if (x_status & XE_PARITY_ERR)
7118 cam_status = CAM_UNCOR_PARITY;
7119 else if (x_status &(XE_EXTRA_DATA|XE_SODL_UNRUN|XE_SWIDE_OVRUN))
7120 cam_status = CAM_DATA_RUN_ERR;
7121 else if (x_status & XE_BAD_PHASE)
7122 cam_status = CAM_REQ_CMP_ERR;
7123 else
7124 cam_status = CAM_REQ_CMP_ERR;
7125 }
7126 return cam_status;
7127 }
7128
7129 /*
7130 * Complete execution of a SCSI command with extented
7131 * error, SCSI status error, or having been auto-sensed.
7132 *
7133 * The SCRIPTS processor is not running there, so we
7134 * can safely access IO registers and remove JOBs from
7135 * the START queue.
7136 * SCRATCHA is assumed to have been loaded with STARTPOS
7137 * before the SCRIPTS called the C code.
7138 */
7139 static void sym_complete_error (hcb_p np, ccb_p cp)
7140 {
7141 struct ccb_scsiio *csio;
7142 u_int cam_status;
7143 int i, sense_returned;
7144
7145 SYM_LOCK_ASSERT(LK_EXCLUSIVE);
7146
7147 /*
7148 * Paranoid check. :)
7149 */
7150 if (!cp || !cp->cam_ccb)
7151 return;
7152
7153 if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_RESULT)) {
7154 kprintf ("CCB=%lx STAT=%x/%x/%x DEV=%d/%d\n", (unsigned long)cp,
7155 cp->host_status, cp->ssss_status, cp->host_flags,
7156 cp->target, cp->lun);
7157 MDELAY(100);
7158 }
7159
7160 /*
7161 * Get CAM command pointer.
7162 */
7163 csio = &cp->cam_ccb->csio;
7164
7165 /*
7166 * Check for extended errors.
7167 */
7168 if (cp->xerr_status) {
7169 if (sym_verbose)
7170 sym_print_xerr(cp, cp->xerr_status);
7171 if (cp->host_status == HS_COMPLETE)
7172 cp->host_status = HS_COMP_ERR;
7173 }
7174
7175 /*
7176 * Calculate the residual.
7177 */
7178 csio->sense_resid = 0;
7179 csio->resid = sym_compute_residual(np, cp);
7180
7181 if (!SYM_CONF_RESIDUAL_SUPPORT) {/* If user does not want residuals */
7182 csio->resid = 0; /* throw them away. :) */
7183 cp->sv_resid = 0;
7184 }
7185
7186 if (cp->host_flags & HF_SENSE) { /* Auto sense */
7187 csio->scsi_status = cp->sv_scsi_status; /* Restore status */
7188 csio->sense_resid = csio->resid; /* Swap residuals */
7189 csio->resid = cp->sv_resid;
7190 cp->sv_resid = 0;
7191 if (sym_verbose && cp->sv_xerr_status)
7192 sym_print_xerr(cp, cp->sv_xerr_status);
7193 if (cp->host_status == HS_COMPLETE &&
7194 cp->ssss_status == S_GOOD &&
7195 cp->xerr_status == 0) {
7196 cam_status = sym_xerr_cam_status(CAM_SCSI_STATUS_ERROR,
7197 cp->sv_xerr_status);
7198 cam_status |= CAM_AUTOSNS_VALID;
7199 /*
7200 * Bounce back the sense data to user and
7201 * fix the residual.
7202 */
7203 bzero(&csio->sense_data, sizeof(csio->sense_data));
7204 sense_returned = SYM_SNS_BBUF_LEN - csio->sense_resid;
7205 if (sense_returned < csio->sense_len)
7206 csio->sense_resid = csio->sense_len -
7207 sense_returned;
7208 else
7209 csio->sense_resid = 0;
7210 bcopy(cp->sns_bbuf, &csio->sense_data,
7211 MIN(csio->sense_len, sense_returned));
7212 #if 0
7213 /*
7214 * If the device reports a UNIT ATTENTION condition
7215 * due to a RESET condition, we should consider all
7216 * disconnect CCBs for this unit as aborted.
7217 */
7218 if (1) {
7219 u_char *p;
7220 p = (u_char *) csio->sense_data;
7221 if (p[0]==0x70 && p[2]==0x6 && p[12]==0x29)
7222 sym_clear_tasks(np, CAM_REQ_ABORTED,
7223 cp->target,cp->lun, -1);
7224 }
7225 #endif
7226 }
7227 else
7228 cam_status = CAM_AUTOSENSE_FAIL;
7229 }
7230 else if (cp->host_status == HS_COMPLETE) { /* Bad SCSI status */
7231 csio->scsi_status = cp->ssss_status;
7232 cam_status = CAM_SCSI_STATUS_ERROR;
7233 }
7234 else if (cp->host_status == HS_SEL_TIMEOUT) /* Selection timeout */
7235 cam_status = CAM_SEL_TIMEOUT;
7236 else if (cp->host_status == HS_UNEXPECTED) /* Unexpected BUS FREE*/
7237 cam_status = CAM_UNEXP_BUSFREE;
7238 else { /* Extended error */
7239 if (sym_verbose) {
7240 PRINT_ADDR(cp);
7241 kprintf ("COMMAND FAILED (%x %x %x).\n",
7242 cp->host_status, cp->ssss_status,
7243 cp->xerr_status);
7244 }
7245 csio->scsi_status = cp->ssss_status;
7246 /*
7247 * Set the most appropriate value for CAM status.
7248 */
7249 cam_status = sym_xerr_cam_status(CAM_REQ_CMP_ERR,
7250 cp->xerr_status);
7251 }
7252
7253 /*
7254 * Dequeue all queued CCBs for that device
7255 * not yet started by SCRIPTS.
7256 */
7257 i = (INL (nc_scratcha) - np->squeue_ba) / 4;
7258 (void) sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1);
7259
7260 /*
7261 * Restart the SCRIPTS processor.
7262 */
7263 OUTL_DSP (SCRIPTA_BA (np, start));
7264
7265 /*
7266 * Synchronize DMA map if needed.
7267 */
7268 if (cp->dmamapped) {
7269 bus_dmamap_sync(np->data_dmat, cp->dmamap,
7270 (cp->dmamapped == SYM_DMA_READ ?
7271 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE));
7272 }
7273 /*
7274 * Add this one to the COMP queue.
7275 * Complete all those commands with either error
7276 * or requeue condition.
7277 */
7278 sym_set_cam_status((union ccb *) csio, cam_status);
7279 sym_remque(&cp->link_ccbq);
7280 sym_insque_head(&cp->link_ccbq, &np->comp_ccbq);
7281 sym_flush_comp_queue(np, 0);
7282 }
7283
7284 /*
7285 * Complete execution of a successful SCSI command.
7286 *
7287 * Only successful commands go to the DONE queue,
7288 * since we need to have the SCRIPTS processor
7289 * stopped on any error condition.
7290 * The SCRIPTS processor is running while we are
7291 * completing successful commands.
7292 */
7293 static void sym_complete_ok (hcb_p np, ccb_p cp)
7294 {
7295 struct ccb_scsiio *csio;
7296 tcb_p tp;
7297 lcb_p lp;
7298
7299 SYM_LOCK_ASSERT(LK_EXCLUSIVE);
7300
7301 /*
7302 * Paranoid check. :)
7303 */
7304 if (!cp || !cp->cam_ccb)
7305 return;
7306 assert (cp->host_status == HS_COMPLETE);
7307
7308 /*
7309 * Get command, target and lun pointers.
7310 */
7311 csio = &cp->cam_ccb->csio;
7312 tp = &np->target[cp->target];
7313 lp = sym_lp(np, tp, cp->lun);
7314
7315 /*
7316 * Assume device discovered on first success.
7317 */
7318 if (!lp)
7319 sym_set_bit(tp->lun_map, cp->lun);
7320
7321 /*
7322 * If all data have been transferred, given than no
7323 * extended error did occur, there is no residual.
7324 */
7325 csio->resid = 0;
7326 if (cp->phys.head.lastp != cp->phys.head.goalp)
7327 csio->resid = sym_compute_residual(np, cp);
7328
7329 /*
7330 * Wrong transfer residuals may be worse than just always
7331 * returning zero. User can disable this feature from
7332 * sym_conf.h. Residual support is enabled by default.
7333 */
7334 if (!SYM_CONF_RESIDUAL_SUPPORT)
7335 csio->resid = 0;
7336
7337 /*
7338 * Synchronize DMA map if needed.
7339 */
7340 if (cp->dmamapped) {
7341 bus_dmamap_sync(np->data_dmat, cp->dmamap,
7342 (cp->dmamapped == SYM_DMA_READ ?
7343 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE));
7344 }
7345 /*
7346 * Set status and complete the command.
7347 */
7348 csio->scsi_status = cp->ssss_status;
7349 sym_set_cam_status((union ccb *) csio, CAM_REQ_CMP);
7350 sym_xpt_done(np, (union ccb *) csio, cp);
7351 sym_free_ccb(np, cp);
7352 }
7353
7354 /*
7355 * Our callout handler
7356 */
7357 static void sym_callout(void *arg)
7358 {
7359 union ccb *ccb = (union ccb *) arg;
7360 hcb_p np = ccb->ccb_h.sym_hcb_ptr;
7361
7362 /*
7363 * Check that the CAM CCB is still queued.
7364 */
7365 if (!np)
7366 return;
7367
7368 SYM_LOCK();
7369
7370 switch(ccb->ccb_h.func_code) {
7371 case XPT_SCSI_IO:
7372 (void) sym_abort_scsiio(np, ccb, 1);
7373 break;
7374 default:
7375 break;
7376 }
7377
7378 SYM_UNLOCK();
7379 }
7380
7381 /*
7382 * Abort an SCSI IO.
7383 */
7384 static int sym_abort_scsiio(hcb_p np, union ccb *ccb, int timed_out)
7385 {
7386 ccb_p cp;
7387 SYM_QUEHEAD *qp;
7388
7389 SYM_LOCK_ASSERT(LK_EXCLUSIVE);
7390
7391 /*
7392 * Look up our CCB control block.
7393 */
7394 cp = NULL;
7395 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) {
7396 ccb_p cp2 = sym_que_entry(qp, struct sym_ccb, link_ccbq);
7397 if (cp2->cam_ccb == ccb) {
7398 cp = cp2;
7399 break;
7400 }
7401 }
7402 if (!cp || cp->host_status == HS_WAIT)
7403 return -1;
7404
7405 /*
7406 * If a previous abort didn't succeed in time,
7407 * perform a BUS reset.
7408 */
7409 if (cp->to_abort) {
7410 sym_reset_scsi_bus(np, 1);
7411 return 0;
7412 }
7413
7414 /*
7415 * Mark the CCB for abort and allow time for.
7416 */
7417 cp->to_abort = timed_out ? 2 : 1;
7418 callout_reset(&cp->ch, 10 * hz, sym_callout, (caddr_t) ccb);
7419
7420 /*
7421 * Tell the SCRIPTS processor to stop and synchronize with us.
7422 */
7423 np->istat_sem = SEM;
7424 OUTB (nc_istat, SIGP|SEM);
7425 return 0;
7426 }
7427
7428 /*
7429 * Reset a SCSI device (all LUNs of a target).
7430 */
7431 static void sym_reset_dev(hcb_p np, union ccb *ccb)
7432 {
7433 tcb_p tp;
7434 struct ccb_hdr *ccb_h = &ccb->ccb_h;
7435
7436 SYM_LOCK_ASSERT(LK_EXCLUSIVE);
7437
7438 if (ccb_h->target_id == np->myaddr ||
7439 ccb_h->target_id >= SYM_CONF_MAX_TARGET ||
7440 ccb_h->target_lun >= SYM_CONF_MAX_LUN) {
7441 sym_xpt_done2(np, ccb, CAM_DEV_NOT_THERE);
7442 return;
7443 }
7444
7445 tp = &np->target[ccb_h->target_id];
7446
7447 tp->to_reset = 1;
7448 sym_xpt_done2(np, ccb, CAM_REQ_CMP);
7449
7450 np->istat_sem = SEM;
7451 OUTB (nc_istat, SIGP|SEM);
7452 }
7453
7454 /*
7455 * SIM action entry point.
7456 */
7457 static void sym_action(struct cam_sim *sim, union ccb *ccb)
7458 {
7459 hcb_p np;
7460 tcb_p tp;
7461 lcb_p lp;
7462 ccb_p cp;
7463 int tmp;
7464 u_char idmsg, *msgptr;
7465 u_int msglen;
7466 struct ccb_scsiio *csio;
7467 struct ccb_hdr *ccb_h;
7468
7469 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("sym_action\n"));
7470
7471 /*
7472 * Retrieve our controller data structure.
7473 */
7474 np = (hcb_p) cam_sim_softc(sim);
7475
7476 SYM_LOCK_ASSERT(LK_EXCLUSIVE);
7477
7478 /*
7479 * The common case is SCSI IO.
7480 * We deal with other ones elsewhere.
7481 */
7482 if (ccb->ccb_h.func_code != XPT_SCSI_IO) {
7483 sym_action2(sim, ccb);
7484 return;
7485 }
7486 csio = &ccb->csio;
7487 ccb_h = &csio->ccb_h;
7488
7489 /*
7490 * Work around races.
7491 */
7492 if ((ccb_h->status & CAM_STATUS_MASK) != CAM_REQ_INPROG) {
7493 xpt_done(ccb);
7494 return;
7495 }
7496
7497 /*
7498 * Minimal checkings, so that we will not
7499 * go outside our tables.
7500 */
7501 if (ccb_h->target_id == np->myaddr ||
7502 ccb_h->target_id >= SYM_CONF_MAX_TARGET ||
7503 ccb_h->target_lun >= SYM_CONF_MAX_LUN) {
7504 sym_xpt_done2(np, ccb, CAM_DEV_NOT_THERE);
7505 return;
7506 }
7507
7508 /*
7509 * Retrieve the target and lun descriptors.
7510 */
7511 tp = &np->target[ccb_h->target_id];
7512 lp = sym_lp(np, tp, ccb_h->target_lun);
7513
7514 /*
7515 * Complete the 1st INQUIRY command with error
7516 * condition if the device is flagged NOSCAN
7517 * at BOOT in the NVRAM. This may speed up
7518 * the boot and maintain coherency with BIOS
7519 * device numbering. Clearing the flag allows
7520 * user to rescan skipped devices later.
7521 * We also return error for devices not flagged
7522 * for SCAN LUNS in the NVRAM since some mono-lun
7523 * devices behave badly when asked for some non
7524 * zero LUN. Btw, this is an absolute hack.:-)
7525 */
7526 if (!(ccb_h->flags & CAM_CDB_PHYS) &&
7527 (0x12 == ((ccb_h->flags & CAM_CDB_POINTER) ?
7528 csio->cdb_io.cdb_ptr[0] : csio->cdb_io.cdb_bytes[0]))) {
7529 if ((tp->usrflags & SYM_SCAN_BOOT_DISABLED) ||
7530 ((tp->usrflags & SYM_SCAN_LUNS_DISABLED) &&
7531 ccb_h->target_lun != 0)) {
7532 tp->usrflags &= ~SYM_SCAN_BOOT_DISABLED;
7533 sym_xpt_done2(np, ccb, CAM_DEV_NOT_THERE);
7534 return;
7535 }
7536 }
7537
7538 /*
7539 * Get a control block for this IO.
7540 */
7541 tmp = ((ccb_h->flags & CAM_TAG_ACTION_VALID) != 0);
7542 cp = sym_get_ccb(np, ccb_h->target_id, ccb_h->target_lun, tmp);
7543 if (!cp) {
7544 sym_xpt_done2(np, ccb, CAM_RESRC_UNAVAIL);
7545 return;
7546 }
7547
7548 /*
7549 * Keep track of the IO in our CCB.
7550 */
7551 cp->cam_ccb = ccb;
7552
7553 /*
7554 * Build the IDENTIFY message.
7555 */
7556 idmsg = M_IDENTIFY | cp->lun;
7557 if (cp->tag != NO_TAG || (lp && (lp->current_flags & SYM_DISC_ENABLED)))
7558 idmsg |= 0x40;
7559
7560 msgptr = cp->scsi_smsg;
7561 msglen = 0;
7562 msgptr[msglen++] = idmsg;
7563
7564 /*
7565 * Build the tag message if present.
7566 */
7567 if (cp->tag != NO_TAG) {
7568 u_char order = csio->tag_action;
7569
7570 switch(order) {
7571 case M_ORDERED_TAG:
7572 break;
7573 case M_HEAD_TAG:
7574 break;
7575 default:
7576 order = M_SIMPLE_TAG;
7577 }
7578 msgptr[msglen++] = order;
7579
7580 /*
7581 * For less than 128 tags, actual tags are numbered
7582 * 1,3,5,..2*MAXTAGS+1,since we may have to deal
7583 * with devices that have problems with #TAG 0 or too
7584 * great #TAG numbers. For more tags (up to 256),
7585 * we use directly our tag number.
7586 */
7587 #if SYM_CONF_MAX_TASK > (512/4)
7588 msgptr[msglen++] = cp->tag;
7589 #else
7590 msgptr[msglen++] = (cp->tag << 1) + 1;
7591 #endif
7592 }
7593
7594 /*
7595 * Build a negotiation message if needed.
7596 * (nego_status is filled by sym_prepare_nego())
7597 */
7598 cp->nego_status = 0;
7599 if (tp->tinfo.current.width != tp->tinfo.goal.width ||
7600 tp->tinfo.current.period != tp->tinfo.goal.period ||
7601 tp->tinfo.current.offset != tp->tinfo.goal.offset ||
7602 tp->tinfo.current.options != tp->tinfo.goal.options) {
7603 if (!tp->nego_cp && lp)
7604 msglen += sym_prepare_nego(np, cp, 0, msgptr + msglen);
7605 }
7606
7607 /*
7608 * Fill in our ccb
7609 */
7610
7611 /*
7612 * Startqueue
7613 */
7614 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA (np, select));
7615 cp->phys.head.go.restart = cpu_to_scr(SCRIPTA_BA (np, resel_dsa));
7616
7617 /*
7618 * select
7619 */
7620 cp->phys.select.sel_id = cp->target;
7621 cp->phys.select.sel_scntl3 = tp->head.wval;
7622 cp->phys.select.sel_sxfer = tp->head.sval;
7623 cp->phys.select.sel_scntl4 = tp->head.uval;
7624
7625 /*
7626 * message
7627 */
7628 cp->phys.smsg.addr = cpu_to_scr(CCB_BA (cp, scsi_smsg));
7629 cp->phys.smsg.size = cpu_to_scr(msglen);
7630
7631 /*
7632 * command
7633 */
7634 if (sym_setup_cdb(np, csio, cp) < 0) {
7635 sym_xpt_done(np, ccb, cp);
7636 sym_free_ccb(np, cp);
7637 return;
7638 }
7639
7640 /*
7641 * status
7642 */
7643 #if 0 /* Provision */
7644 cp->actualquirks = tp->quirks;
7645 #endif
7646 cp->actualquirks = SYM_QUIRK_AUTOSAVE;
7647 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY;
7648 cp->ssss_status = S_ILLEGAL;
7649 cp->xerr_status = 0;
7650 cp->host_flags = 0;
7651 cp->extra_bytes = 0;
7652
7653 /*
7654 * extreme data pointer.
7655 * shall be positive, so -1 is lower than lowest.:)
7656 */
7657 cp->ext_sg = -1;
7658 cp->ext_ofs = 0;
7659
7660 /*
7661 * Build the data descriptor block
7662 * and start the IO.
7663 */
7664 sym_setup_data_and_start(np, csio, cp);
7665 }
7666
7667 /*
7668 * Setup buffers and pointers that address the CDB.
7669 * I bet, physical CDBs will never be used on the planet,
7670 * since they can be bounced without significant overhead.
7671 */
7672 static int sym_setup_cdb(hcb_p np, struct ccb_scsiio *csio, ccb_p cp)
7673 {
7674 struct ccb_hdr *ccb_h;
7675 u32 cmd_ba;
7676 int cmd_len;
7677
7678 SYM_LOCK_ASSERT(LK_EXCLUSIVE);
7679
7680 ccb_h = &csio->ccb_h;
7681
7682 /*
7683 * CDB is 16 bytes max.
7684 */
7685 if (csio->cdb_len > sizeof(cp->cdb_buf)) {
7686 sym_set_cam_status(cp->cam_ccb, CAM_REQ_INVALID);
7687 return -1;
7688 }
7689 cmd_len = csio->cdb_len;
7690
7691 if (ccb_h->flags & CAM_CDB_POINTER) {
7692 /* CDB is a pointer */
7693 if (!(ccb_h->flags & CAM_CDB_PHYS)) {
7694 /* CDB pointer is virtual */
7695 bcopy(csio->cdb_io.cdb_ptr, cp->cdb_buf, cmd_len);
7696 cmd_ba = CCB_BA (cp, cdb_buf[0]);
7697 } else {
7698 /* CDB pointer is physical */
7699 #if 0
7700 cmd_ba = ((u32)csio->cdb_io.cdb_ptr) & 0xffffffff;
7701 #else
7702 sym_set_cam_status(cp->cam_ccb, CAM_REQ_INVALID);
7703 return -1;
7704 #endif
7705 }
7706 } else {
7707 /* CDB is in the CAM ccb (buffer) */
7708 bcopy(csio->cdb_io.cdb_bytes, cp->cdb_buf, cmd_len);
7709 cmd_ba = CCB_BA (cp, cdb_buf[0]);
7710 }
7711
7712 cp->phys.cmd.addr = cpu_to_scr(cmd_ba);
7713 cp->phys.cmd.size = cpu_to_scr(cmd_len);
7714
7715 return 0;
7716 }
7717
7718 /*
7719 * Set up data pointers used by SCRIPTS.
7720 */
7721 static __inline void
7722 sym_setup_data_pointers(hcb_p np, ccb_p cp, int dir)
7723 {
7724 u32 lastp, goalp;
7725
7726 SYM_LOCK_ASSERT(LK_EXCLUSIVE);
7727
7728 /*
7729 * No segments means no data.
7730 */
7731 if (!cp->segments)
7732 dir = CAM_DIR_NONE;
7733
7734 /*
7735 * Set the data pointer.
7736 */
7737 switch(dir) {
7738 case CAM_DIR_OUT:
7739 goalp = SCRIPTA_BA (np, data_out2) + 8;
7740 lastp = goalp - 8 - (cp->segments * (2*4));
7741 break;
7742 case CAM_DIR_IN:
7743 cp->host_flags |= HF_DATA_IN;
7744 goalp = SCRIPTA_BA (np, data_in2) + 8;
7745 lastp = goalp - 8 - (cp->segments * (2*4));
7746 break;
7747 case CAM_DIR_NONE:
7748 default:
7749 lastp = goalp = SCRIPTB_BA (np, no_data);
7750 break;
7751 }
7752
7753 cp->phys.head.lastp = cpu_to_scr(lastp);
7754 cp->phys.head.goalp = cpu_to_scr(goalp);
7755 cp->phys.head.savep = cpu_to_scr(lastp);
7756 cp->startp = cp->phys.head.savep;
7757 }
7758
7759
7760 /*
7761 * Call back routine for the DMA map service.
7762 * If bounce buffers are used (why ?), we may sleep and then
7763 * be called there in another context.
7764 */
7765 static void
7766 sym_execute_ccb(void *arg, bus_dma_segment_t *psegs, int nsegs, int error)
7767 {
7768 ccb_p cp;
7769 hcb_p np;
7770 union ccb *ccb;
7771
7772 cp = (ccb_p) arg;
7773 ccb = cp->cam_ccb;
7774 np = (hcb_p) cp->arg;
7775
7776 SYM_LOCK_ASSERT(LK_EXCLUSIVE);
7777
7778 /*
7779 * Deal with weird races.
7780 */
7781 if (sym_get_cam_status(ccb) != CAM_REQ_INPROG)
7782 goto out_abort;
7783
7784 /*
7785 * Deal with weird errors.
7786 */
7787 if (error) {
7788 cp->dmamapped = 0;
7789 sym_set_cam_status(cp->cam_ccb, CAM_REQ_ABORTED);
7790 goto out_abort;
7791 }
7792
7793 /*
7794 * Build the data descriptor for the chip.
7795 */
7796 if (nsegs) {
7797 int retv;
7798 /* 896 rev 1 requires to be careful about boundaries */
7799 if (np->device_id == PCI_ID_SYM53C896 && np->revision_id <= 1)
7800 retv = sym_scatter_sg_physical(np, cp, psegs, nsegs);
7801 else
7802 retv = sym_fast_scatter_sg_physical(np,cp, psegs,nsegs);
7803 if (retv < 0) {
7804 sym_set_cam_status(cp->cam_ccb, CAM_REQ_TOO_BIG);
7805 goto out_abort;
7806 }
7807 }
7808
7809 /*
7810 * Synchronize the DMA map only if we have
7811 * actually mapped the data.
7812 */
7813 if (cp->dmamapped) {
7814 bus_dmamap_sync(np->data_dmat, cp->dmamap,
7815 (cp->dmamapped == SYM_DMA_READ ?
7816 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE));
7817 }
7818
7819 /*
7820 * Set host status to busy state.
7821 * May have been set back to HS_WAIT to avoid a race.
7822 */
7823 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY;
7824
7825 /*
7826 * Set data pointers.
7827 */
7828 sym_setup_data_pointers(np, cp, (ccb->ccb_h.flags & CAM_DIR_MASK));
7829
7830 /*
7831 * Enqueue this IO in our pending queue.
7832 */
7833 sym_enqueue_cam_ccb(cp);
7834
7835 /*
7836 * When `#ifed 1', the code below makes the driver
7837 * panic on the first attempt to write to a SCSI device.
7838 * It is the first test we want to do after a driver
7839 * change that does not seem obviously safe. :)
7840 */
7841 #if 0
7842 switch (cp->cdb_buf[0]) {
7843 case 0x0A: case 0x2A: case 0xAA:
7844 panic("XXXXXXXXXXXXX WRITE NOT YET ALLOWED XXXXXXXXXXXXXX");
7845 MDELAY(10000);
7846 break;
7847 default:
7848 break;
7849 }
7850 #endif
7851 /*
7852 * Activate this job.
7853 */
7854 sym_put_start_queue(np, cp);
7855 return;
7856 out_abort:
7857 sym_xpt_done(np, ccb, cp);
7858 sym_free_ccb(np, cp);
7859 }
7860
7861 /*
7862 * How complex it gets to deal with the data in CAM.
7863 * The Bus Dma stuff makes things still more complex.
7864 */
7865 static void
7866 sym_setup_data_and_start(hcb_p np, struct ccb_scsiio *csio, ccb_p cp)
7867 {
7868 struct ccb_hdr *ccb_h;
7869 int dir, retv;
7870
7871 SYM_LOCK_ASSERT(LK_EXCLUSIVE);
7872
7873 ccb_h = &csio->ccb_h;
7874
7875 /*
7876 * Now deal with the data.
7877 */
7878 cp->data_len = csio->dxfer_len;
7879 cp->arg = np;
7880
7881 /*
7882 * No direction means no data.
7883 */
7884 dir = (ccb_h->flags & CAM_DIR_MASK);
7885 if (dir == CAM_DIR_NONE) {
7886 sym_execute_ccb(cp, NULL, 0, 0);
7887 return;
7888 }
7889
7890 if (!(ccb_h->flags & CAM_SCATTER_VALID)) {
7891 /* Single buffer */
7892 if (!(ccb_h->flags & CAM_DATA_PHYS)) {
7893 /* Buffer is virtual */
7894 cp->dmamapped = (dir == CAM_DIR_IN) ?
7895 SYM_DMA_READ : SYM_DMA_WRITE;
7896 retv = bus_dmamap_load(np->data_dmat, cp->dmamap,
7897 csio->data_ptr, csio->dxfer_len,
7898 sym_execute_ccb, cp, 0);
7899 if (retv == EINPROGRESS) {
7900 cp->host_status = HS_WAIT;
7901 xpt_freeze_simq(np->sim, 1);
7902 csio->ccb_h.status |= CAM_RELEASE_SIMQ;
7903 }
7904 } else {
7905 /* Buffer is physical */
7906 struct bus_dma_segment seg;
7907
7908 seg.ds_addr = (bus_addr_t) csio->data_ptr;
7909 sym_execute_ccb(cp, &seg, 1, 0);
7910 }
7911 } else {
7912 /* Scatter/gather list */
7913 struct bus_dma_segment *segs;
7914
7915 if ((ccb_h->flags & CAM_SG_LIST_PHYS) != 0) {
7916 /* The SG list pointer is physical */
7917 sym_set_cam_status(cp->cam_ccb, CAM_REQ_INVALID);
7918 goto out_abort;
7919 }
7920
7921 if (!(ccb_h->flags & CAM_DATA_PHYS)) {
7922 /* SG buffer pointers are virtual */
7923 sym_set_cam_status(cp->cam_ccb, CAM_REQ_INVALID);
7924 goto out_abort;
7925 }
7926
7927 /* SG buffer pointers are physical */
7928 segs = (struct bus_dma_segment *)csio->data_ptr;
7929 sym_execute_ccb(cp, segs, csio->sglist_cnt, 0);
7930 }
7931 return;
7932 out_abort:
7933 sym_xpt_done(np, (union ccb *) csio, cp);
7934 sym_free_ccb(np, cp);
7935 }
7936
7937 /*
7938 * Move the scatter list to our data block.
7939 */
7940 static int
7941 sym_fast_scatter_sg_physical(hcb_p np, ccb_p cp,
7942 bus_dma_segment_t *psegs, int nsegs)
7943 {
7944 struct sym_tblmove *data;
7945 bus_dma_segment_t *psegs2;
7946
7947 SYM_LOCK_ASSERT(LK_EXCLUSIVE);
7948
7949 if (nsegs > SYM_CONF_MAX_SG)
7950 return -1;
7951
7952 data = &cp->phys.data[SYM_CONF_MAX_SG-1];
7953 psegs2 = &psegs[nsegs-1];
7954 cp->segments = nsegs;
7955
7956 while (1) {
7957 data->addr = cpu_to_scr(psegs2->ds_addr);
7958 data->size = cpu_to_scr(psegs2->ds_len);
7959 if (DEBUG_FLAGS & DEBUG_SCATTER) {
7960 kprintf ("%s scatter: paddr=%lx len=%ld\n",
7961 sym_name(np), (long) psegs2->ds_addr,
7962 (long) psegs2->ds_len);
7963 }
7964 if (psegs2 != psegs) {
7965 --data;
7966 --psegs2;
7967 continue;
7968 }
7969 break;
7970 }
7971 return 0;
7972 }
7973
7974
7975 /*
7976 * Scatter a SG list with physical addresses into bus addressable chunks.
7977 * We need to ensure 16MB boundaries not to be crossed during DMA of
7978 * each segment, due to some chips being flawed.
7979 */
7980 #define BOUND_MASK ((1UL<<24)-1)
7981 static int
7982 sym_scatter_sg_physical(hcb_p np, ccb_p cp, bus_dma_segment_t *psegs, int nsegs)
7983 {
7984 u_long ps, pe, pn;
7985 u_long k;
7986 int s, t;
7987
7988 SYM_LOCK_ASSERT(LK_EXCLUSIVE);
7989
7990 s = SYM_CONF_MAX_SG - 1;
7991 t = nsegs - 1;
7992 ps = psegs[t].ds_addr;
7993 pe = ps + psegs[t].ds_len;
7994
7995 while (s >= 0) {
7996 pn = (pe - 1) & ~BOUND_MASK;
7997 if (pn <= ps)
7998 pn = ps;
7999 k = pe - pn;
8000 if (DEBUG_FLAGS & DEBUG_SCATTER) {
8001 kprintf ("%s scatter: paddr=%lx len=%ld\n",
8002 sym_name(np), pn, k);
8003 }
8004 cp->phys.data[s].addr = cpu_to_scr(pn);
8005 cp->phys.data[s].size = cpu_to_scr(k);
8006 --s;
8007 if (pn == ps) {
8008 if (--t < 0)
8009 break;
8010 ps = psegs[t].ds_addr;
8011 pe = ps + psegs[t].ds_len;
8012 }
8013 else
8014 pe = pn;
8015 }
8016
8017 cp->segments = SYM_CONF_MAX_SG - 1 - s;
8018
8019 return t >= 0 ? -1 : 0;
8020 }
8021 #undef BOUND_MASK
8022
8023 /*
8024 * SIM action for non performance critical stuff.
8025 */
8026 static void sym_action2(struct cam_sim *sim, union ccb *ccb)
8027 {
8028 hcb_p np;
8029 tcb_p tp;
8030 lcb_p lp;
8031 struct ccb_hdr *ccb_h;
8032
8033 /*
8034 * Retrieve our controller data structure.
8035 */
8036 np = (hcb_p) cam_sim_softc(sim);
8037
8038 SYM_LOCK_ASSERT(LK_EXCLUSIVE);
8039
8040 ccb_h = &ccb->ccb_h;
8041
8042 switch (ccb_h->func_code) {
8043 case XPT_SET_TRAN_SETTINGS:
8044 {
8045 struct ccb_trans_settings *cts;
8046
8047 cts = &ccb->cts;
8048 tp = &np->target[ccb_h->target_id];
8049
8050 /*
8051 * Update SPI transport settings in TARGET control block.
8052 * Update SCSI device settings in LUN control block.
8053 */
8054 lp = sym_lp(np, tp, ccb_h->target_lun);
8055 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) {
8056 sym_update_trans(np, tp, &tp->tinfo.goal, cts);
8057 if (lp)
8058 sym_update_dflags(np, &lp->current_flags, cts);
8059 }
8060 if (cts->type == CTS_TYPE_USER_SETTINGS) {
8061 sym_update_trans(np, tp, &tp->tinfo.user, cts);
8062 if (lp)
8063 sym_update_dflags(np, &lp->user_flags, cts);
8064 }
8065
8066 sym_xpt_done2(np, ccb, CAM_REQ_CMP);
8067 break;
8068 }
8069 case XPT_GET_TRAN_SETTINGS:
8070 {
8071 struct ccb_trans_settings *cts;
8072 struct sym_trans *tip;
8073 u_char dflags;
8074
8075 cts = &ccb->cts;
8076 tp = &np->target[ccb_h->target_id];
8077 lp = sym_lp(np, tp, ccb_h->target_lun);
8078
8079 #define cts__scsi (&cts->proto_specific.scsi)
8080 #define cts__spi (&cts->xport_specific.spi)
8081 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) {
8082 tip = &tp->tinfo.current;
8083 dflags = lp ? lp->current_flags : 0;
8084 }
8085 else {
8086 tip = &tp->tinfo.user;
8087 dflags = lp ? lp->user_flags : tp->usrflags;
8088 }
8089
8090 cts->protocol = PROTO_SCSI;
8091 cts->transport = XPORT_SPI;
8092 cts->protocol_version = tip->scsi_version;
8093 cts->transport_version = tip->spi_version;
8094
8095 cts__spi->sync_period = tip->period;
8096 cts__spi->sync_offset = tip->offset;
8097 cts__spi->bus_width = tip->width;
8098 cts__spi->ppr_options = tip->options;
8099
8100 cts__spi->valid = CTS_SPI_VALID_SYNC_RATE
8101 | CTS_SPI_VALID_SYNC_OFFSET
8102 | CTS_SPI_VALID_BUS_WIDTH
8103 | CTS_SPI_VALID_PPR_OPTIONS;
8104
8105 cts__spi->flags &= ~CTS_SPI_FLAGS_DISC_ENB;
8106 if (dflags & SYM_DISC_ENABLED)
8107 cts__spi->flags |= CTS_SPI_FLAGS_DISC_ENB;
8108 cts__spi->valid |= CTS_SPI_VALID_DISC;
8109
8110 cts__scsi->flags &= ~CTS_SCSI_FLAGS_TAG_ENB;
8111 if (dflags & SYM_TAGS_ENABLED)
8112 cts__scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB;
8113 cts__scsi->valid |= CTS_SCSI_VALID_TQ;
8114 #undef cts__spi
8115 #undef cts__scsi
8116 sym_xpt_done2(np, ccb, CAM_REQ_CMP);
8117 break;
8118 }
8119 case XPT_CALC_GEOMETRY:
8120 {
8121 cam_calc_geometry(&ccb->ccg, /*extended*/1);
8122 sym_xpt_done2(np, ccb, CAM_REQ_CMP);
8123 break;
8124 }
8125 case XPT_PATH_INQ:
8126 {
8127 struct ccb_pathinq *cpi = &ccb->cpi;
8128 cpi->version_num = 1;
8129 cpi->hba_inquiry = PI_MDP_ABLE|PI_SDTR_ABLE|PI_TAG_ABLE;
8130 if ((np->features & FE_WIDE) != 0)
8131 cpi->hba_inquiry |= PI_WIDE_16;
8132 cpi->target_sprt = 0;
8133 cpi->hba_misc = 0;
8134 if (np->usrflags & SYM_SCAN_TARGETS_HILO)
8135 cpi->hba_misc |= PIM_SCANHILO;
8136 if (np->usrflags & SYM_AVOID_BUS_RESET)
8137 cpi->hba_misc |= PIM_NOBUSRESET;
8138 cpi->hba_eng_cnt = 0;
8139 cpi->max_target = (np->features & FE_WIDE) ? 15 : 7;
8140 /* Semantic problem:)LUN number max = max number of LUNs - 1 */
8141 cpi->max_lun = SYM_CONF_MAX_LUN-1;
8142 if (SYM_SETUP_MAX_LUN < SYM_CONF_MAX_LUN)
8143 cpi->max_lun = SYM_SETUP_MAX_LUN-1;
8144 cpi->bus_id = cam_sim_bus(sim);
8145 cpi->initiator_id = np->myaddr;
8146 cpi->base_transfer_speed = 3300;
8147 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
8148 strncpy(cpi->hba_vid, "Symbios", HBA_IDLEN);
8149 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
8150 cpi->unit_number = cam_sim_unit(sim);
8151
8152 cpi->protocol = PROTO_SCSI;
8153 cpi->protocol_version = SCSI_REV_2;
8154 cpi->transport = XPORT_SPI;
8155 cpi->transport_version = 2;
8156 cpi->xport_specific.spi.ppr_options = SID_SPI_CLOCK_ST;
8157 if (np->features & FE_ULTRA3) {
8158 cpi->transport_version = 3;
8159 cpi->xport_specific.spi.ppr_options =
8160 SID_SPI_CLOCK_DT_ST;
8161 }
8162 sym_xpt_done2(np, ccb, CAM_REQ_CMP);
8163 break;
8164 }
8165 case XPT_ABORT:
8166 {
8167 union ccb *abort_ccb = ccb->cab.abort_ccb;
8168 switch(abort_ccb->ccb_h.func_code) {
8169 case XPT_SCSI_IO:
8170 if (sym_abort_scsiio(np, abort_ccb, 0) == 0) {
8171 sym_xpt_done2(np, ccb, CAM_REQ_CMP);
8172 break;
8173 }
8174 default:
8175 sym_xpt_done2(np, ccb, CAM_UA_ABORT);
8176 break;
8177 }
8178 break;
8179 }
8180 case XPT_RESET_DEV:
8181 {
8182 sym_reset_dev(np, ccb);
8183 break;
8184 }
8185 case XPT_RESET_BUS:
8186 {
8187 sym_reset_scsi_bus(np, 0);
8188 if (sym_verbose) {
8189 xpt_print_path(np->path);
8190 kprintf("SCSI BUS reset delivered.\n");
8191 }
8192 sym_init (np, 1);
8193 sym_xpt_done2(np, ccb, CAM_REQ_CMP);
8194 break;
8195 }
8196 case XPT_ACCEPT_TARGET_IO:
8197 case XPT_CONT_TARGET_IO:
8198 case XPT_EN_LUN:
8199 case XPT_NOTIFY_ACK:
8200 case XPT_IMMED_NOTIFY:
8201 case XPT_TERM_IO:
8202 default:
8203 sym_xpt_done2(np, ccb, CAM_REQ_INVALID);
8204 break;
8205 }
8206 }
8207
8208 /*
8209 * Asynchronous notification handler.
8210 */
8211 static void
8212 sym_async(void *cb_arg, u32 code, struct cam_path *path, void *arg)
8213 {
8214 hcb_p np;
8215 struct cam_sim *sim;
8216 u_int tn;
8217 tcb_p tp;
8218
8219 sim = (struct cam_sim *) cb_arg;
8220 np = (hcb_p) cam_sim_softc(sim);
8221
8222 SYM_LOCK_ASSERT(LK_EXCLUSIVE);
8223
8224 switch (code) {
8225 case AC_LOST_DEVICE:
8226 tn = xpt_path_target_id(path);
8227 if (tn >= SYM_CONF_MAX_TARGET)
8228 break;
8229
8230 tp = &np->target[tn];
8231
8232 tp->to_reset = 0;
8233 tp->head.sval = 0;
8234 tp->head.wval = np->rv_scntl3;
8235 tp->head.uval = 0;
8236
8237 tp->tinfo.current.period = tp->tinfo.goal.period = 0;
8238 tp->tinfo.current.offset = tp->tinfo.goal.offset = 0;
8239 tp->tinfo.current.width = tp->tinfo.goal.width = BUS_8_BIT;
8240 tp->tinfo.current.options = tp->tinfo.goal.options = 0;
8241
8242 break;
8243 default:
8244 break;
8245 }
8246 }
8247
8248 /*
8249 * Update transfer settings of a target.
8250 */
8251 static void sym_update_trans(hcb_p np, tcb_p tp, struct sym_trans *tip,
8252 struct ccb_trans_settings *cts)
8253 {
8254 SYM_LOCK_ASSERT(LK_EXCLUSIVE);
8255
8256 /*
8257 * Update the infos.
8258 */
8259 #define cts__spi (&cts->xport_specific.spi)
8260 if ((cts__spi->valid & CTS_SPI_VALID_BUS_WIDTH) != 0)
8261 tip->width = cts__spi->bus_width;
8262 if ((cts__spi->valid & CTS_SPI_VALID_SYNC_OFFSET) != 0)
8263 tip->offset = cts__spi->sync_offset;
8264 if ((cts__spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0)
8265 tip->period = cts__spi->sync_period;
8266 if ((cts__spi->valid & CTS_SPI_VALID_PPR_OPTIONS) != 0)
8267 tip->options = (cts__spi->ppr_options & PPR_OPT_DT);
8268 if (cts->protocol_version != PROTO_VERSION_UNSPECIFIED &&
8269 cts->protocol_version != PROTO_VERSION_UNKNOWN)
8270 tip->scsi_version = cts->protocol_version;
8271 if (cts->transport_version != XPORT_VERSION_UNSPECIFIED &&
8272 cts->transport_version != XPORT_VERSION_UNKNOWN)
8273 tip->spi_version = cts->transport_version;
8274 #undef cts__spi
8275 /*
8276 * Scale against driver configuration limits.
8277 */
8278 if (tip->width > SYM_SETUP_MAX_WIDE) tip->width = SYM_SETUP_MAX_WIDE;
8279 if (tip->offset > SYM_SETUP_MAX_OFFS) tip->offset = SYM_SETUP_MAX_OFFS;
8280 if (tip->period < SYM_SETUP_MIN_SYNC) tip->period = SYM_SETUP_MIN_SYNC;
8281
8282 /*
8283 * Scale against actual controller BUS width.
8284 */
8285 if (tip->width > np->maxwide)
8286 tip->width = np->maxwide;
8287
8288 /*
8289 * Only accept DT if controller supports and SYNC/WIDE asked.
8290 */
8291 if (!((np->features & (FE_C10|FE_ULTRA3)) == (FE_C10|FE_ULTRA3)) ||
8292 !(tip->width == BUS_16_BIT && tip->offset)) {
8293 tip->options &= ~PPR_OPT_DT;
8294 }
8295
8296 /*
8297 * Scale period factor and offset against controller limits.
8298 */
8299 if (tip->options & PPR_OPT_DT) {
8300 if (tip->period < np->minsync_dt)
8301 tip->period = np->minsync_dt;
8302 if (tip->period > np->maxsync_dt)
8303 tip->period = np->maxsync_dt;
8304 if (tip->offset > np->maxoffs_dt)
8305 tip->offset = np->maxoffs_dt;
8306 }
8307 else {
8308 if (tip->period < np->minsync)
8309 tip->period = np->minsync;
8310 if (tip->period > np->maxsync)
8311 tip->period = np->maxsync;
8312 if (tip->offset > np->maxoffs)
8313 tip->offset = np->maxoffs;
8314 }
8315 }
8316
8317 /*
8318 * Update flags for a device (logical unit).
8319 */
8320 static void
8321 sym_update_dflags(hcb_p np, u_char *flags, struct ccb_trans_settings *cts)
8322 {
8323 SYM_LOCK_ASSERT(LK_EXCLUSIVE);
8324
8325 #define cts__scsi (&cts->proto_specific.scsi)
8326 #define cts__spi (&cts->xport_specific.spi)
8327 if ((cts__spi->valid & CTS_SPI_VALID_DISC) != 0) {
8328 if ((cts__spi->flags & CTS_SPI_FLAGS_DISC_ENB) != 0)
8329 *flags |= SYM_DISC_ENABLED;
8330 else
8331 *flags &= ~SYM_DISC_ENABLED;
8332 }
8333
8334 if ((cts__scsi->valid & CTS_SCSI_VALID_TQ) != 0) {
8335 if ((cts__scsi->flags & CTS_SCSI_FLAGS_TAG_ENB) != 0)
8336 *flags |= SYM_TAGS_ENABLED;
8337 else
8338 *flags &= ~SYM_TAGS_ENABLED;
8339 }
8340 #undef cts__spi
8341 #undef cts__scsi
8342 }
8343
8344
8345 /*============= DRIVER INITIALISATION ==================*/
8346
8347
8348 static device_method_t sym_pci_methods[] = {
8349 DEVMETHOD(device_probe, sym_pci_probe),
8350 DEVMETHOD(device_attach, sym_pci_attach),
8351 DEVMETHOD_END
8352 };
8353
8354 static driver_t sym_pci_driver = {
8355 "sym",
8356 sym_pci_methods,
8357 1 /* no softc */
8358 };
8359
8360 static devclass_t sym_devclass;
8361
8362 DRIVER_MODULE(sym, pci, sym_pci_driver, sym_devclass, NULL, NULL);
8363 MODULE_VERSION(sym, 1);
8364 MODULE_DEPEND(sym, cam, 1, 1, 1);
8365 MODULE_DEPEND(sym, pci, 1, 1, 1);
8366
8367
8368 static const struct sym_pci_chip sym_pci_dev_table[] = {
8369 {PCI_ID_SYM53C810, 0x0f, "810", 4, 8, 4, 64,
8370 FE_ERL}
8371 ,
8372 #ifdef SYM_DEBUG_GENERIC_SUPPORT
8373 {PCI_ID_SYM53C810, 0xff, "810a", 4, 8, 4, 1,
8374 FE_BOF}
8375 ,
8376 #else
8377 {PCI_ID_SYM53C810, 0xff, "810a", 4, 8, 4, 1,
8378 FE_CACHE_SET|FE_LDSTR|FE_PFEN|FE_BOF}
8379 ,
8380 #endif
8381 {PCI_ID_SYM53C815, 0xff, "815", 4, 8, 4, 64,
8382 FE_BOF|FE_ERL}
8383 ,
8384 {PCI_ID_SYM53C825, 0x0f, "825", 6, 8, 4, 64,
8385 FE_WIDE|FE_BOF|FE_ERL|FE_DIFF}
8386 ,
8387 {PCI_ID_SYM53C825, 0xff, "825a", 6, 8, 4, 2,
8388 FE_WIDE|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM|FE_DIFF}
8389 ,
8390 {PCI_ID_SYM53C860, 0xff, "860", 4, 8, 5, 1,
8391 FE_ULTRA|FE_CLK80|FE_CACHE_SET|FE_BOF|FE_LDSTR|FE_PFEN}
8392 ,
8393 {PCI_ID_SYM53C875, 0x01, "875", 6, 16, 5, 2,
8394 FE_WIDE|FE_ULTRA|FE_CLK80|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
8395 FE_RAM|FE_DIFF}
8396 ,
8397 {PCI_ID_SYM53C875, 0xff, "875", 6, 16, 5, 2,
8398 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
8399 FE_RAM|FE_DIFF}
8400 ,
8401 {PCI_ID_SYM53C875_2, 0xff, "875", 6, 16, 5, 2,
8402 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
8403 FE_RAM|FE_DIFF}
8404 ,
8405 {PCI_ID_SYM53C885, 0xff, "885", 6, 16, 5, 2,
8406 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
8407 FE_RAM|FE_DIFF}
8408 ,
8409 #ifdef SYM_DEBUG_GENERIC_SUPPORT
8410 {PCI_ID_SYM53C895, 0xff, "895", 6, 31, 7, 2,
8411 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|
8412 FE_RAM|FE_LCKFRQ}
8413 ,
8414 #else
8415 {PCI_ID_SYM53C895, 0xff, "895", 6, 31, 7, 2,
8416 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
8417 FE_RAM|FE_LCKFRQ}
8418 ,
8419 #endif
8420 {PCI_ID_SYM53C896, 0xff, "896", 6, 31, 7, 4,
8421 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
8422 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ}
8423 ,
8424 {PCI_ID_SYM53C895A, 0xff, "895a", 6, 31, 7, 4,
8425 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
8426 FE_RAM|FE_RAM8K|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ}
8427 ,
8428 {PCI_ID_LSI53C1010, 0x00, "1010-33", 6, 31, 7, 8,
8429 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN|
8430 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_CRC|
8431 FE_C10}
8432 ,
8433 {PCI_ID_LSI53C1010, 0xff, "1010-33", 6, 31, 7, 8,
8434 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN|
8435 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_CRC|
8436 FE_C10|FE_U3EN}
8437 ,
8438 {PCI_ID_LSI53C1010_2, 0xff, "1010-66", 6, 31, 7, 8,
8439 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN|
8440 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_66MHZ|FE_CRC|
8441 FE_C10|FE_U3EN}
8442 ,
8443 {PCI_ID_LSI53C1510D, 0xff, "1510d", 6, 31, 7, 4,
8444 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
8445 FE_RAM|FE_IO256|FE_LEDC}
8446 };
8447
8448 #define sym_pci_num_devs NELEM(sym_pci_dev_table)
8449
8450 /*
8451 * Look up the chip table.
8452 *
8453 * Return a pointer to the chip entry if found,
8454 * zero otherwise.
8455 */
8456 static const struct sym_pci_chip *
8457 sym_find_pci_chip(device_t dev)
8458 {
8459 const struct sym_pci_chip *chip;
8460 int i;
8461 u_short device_id;
8462 u_char revision;
8463
8464 if (pci_get_vendor(dev) != PCI_VENDOR_NCR)
8465 return NULL;
8466
8467 device_id = pci_get_device(dev);
8468 revision = pci_get_revid(dev);
8469
8470 for (i = 0; i < sym_pci_num_devs; i++) {
8471 chip = &sym_pci_dev_table[i];
8472 if (device_id != chip->device_id)
8473 continue;
8474 if (revision > chip->revision_id)
8475 continue;
8476 return chip;
8477 }
8478
8479 return NULL;
8480 }
8481
8482 /*
8483 * Tell upper layer if the chip is supported.
8484 */
8485 static int
8486 sym_pci_probe(device_t dev)
8487 {
8488 const struct sym_pci_chip *chip;
8489
8490 chip = sym_find_pci_chip(dev);
8491 if (chip && sym_find_firmware(chip)) {
8492 device_set_desc(dev, chip->name);
8493 return (chip->lp_probe_bit & SYM_SETUP_LP_PROBE_MAP)?
8494 BUS_PROBE_LOW_PRIORITY : BUS_PROBE_DEFAULT;
8495 }
8496 return ENXIO;
8497 }
8498
8499 /*
8500 * Attach a sym53c8xx device.
8501 */
8502 static int
8503 sym_pci_attach(device_t dev)
8504 {
8505 const struct sym_pci_chip *chip;
8506 u_short command;
8507 u_char cachelnsz;
8508 struct sym_hcb *np = NULL;
8509 struct sym_nvram nvram;
8510 const struct sym_fw *fw = NULL;
8511 int i;
8512 bus_dma_tag_t bus_dmat;
8513
8514 #if 0 /* XXX swildner */
8515 bus_dmat = bus_get_dma_tag(dev);
8516 #else
8517 bus_dmat = NULL;
8518 #endif
8519
8520 /*
8521 * Only probed devices should be attached.
8522 * We just enjoy being paranoid. :)
8523 */
8524 chip = sym_find_pci_chip(dev);
8525 if (chip == NULL || (fw = sym_find_firmware(chip)) == NULL)
8526 return (ENXIO);
8527
8528 /*
8529 * Allocate immediately the host control block,
8530 * since we are only expecting to succeed. :)
8531 * We keep track in the HCB of all the resources that
8532 * are to be released on error.
8533 */
8534 np = __sym_calloc_dma(bus_dmat, sizeof(*np), "HCB");
8535 if (np)
8536 np->bus_dmat = bus_dmat;
8537 else
8538 return (ENXIO);
8539 device_set_softc(dev, np);
8540
8541 SYM_LOCK_INIT();
8542
8543 /*
8544 * Copy some useful infos to the HCB.
8545 */
8546 np->hcb_ba = vtobus(np);
8547 np->verbose = bootverbose;
8548 np->device = dev;
8549 np->device_id = pci_get_device(dev);
8550 np->revision_id = pci_get_revid(dev);
8551 np->features = chip->features;
8552 np->clock_divn = chip->nr_divisor;
8553 np->maxoffs = chip->offset_max;
8554 np->maxburst = chip->burst_max;
8555 np->scripta_sz = fw->a_size;
8556 np->scriptb_sz = fw->b_size;
8557 np->fw_setup = fw->setup;
8558 np->fw_patch = fw->patch;
8559 np->fw_name = fw->name;
8560
8561 #ifdef __x86_64__
8562 np->target = sym_calloc_dma(SYM_CONF_MAX_TARGET * sizeof(*(np->target)),
8563 "TARGET");
8564 if (!np->target)
8565 goto attach_failed;
8566 #endif
8567
8568 /*
8569 * Initialize the CCB free and busy queues.
8570 */
8571 sym_que_init(&np->free_ccbq);
8572 sym_que_init(&np->busy_ccbq);
8573 sym_que_init(&np->comp_ccbq);
8574 sym_que_init(&np->cam_ccbq);
8575
8576 /*
8577 * Allocate a tag for the DMA of user data.
8578 */
8579 if (bus_dma_tag_create(np->bus_dmat, 1, (1<<24),
8580 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
8581 BUS_SPACE_MAXSIZE, SYM_CONF_MAX_SG,
8582 (1<<24), 0,
8583 &np->data_dmat)) {
8584 device_printf(dev, "failed to create DMA tag.\n");
8585 goto attach_failed;
8586 }
8587 /*
8588 * Read and apply some fix-ups to the PCI COMMAND
8589 * register. We want the chip to be enabled for:
8590 * - BUS mastering
8591 * - PCI parity checking (reporting would also be fine)
8592 * - Write And Invalidate.
8593 */
8594 command = pci_read_config(dev, PCIR_COMMAND, 2);
8595 command |= PCIM_CMD_BUSMASTEREN;
8596 command |= PCIM_CMD_PERRESPEN;
8597 command |= /* PCIM_CMD_MWIEN */ 0x0010;
8598 pci_write_config(dev, PCIR_COMMAND, command, 2);
8599
8600 /*
8601 * Let the device know about the cache line size,
8602 * if it doesn't yet.
8603 */
8604 cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
8605 if (!cachelnsz) {
8606 cachelnsz = 8;
8607 pci_write_config(dev, PCIR_CACHELNSZ, cachelnsz, 1);
8608 }
8609
8610 /*
8611 * Alloc/get/map/retrieve everything that deals with MMIO.
8612 */
8613 if ((command & PCIM_CMD_MEMEN) != 0) {
8614 int regs_id = SYM_PCI_MMIO;
8615 np->mmio_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
8616 ®s_id, RF_ACTIVE);
8617 }
8618 if (!np->mmio_res) {
8619 device_printf(dev, "failed to allocate MMIO resources\n");
8620 goto attach_failed;
8621 }
8622 np->mmio_ba = rman_get_start(np->mmio_res);
8623
8624 /*
8625 * Allocate the IRQ.
8626 */
8627 i = 0;
8628 np->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i,
8629 RF_ACTIVE | RF_SHAREABLE);
8630 if (!np->irq_res) {
8631 device_printf(dev, "failed to allocate IRQ resource\n");
8632 goto attach_failed;
8633 }
8634
8635 #ifdef SYM_CONF_IOMAPPED
8636 /*
8637 * User want us to use normal IO with PCI.
8638 * Alloc/get/map/retrieve everything that deals with IO.
8639 */
8640 if ((command & PCI_COMMAND_IO_ENABLE) != 0) {
8641 int regs_id = SYM_PCI_IO;
8642 np->io_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
8643 ®s_id, RF_ACTIVE);
8644 }
8645 if (!np->io_res) {
8646 device_printf(dev, "failed to allocate IO resources\n");
8647 goto attach_failed;
8648 }
8649
8650 #endif /* SYM_CONF_IOMAPPED */
8651
8652 /*
8653 * If the chip has RAM.
8654 * Alloc/get/map/retrieve the corresponding resources.
8655 */
8656 if ((np->features & (FE_RAM|FE_RAM8K)) &&
8657 (command & PCIM_CMD_MEMEN) != 0) {
8658 int regs_id = SYM_PCI_RAM;
8659 if (np->features & FE_64BIT)
8660 regs_id = SYM_PCI_RAM64;
8661 np->ram_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
8662 ®s_id, RF_ACTIVE);
8663 if (!np->ram_res) {
8664 device_printf(dev,"failed to allocate RAM resources\n");
8665 goto attach_failed;
8666 }
8667 np->ram_id = regs_id;
8668 np->ram_ba = rman_get_start(np->ram_res);
8669 }
8670
8671 /*
8672 * Save setting of some IO registers, so we will
8673 * be able to probe specific implementations.
8674 */
8675 sym_save_initial_setting (np);
8676
8677 /*
8678 * Reset the chip now, since it has been reported
8679 * that SCSI clock calibration may not work properly
8680 * if the chip is currently active.
8681 */
8682 sym_chip_reset (np);
8683
8684 /*
8685 * Try to read the user set-up.
8686 */
8687 (void) sym_read_nvram(np, &nvram);
8688
8689 /*
8690 * Prepare controller and devices settings, according
8691 * to chip features, user set-up and driver set-up.
8692 */
8693 (void) sym_prepare_setting(np, &nvram);
8694
8695 /*
8696 * Check the PCI clock frequency.
8697 * Must be performed after prepare_setting since it destroys
8698 * STEST1 that is used to probe for the clock doubler.
8699 */
8700 i = sym_getpciclock(np);
8701 if (i > 37000)
8702 device_printf(dev, "PCI BUS clock seems too high: %u KHz.\n",i);
8703
8704 /*
8705 * Allocate the start queue.
8706 */
8707 np->squeue = (u32 *) sym_calloc_dma(sizeof(u32)*(MAX_QUEUE*2),"SQUEUE");
8708 if (!np->squeue)
8709 goto attach_failed;
8710 np->squeue_ba = vtobus(np->squeue);
8711
8712 /*
8713 * Allocate the done queue.
8714 */
8715 np->dqueue = (u32 *) sym_calloc_dma(sizeof(u32)*(MAX_QUEUE*2),"DQUEUE");
8716 if (!np->dqueue)
8717 goto attach_failed;
8718 np->dqueue_ba = vtobus(np->dqueue);
8719
8720 /*
8721 * Allocate the target bus address array.
8722 */
8723 np->targtbl = (u32 *) sym_calloc_dma(256, "TARGTBL");
8724 if (!np->targtbl)
8725 goto attach_failed;
8726 np->targtbl_ba = vtobus(np->targtbl);
8727
8728 /*
8729 * Allocate SCRIPTS areas.
8730 */
8731 np->scripta0 = sym_calloc_dma(np->scripta_sz, "SCRIPTA0");
8732 np->scriptb0 = sym_calloc_dma(np->scriptb_sz, "SCRIPTB0");
8733 if (!np->scripta0 || !np->scriptb0)
8734 goto attach_failed;
8735
8736 /*
8737 * Allocate the CCBs. We need at least ONE.
8738 */
8739 for (i = 0; sym_alloc_ccb(np) != NULL; i++)
8740 ;
8741 if (i < 1)
8742 goto attach_failed;
8743
8744 /*
8745 * Calculate BUS addresses where we are going
8746 * to load the SCRIPTS.
8747 */
8748 np->scripta_ba = vtobus(np->scripta0);
8749 np->scriptb_ba = vtobus(np->scriptb0);
8750 np->scriptb0_ba = np->scriptb_ba;
8751
8752 if (np->ram_ba) {
8753 np->scripta_ba = np->ram_ba;
8754 if (np->features & FE_RAM8K) {
8755 np->ram_ws = 8192;
8756 np->scriptb_ba = np->scripta_ba + 4096;
8757 #ifdef __LP64__
8758 np->scr_ram_seg = cpu_to_scr(np->scripta_ba >> 32);
8759 #endif
8760 }
8761 else
8762 np->ram_ws = 4096;
8763 }
8764
8765 /*
8766 * Copy scripts to controller instance.
8767 */
8768 bcopy(fw->a_base, np->scripta0, np->scripta_sz);
8769 bcopy(fw->b_base, np->scriptb0, np->scriptb_sz);
8770
8771 /*
8772 * Setup variable parts in scripts and compute
8773 * scripts bus addresses used from the C code.
8774 */
8775 np->fw_setup(np, fw);
8776
8777 /*
8778 * Bind SCRIPTS with physical addresses usable by the
8779 * SCRIPTS processor (as seen from the BUS = BUS addresses).
8780 */
8781 sym_fw_bind_script(np, (u32 *) np->scripta0, np->scripta_sz);
8782 sym_fw_bind_script(np, (u32 *) np->scriptb0, np->scriptb_sz);
8783
8784 #ifdef SYM_CONF_IARB_SUPPORT
8785 /*
8786 * If user wants IARB to be set when we win arbitration
8787 * and have other jobs, compute the max number of consecutive
8788 * settings of IARB hints before we leave devices a chance to
8789 * arbitrate for reselection.
8790 */
8791 #ifdef SYM_SETUP_IARB_MAX
8792 np->iarb_max = SYM_SETUP_IARB_MAX;
8793 #else
8794 np->iarb_max = 4;
8795 #endif
8796 #endif
8797
8798 /*
8799 * Prepare the idle and invalid task actions.
8800 */
8801 np->idletask.start = cpu_to_scr(SCRIPTA_BA (np, idle));
8802 np->idletask.restart = cpu_to_scr(SCRIPTB_BA (np, bad_i_t_l));
8803 np->idletask_ba = vtobus(&np->idletask);
8804
8805 np->notask.start = cpu_to_scr(SCRIPTA_BA (np, idle));
8806 np->notask.restart = cpu_to_scr(SCRIPTB_BA (np, bad_i_t_l));
8807 np->notask_ba = vtobus(&np->notask);
8808
8809 np->bad_itl.start = cpu_to_scr(SCRIPTA_BA (np, idle));
8810 np->bad_itl.restart = cpu_to_scr(SCRIPTB_BA (np, bad_i_t_l));
8811 np->bad_itl_ba = vtobus(&np->bad_itl);
8812
8813 np->bad_itlq.start = cpu_to_scr(SCRIPTA_BA (np, idle));
8814 np->bad_itlq.restart = cpu_to_scr(SCRIPTB_BA (np,bad_i_t_l_q));
8815 np->bad_itlq_ba = vtobus(&np->bad_itlq);
8816
8817 /*
8818 * Allocate and prepare the lun JUMP table that is used
8819 * for a target prior the probing of devices (bad lun table).
8820 * A private table will be allocated for the target on the
8821 * first INQUIRY response received.
8822 */
8823 np->badluntbl = sym_calloc_dma(256, "BADLUNTBL");
8824 if (!np->badluntbl)
8825 goto attach_failed;
8826
8827 np->badlun_sa = cpu_to_scr(SCRIPTB_BA (np, resel_bad_lun));
8828 for (i = 0 ; i < 64 ; i++) /* 64 luns/target, no less */
8829 np->badluntbl[i] = cpu_to_scr(vtobus(&np->badlun_sa));
8830
8831 /*
8832 * Prepare the bus address array that contains the bus
8833 * address of each target control block.
8834 * For now, assume all logical units are wrong. :)
8835 */
8836 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) {
8837 np->targtbl[i] = cpu_to_scr(vtobus(&np->target[i]));
8838 np->target[i].head.luntbl_sa =
8839 cpu_to_scr(vtobus(np->badluntbl));
8840 np->target[i].head.lun0_sa =
8841 cpu_to_scr(vtobus(&np->badlun_sa));
8842 }
8843
8844 /*
8845 * Now check the cache handling of the pci chipset.
8846 */
8847 if (sym_snooptest (np)) {
8848 device_printf(dev, "CACHE INCORRECTLY CONFIGURED.\n");
8849 goto attach_failed;
8850 }
8851
8852 /*
8853 * Now deal with CAM.
8854 * Hopefully, we will succeed with that one.:)
8855 */
8856 if (!sym_cam_attach(np))
8857 goto attach_failed;
8858
8859 /*
8860 * Sigh! we are done.
8861 */
8862 return 0;
8863
8864 /*
8865 * We have failed.
8866 * We will try to free all the resources we have
8867 * allocated, but if we are a boot device, this
8868 * will not help that much.;)
8869 */
8870 attach_failed:
8871 if (np)
8872 sym_pci_free(np);
8873 return ENXIO;
8874 }
8875
8876 /*
8877 * Free everything that have been allocated for this device.
8878 */
8879 static void sym_pci_free(hcb_p np)
8880 {
8881 SYM_QUEHEAD *qp;
8882 ccb_p cp;
8883 tcb_p tp;
8884 lcb_p lp;
8885 int target, lun;
8886
8887 /*
8888 * First free CAM resources.
8889 */
8890 sym_cam_free(np);
8891
8892 /*
8893 * Now every should be quiet for us to
8894 * free other resources.
8895 */
8896 if (np->ram_res)
8897 bus_release_resource(np->device, SYS_RES_MEMORY,
8898 np->ram_id, np->ram_res);
8899 if (np->mmio_res)
8900 bus_release_resource(np->device, SYS_RES_MEMORY,
8901 SYM_PCI_MMIO, np->mmio_res);
8902 if (np->io_res)
8903 bus_release_resource(np->device, SYS_RES_IOPORT,
8904 SYM_PCI_IO, np->io_res);
8905 if (np->irq_res)
8906 bus_release_resource(np->device, SYS_RES_IRQ,
8907 0, np->irq_res);
8908
8909 if (np->scriptb0)
8910 sym_mfree_dma(np->scriptb0, np->scriptb_sz, "SCRIPTB0");
8911 if (np->scripta0)
8912 sym_mfree_dma(np->scripta0, np->scripta_sz, "SCRIPTA0");
8913 if (np->squeue)
8914 sym_mfree_dma(np->squeue, sizeof(u32)*(MAX_QUEUE*2), "SQUEUE");
8915 if (np->dqueue)
8916 sym_mfree_dma(np->dqueue, sizeof(u32)*(MAX_QUEUE*2), "DQUEUE");
8917
8918 while ((qp = sym_remque_head(&np->free_ccbq)) != NULL) {
8919 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
8920 bus_dmamap_destroy(np->data_dmat, cp->dmamap);
8921 sym_mfree_dma(cp->sns_bbuf, SYM_SNS_BBUF_LEN, "SNS_BBUF");
8922 sym_mfree_dma(cp, sizeof(*cp), "CCB");
8923 }
8924
8925 if (np->badluntbl)
8926 sym_mfree_dma(np->badluntbl, 256,"BADLUNTBL");
8927
8928 for (target = 0; target < SYM_CONF_MAX_TARGET ; target++) {
8929 tp = &np->target[target];
8930 for (lun = 0 ; lun < SYM_CONF_MAX_LUN ; lun++) {
8931 lp = sym_lp(np, tp, lun);
8932 if (!lp)
8933 continue;
8934 if (lp->itlq_tbl)
8935 sym_mfree_dma(lp->itlq_tbl, SYM_CONF_MAX_TASK*4,
8936 "ITLQ_TBL");
8937 if (lp->cb_tags)
8938 sym_mfree(lp->cb_tags, SYM_CONF_MAX_TASK,
8939 "CB_TAGS");
8940 sym_mfree_dma(lp, sizeof(*lp), "LCB");
8941 }
8942 #if SYM_CONF_MAX_LUN > 1
8943 if (tp->lunmp)
8944 sym_mfree(tp->lunmp, SYM_CONF_MAX_LUN*sizeof(lcb_p),
8945 "LUNMP");
8946 #endif
8947 }
8948 #ifdef __x86_64__
8949 if (np->target)
8950 sym_mfree_dma(np->target,
8951 SYM_CONF_MAX_TARGET * sizeof(*(np->target)), "TARGET");
8952 #endif
8953 if (np->targtbl)
8954 sym_mfree_dma(np->targtbl, 256, "TARGTBL");
8955 if (np->data_dmat)
8956 bus_dma_tag_destroy(np->data_dmat);
8957 #if 0 /* XXX swildner */
8958 if (SYM_LOCK_INITIALIZED() != 0)
8959 #endif
8960 SYM_LOCK_DESTROY();
8961 device_set_softc(np->device, NULL);
8962 sym_mfree_dma(np, sizeof(*np), "HCB");
8963 }
8964
8965 /*
8966 * Allocate CAM resources and register a bus to CAM.
8967 */
8968 static int sym_cam_attach(hcb_p np)
8969 {
8970 struct cam_devq *devq = NULL;
8971 struct cam_sim *sim = NULL;
8972 struct cam_path *path = NULL;
8973 int err;
8974
8975 /*
8976 * Establish our interrupt handler.
8977 */
8978 err = bus_setup_intr(np->device, np->irq_res,
8979 INTR_MPSAFE,
8980 sym_intr, np, &np->intr, NULL);
8981 if (err) {
8982 device_printf(np->device, "bus_setup_intr() failed: %d\n",
8983 err);
8984 goto fail;
8985 }
8986
8987 /*
8988 * Create the device queue for our sym SIM.
8989 */
8990 devq = cam_simq_alloc(SYM_CONF_MAX_START);
8991 if (!devq)
8992 goto fail;
8993
8994 /*
8995 * Construct our SIM entry.
8996 */
8997 sim = cam_sim_alloc(sym_action, sym_poll, "sym", np,
8998 device_get_unit(np->device),
8999 &np->lock, 1, SYM_SETUP_MAX_TAG, devq);
9000 cam_simq_release(devq);
9001 if (!sim)
9002 goto fail;
9003
9004 SYM_LOCK();
9005
9006 if (xpt_bus_register(sim, 0) != CAM_SUCCESS)
9007 goto fail;
9008 np->sim = sim;
9009
9010 if (xpt_create_path(&path, 0,
9011 cam_sim_path(np->sim), CAM_TARGET_WILDCARD,
9012 CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
9013 goto fail;
9014 }
9015 np->path = path;
9016
9017 /*
9018 * Establish our async notification handler.
9019 */
9020 if (xpt_register_async(AC_LOST_DEVICE, sym_async, sim, path) !=
9021 CAM_REQ_CMP)
9022 goto fail;
9023
9024 /*
9025 * Start the chip now, without resetting the BUS, since
9026 * it seems that this must stay under control of CAM.
9027 * With LVD/SE capable chips and BUS in SE mode, we may
9028 * get a spurious SMBC interrupt.
9029 */
9030 sym_init (np, 0);
9031
9032 SYM_UNLOCK();
9033
9034 return 1;
9035 fail:
9036 if (sim)
9037 cam_sim_free(sim);
9038
9039 SYM_UNLOCK();
9040
9041 sym_cam_free(np);
9042
9043 return 0;
9044 }
9045
9046 /*
9047 * Free everything that deals with CAM.
9048 */
9049 static void sym_cam_free(hcb_p np)
9050 {
9051 SYM_LOCK_ASSERT(0);
9052
9053 if (np->intr) {
9054 bus_teardown_intr(np->device, np->irq_res, np->intr);
9055 np->intr = NULL;
9056 }
9057
9058 SYM_LOCK();
9059
9060 if (np->sim) {
9061 xpt_bus_deregister(cam_sim_path(np->sim));
9062 cam_sim_free(np->sim);
9063 np->sim = NULL;
9064 }
9065 if (np->path) {
9066 xpt_free_path(np->path);
9067 np->path = NULL;
9068 }
9069
9070 SYM_UNLOCK();
9071 }
9072
9073 /*============ OPTIONNAL NVRAM SUPPORT =================*/
9074
9075 /*
9076 * Get host setup from NVRAM.
9077 */
9078 static void sym_nvram_setup_host (hcb_p np, struct sym_nvram *nvram)
9079 {
9080 #ifdef SYM_CONF_NVRAM_SUPPORT
9081 /*
9082 * Get parity checking, host ID, verbose mode
9083 * and miscellaneous host flags from NVRAM.
9084 */
9085 switch(nvram->type) {
9086 case SYM_SYMBIOS_NVRAM:
9087 if (!(nvram->data.Symbios.flags & SYMBIOS_PARITY_ENABLE))
9088 np->rv_scntl0 &= ~0x0a;
9089 np->myaddr = nvram->data.Symbios.host_id & 0x0f;
9090 if (nvram->data.Symbios.flags & SYMBIOS_VERBOSE_MSGS)
9091 np->verbose += 1;
9092 if (nvram->data.Symbios.flags1 & SYMBIOS_SCAN_HI_LO)
9093 np->usrflags |= SYM_SCAN_TARGETS_HILO;
9094 if (nvram->data.Symbios.flags2 & SYMBIOS_AVOID_BUS_RESET)
9095 np->usrflags |= SYM_AVOID_BUS_RESET;
9096 break;
9097 case SYM_TEKRAM_NVRAM:
9098 np->myaddr = nvram->data.Tekram.host_id & 0x0f;
9099 break;
9100 default:
9101 break;
9102 }
9103 #endif
9104 }
9105
9106 /*
9107 * Get target setup from NVRAM.
9108 */
9109 #ifdef SYM_CONF_NVRAM_SUPPORT
9110 static void sym_Symbios_setup_target(hcb_p np,int target, Symbios_nvram *nvram);
9111 static void sym_Tekram_setup_target(hcb_p np,int target, Tekram_nvram *nvram);
9112 #endif
9113
9114 static void
9115 sym_nvram_setup_target (hcb_p np, int target, struct sym_nvram *nvp)
9116 {
9117 #ifdef SYM_CONF_NVRAM_SUPPORT
9118 switch(nvp->type) {
9119 case SYM_SYMBIOS_NVRAM:
9120 sym_Symbios_setup_target (np, target, &nvp->data.Symbios);
9121 break;
9122 case SYM_TEKRAM_NVRAM:
9123 sym_Tekram_setup_target (np, target, &nvp->data.Tekram);
9124 break;
9125 default:
9126 break;
9127 }
9128 #endif
9129 }
9130
9131 #ifdef SYM_CONF_NVRAM_SUPPORT
9132 /*
9133 * Get target set-up from Symbios format NVRAM.
9134 */
9135 static void
9136 sym_Symbios_setup_target(hcb_p np, int target, Symbios_nvram *nvram)
9137 {
9138 tcb_p tp = &np->target[target];
9139 Symbios_target *tn = &nvram->target[target];
9140
9141 tp->tinfo.user.period = tn->sync_period ? (tn->sync_period + 3) / 4 : 0;
9142 tp->tinfo.user.width = tn->bus_width == 0x10 ? BUS_16_BIT : BUS_8_BIT;
9143 tp->usrtags =
9144 (tn->flags & SYMBIOS_QUEUE_TAGS_ENABLED)? SYM_SETUP_MAX_TAG : 0;
9145
9146 if (!(tn->flags & SYMBIOS_DISCONNECT_ENABLE))
9147 tp->usrflags &= ~SYM_DISC_ENABLED;
9148 if (!(tn->flags & SYMBIOS_SCAN_AT_BOOT_TIME))
9149 tp->usrflags |= SYM_SCAN_BOOT_DISABLED;
9150 if (!(tn->flags & SYMBIOS_SCAN_LUNS))
9151 tp->usrflags |= SYM_SCAN_LUNS_DISABLED;
9152 }
9153
9154 /*
9155 * Get target set-up from Tekram format NVRAM.
9156 */
9157 static void
9158 sym_Tekram_setup_target(hcb_p np, int target, Tekram_nvram *nvram)
9159 {
9160 tcb_p tp = &np->target[target];
9161 struct Tekram_target *tn = &nvram->target[target];
9162 int i;
9163
9164 if (tn->flags & TEKRAM_SYNC_NEGO) {
9165 i = tn->sync_index & 0xf;
9166 tp->tinfo.user.period = Tekram_sync[i];
9167 }
9168
9169 tp->tinfo.user.width =
9170 (tn->flags & TEKRAM_WIDE_NEGO) ? BUS_16_BIT : BUS_8_BIT;
9171
9172 if (tn->flags & TEKRAM_TAGGED_COMMANDS) {
9173 tp->usrtags = 2 << nvram->max_tags_index;
9174 }
9175
9176 if (tn->flags & TEKRAM_DISCONNECT_ENABLE)
9177 tp->usrflags |= SYM_DISC_ENABLED;
9178
9179 /* If any device does not support parity, we will not use this option */
9180 if (!(tn->flags & TEKRAM_PARITY_CHECK))
9181 np->rv_scntl0 &= ~0x0a; /* SCSI parity checking disabled */
9182 }
9183
9184 #ifdef SYM_CONF_DEBUG_NVRAM
9185 /*
9186 * Dump Symbios format NVRAM for debugging purpose.
9187 */
9188 static void sym_display_Symbios_nvram(hcb_p np, Symbios_nvram *nvram)
9189 {
9190 int i;
9191
9192 /* display Symbios nvram host data */
9193 kprintf("%s: HOST ID=%d%s%s%s%s%s%s\n",
9194 sym_name(np), nvram->host_id & 0x0f,
9195 (nvram->flags & SYMBIOS_SCAM_ENABLE) ? " SCAM" :"",
9196 (nvram->flags & SYMBIOS_PARITY_ENABLE) ? " PARITY" :"",
9197 (nvram->flags & SYMBIOS_VERBOSE_MSGS) ? " VERBOSE" :"",
9198 (nvram->flags & SYMBIOS_CHS_MAPPING) ? " CHS_ALT" :"",
9199 (nvram->flags2 & SYMBIOS_AVOID_BUS_RESET)?" NO_RESET" :"",
9200 (nvram->flags1 & SYMBIOS_SCAN_HI_LO) ? " HI_LO" :"");
9201
9202 /* display Symbios nvram drive data */
9203 for (i = 0 ; i < 15 ; i++) {
9204 struct Symbios_target *tn = &nvram->target[i];
9205 kprintf("%s-%d:%s%s%s%s WIDTH=%d SYNC=%d TMO=%d\n",
9206 sym_name(np), i,
9207 (tn->flags & SYMBIOS_DISCONNECT_ENABLE) ? " DISC" : "",
9208 (tn->flags & SYMBIOS_SCAN_AT_BOOT_TIME) ? " SCAN_BOOT" : "",
9209 (tn->flags & SYMBIOS_SCAN_LUNS) ? " SCAN_LUNS" : "",
9210 (tn->flags & SYMBIOS_QUEUE_TAGS_ENABLED)? " TCQ" : "",
9211 tn->bus_width,
9212 tn->sync_period / 4,
9213 tn->timeout);
9214 }
9215 }
9216
9217 /*
9218 * Dump TEKRAM format NVRAM for debugging purpose.
9219 */
9220 static const u_char Tekram_boot_delay[7] = {3, 5, 10, 20, 30, 60, 120};
9221 static void sym_display_Tekram_nvram(hcb_p np, Tekram_nvram *nvram)
9222 {
9223 int i, tags, boot_delay;
9224 char *rem;
9225
9226 /* display Tekram nvram host data */
9227 tags = 2 << nvram->max_tags_index;
9228 boot_delay = 0;
9229 if (nvram->boot_delay_index < 6)
9230 boot_delay = Tekram_boot_delay[nvram->boot_delay_index];
9231 switch((nvram->flags & TEKRAM_REMOVABLE_FLAGS) >> 6) {
9232 default:
9233 case 0: rem = ""; break;
9234 case 1: rem = " REMOVABLE=boot device"; break;
9235 case 2: rem = " REMOVABLE=all"; break;
9236 }
9237
9238 kprintf("%s: HOST ID=%d%s%s%s%s%s%s%s%s%s BOOT DELAY=%d tags=%d\n",
9239 sym_name(np), nvram->host_id & 0x0f,
9240 (nvram->flags1 & SYMBIOS_SCAM_ENABLE) ? " SCAM" :"",
9241 (nvram->flags & TEKRAM_MORE_THAN_2_DRIVES) ? " >2DRIVES" :"",
9242 (nvram->flags & TEKRAM_DRIVES_SUP_1GB) ? " >1GB" :"",
9243 (nvram->flags & TEKRAM_RESET_ON_POWER_ON) ? " RESET" :"",
9244 (nvram->flags & TEKRAM_ACTIVE_NEGATION) ? " ACT_NEG" :"",
9245 (nvram->flags & TEKRAM_IMMEDIATE_SEEK) ? " IMM_SEEK" :"",
9246 (nvram->flags & TEKRAM_SCAN_LUNS) ? " SCAN_LUNS" :"",
9247 (nvram->flags1 & TEKRAM_F2_F6_ENABLED) ? " F2_F6" :"",
9248 rem, boot_delay, tags);
9249
9250 /* display Tekram nvram drive data */
9251 for (i = 0; i <= 15; i++) {
9252 int sync, j;
9253 struct Tekram_target *tn = &nvram->target[i];
9254 j = tn->sync_index & 0xf;
9255 sync = Tekram_sync[j];
9256 kprintf("%s-%d:%s%s%s%s%s%s PERIOD=%d\n",
9257 sym_name(np), i,
9258 (tn->flags & TEKRAM_PARITY_CHECK) ? " PARITY" : "",
9259 (tn->flags & TEKRAM_SYNC_NEGO) ? " SYNC" : "",
9260 (tn->flags & TEKRAM_DISCONNECT_ENABLE) ? " DISC" : "",
9261 (tn->flags & TEKRAM_START_CMD) ? " START" : "",
9262 (tn->flags & TEKRAM_TAGGED_COMMANDS) ? " TCQ" : "",
9263 (tn->flags & TEKRAM_WIDE_NEGO) ? " WIDE" : "",
9264 sync);
9265 }
9266 }
9267 #endif /* SYM_CONF_DEBUG_NVRAM */
9268 #endif /* SYM_CONF_NVRAM_SUPPORT */
9269
9270
9271 /*
9272 * Try reading Symbios or Tekram NVRAM
9273 */
9274 #ifdef SYM_CONF_NVRAM_SUPPORT
9275 static int sym_read_Symbios_nvram (hcb_p np, Symbios_nvram *nvram);
9276 static int sym_read_Tekram_nvram (hcb_p np, Tekram_nvram *nvram);
9277 #endif
9278
9279 static int sym_read_nvram(hcb_p np, struct sym_nvram *nvp)
9280 {
9281 #ifdef SYM_CONF_NVRAM_SUPPORT
9282 /*
9283 * Try to read SYMBIOS nvram.
9284 * Try to read TEKRAM nvram if Symbios nvram not found.
9285 */
9286 if (SYM_SETUP_SYMBIOS_NVRAM &&
9287 !sym_read_Symbios_nvram (np, &nvp->data.Symbios)) {
9288 nvp->type = SYM_SYMBIOS_NVRAM;
9289 #ifdef SYM_CONF_DEBUG_NVRAM
9290 sym_display_Symbios_nvram(np, &nvp->data.Symbios);
9291 #endif
9292 }
9293 else if (SYM_SETUP_TEKRAM_NVRAM &&
9294 !sym_read_Tekram_nvram (np, &nvp->data.Tekram)) {
9295 nvp->type = SYM_TEKRAM_NVRAM;
9296 #ifdef SYM_CONF_DEBUG_NVRAM
9297 sym_display_Tekram_nvram(np, &nvp->data.Tekram);
9298 #endif
9299 }
9300 else
9301 nvp->type = 0;
9302 #else
9303 nvp->type = 0;
9304 #endif
9305 return nvp->type;
9306 }
9307
9308
9309 #ifdef SYM_CONF_NVRAM_SUPPORT
9310 /*
9311 * 24C16 EEPROM reading.
9312 *
9313 * GPOI0 - data in/data out
9314 * GPIO1 - clock
9315 * Symbios NVRAM wiring now also used by Tekram.
9316 */
9317
9318 #define SET_BIT 0
9319 #define CLR_BIT 1
9320 #define SET_CLK 2
9321 #define CLR_CLK 3
9322
9323 /*
9324 * Set/clear data/clock bit in GPIO0
9325 */
9326 static void S24C16_set_bit(hcb_p np, u_char write_bit, u_char *gpreg,
9327 int bit_mode)
9328 {
9329 UDELAY (5);
9330 switch (bit_mode){
9331 case SET_BIT:
9332 *gpreg |= write_bit;
9333 break;
9334 case CLR_BIT:
9335 *gpreg &= 0xfe;
9336 break;
9337 case SET_CLK:
9338 *gpreg |= 0x02;
9339 break;
9340 case CLR_CLK:
9341 *gpreg &= 0xfd;
9342 break;
9343
9344 }
9345 OUTB (nc_gpreg, *gpreg);
9346 UDELAY (5);
9347 }
9348
9349 /*
9350 * Send START condition to NVRAM to wake it up.
9351 */
9352 static void S24C16_start(hcb_p np, u_char *gpreg)
9353 {
9354 S24C16_set_bit(np, 1, gpreg, SET_BIT);
9355 S24C16_set_bit(np, 0, gpreg, SET_CLK);
9356 S24C16_set_bit(np, 0, gpreg, CLR_BIT);
9357 S24C16_set_bit(np, 0, gpreg, CLR_CLK);
9358 }
9359
9360 /*
9361 * Send STOP condition to NVRAM - puts NVRAM to sleep... ZZzzzz!!
9362 */
9363 static void S24C16_stop(hcb_p np, u_char *gpreg)
9364 {
9365 S24C16_set_bit(np, 0, gpreg, SET_CLK);
9366 S24C16_set_bit(np, 1, gpreg, SET_BIT);
9367 }
9368
9369 /*
9370 * Read or write a bit to the NVRAM,
9371 * read if GPIO0 input else write if GPIO0 output
9372 */
9373 static void S24C16_do_bit(hcb_p np, u_char *read_bit, u_char write_bit,
9374 u_char *gpreg)
9375 {
9376 S24C16_set_bit(np, write_bit, gpreg, SET_BIT);
9377 S24C16_set_bit(np, 0, gpreg, SET_CLK);
9378 if (read_bit)
9379 *read_bit = INB (nc_gpreg);
9380 S24C16_set_bit(np, 0, gpreg, CLR_CLK);
9381 S24C16_set_bit(np, 0, gpreg, CLR_BIT);
9382 }
9383
9384 /*
9385 * Output an ACK to the NVRAM after reading,
9386 * change GPIO0 to output and when done back to an input
9387 */
9388 static void S24C16_write_ack(hcb_p np, u_char write_bit, u_char *gpreg,
9389 u_char *gpcntl)
9390 {
9391 OUTB (nc_gpcntl, *gpcntl & 0xfe);
9392 S24C16_do_bit(np, 0, write_bit, gpreg);
9393 OUTB (nc_gpcntl, *gpcntl);
9394 }
9395
9396 /*
9397 * Input an ACK from NVRAM after writing,
9398 * change GPIO0 to input and when done back to an output
9399 */
9400 static void S24C16_read_ack(hcb_p np, u_char *read_bit, u_char *gpreg,
9401 u_char *gpcntl)
9402 {
9403 OUTB (nc_gpcntl, *gpcntl | 0x01);
9404 S24C16_do_bit(np, read_bit, 1, gpreg);
9405 OUTB (nc_gpcntl, *gpcntl);
9406 }
9407
9408 /*
9409 * WRITE a byte to the NVRAM and then get an ACK to see it was accepted OK,
9410 * GPIO0 must already be set as an output
9411 */
9412 static void S24C16_write_byte(hcb_p np, u_char *ack_data, u_char write_data,
9413 u_char *gpreg, u_char *gpcntl)
9414 {
9415 int x;
9416
9417 for (x = 0; x < 8; x++)
9418 S24C16_do_bit(np, 0, (write_data >> (7 - x)) & 0x01, gpreg);
9419
9420 S24C16_read_ack(np, ack_data, gpreg, gpcntl);
9421 }
9422
9423 /*
9424 * READ a byte from the NVRAM and then send an ACK to say we have got it,
9425 * GPIO0 must already be set as an input
9426 */
9427 static void S24C16_read_byte(hcb_p np, u_char *read_data, u_char ack_data,
9428 u_char *gpreg, u_char *gpcntl)
9429 {
9430 int x;
9431 u_char read_bit;
9432
9433 *read_data = 0;
9434 for (x = 0; x < 8; x++) {
9435 S24C16_do_bit(np, &read_bit, 1, gpreg);
9436 *read_data |= ((read_bit & 0x01) << (7 - x));
9437 }
9438
9439 S24C16_write_ack(np, ack_data, gpreg, gpcntl);
9440 }
9441
9442 /*
9443 * Read 'len' bytes starting at 'offset'.
9444 */
9445 static int sym_read_S24C16_nvram (hcb_p np, int offset, u_char *data, int len)
9446 {
9447 u_char gpcntl, gpreg;
9448 u_char old_gpcntl, old_gpreg;
9449 u_char ack_data;
9450 int retv = 1;
9451 int x;
9452
9453 /* save current state of GPCNTL and GPREG */
9454 old_gpreg = INB (nc_gpreg);
9455 old_gpcntl = INB (nc_gpcntl);
9456 gpcntl = old_gpcntl & 0x1c;
9457
9458 /* set up GPREG & GPCNTL to set GPIO0 and GPIO1 in to known state */
9459 OUTB (nc_gpreg, old_gpreg);
9460 OUTB (nc_gpcntl, gpcntl);
9461
9462 /* this is to set NVRAM into a known state with GPIO0/1 both low */
9463 gpreg = old_gpreg;
9464 S24C16_set_bit(np, 0, &gpreg, CLR_CLK);
9465 S24C16_set_bit(np, 0, &gpreg, CLR_BIT);
9466
9467 /* now set NVRAM inactive with GPIO0/1 both high */
9468 S24C16_stop(np, &gpreg);
9469
9470 /* activate NVRAM */
9471 S24C16_start(np, &gpreg);
9472
9473 /* write device code and random address MSB */
9474 S24C16_write_byte(np, &ack_data,
9475 0xa0 | ((offset >> 7) & 0x0e), &gpreg, &gpcntl);
9476 if (ack_data & 0x01)
9477 goto out;
9478
9479 /* write random address LSB */
9480 S24C16_write_byte(np, &ack_data,
9481 offset & 0xff, &gpreg, &gpcntl);
9482 if (ack_data & 0x01)
9483 goto out;
9484
9485 /* regenerate START state to set up for reading */
9486 S24C16_start(np, &gpreg);
9487
9488 /* rewrite device code and address MSB with read bit set (lsb = 0x01) */
9489 S24C16_write_byte(np, &ack_data,
9490 0xa1 | ((offset >> 7) & 0x0e), &gpreg, &gpcntl);
9491 if (ack_data & 0x01)
9492 goto out;
9493
9494 /* now set up GPIO0 for inputting data */
9495 gpcntl |= 0x01;
9496 OUTB (nc_gpcntl, gpcntl);
9497
9498 /* input all requested data - only part of total NVRAM */
9499 for (x = 0; x < len; x++)
9500 S24C16_read_byte(np, &data[x], (x == (len-1)), &gpreg, &gpcntl);
9501
9502 /* finally put NVRAM back in inactive mode */
9503 gpcntl &= 0xfe;
9504 OUTB (nc_gpcntl, gpcntl);
9505 S24C16_stop(np, &gpreg);
9506 retv = 0;
9507 out:
9508 /* return GPIO0/1 to original states after having accessed NVRAM */
9509 OUTB (nc_gpcntl, old_gpcntl);
9510 OUTB (nc_gpreg, old_gpreg);
9511
9512 return retv;
9513 }
9514
9515 #undef SET_BIT /* 0 */
9516 #undef CLR_BIT /* 1 */
9517 #undef SET_CLK /* 2 */
9518 #undef CLR_CLK /* 3 */
9519
9520 /*
9521 * Try reading Symbios NVRAM.
9522 * Return 0 if OK.
9523 */
9524 static int sym_read_Symbios_nvram (hcb_p np, Symbios_nvram *nvram)
9525 {
9526 static u_char Symbios_trailer[6] = {0xfe, 0xfe, 0, 0, 0, 0};
9527 u_char *data = (u_char *) nvram;
9528 int len = sizeof(*nvram);
9529 u_short csum;
9530 int x;
9531
9532 /* probe the 24c16 and read the SYMBIOS 24c16 area */
9533 if (sym_read_S24C16_nvram (np, SYMBIOS_NVRAM_ADDRESS, data, len))
9534 return 1;
9535
9536 /* check valid NVRAM signature, verify byte count and checksum */
9537 if (nvram->type != 0 ||
9538 bcmp(nvram->trailer, Symbios_trailer, 6) ||
9539 nvram->byte_count != len - 12)
9540 return 1;
9541
9542 /* verify checksum */
9543 for (x = 6, csum = 0; x < len - 6; x++)
9544 csum += data[x];
9545 if (csum != nvram->checksum)
9546 return 1;
9547
9548 return 0;
9549 }
9550
9551 /*
9552 * 93C46 EEPROM reading.
9553 *
9554 * GPOI0 - data in
9555 * GPIO1 - data out
9556 * GPIO2 - clock
9557 * GPIO4 - chip select
9558 *
9559 * Used by Tekram.
9560 */
9561
9562 /*
9563 * Pulse clock bit in GPIO0
9564 */
9565 static void T93C46_Clk(hcb_p np, u_char *gpreg)
9566 {
9567 OUTB (nc_gpreg, *gpreg | 0x04);
9568 UDELAY (2);
9569 OUTB (nc_gpreg, *gpreg);
9570 }
9571
9572 /*
9573 * Read bit from NVRAM
9574 */
9575 static void T93C46_Read_Bit(hcb_p np, u_char *read_bit, u_char *gpreg)
9576 {
9577 UDELAY (2);
9578 T93C46_Clk(np, gpreg);
9579 *read_bit = INB (nc_gpreg);
9580 }
9581
9582 /*
9583 * Write bit to GPIO0
9584 */
9585 static void T93C46_Write_Bit(hcb_p np, u_char write_bit, u_char *gpreg)
9586 {
9587 if (write_bit & 0x01)
9588 *gpreg |= 0x02;
9589 else
9590 *gpreg &= 0xfd;
9591
9592 *gpreg |= 0x10;
9593
9594 OUTB (nc_gpreg, *gpreg);
9595 UDELAY (2);
9596
9597 T93C46_Clk(np, gpreg);
9598 }
9599
9600 /*
9601 * Send STOP condition to NVRAM - puts NVRAM to sleep... ZZZzzz!!
9602 */
9603 static void T93C46_Stop(hcb_p np, u_char *gpreg)
9604 {
9605 *gpreg &= 0xef;
9606 OUTB (nc_gpreg, *gpreg);
9607 UDELAY (2);
9608
9609 T93C46_Clk(np, gpreg);
9610 }
9611
9612 /*
9613 * Send read command and address to NVRAM
9614 */
9615 static void T93C46_Send_Command(hcb_p np, u_short write_data,
9616 u_char *read_bit, u_char *gpreg)
9617 {
9618 int x;
9619
9620 /* send 9 bits, start bit (1), command (2), address (6) */
9621 for (x = 0; x < 9; x++)
9622 T93C46_Write_Bit(np, (u_char) (write_data >> (8 - x)), gpreg);
9623
9624 *read_bit = INB (nc_gpreg);
9625 }
9626
9627 /*
9628 * READ 2 bytes from the NVRAM
9629 */
9630 static void T93C46_Read_Word(hcb_p np, u_short *nvram_data, u_char *gpreg)
9631 {
9632 int x;
9633 u_char read_bit;
9634
9635 *nvram_data = 0;
9636 for (x = 0; x < 16; x++) {
9637 T93C46_Read_Bit(np, &read_bit, gpreg);
9638
9639 if (read_bit & 0x01)
9640 *nvram_data |= (0x01 << (15 - x));
9641 else
9642 *nvram_data &= ~(0x01 << (15 - x));
9643 }
9644 }
9645
9646 /*
9647 * Read Tekram NvRAM data.
9648 */
9649 static int T93C46_Read_Data(hcb_p np, u_short *data,int len,u_char *gpreg)
9650 {
9651 u_char read_bit;
9652 int x;
9653
9654 for (x = 0; x < len; x++) {
9655
9656 /* output read command and address */
9657 T93C46_Send_Command(np, 0x180 | x, &read_bit, gpreg);
9658 if (read_bit & 0x01)
9659 return 1; /* Bad */
9660 T93C46_Read_Word(np, &data[x], gpreg);
9661 T93C46_Stop(np, gpreg);
9662 }
9663
9664 return 0;
9665 }
9666
9667 /*
9668 * Try reading 93C46 Tekram NVRAM.
9669 */
9670 static int sym_read_T93C46_nvram (hcb_p np, Tekram_nvram *nvram)
9671 {
9672 u_char gpcntl, gpreg;
9673 u_char old_gpcntl, old_gpreg;
9674 int retv = 1;
9675
9676 /* save current state of GPCNTL and GPREG */
9677 old_gpreg = INB (nc_gpreg);
9678 old_gpcntl = INB (nc_gpcntl);
9679
9680 /* set up GPREG & GPCNTL to set GPIO0/1/2/4 in to known state, 0 in,
9681 1/2/4 out */
9682 gpreg = old_gpreg & 0xe9;
9683 OUTB (nc_gpreg, gpreg);
9684 gpcntl = (old_gpcntl & 0xe9) | 0x09;
9685 OUTB (nc_gpcntl, gpcntl);
9686
9687 /* input all of NVRAM, 64 words */
9688 retv = T93C46_Read_Data(np, (u_short *) nvram,
9689 sizeof(*nvram) / sizeof(short), &gpreg);
9690
9691 /* return GPIO0/1/2/4 to original states after having accessed NVRAM */
9692 OUTB (nc_gpcntl, old_gpcntl);
9693 OUTB (nc_gpreg, old_gpreg);
9694
9695 return retv;
9696 }
9697
9698 /*
9699 * Try reading Tekram NVRAM.
9700 * Return 0 if OK.
9701 */
9702 static int sym_read_Tekram_nvram (hcb_p np, Tekram_nvram *nvram)
9703 {
9704 u_char *data = (u_char *) nvram;
9705 int len = sizeof(*nvram);
9706 u_short csum;
9707 int x;
9708
9709 switch (np->device_id) {
9710 case PCI_ID_SYM53C885:
9711 case PCI_ID_SYM53C895:
9712 case PCI_ID_SYM53C896:
9713 x = sym_read_S24C16_nvram(np, TEKRAM_24C16_NVRAM_ADDRESS,
9714 data, len);
9715 break;
9716 case PCI_ID_SYM53C875:
9717 x = sym_read_S24C16_nvram(np, TEKRAM_24C16_NVRAM_ADDRESS,
9718 data, len);
9719 if (!x)
9720 break;
9721 default:
9722 x = sym_read_T93C46_nvram(np, nvram);
9723 break;
9724 }
9725 if (x)
9726 return 1;
9727
9728 /* verify checksum */
9729 for (x = 0, csum = 0; x < len - 1; x += 2)
9730 csum += data[x] + (data[x+1] << 8);
9731 if (csum != 0x1234)
9732 return 1;
9733
9734 return 0;
9735 }
9736
9737 #endif /* SYM_CONF_NVRAM_SUPPORT */
9738