1 /* $NetBSD: intreg.h,v 1.13 2005/11/16 22:10:58 uwe Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)intreg.h 8.1 (Berkeley) 6/11/93 41 */ 42 43 #include <sparc/sparc/vaddrs.h> 44 45 /* 46 * sun4c interrupt enable register. 47 * 48 * The register is a single byte. C code must use the ienab_bis and 49 * ienab_bic functions found in locore.s. 50 * 51 * The register's physical address is defined here as the register 52 * must be mapped early in the boot process (otherwise NMI handling 53 * will fail). 54 */ 55 #define INT_ENABLE_REG_PHYSADR 0xf5000000 /* phys addr in IOspace */ 56 57 /* 58 * Bits in interrupt enable register. Software interrupt requests must 59 * be cleared in software. This is done in locore.s. The ALLIE bit must 60 * be cleared to clear asynchronous memory error (level 15) interrupts. 61 */ 62 #define IE_L14 0x80 /* enable level 14 (counter 1) interrupts */ 63 #define IE_L10 0x20 /* enable level 10 (counter 0) interrupts */ 64 #define IE_L8 0x10 /* enable level 8 interrupts */ 65 #define IE_L6 0x08 /* request software level 6 interrupt */ 66 #define IE_L4 0x04 /* request software level 4 interrupt */ 67 #define IE_L1 0x02 /* request software level 1 interrupt */ 68 #define IE_ALLIE 0x01 /* enable interrupts */ 69 70 #ifndef _LOCORE 71 void ienab_bis(int); /* set given bits */ 72 void ienab_bic(int); /* clear given bits */ 73 #endif 74 75 #ifdef notyet 76 #define IENAB_SYS ((_MAXNBPG * _MAXNCPU) + 0xc) 77 #define IENAB_P0 0x0008 78 #define IENAB_P1 0x1008 79 #define IENAB_P2 0x2008 80 #define IENAB_P3 0x3008 81 #endif /* notyet */ 82 83 /* 84 * sun4m Interrupt Control Registers, located in IO space. 85 * There are two sets of interrupt registers called `Processor Interrupts' 86 * and `System Interrupts'. The `Processor' set corresponds to the 15 87 * interrupt levels as seen by the CPU. The `System' set corresponds to 88 * a set of devices supported by the implementing chip-set. 89 * 90 * Briefly, the ICR_PI_* are per-processor interrupts; the ICR_SI_* are 91 * system-wide interrupts, and the ICR_ITR selects the processor to get 92 * the system's interrupts. 93 */ 94 #ifndef _LOCORE 95 struct icr_pi { 96 uint32_t pi_pend; /* Pending interrupts (read-only) */ 97 uint32_t pi_clr; /* Clear interrupts (write-only) */ 98 uint32_t pi_set; /* Raise interrupts (write-only) */ 99 }; 100 #endif 101 #define ICR_PI_PEND_OFFSET 0 102 #define ICR_PI_CLR_OFFSET 4 103 #define ICR_PI_SET_OFFSET 8 104 105 #define ICR_PI_PEND (PI_INTR_VA + ICR_PI_PEND_OFFSET) 106 #define ICR_PI_CLR (PI_INTR_VA + ICR_PI_CLR_OFFSET) 107 #define ICR_PI_SET (PI_INTR_VA + ICR_PI_SET_OFFSET) 108 109 110 /* The system interrupt register */ 111 #define ICR_SI_PEND (SI_INTR_VA) 112 #define ICR_SI_MASK (SI_INTR_VA + 0x4) 113 #define ICR_SI_CLR (SI_INTR_VA + 0x8) 114 #define ICR_SI_SET (SI_INTR_VA + 0xc) 115 #define ICR_ITR (SI_INTR_VA + 0x10) 116 117 /* 118 * Bits in interrupt registers. Software interrupt requests must 119 * be cleared in software. This is done in locore.s. 120 * There are separate registers for reading pending interrupts and 121 * setting/clearing (software) interrupts. 122 */ 123 #define PINTR_SINTRLEV(n) (1 << (16 + (n))) 124 #define PINTR_IC 0x8000 /* Level 15 clear */ 125 126 #define SINTR_MA 0x80000000 /* Mask All interrupts */ 127 #define SINTR_ME 0x40000000 /* Module Error (async) */ 128 #define SINTR_I 0x20000000 /* MSI (MBus-SBus) */ 129 #define SINTR_M 0x10000000 /* ECC Memory controller */ 130 #define SINTR_V 0x08000000 /* VME Async error */ 131 #define SINTR_RSVD2 0x07800000 132 #define SINTR_F 0x00400000 /* Floppy */ 133 #define SINTR_MI 0x00200000 /* Module interrupt */ 134 #define SINTR_VI 0x00100000 /* Video (Supersparc only) */ 135 #define SINTR_T 0x00080000 /* Level 10 counter */ 136 #define SINTR_SC 0x00040000 /* SCSI */ 137 #define SINTR_A 0x00020000 /* Audio/ISDN */ 138 #define SINTR_E 0x00010000 /* Ethernet */ 139 #define SINTR_S 0x00008000 /* Serial port */ 140 #define SINTR_K 0x00004000 /* Keyboard/mouse */ 141 #define SINTR_SBUSMASK 0x00003f80 /* SBus */ 142 #define SINTR_SBUS(n) (1 << (7+(n)-1)) 143 #define SINTR_VMEMASK 0x0000007f /* VME */ 144 #define SINTR_VME(n) (1 << ((n)-1)) 145 #define SINTR_BITS "\177\020" \ 146 "f\0\7VME\0f\7\7SBUS\0b\16K\0b\17S\0b\20E\0" \ 147 "b\21A\0b\22SC\0b\23T\0b\24VI\0b\25MI\0" \ 148 "b\26F\0b\33V\0b\34M\0b\35I\0b\36ME\0b\37MA\0" 149 150 /* 151 * Set & clear bits in the system interrupt register 152 */ 153 #define icr_si_bis(bis) do { \ 154 *((uint32_t *)ICR_SI_SET) = (bis); \ 155 } while (0) 156 157 #define icr_si_bic(bic) do { \ 158 *((uint32_t *)ICR_SI_CLR) = (bic); \ 159 } while (0) 160