| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 676 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeAddiGroupBranch() local
704 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP35GroupBranchMMR6() local
749 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeDaddiGroupBranch() local
777 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP37GroupBranchMMR6() local
818 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP65GroupBranchMMR6() local
857 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP75GroupBranchMMR6() local
901 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeBlezlGroupBranch() local
946 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeBgtzlGroupBranch() local
988 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeBgtzGroupBranch() local
1037 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeBlezGroupBranch() local
[all …]
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| /freebsd-12-stable/contrib/llvm-project/compiler-rt/lib/xray/ |
| D | xray_mips.cpp | 41 uint32_t Rt, in encodeInstruction()
47 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction()
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| D | xray_mips64.cpp | 42 uint32_t Rt, in encodeInstruction()
48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonAsmPrinter.cpp | 374 MCOperand &Rt = Inst.getOperand(3); in HexagonProcessInstruction() local
385 MCOperand &Rt = Inst.getOperand(2); in HexagonProcessInstruction() local
397 MCOperand &Rt = Inst.getOperand(2); in HexagonProcessInstruction() local
594 MCOperand &Rt = Inst.getOperand(1); in HexagonProcessInstruction() local
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| D | HexagonBitTracker.cpp | 295 uint16_t BW, bool Odd) -> BT::RegisterCell { in evaluate()
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| D | HexagonSplitDouble.cpp | 375 Register Rt = MI->getOperand(2).getReg(); in profit() local
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| D | HexagonBitSimplify.cpp | 1895 BitTracker::RegisterRef &Rt) { in matchPackhl()
2028 BitTracker::RegisterRef Rs, Rt; in genPackhl() local
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| D | HexagonISelDAGToDAGHVX.cpp | 2373 SDValue Rt = N->getOperand(2); in selectVAlign() local
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| D | HexagonInstrInfo.cpp | 1261 Register Rt = Op3.getReg(); in expandPostRAPseudo() local
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1849 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeAddrMode2IdxInstruction() local
1997 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeAddrMode3Instruction() local
3792 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadShift() local
3876 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadImm8() local
3960 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadImm12() local
4040 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadT() local
4078 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadLabel() local
4315 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LdStPre() local
4778 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeDoubleRegLoad() local
4801 unsigned Rt = fieldFromInstruction(Insn, 0, 4); in DecodeDoubleRegStore() local
[all …]
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 1174 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeUnsignedLdStInstruction() local
1235 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeSignedLdStInstruction() local
1433 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeExclusiveLdStInstruction() local
1516 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodePairLdStInstruction() local
1650 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeAuthLoadInstruction() local
1929 uint64_t Rt = fieldFromInstruction(insn, 0, 5); in DecodeTestAndBranch() local
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVMergeBaseOffset.cpp | 139 Register Rt = TailAdd.getOperand(2).getReg(); in matchLargeOffset() local
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCCompound.cpp | 201 MCOperand Rs, Rt; in getCompoundInsn() local
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 3462 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
3469 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
3499 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
3511 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
3534 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
3549 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
3575 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
3585 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
3622 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
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| D | Thumb2SizeReduction.cpp | 467 Register Rt = MI->getOperand(IsStore ? 1 : 0).getReg(); in ReduceLoadStore() local
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1392 MCOperand &Rt = Inst.getOperand(1); in processInstruction() local
1813 MCOperand &Rt = Inst.getOperand(2); in processInstruction() local
1833 MCOperand &Rt = Inst.getOperand(3); in processInstruction() local
1856 MCOperand &Rt = Inst.getOperand(2); in processInstruction() local
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| /freebsd-12-stable/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/ |
| D | EmulateInstructionARM.cpp | 930 uint32_t Rt; // the source register in EmulatePUSH() local
1045 uint32_t Rt; // the destination register in EmulatePOP() local
1776 uint32_t Rt; // the destination register in EmulateLDRRtPCRelative() local
2480 uint32_t Rt; // the source register in EmulateSTRRtSP() local
4444 uint32_t Rt; // the destination register in EmulateLDRRtRnImm() local
5764 uint32_t Rt = ReadCoreReg(t, &success); in EmulateSTRHRegister() local
10427 uint32_t Rt = in EmulateSTREX() local
10519 uint32_t Rt = ReadCoreReg(t, &success); in EmulateSTRBImmARM() local
10620 uint32_t Rt = ReadCoreReg(t, &success); in EmulateSTRImmARM() local
11174 uint32_t Rt = ReadCoreReg(t, &success); in EmulateSTRDReg() local
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 4738 unsigned Rt = Inst.getOperand(1).getReg(); in validateInstruction() local
4755 unsigned Rt = Inst.getOperand(0).getReg(); in validateInstruction() local
4768 unsigned Rt = Inst.getOperand(1).getReg(); in validateInstruction() local
4784 unsigned Rt = Inst.getOperand(1).getReg(); in validateInstruction() local
4817 unsigned Rt = Inst.getOperand(1).getReg(); in validateInstruction() local
4836 unsigned Rt = Inst.getOperand(1).getReg(); in validateInstruction() local
4852 unsigned Rt = Inst.getOperand(1).getReg(); in validateInstruction() local
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| /freebsd-12-stable/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM64/ |
| D | EmulateInstructionARM64.cpp | 710 uint32_t Rt = Bits32(opcode, 4, 0); in EmulateLDPSTP() local
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 3515 Register Rt = MI.getOperand(1).getReg(); in emitST_F16_PSEUDO() local
3580 Register Rt = RegInfo.createVirtualRegister(RC); in emitLD_F16_PSEUDO() local
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 7416 unsigned Rt = MRI->getEncodingValue(Reg1); in ParseInstruction() local
7537 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(RtIndex).getReg()); in validateLDRDSTRD() local
7762 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); in validateInstruction() local
7775 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); in validateInstruction() local
7822 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); in validateInstruction() local
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| /freebsd-12-stable/contrib/llvm-project/clang/lib/CodeGen/ |
| D | CGOpenMPRuntimeGPU.cpp | 1344 auto &Rt = in emitTeamsOutlinedFunction() local
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| D | CGBuiltin.cpp | 7444 Value *Rt = Builder.CreateTruncOrBitCast(RtAndRt2, Int32Ty); in EmitARMBuiltinExpr() local
7473 Value *Rt = Builder.CreateExtractValue(RtAndRt2, 1); in EmitARMBuiltinExpr() local
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