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Searched defs:Regs (Results 1 – 25 of 49) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/Disassembler/
HDSystemZDisassembler.cpp83 const unsigned *Regs, unsigned Size) { in decodeRegisterClass()
292 const unsigned *Regs) { in decodeBDAddr12Operand()
302 const unsigned *Regs) { in decodeBDAddr20Operand()
312 const unsigned *Regs) { in decodeBDXAddr12Operand()
324 const unsigned *Regs) { in decodeBDXAddr20Operand()
336 const unsigned *Regs) { in decodeBDLAddr12Len4Operand()
348 const unsigned *Regs) { in decodeBDLAddr12Len8Operand()
360 const unsigned *Regs) { in decodeBDRAddr12Operand()
372 const unsigned *Regs) { in decodeBDVAddr12Operand()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86CallLowering.cpp212 [&](ArrayRef<Register> Regs) { in lowerReturn()
357 [&](ArrayRef<Register> Regs) { in lowerFormalArguments()
418 [&](ArrayRef<Register> Regs) { in lowerCall()
468 [&](ArrayRef<Register> Regs) { in lowerCall()
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
HDCallingConvLower.h344 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated()
371 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg()
385 unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock()
412 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg()
HDRegisterPressure.h275 RegSet Regs; variable
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MCA/
HDHWEventListener.h74 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, in HWInstructionDispatchedEvent()
95 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent()
/freebsd-11-stable/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/
HDTaint.cpp136 TaintedSubRegions Regs = SavedRegs ? *SavedRegs : F.getEmptyMap(); in addPartialTaint() local
202 if (const TaintedSubRegions *Regs = in isTainted() local
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
HDRegisterInfoEmitter.cpp204 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure() local
371 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables()
506 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping()
870 const auto &Regs = RegBank.getRegisters(); in runMCDesc() local
1438 const auto &Regs = RegBank.getRegisters(); in runTargetDesc() local
1538 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); in runTargetDesc() local
HDCodeGenRegisters.cpp212 RegUnitIterator(const CodeGenRegister::Vec &Regs): in RegUnitIterator()
1114 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); in CodeGenRegBank() local
1570 CodeGenRegister::Vec Regs; member
1599 const CodeGenRegister::Vec &Regs = RegClass.getMembers(); in computeUberSets() local
2386 BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) { in computeCoveredRegisters()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
HDAMDGPUPALMetadata.cpp161 auto Regs = getRegisters(); in getRegister() local
555 auto Regs = getRegisters(); in toString() local
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
HDWebAssemblyRegisterInfo.cpp135 static const unsigned Regs[2][2] = { in getFrameRegister() local
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
HDRDFRegisters.cpp324 auto AliasedRegs = [this] (uint32_t Unit, BitVector &Regs) { in makeRegRef()
334 BitVector Regs(PRI.getTRI().getNumRegs()); in makeRegRef() local
HDExecutionDomainFix.cpp329 SmallVector<int, 4> Regs; in visitSoftInstr() local
HDAggressiveAntiDepBreaker.cpp85 std::vector<unsigned> &Regs, in GetGroupRegs()
562 std::vector<unsigned> Regs; in FindSuitableFreeRegisters() local
HDCallingConvLower.cpp199 void CCState::getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, in getRemainingRegParmsForType()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64ISelDAGToDAG.cpp1117 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) { in createDTuple()
1126 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple()
1135 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs, in createTuple()
1173 SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off, in SelectTable() local
1344 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStore() local
1366 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStore() local
1420 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectLoadLane() local
1459 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostLoadLane() local
1514 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStoreLane() local
1543 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStoreLane() local
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDAMDGPUCallLowering.cpp281 [&](ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT, int VTSplitIdx) { in lowerReturnVal()
491 ArrayRef<Register> Regs, in packSplitRegsToOrigType()
653 [&](ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT, int VTSplitIdx) { in lowerFormalArguments()
HDSILoadStoreOptimizer.cpp520 const unsigned Regs = getRegs(I->getOpcode(), TII); in setMI() local
1236 const unsigned Regs = getRegs(Opcode, *TII); in mergeBufferLoadPair() local
1298 const unsigned Regs = getRegs(Opcode, *TII); in mergeTBufferLoadPair() local
1377 const unsigned Regs = getRegs(Opcode, *TII); in mergeTBufferStorePair() local
1539 const unsigned Regs = getRegs(Opcode, *TII); in mergeBufferStorePair() local
HDSIMachineFunctionInfo.cpp344 auto Regs = RC.getRegisters(); in allocateVGPRSpillToAGPR() local
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDThumb2ITBlockPass.cpp99 auto InsertUsesDefs = [&](RegList &Regs, RegisterSet &UsesDefs) { in INITIALIZE_PASS()
HDARMLoadStoreOptimizer.cpp612 static bool ContainsReg(const ArrayRef<std::pair<unsigned, bool>> &Regs, in ContainsReg()
627 ArrayRef<std::pair<unsigned, bool>> Regs, in CreateLoadStoreMulti()
834 ArrayRef<std::pair<unsigned, bool>> Regs, in CreateLoadStoreDouble()
860 SmallVector<std::pair<unsigned, bool>, 8> Regs; in MergeOpsUpdate() local
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
HDCallLowering.h47 SmallVector<Register, 4> Regs; member
HDLegalizationArtifactCombiner.h364 SmallVector<Register, 2> Regs; in tryCombineMerges() local
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
HDIRTranslator.cpp164 auto *Regs = VMap.getVRegs(Val); in allocateVRegs() local
870 ArrayRef<Register> Regs = getOrCreateVRegs(LI); in translateLoad() local
1032 auto &Regs = *VMap.getVRegs(U); in translateBitCast() local
1879 auto &Regs = *VMap.getVRegs(U); in translateInsertElement() local
1903 auto &Regs = *VMap.getVRegs(U); in translateExtractElement() local
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
HDRISCVFrameLowering.cpp388 const MCPhysReg * Regs = MF.getRegInfo().getCalleeSavedRegs(); in determineCalleeSaves() local
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/
HDSystemZAsmParser.cpp742 const unsigned *Regs, bool IsAddress) { in parseRegister()
759 const unsigned *Regs, RegisterKind Kind) { in parseRegister()
897 const unsigned *Regs, RegisterKind RegKind) { in parseAddress()

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